Re: [EXT] Re: [PATCH] bus: fsl-mc: Add ACPI support for fsl-mc

From: Andrew Lunn <andrew@lunn.ch>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Jon Nettleton <jon@solid-run.com>,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	Marc Zyngier <maz@kernel.org>,
	Makarand Pawagi <makarand.pawagi@nxp.com>,
	Calvin Johnson <calvin.johnson@nxp.com>,
	stuyoder@gmail.com, nleeder@codeaurora.org,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	Cristi Sovaiala <cristian.sovaiala@nxp.com>,
	Hanjun Guo <guohanjun@huawei.com>, Will Deacon <will@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Pankaj Bansal <pankaj.bansal@nxp.com>,
	Russell King <linux@armlinux.org.uk>,
	ACPI Devel Maling List <linux-acpi@vger.kernel.org>,
	Len Brown <lenb@kernel.org>, Jason Cooper <jason@lakedaemon.net>,
	Andy Wang <Andy.Wang@arm.com>, Varun Sethi <V.Sethi@nxp.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Laurentiu Tudor <laurentiu.tudor@nxp.com>,
	Paul Yang <Paul.Yang@arm.com>,
	"<netdev@vger.kernel.org>" <netdev@vger.kernel.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Shameerali Kolothum Thodi  <shameerali.kolothum.thodi@huawei.com>,
	Sudeep Holla <sudeep.holla@arm.com>
Subject: Re: [EXT] Re: [PATCH] bus: fsl-mc: Add ACPI support for fsl-mc
Date: Fri, 31 Jan 2020 15:29:06 +0100	[thread overview]
Message-ID: <20200131142906.GG9639@lunn.ch> (raw)
In-Reply-To: <b136adc4-be48-82df-0592-97b4ba11dd79@arm.com>

> > But by design SFP, SFP+, and QSFP cages are not fixed function network
> > adapters.  They are physical and logical devices that can adapt to
> > what is plugged into them.  How the devices are exposed should be
> > irrelevant to this conversation it is about the underlying
> > connectivity.
> 
> Apologies - I was under the impression that SFP and friends were a
> physical-layer thing and that a MAC in the SoC would still be fixed such
> that its DMA and interrupt configuration could be statically described
> regardless of what transceiver was plugged in (even if some configurations
> might not use every interrupt/stream ID/etc.) If that isn't the case I shall
> go and educate myself further.

Hi Robin

It gets interesting with QSFP cages. The Q is quad, there are 4 SERDES
lanes. You can use them for 1x 40G link, or you can split them into 4x
10G links. So you either need one MAC or 4 MACs connecting to the
cage, and this can change on the fly when a modules is ejected and
replaced with another module. There are only one set of control pins
for i2c, loss of signal, TX disable, module inserted. So where the
interrupt/stream ID/etc are mapped needs some flexibility.

There is also to some degree a conflict with hiding all this inside
firmware. This is complex stuff. It is much better to have one core
implementing in Linux plus some per hardware driver support, than
having X firmware blobs, generally closed source, each with there own
bugs which nobody can fix.

     Andrew