* [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
@ 2020-02-06 14:09 Chris Wilson
2020-02-06 15:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Trim blitter block size (rev4) Patchwork
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Chris Wilson @ 2020-02-06 14:09 UTC (permalink / raw)
To: intel-gfx
Reduce the amount of work we do to verify client blt correctness as
currently our 0.5s subtests takes about 15s on slower devices!
v2: Grow the maximum block size until we run out of time
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../i915/gem/selftests/i915_gem_object_blt.c | 54 +++++++++++--------
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 62077fe46715..b98705821b84 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -210,6 +210,7 @@ static int igt_fill_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total;
int err;
ctx = thread->ctx;
@@ -225,10 +226,11 @@ static int igt_fill_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
@@ -238,11 +240,9 @@ static int igt_fill_blt_thread(void *arg)
* If we have a tiny shared address space, like for the GGTT
* then we can't be too greedy.
*/
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, ce->vm->total / 2);
+ sz = i915_prandom_u32_max_state(total, prng) + 1;
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -276,13 +276,16 @@ static int igt_fill_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
+ err = i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); i += 17) {
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -293,6 +296,8 @@ static int igt_fill_blt_thread(void *arg)
i915_gem_object_unpin_map(obj);
i915_gem_object_put(obj);
+
+ total <<= 1;
} while (!time_after(jiffies, end));
goto err_flush;
@@ -319,6 +324,7 @@ static int igt_copy_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total;
int err;
ctx = thread->ctx;
@@ -334,20 +340,19 @@ static int igt_copy_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
u32 i;
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, ce->vm->total / 2);
+ sz = i915_prandom_u32_max_state(total, prng) + 1;
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -397,13 +402,16 @@ static int igt_copy_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(dst);
- err = i915_gem_object_set_to_cpu_domain(dst, false);
- i915_gem_object_unlock(dst);
+ err = i915_gem_object_wait(dst, 0, MAX_SCHEDULE_TIMEOUT);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); i += 17) {
+ if (!(dst->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -416,6 +424,8 @@ static int igt_copy_blt_thread(void *arg)
i915_gem_object_put(src);
i915_gem_object_put(dst);
+
+ total <<= 1;
} while (!time_after(jiffies, end));
goto err_flush;
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Trim blitter block size (rev4)
2020-02-06 14:09 [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Chris Wilson
@ 2020-02-06 15:09 ` Patchwork
2020-02-06 15:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-02-10 12:47 ` [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Matthew Auld
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-02-06 15:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Trim blitter block size (rev4)
URL : https://patchwork.freedesktop.org/series/73066/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d8de8a6b2e7e drm/i915/selftests: Trim blitter block size
-:69: WARNING:MEMORY_BARRIER: memory barrier without comment
#69: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:286:
+ mb();
-:134: WARNING:MEMORY_BARRIER: memory barrier without comment
#134: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:412:
+ mb();
total: 0 errors, 2 warnings, 0 checks, 123 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Trim blitter block size (rev4)
2020-02-06 14:09 [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Chris Wilson
2020-02-06 15:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Trim blitter block size (rev4) Patchwork
@ 2020-02-06 15:28 ` Patchwork
2020-02-10 12:47 ` [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Matthew Auld
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-02-06 15:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Trim blitter block size (rev4)
URL : https://patchwork.freedesktop.org/series/73066/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7876 -> Patchwork_16458
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16458 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16458, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16458:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-snb-2600: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-snb-2600/igt@i915_selftest@live_blt.html
- fi-snb-2520m: NOTRUN -> [DMESG-FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-snb-2520m/igt@i915_selftest@live_blt.html
- fi-bsw-kefka: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-bsw-kefka/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-bsw-kefka/igt@i915_selftest@live_blt.html
- fi-ivb-3770: NOTRUN -> [DMESG-FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [PASS][6] -> [DMESG-FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-hsw-4770/igt@i915_selftest@live_blt.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-hsw-4770/igt@i915_selftest@live_blt.html
Known issues
------------
Here are the changes found in Patchwork_16458 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][8] -> [INCOMPLETE][9] ([i915#45])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-byt-j1900/igt@gem_close_race@basic-threads.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][10] -> [DMESG-FAIL][11] ([i915#725])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_execlists:
- fi-icl-y: [PASS][12] -> [DMESG-FAIL][13] ([fdo#108569])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-icl-y/igt@i915_selftest@live_execlists.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-icl-y/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][14] -> [FAIL][15] ([fdo#111096] / [i915#323])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_exec_parallel@contexts:
- fi-byt-n2820: [FAIL][16] ([i915#694]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
* igt@i915_selftest@live_blt:
- fi-bsw-nick: [INCOMPLETE][18] ([i915#392]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-bsw-nick/igt@i915_selftest@live_blt.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-bsw-nick/igt@i915_selftest@live_blt.html
#### Warnings ####
* igt@gem_exec_parallel@fds:
- fi-byt-n2820: [FAIL][20] ([i915#694]) -> [TIMEOUT][21] ([fdo#112271])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7876/fi-byt-n2820/igt@gem_exec_parallel@fds.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/fi-byt-n2820/igt@gem_exec_parallel@fds.html
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
Participating hosts (41 -> 40)
------------------------------
Additional (5): fi-snb-2520m fi-gdg-551 fi-ivb-3770 fi-skl-6700k2 fi-snb-2600
Missing (6): fi-bsw-n3050 fi-hsw-peppy fi-byt-squawks fi-ilk-650 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7876 -> Patchwork_16458
CI-20190529: 20190529
CI_DRM_7876: 6ac39d9964f464065511d439afcf4da065ff96db @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5421: 40946e61f9c47e23fdf1fff8090fadee8a4d7d3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16458: d8de8a6b2e7eefe6e4102a8bb082ac1363360877 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d8de8a6b2e7e drm/i915/selftests: Trim blitter block size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16458/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
2020-02-06 14:09 [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Chris Wilson
2020-02-06 15:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Trim blitter block size (rev4) Patchwork
2020-02-06 15:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-02-10 12:47 ` Matthew Auld
2020-02-10 12:52 ` Chris Wilson
2 siblings, 1 reply; 10+ messages in thread
From: Matthew Auld @ 2020-02-10 12:47 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development
On Thu, 6 Feb 2020 at 14:10, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Reduce the amount of work we do to verify client blt correctness as
> currently our 0.5s subtests takes about 15s on slower devices!
>
> v2: Grow the maximum block size until we run out of time
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Is that bsw-kefka issue(coherency?) something new?
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
2020-02-10 12:47 ` [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Matthew Auld
@ 2020-02-10 12:52 ` Chris Wilson
2020-02-10 23:02 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2020-02-10 12:52 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development
Quoting Matthew Auld (2020-02-10 12:47:35)
> On Thu, 6 Feb 2020 at 14:10, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Reduce the amount of work we do to verify client blt correctness as
> > currently our 0.5s subtests takes about 15s on slower devices!
> >
> > v2: Grow the maximum block size until we run out of time
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Is that bsw-kefka issue(coherency?) something new?
It's something to worry about.
This version is much harsher on the shared-gtt as it doesn't try to
relax our requests to allow parallelism between threads. We can reduce
the per-thread sizes again to sweep the problem under the carpet for a
bit longer.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
2020-02-10 12:52 ` Chris Wilson
@ 2020-02-10 23:02 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-02-10 23:02 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development
Quoting Chris Wilson (2020-02-10 12:52:26)
> Quoting Matthew Auld (2020-02-10 12:47:35)
> > On Thu, 6 Feb 2020 at 14:10, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > >
> > > Reduce the amount of work we do to verify client blt correctness as
> > > currently our 0.5s subtests takes about 15s on slower devices!
> > >
> > > v2: Grow the maximum block size until we run out of time
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >
> > Is that bsw-kefka issue(coherency?) something new?
>
> It's something to worry about.
Oh, it's just the vlv/chv clflush bug. Nothing to see here...
-Chris
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
@ 2020-02-10 23:10 Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-02-10 23:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld
Reduce the amount of work we do to verify client blt correctness as
currently our 0.5s subtests takes about 15s on slower devices!
v2: Grow the maximum block size until we run out of time
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
.../i915/gem/selftests/i915_gem_object_blt.c | 72 ++++++++++++-------
1 file changed, 46 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 62077fe46715..f29da4560dc0 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -210,6 +210,7 @@ static int igt_fill_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total, max;
int err;
ctx = thread->ctx;
@@ -225,24 +226,28 @@ static int igt_fill_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ /*
+ * If we have a tiny shared address space, like for the GGTT
+ * then we can't be too greedy.
+ */
+ max = ce->vm->total;
+ if (i915_is_ggtt(ce->vm) || thread->ctx)
+ max = div_u64(max, thread->n_cpus);
+ max >>= 4;
+
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
u32 i;
- /*
- * If we have a tiny shared address space, like for the GGTT
- * then we can't be too greedy.
- */
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, max);
+ sz = i915_prandom_u32_max_state(total, prng) + 1;
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -276,13 +281,14 @@ static int igt_fill_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
+ err = i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); i += 17) {
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
+ drm_clflush_virt_range(&vaddr[i], sizeof(vaddr[i]));
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -293,6 +299,8 @@ static int igt_fill_blt_thread(void *arg)
i915_gem_object_unpin_map(obj);
i915_gem_object_put(obj);
+
+ total <<= 1;
} while (!time_after(jiffies, end));
goto err_flush;
@@ -319,6 +327,7 @@ static int igt_copy_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total, max;
int err;
ctx = thread->ctx;
@@ -334,20 +343,28 @@ static int igt_copy_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ /*
+ * If we have a tiny shared address space, like for the GGTT
+ * then we can't be too greedy.
+ */
+ max = ce->vm->total;
+ if (i915_is_ggtt(ce->vm) || thread->ctx)
+ max = div_u64(max, thread->n_cpus);
+ max >>= 4;
+
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
u32 i;
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, max);
+ sz = i915_prandom_u32_max_state(total, prng) + 1;
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -397,13 +414,14 @@ static int igt_copy_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(dst);
- err = i915_gem_object_set_to_cpu_domain(dst, false);
- i915_gem_object_unlock(dst);
+ err = i915_gem_object_wait(dst, 0, MAX_SCHEDULE_TIMEOUT);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); i += 17) {
+ if (!(dst->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
+ drm_clflush_virt_range(&vaddr[i], sizeof(vaddr[i]));
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -416,6 +434,8 @@ static int igt_copy_blt_thread(void *arg)
i915_gem_object_put(src);
i915_gem_object_put(dst);
+
+ total <<= 1;
} while (!time_after(jiffies, end));
goto err_flush;
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
2020-02-06 0:33 Chris Wilson
@ 2020-02-06 12:52 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-02-06 12:52 UTC (permalink / raw)
To: intel-gfx
Reduce the amount of work we do to verify client blt correctness as
currently our 0.5s subtests takes about 15s on slower devices!
v2: Grow the maximum block size until we run out of time
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../i915/gem/selftests/i915_gem_object_blt.c | 54 +++++++++++--------
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 62077fe46715..b98705821b84 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -210,6 +210,7 @@ static int igt_fill_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total;
int err;
ctx = thread->ctx;
@@ -225,10 +226,11 @@ static int igt_fill_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
@@ -238,11 +240,9 @@ static int igt_fill_blt_thread(void *arg)
* If we have a tiny shared address space, like for the GGTT
* then we can't be too greedy.
*/
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, ce->vm->total / 2);
+ sz = i915_prandom_u32_max_state(total, prng) + 1;
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -276,13 +276,16 @@ static int igt_fill_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
+ err = i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); i += 17) {
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -293,6 +296,8 @@ static int igt_fill_blt_thread(void *arg)
i915_gem_object_unpin_map(obj);
i915_gem_object_put(obj);
+
+ total <<= 1;
} while (!time_after(jiffies, end));
goto err_flush;
@@ -319,6 +324,7 @@ static int igt_copy_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total;
int err;
ctx = thread->ctx;
@@ -334,20 +340,19 @@ static int igt_copy_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
u32 i;
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, ce->vm->total / 2);
+ sz = i915_prandom_u32_max_state(total, prng) + 1;
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -397,13 +402,16 @@ static int igt_copy_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(dst);
- err = i915_gem_object_set_to_cpu_domain(dst, false);
- i915_gem_object_unlock(dst);
+ err = i915_gem_object_wait(dst, 0, MAX_SCHEDULE_TIMEOUT);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); i += 17) {
+ if (!(dst->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -416,6 +424,8 @@ static int igt_copy_blt_thread(void *arg)
i915_gem_object_put(src);
i915_gem_object_put(dst);
+
+ total <<= 1;
} while (!time_after(jiffies, end));
goto err_flush;
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
2020-02-06 3:33 [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
@ 2020-02-06 9:20 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-02-06 9:20 UTC (permalink / raw)
To: intel-gfx
Reduce the amount of work we do to verify client blt correctness as
currently our 0.5s subtests takes about 15s on slower devices!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../i915/gem/selftests/i915_gem_object_blt.c | 40 ++++++++++++-------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 62077fe46715..674f4298f9a6 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -226,7 +226,9 @@ static int igt_fill_blt_thread(void *arg)
GEM_BUG_ON(IS_ERR(ce));
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_block_size = SZ_64M; /* max S16_MAX * PAGE_SIZE */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
u64 total = ce->vm->total;
u32 phys_sz;
@@ -240,9 +242,10 @@ static int igt_fill_blt_thread(void *arg)
*/
if (i915_is_ggtt(ce->vm))
total = div64_u64(total, thread->n_cpus);
+ total = min_t(u64, total, max_block_size);
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ sz = i915_prandom_u32_max_state(total, prng);
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -276,13 +279,16 @@ static int igt_fill_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
+ err = i915_gem_object_wait(obj, I915_WAIT_ALL, HZ / 2);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); i += 17) {
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -335,7 +341,9 @@ static int igt_copy_blt_thread(void *arg)
GEM_BUG_ON(IS_ERR(ce));
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_block_size = SZ_64M; /* max S16_MAX * PAGE_SIZE */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
u64 total = ce->vm->total;
u32 phys_sz;
@@ -345,9 +353,10 @@ static int igt_copy_blt_thread(void *arg)
if (i915_is_ggtt(ce->vm))
total = div64_u64(total, thread->n_cpus);
+ total = min_t(u64, total, max_block_size);
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ sz = i915_prandom_u32_max_state(total, prng);
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -397,13 +406,16 @@ static int igt_copy_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(dst);
- err = i915_gem_object_set_to_cpu_domain(dst, false);
- i915_gem_object_unlock(dst);
+ err = i915_gem_object_wait(dst, I915_WAIT_ALL, HZ / 2);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); i += 17) {
+ if (!(dst->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
@ 2020-02-06 0:33 Chris Wilson
2020-02-06 12:52 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2020-02-06 0:33 UTC (permalink / raw)
To: intel-gfx
Reduce the amount of work we do to verify client blt correctness as
currently our 0.5s subtests takes about 15s on slower devices!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../i915/gem/selftests/i915_gem_object_blt.c | 24 ++++++++++++-------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 62077fe46715..cebbe3c3ca86 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -226,7 +226,7 @@ static int igt_fill_blt_thread(void *arg)
GEM_BUG_ON(IS_ERR(ce));
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ const u32 max_block_size = SZ_64M; /* max S16_MAX * PAGE_SIZE */
u32 val = prandom_u32_state(prng);
u64 total = ce->vm->total;
u32 phys_sz;
@@ -276,13 +276,16 @@ static int igt_fill_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
+ err = i915_gem_object_wait(obj, I915_WAIT_ALL, HZ / 2);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
+ for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); i += 17) {
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -335,7 +338,7 @@ static int igt_copy_blt_thread(void *arg)
GEM_BUG_ON(IS_ERR(ce));
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ const u32 max_block_size = SZ_64M; /* max S16_MAX * PAGE_SIZE */
u32 val = prandom_u32_state(prng);
u64 total = ce->vm->total;
u32 phys_sz;
@@ -397,13 +400,16 @@ static int igt_copy_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(dst);
- err = i915_gem_object_set_to_cpu_domain(dst, false);
- i915_gem_object_unlock(dst);
+ err = i915_gem_object_wait(dst, I915_WAIT_ALL, HZ / 2);
if (err)
goto err_unpin;
for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32); ++i) {
+ if (!(dst->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush(&vaddr[i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-02-10 23:11 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-06 14:09 [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Chris Wilson
2020-02-06 15:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Trim blitter block size (rev4) Patchwork
2020-02-06 15:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-02-10 12:47 ` [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size Matthew Auld
2020-02-10 12:52 ` Chris Wilson
2020-02-10 23:02 ` Chris Wilson
-- strict thread matches above, loose matches on Subject: below --
2020-02-10 23:10 Chris Wilson
2020-02-06 3:33 [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2020-02-06 9:20 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-02-06 0:33 Chris Wilson
2020-02-06 12:52 ` Chris Wilson
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