[PATCH v4 00/17] riscv: Add Sipeed Maix support

[PATCH v4 00/17] riscv: Add Sipeed Maix support

[Sean Anderson]

This patch series adds support for Sipeed Maix boards and the Kendryte
K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
models are similar. This series depends on
<https://patchwork.ozlabs.org/patch/1215327/>
(clk: Include missing headers for linux/clk-provider.h).
In addition, there are optional dependencies on
<https://patchwork.ozlabs.org/project/uboot/list/?series=156377>
<https://patchwork.ozlabs.org/project/uboot/list/?series=156381> and
<https://patchwork.ozlabs.org/patch/1232422/>
(wdt: Add DM support for Designware WDT)
(riscv: Try to get cpu frequency from device tree)
(serial: Set baudrate on boot)

To flash u-boot to a maix bit, run
kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin

Boot output should look like the following:

U-Boot 2020.01-00465-g1da52c6c9a (Feb 10 2020 - 20:26:50 -0500)

DRAM:  8 MiB
MMC:
In:    serial at 38000000
Out:   serial at 38000000
Err:   serial at 38000000
=>

The MMC (SD-card reader) does not work yet (see the second spi patch for
details). I'm not sure how to set up autoboot.  Should I arbitrarily assign
partitions? Should I use MTD/UBI?

Changes for v4:
- Linted several patches
- Updated the copyright year for several files
- Added tests for syscon-reset, simple-pm-bus, and the pll calc_rate function
- Added/updated documentation
- Fixed SPI for the nor flash
- Fixed PLLs not enabling/setting rate properly
- RISCV_PRIV_1_9_1 now (un)defines all deferring CSRs, and also disables VM
- More devicetree changes

Changes for v3:
- Remove patch to set RV64I as default
- Remove patch for a separate sysctl driver
- Split off cpu frequency patch into its own series
- Reorder support/devicetree patches to come last
- Add patch for reset driver
- Add simple-pm-bus for busses with their own clocks
- Add additional documentation
- Reword mcounteren patch to refer to the RISC-V priv spec 1.9.1
- Many devicetree changes
- Switch to "make savedefconfig" to generate the config

Changes for v2:
- Many bugfixes for the device tree
- Modify the config to build without errors
- Add support for keeping internal PLL frequencies in-range
- Fix several rebase-induced artifacts

Sean Anderson (17):
  clk: Always use the supplied struct clk
  clk: Check that ops of composite clock components exist before calling
  clk: Unconditionally recursively en-/dis-able clocks
  reset: Add generic reset driver
  dm: Add support for simple-pm-bus
  spi: dw: Add device tree properties for fields in CTRL1
  spi: dw: Add mem_ops
  riscv: Add headers for asm/global_data.h
  riscv: Add option to support RISC-V privileged spec 1.9.1
  riscv: Allow use of reset drivers
  riscv: Add K210 pll support
  riscv: Add a bypass clock for K210
  riscv: Add K210 clock support
  riscv: Try to get cpu frequency from device tree
  riscv: Enable cpu clock if it is present
  riscv: Add device tree for K210
  riscv: Add Sipeed Maix support

 MAINTAINERS                                   |   6 +
 arch/riscv/Kconfig                            |  14 +
 arch/riscv/cpu/cpu.c                          |   9 +
 arch/riscv/dts/Makefile                       |   1 +
 arch/riscv/dts/k210-maix-bit.dts              |  41 ++
 arch/riscv/dts/k210.dtsi                      | 568 ++++++++++++++++
 arch/riscv/include/asm/csr.h                  |  40 ++
 arch/riscv/include/asm/global_data.h          |   2 +
 arch/riscv/lib/reset.c                        |   2 +
 arch/sandbox/dts/test.dts                     |  21 +
 arch/sandbox/include/asm/clk.h                |   1 +
 board/sipeed/maix/Kconfig                     |  56 ++
 board/sipeed/maix/MAINTAINERS                 |  11 +
 board/sipeed/maix/Makefile                    |   5 +
 board/sipeed/maix/maix.c                      |   9 +
 configs/sandbox_defconfig                     |   2 +
 configs/sipeed_maix_bitm_defconfig            |  10 +
 doc/board/index.rst                           |   1 +
 doc/board/sipeed/index.rst                    |   9 +
 doc/board/sipeed/maix.rst                     |  94 +++
 .../bus/simple-pm-bus.txt                     |  44 ++
 .../reset/syscon-reset.txt                    |  36 ++
 .../spi/snps,dw-apb-ssi.txt                   |  43 ++
 doc/imx/clk/ccf.txt                           |  63 +-
 drivers/clk/Kconfig                           |   1 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-composite.c                   |  64 +-
 drivers/clk/clk-divider.c                     |   6 +-
 drivers/clk/clk-fixed-factor.c                |   3 +-
 drivers/clk/clk-gate.c                        |   6 +-
 drivers/clk/clk-mux.c                         |  12 +-
 drivers/clk/clk-uclass.c                      |  59 +-
 drivers/clk/imx/clk-gate2.c                   |   4 +-
 drivers/clk/kendryte/Kconfig                  |  12 +
 drivers/clk/kendryte/Makefile                 |   1 +
 drivers/clk/kendryte/bypass.c                 | 268 ++++++++
 drivers/clk/kendryte/clk.c                    | 409 ++++++++++++
 drivers/clk/kendryte/pll.c                    | 604 ++++++++++++++++++
 drivers/core/Kconfig                          |   7 +
 drivers/core/Makefile                         |   1 +
 drivers/core/simple-pm-bus.c                  |  55 ++
 drivers/cpu/riscv_cpu.c                       |  38 +-
 drivers/reset/Kconfig                         |   5 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-syscon.c                  |  79 +++
 drivers/spi/designware_spi.c                  | 163 ++++-
 include/configs/sipeed-maix.h                 |  17 +
 include/dt-bindings/clock/k210-sysctl.h       |  53 ++
 include/dt-bindings/mfd/k210-sysctl.h         |  38 ++
 include/dt-bindings/reset/k210-sysctl.h       |  38 ++
 include/kendryte/bypass.h                     |  28 +
 include/kendryte/clk.h                        |  27 +
 include/kendryte/pll.h                        |  57 ++
 include/test/export.h                         |  16 +
 test/dm/Makefile                              |   3 +
 test/dm/k210_pll.c                            |  95 +++
 test/dm/simple-pm-bus.c                       |  44 ++
 test/dm/syscon-reset.c                        |  58 ++
 58 files changed, 3235 insertions(+), 126 deletions(-)
 create mode 100644 arch/riscv/dts/k210-maix-bit.dts
 create mode 100644 arch/riscv/dts/k210.dtsi
 create mode 100644 board/sipeed/maix/Kconfig
 create mode 100644 board/sipeed/maix/MAINTAINERS
 create mode 100644 board/sipeed/maix/Makefile
 create mode 100644 board/sipeed/maix/maix.c
 create mode 100644 configs/sipeed_maix_bitm_defconfig
 create mode 100644 doc/board/sipeed/index.rst
 create mode 100644 doc/board/sipeed/maix.rst
 create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt
 create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt
 create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
 create mode 100644 drivers/clk/kendryte/Kconfig
 create mode 100644 drivers/clk/kendryte/Makefile
 create mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 drivers/clk/kendryte/clk.c
 create mode 100644 drivers/clk/kendryte/pll.c
 create mode 100644 drivers/core/simple-pm-bus.c
 create mode 100644 drivers/reset/reset-syscon.c
 create mode 100644 include/configs/sipeed-maix.h
 create mode 100644 include/dt-bindings/clock/k210-sysctl.h
 create mode 100644 include/dt-bindings/mfd/k210-sysctl.h
 create mode 100644 include/dt-bindings/reset/k210-sysctl.h
 create mode 100644 include/kendryte/bypass.h
 create mode 100644 include/kendryte/clk.h
 create mode 100644 include/kendryte/pll.h
 create mode 100644 include/test/export.h
 create mode 100644 test/dm/k210_pll.c
 create mode 100644 test/dm/simple-pm-bus.c
 create mode 100644 test/dm/syscon-reset.c

-- 
2.25.0

[PATCH v4 01/17] clk: Always use the supplied struct clk

[Sean Anderson]

CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.

The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks.  This allows child clocks to make calls like clk_get_parent()
without issue.

imx avoided the above problem by using a custom get_rate function with
composite clocks.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4:
- Lint

Changes in v3:
- Documented new assumptions in the CCF
- Wrapped docs to 80 columns

 doc/imx/clk/ccf.txt            | 63 +++++++++++++++++-----------------
 drivers/clk/clk-composite.c    |  7 ++++
 drivers/clk/clk-divider.c      |  6 ++--
 drivers/clk/clk-fixed-factor.c |  3 +-
 drivers/clk/clk-gate.c         |  6 ++--
 drivers/clk/clk-mux.c          | 12 +++----
 drivers/clk/imx/clk-gate2.c    |  4 +--
 7 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/doc/imx/clk/ccf.txt b/doc/imx/clk/ccf.txt
index 36b60dc438..e40ac360e8 100644
--- a/doc/imx/clk/ccf.txt
+++ b/doc/imx/clk/ccf.txt
@@ -1,42 +1,37 @@
 Introduction:
 =============
 
-This documentation entry describes the Common Clock Framework [CCF]
-port from Linux kernel (v5.1.12) to U-Boot.
+This documentation entry describes the Common Clock Framework [CCF] port from
+Linux kernel (v5.1.12) to U-Boot.
 
-This code is supposed to bring CCF to IMX based devices (imx6q, imx7
-imx8). Moreover, it also provides some common clock code, which would
-allow easy porting of CCF Linux code to other platforms.
+This code is supposed to bring CCF to IMX based devices (imx6q, imx7 imx8).
+Moreover, it also provides some common clock code, which would allow easy
+porting of CCF Linux code to other platforms.
 
 Design decisions:
 =================
 
-* U-Boot's driver model [DM] for clk differs from Linux CCF. The most
-  notably difference is the lack of support for hierarchical clocks and
-  "clock as a manager driver" (single clock DTS node acts as a starting
-  point for all other clocks).
+* U-Boot's driver model [DM] for clk differs from Linux CCF. The most notably
+  difference is the lack of support for hierarchical clocks and "clock as a
+  manager driver" (single clock DTS node acts as a starting point for all other
+  clocks).
 
-* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE
-  is not set (no need for recursive access).
+* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE is
+  not set (no need for recursive access).
 
-* On purpose the "manager" clk driver (clk-imx6q.c) is not using large
-  table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = ....
-  Instead we use udevice's linked list for the same class (UCLASS_CLK).
+* On purpose the "manager" clk driver (clk-imx6q.c) is not using large table to
+  store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = .... Instead we
+  use udevice's linked list for the same class (UCLASS_CLK).
 
   Rationale:
   ----------
-    When porting the code as is from Linux, one would need ~1KiB of RAM to
-    store it. This is way too much if we do plan to use this driver in SPL.
+    When porting the code as is from Linux, one would need ~1KiB of RAM to store
+    it. This is way too much if we do plan to use this driver in SPL.
 
 * The "central" structure of this patch series is struct udevice and its
   uclass_priv field contains the struct clk pointer (to the originally created
   one).
 
-* Up till now U-Boot's driver model (DM) CLK operates on udevice (main
-  access to clock is by udevice ops)
-  In the CCF the access to struct clk (embodying pointer to *dev) is
-  possible via dev_get_clk_ptr() (it is a wrapper on dev_get_uclass_priv()).
-
 * To keep things simple the struct udevice's uclass_priv pointer is used to
   store back pointer to corresponding struct clk. However, it is possible to
   modify clk-uclass.c file and add there struct uc_clk_priv, which would have
@@ -45,13 +40,17 @@ Design decisions:
   setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the
   uclass_priv stores the pointer to struct clk.
 
+* Non-CCF clocks do not have a pointer to a clock in clk->dev->priv. In the case
+  of composite clocks, clk->dev->priv may not match clk. Drivers should always
+  use the struct clk which is passed to them, and not clk->dev->priv.
+
 * It is advised to add common clock code (like already added rate and flags) to
   the struct clk, which is a top level description of the clock.
 
 * U-Boot's driver model already provides the facility to automatically allocate
-  (via private_alloc_size) device private data (accessible via dev->priv).
-  It may look appealing to use this feature to allocate private structures for
-  CCF clk devices e.g. divider (struct clk_divider *divider) for IMX6Q clock.
+  (via private_alloc_size) device private data (accessible via dev->priv). It
+  may look appealing to use this feature to allocate private structures for CCF
+  clk devices e.g. divider (struct clk_divider *divider) for IMX6Q clock.
 
   The above feature had not been used for following reasons:
   - The original CCF Linux kernel driver is the "manager" for clocks - it
@@ -64,21 +63,23 @@ Design decisions:
 
 * I've added the clk_get_parent(), which reads parent's dev->uclass_priv to
   provide parent's struct clk pointer. This seems the easiest way to get
-  child/parent relationship for struct clk in U-Boot's udevice based clocks.
+  child/parent relationship for struct clk in U-Boot's udevice based clocks.  In
+  the future arbitrary parents may be supported by adding a get_parent function
+  to clk_ops.
 
 * Linux's CCF 'struct clk_core' corresponds to U-Boot's udevice in 'struct clk'.
   Clock IP block agnostic flags from 'struct clk_core' (e.g. NOCACHE) have been
-  moved from this struct one level up to 'struct clk'.
+  moved from this struct one level up to 'struct clk'. Many flags are
+  unimplemented at the moment.
 
 * For tests the new ./test/dm/clk_ccf.c and ./drivers/clk/clk_sandbox_ccf.c
   files have been introduced. The latter setups the CCF clock structure for
-  sandbox by reusing, if possible, generic clock primitives - like divier
-  and mux. The former file provides code to tests this setup.
+  sandbox by reusing, if possible, generic clock primitives - like divier and
+  mux. The former file provides code to tests this setup.
 
   For sandbox new CONFIG_SANDBOX_CLK_CCF Kconfig define has been introduced.
-  All new primitives added for new architectures must have corresponding test
-  in the two aforementioned files.
-
+  All new primitives added for new architectures must have corresponding test in
+  the two aforementioned files.
 
 Testing (sandbox):
 ==================
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index a5626c33d1..3d84036c9e 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -145,6 +145,13 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 		goto err;
 	}
 
+	if (composite->mux)
+		composite->mux->dev = clk->dev;
+	if (composite->rate)
+		composite->rate->dev = clk->dev;
+	if (composite->gate)
+		composite->gate->dev = clk->dev;
+
 	return clk;
 
 err:
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 822e09b084..bfa05f24a3 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -70,8 +70,7 @@ unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
 
 static ulong clk_divider_recalc_rate(struct clk *clk)
 {
-	struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_divider *divider = to_clk_divider(clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	unsigned int val;
 
@@ -150,8 +149,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
 
 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
 {
-	struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_divider *divider = to_clk_divider(clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	int value;
 	u32 val;
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 711b0588bc..d2401cf440 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -18,8 +18,7 @@
 
 static ulong clk_factor_recalc_rate(struct clk *clk)
 {
-	struct clk_fixed_factor *fix =
-		to_clk_fixed_factor(dev_get_clk_ptr(clk->dev));
+	struct clk_fixed_factor *fix = to_clk_fixed_factor(clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	unsigned long long int rate;
 
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 70b8794554..b2933bc24a 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -43,8 +43,7 @@
  */
 static void clk_gate_endisable(struct clk *clk, int enable)
 {
-	struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_gate *gate = to_clk_gate(clk);
 	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
 	u32 reg;
 
@@ -86,8 +85,7 @@ static int clk_gate_disable(struct clk *clk)
 
 int clk_gate_is_enabled(struct clk *clk)
 {
-	struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_gate *gate = to_clk_gate(clk);
 	u32 reg;
 
 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 5acc0b8cbd..67b4afef28 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -35,8 +35,7 @@
 int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
 			 unsigned int val)
 {
-	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_mux *mux = to_clk_mux(clk);
 	int num_parents = mux->num_parents;
 
 	if (table) {
@@ -79,8 +78,7 @@ unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
 
 u8 clk_mux_get_parent(struct clk *clk)
 {
-	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_mux *mux = to_clk_mux(clk);
 	u32 val;
 
 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
@@ -97,8 +95,7 @@ u8 clk_mux_get_parent(struct clk *clk)
 static int clk_fetch_parent_index(struct clk *clk,
 				  struct clk *parent)
 {
-	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_mux *mux = to_clk_mux(clk);
 
 	int i;
 
@@ -115,8 +112,7 @@ static int clk_fetch_parent_index(struct clk *clk,
 
 static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
 {
-	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
+	struct clk_mux *mux = to_clk_mux(clk);
 	int index;
 	u32 val;
 	u32 reg;
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 1b9db6e791..e32c0cb53e 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -37,7 +37,7 @@ struct clk_gate2 {
 
 static int clk_gate2_enable(struct clk *clk)
 {
-	struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+	struct clk_gate2 *gate = to_clk_gate2(clk);
 	u32 reg;
 
 	reg = readl(gate->reg);
@@ -50,7 +50,7 @@ static int clk_gate2_enable(struct clk *clk)
 
 static int clk_gate2_disable(struct clk *clk)
 {
-	struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+	struct clk_gate2 *gate = to_clk_gate2(clk);
 	u32 reg;
 
 	reg = readl(gate->reg);
-- 
2.25.0

[PATCH v4 02/17] clk: Check that ops of composite clock components exist before calling

[Sean Anderson]

clk_composite_ops was shared between all devices in the composite clock
driver.  If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.

This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.

The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4:
- Return ENOTSUPP not ENOSYS with no set_parent

Changes in v3:
- Don't return an error code where a no-op would be fine

 drivers/clk/clk-composite.c | 57 +++++++++++++++++++++++--------------
 1 file changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 3d84036c9e..bcf6b9c689 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -22,7 +22,10 @@ static u8 clk_composite_get_parent(struct clk *clk)
 		(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
 	struct clk *mux = composite->mux;
 
-	return clk_mux_get_parent(mux);
+	if (mux)
+		return clk_mux_get_parent(mux);
+	else
+		return 0;
 }
 
 static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
@@ -32,7 +35,10 @@ static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
 	const struct clk_ops *mux_ops = composite->mux_ops;
 	struct clk *mux = composite->mux;
 
-	return mux_ops->set_parent(mux, parent);
+	if (mux && mux_ops)
+		return mux_ops->set_parent(mux, parent);
+	else
+		return -ENOTSUPP;
 }
 
 static unsigned long clk_composite_recalc_rate(struct clk *clk)
@@ -42,7 +48,10 @@ static unsigned long clk_composite_recalc_rate(struct clk *clk)
 	const struct clk_ops *rate_ops = composite->rate_ops;
 	struct clk *rate = composite->rate;
 
-	return rate_ops->get_rate(rate);
+	if (rate && rate_ops)
+		return rate_ops->get_rate(rate);
+	else
+		return clk_get_parent_rate(clk);
 }
 
 static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
@@ -52,7 +61,10 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
 	const struct clk_ops *rate_ops = composite->rate_ops;
 	struct clk *clk_rate = composite->rate;
 
-	return rate_ops->set_rate(clk_rate, rate);
+	if (rate && rate_ops)
+		return rate_ops->set_rate(clk_rate, rate);
+	else
+		return clk_get_rate(clk);
 }
 
 static int clk_composite_enable(struct clk *clk)
@@ -62,7 +74,10 @@ static int clk_composite_enable(struct clk *clk)
 	const struct clk_ops *gate_ops = composite->gate_ops;
 	struct clk *gate = composite->gate;
 
-	return gate_ops->enable(gate);
+	if (gate && gate_ops)
+		return gate_ops->enable(gate);
+	else
+		return 0;
 }
 
 static int clk_composite_disable(struct clk *clk)
@@ -72,15 +87,12 @@ static int clk_composite_disable(struct clk *clk)
 	const struct clk_ops *gate_ops = composite->gate_ops;
 	struct clk *gate = composite->gate;
 
-	gate_ops->disable(gate);
-
-	return 0;
+	if (gate && gate_ops)
+		return gate_ops->disable(gate);
+	else
+		return 0;
 }
 
-struct clk_ops clk_composite_ops = {
-	/* This will be set according to clk_register_composite */
-};
-
 struct clk *clk_register_composite(struct device *dev, const char *name,
 				   const char * const *parent_names,
 				   int num_parents, struct clk *mux,
@@ -94,7 +106,9 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 	struct clk *clk;
 	struct clk_composite *composite;
 	int ret;
-	struct clk_ops *composite_ops = &clk_composite_ops;
+
+	if (!num_parents || (num_parents != 1 && !mux))
+		return ERR_PTR(-EINVAL);
 
 	composite = kzalloc(sizeof(*composite), GFP_KERNEL);
 	if (!composite)
@@ -103,8 +117,6 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 	if (mux && mux_ops) {
 		composite->mux = mux;
 		composite->mux_ops = mux_ops;
-		if (mux_ops->set_parent)
-			composite_ops->set_parent = clk_composite_set_parent;
 		mux->data = (ulong)composite;
 	}
 
@@ -113,11 +125,6 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 			clk = ERR_PTR(-EINVAL);
 			goto err;
 		}
-		composite_ops->get_rate = clk_composite_recalc_rate;
-
-		/* .set_rate requires either .round_rate or .determine_rate */
-		if (rate_ops->set_rate)
-			composite_ops->set_rate = clk_composite_set_rate;
 
 		composite->rate = rate;
 		composite->rate_ops = rate_ops;
@@ -132,8 +139,6 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 
 		composite->gate = gate;
 		composite->gate_ops = gate_ops;
-		composite_ops->enable = clk_composite_enable;
-		composite_ops->disable = clk_composite_disable;
 		gate->data = (ulong)composite;
 	}
 
@@ -159,6 +164,14 @@ err:
 	return clk;
 }
 
+static const struct clk_ops clk_composite_ops = {
+	.set_parent = clk_composite_set_parent,
+	.get_rate = clk_composite_recalc_rate,
+	.set_rate = clk_composite_set_rate,
+	.enable = clk_composite_enable,
+	.disable = clk_composite_disable,
+};
+
 U_BOOT_DRIVER(clk_composite) = {
 	.name	= UBOOT_DM_CLK_COMPOSITE,
 	.id	= UCLASS_CLK,
-- 
2.25.0

[PATCH v4 03/17] clk: Unconditionally recursively en-/dis-able clocks

[Sean Anderson]

For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
just enable them as normal. The enable count is local to the struct clk,
but this will never result in the actual en-/dis-able op being called
(unless the same struct clk is enabled twice).

For clocks in the CCF, we always traverse up the tree when enabling.
Previously, CCF clocks without id set would be skipped, stopping the
traversal too early.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
---

Changes in v4:
- Lint

Changes in v3:
- New

 drivers/clk/clk-uclass.c | 59 ++++++++++++++++++----------------------
 1 file changed, 26 insertions(+), 33 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 246b9c0ab8..c5f87fee72 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -491,7 +491,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 int clk_enable(struct clk *clk)
 {
 	const struct clk_ops *ops;
-	struct clk *clkp = NULL;
 	int ret;
 
 	debug("%s(clk=%p \"%s\")\n", __func__, clk, clk->dev->name);
@@ -500,32 +499,29 @@ int clk_enable(struct clk *clk)
 	ops = clk_dev_ops(clk->dev);
 
 	if (CONFIG_IS_ENABLED(CLK_CCF)) {
-		/* Take id 0 as a non-valid clk, such as dummy */
-		if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
-			if (clkp->enable_count) {
-				clkp->enable_count++;
-				return 0;
-			}
-			if (clkp->dev->parent &&
-			    device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-				ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
-				if (ret) {
-					printf("Enable %s failed\n",
-					       clkp->dev->parent->name);
-					return ret;
-				}
+		if (clk->enable_count) {
+			clk->enable_count++;
+			return 0;
+		}
+		if (clk->dev->parent &&
+		    device_get_uclass_id(clk->dev->parent) == UCLASS_CLK) {
+			ret = clk_enable(dev_get_clk_ptr(clk->dev->parent));
+			if (ret) {
+				printf("Enable %s failed\n",
+				       clk->dev->parent->name);
+				return ret;
 			}
 		}
 
 		if (ops->enable) {
 			ret = ops->enable(clk);
 			if (ret) {
-				printf("Enable %s failed\n", clk->dev->name);
+				printf("Enable %s failed (error %d)\n",
+				       clk->dev->name, ret);
 				return ret;
 			}
 		}
-		if (clkp)
-			clkp->enable_count++;
+		clk->enable_count++;
 	} else {
 		if (!ops->enable)
 			return -ENOSYS;
@@ -551,7 +547,6 @@ int clk_enable_bulk(struct clk_bulk *bulk)
 int clk_disable(struct clk *clk)
 {
 	const struct clk_ops *ops;
-	struct clk *clkp = NULL;
 	int ret;
 
 	debug("%s(clk=%p)\n", __func__, clk);
@@ -560,29 +555,27 @@ int clk_disable(struct clk *clk)
 	ops = clk_dev_ops(clk->dev);
 
 	if (CONFIG_IS_ENABLED(CLK_CCF)) {
-		if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
-			if (clkp->enable_count == 0) {
-				printf("clk %s already disabled\n",
-				       clkp->dev->name);
-				return 0;
-			}
-
-			if (--clkp->enable_count > 0)
-				return 0;
+		if (clk->enable_count == 0) {
+			printf("clk %s already disabled\n",
+			       clk->dev->name);
+			return 0;
 		}
 
+		if (--clk->enable_count > 0)
+			return 0;
+
 		if (ops->disable) {
 			ret = ops->disable(clk);
 			if (ret)
 				return ret;
 		}
 
-		if (clkp && clkp->dev->parent &&
-		    device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-			ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
+		if (clk->dev->parent &&
+		    device_get_uclass_id(clk->dev) == UCLASS_CLK) {
+			ret = clk_disable(dev_get_clk_ptr(clk->dev->parent));
 			if (ret) {
-				printf("Disable %s failed\n",
-				       clkp->dev->parent->name);
+				printf("Disable %s failed (error %d)\n",
+				       clk->dev->parent->name, ret);
 				return ret;
 			}
 		}
-- 
2.25.0

[PATCH v4 04/17] reset: Add generic reset driver

[Sean Anderson]

This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- Added basic test
- Fix incorrect usage of regmap_update_bits

Changes in v3:
- New

 arch/sandbox/dts/test.dts                     | 15 ++++
 configs/sandbox_defconfig                     |  1 +
 .../reset/syscon-reset.txt                    | 36 +++++++++
 drivers/reset/Kconfig                         |  5 ++
 drivers/reset/Makefile                        |  1 +
 drivers/reset/reset-syscon.c                  | 79 +++++++++++++++++++
 test/dm/Makefile                              |  1 +
 test/dm/syscon-reset.c                        | 58 ++++++++++++++
 8 files changed, 196 insertions(+)
 create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt
 create mode 100644 drivers/reset/reset-syscon.c
 create mode 100644 test/dm/syscon-reset.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index e529c54d8d..23f2aefd43 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -928,6 +928,21 @@
 	mdio: mdio-test {
 		compatible = "sandbox,mdio";
 	};
+
+	resetc2: syscon-reset {
+		compatible = "syscon-reset";
+		#reset-cells = <1>;
+		regmap = <&syscon0>;
+		offset = <1>;
+		mask = <0x27FFFFFF>;
+		assert-high = <0>;
+	};
+
+	syscon-reset-test {
+		compatible = "sandbox,misc_sandbox";
+		resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
+		reset-names = "valid", "no_mask", "out_of_range";
+	};
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index d8d8645425..19970f1db5 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -189,6 +189,7 @@ CONFIG_RAM=y
 CONFIG_REMOTEPROC_SANDBOX=y
 CONFIG_DM_RESET=y
 CONFIG_SANDBOX_RESET=y
+CONFIG_RESET_SYSCON=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y
 CONFIG_DEBUG_UART_SANDBOX=y
diff --git a/doc/device-tree-bindings/reset/syscon-reset.txt b/doc/device-tree-bindings/reset/syscon-reset.txt
new file mode 100644
index 0000000000..f136b3d225
--- /dev/null
+++ b/doc/device-tree-bindings/reset/syscon-reset.txt
@@ -0,0 +1,36 @@
+Generic SYSCON mapped register reset driver
+
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset and
+shifted by the reset specifier/
+
+To assert a reset on some device, the equivalent of the following operation is
+performed, where reset_id is the reset specifier from the device's resets
+property.
+
+	if (BIT(reset_id) & mask)
+		regmap[offset][reset_id] = assert-high;
+
+Required properties:
+- compatible: should contain "syscon-reset"
+- #reset-cells: must be 1
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+
+Optional properties:
+- mask: accept only the reset specifiers defined by the mask (32 bit)
+- assert-high: Bit to write when asserting a reset. Defaults to 1.
+
+Default will be little endian mode, 32 bit access only.
+
+Example:
+
+	reset-controller {
+		compatible = "syscon-reset";
+		#reset-cells = <1>;
+		regmap = <&sysctl>;
+		offset = <0x20>;
+		mask = <0x27FFFFFF>;
+		assert-high = <0>;
+	};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 75ccd65799..097bf32b21 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -148,4 +148,9 @@ config RESET_IMX7
 	help
 	  Support for reset controller on i.MX7/8 SoCs.
 
+config RESET_SYSCON
+	bool "Enable generic syscon reset driver support"
+	depends on DM_RESET
+	help
+	  Support generic syscon mapped register reset devices.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 0a044d5d8c..433f1eca54 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c
new file mode 100644
index 0000000000..37ca181981
--- /dev/null
+++ b/drivers/reset/reset-syscon.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson
+ */
+
+#include <dm.h>
+#include <linux/bitops.h>
+#include <regmap.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+
+struct syscon_reset_priv {
+	struct regmap *regmap;
+	uint offset;
+	uint mask;
+	bool assert_high;
+};
+
+static int syscon_reset_request(struct reset_ctl *rst)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+	if (BIT(rst->id) & priv->mask)
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int syscon_reset_assert(struct reset_ctl *rst)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+	return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+				  priv->assert_high ? BIT(rst->id) : 0);
+}
+
+static int syscon_reset_deassert(struct reset_ctl *rst)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+	return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+				  priv->assert_high ? 0 : BIT(rst->id));
+}
+
+static const struct reset_ops syscon_reset_ops = {
+	.request = syscon_reset_request,
+	.rst_assert = syscon_reset_assert,
+	.rst_deassert = syscon_reset_deassert,
+};
+
+int syscon_reset_probe(struct udevice *dev)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(dev);
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
+	if (IS_ERR(priv->regmap))
+		return -ENODEV;
+
+	priv->offset = dev_read_u32_default(dev, "offset", 0);
+	priv->mask = dev_read_u32_default(dev, "mask", 0);
+	priv->assert_high = dev_read_u32_default(dev, "assert-high", true);
+
+	return 0;
+}
+
+static const struct udevice_id syscon_reset_ids[] = {
+	{ .compatible = "syscon-reset" },
+	{ },
+};
+
+U_BOOT_DRIVER(syscon_reset) = {
+	.name = "syscon_reset",
+	.id = UCLASS_RESET,
+	.of_match = syscon_reset_ids,
+	.probe = syscon_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct syscon_reset_priv),
+	.ops = &syscon_reset_ops,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index dd1ceff86c..1f0e0febb4 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -70,4 +70,5 @@ obj-$(CONFIG_DMA) += dma.o
 obj-$(CONFIG_DM_MDIO) += mdio.o
 obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
 obj-$(CONFIG_DM_RNG) += rng.o
+obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
 endif
diff --git a/test/dm/syscon-reset.c b/test/dm/syscon-reset.c
new file mode 100644
index 0000000000..e9a36ba354
--- /dev/null
+++ b/test/dm/syscon-reset.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/test.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <test/ut.h>
+
+/* The following values must match the device tree */
+#define TEST_RESET_REG 1
+#define TEST_RESET_ASSERT_HIGH 0
+#define TEST_RESET_ASSERT (TEST_RESET_ASSERT_HIGH ? (u32)-1 : (u32)0)
+#define TEST_RESET_DEASSERT (~TEST_RESET_ASSERT)
+
+#define TEST_RESET_VALID 15
+#define TEST_RESET_NOMASK 30
+#define TEST_RESET_OUTOFRANGE 60
+
+static int dm_test_syscon_reset(struct unit_test_state *uts)
+{
+	struct regmap *map;
+	struct reset_ctl rst;
+	struct udevice *reset;
+	struct udevice *syscon;
+	struct udevice *syscon_reset;
+	uint reg;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "syscon-reset-test",
+					      &reset));
+	ut_assertok(uclass_get_device_by_name(UCLASS_SYSCON, "syscon at 0",
+					      &syscon));
+	ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "syscon-reset",
+					      &syscon_reset));
+	ut_assertok_ptr((map = syscon_get_regmap(syscon)));
+
+	ut_asserteq(-EINVAL, reset_get_by_name(reset, "no_mask", &rst));
+	ut_asserteq(-EINVAL, reset_get_by_name(reset, "out_of_range", &rst));
+	ut_assertok(reset_get_by_name(reset, "valid", &rst));
+
+	sandbox_set_enable_memio(true);
+	ut_assertok(regmap_write(map, TEST_RESET_REG, TEST_RESET_DEASSERT));
+	ut_assertok(reset_assert(&rst));
+	ut_assertok(regmap_read(map, TEST_RESET_REG, &reg));
+	ut_asserteq(TEST_RESET_DEASSERT ^ BIT(TEST_RESET_VALID), reg);
+
+	ut_assertok(reset_deassert(&rst));
+	ut_assertok(regmap_read(map, TEST_RESET_REG, &reg));
+	ut_asserteq(TEST_RESET_DEASSERT, reg);
+
+	return 0;
+}
+DM_TEST(dm_test_syscon_reset, DM_TESTF_SCAN_FDT);
-- 
2.25.0

[PATCH v4 05/17] dm: Add support for simple-pm-bus

[Sean Anderson]

This type of bus is used in Linux to designate busses which have power
domains and/or clocks which need to be enabled before their child devices
can be used.  Because power domains are automatically enabled before
probing in u-boot, we just need to enable any clocks present.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- Split the bus off into its own driver
- Add test
- Fix line spacing in Kconfig
- Lint

Changes in v3:
- New

 arch/sandbox/dts/test.dts                     |  6 ++
 arch/sandbox/include/asm/clk.h                |  1 +
 configs/sandbox_defconfig                     |  1 +
 .../bus/simple-pm-bus.txt                     | 44 +++++++++++++++
 drivers/core/Kconfig                          |  7 +++
 drivers/core/Makefile                         |  1 +
 drivers/core/simple-pm-bus.c                  | 55 +++++++++++++++++++
 test/dm/Makefile                              |  1 +
 test/dm/simple-pm-bus.c                       | 44 +++++++++++++++
 9 files changed, 160 insertions(+)
 create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt
 create mode 100644 drivers/core/simple-pm-bus.c
 create mode 100644 test/dm/simple-pm-bus.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 23f2aefd43..648f21239a 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -929,6 +929,12 @@
 		compatible = "sandbox,mdio";
 	};
 
+	pm-bus-test {
+		compatible = "simple-pm-bus";
+		clocks = <&clk_sandbox 4>;
+		power-domains = <&pwrdom 1>;
+	};
+
 	resetc2: syscon-reset {
 		compatible = "syscon-reset";
 		#reset-cells = <1>;
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index 1573e4a134..c184c4bffc 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -21,6 +21,7 @@ enum sandbox_clk_id {
 	SANDBOX_CLK_ID_I2C,
 	SANDBOX_CLK_ID_UART1,
 	SANDBOX_CLK_ID_UART2,
+	SANDBOX_CLK_ID_BUS,
 
 	SANDBOX_CLK_ID_COUNT,
 };
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 19970f1db5..c637b39b96 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -89,6 +89,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
+CONFIG_SIMPLE_PM_BUS=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_AXI=y
diff --git a/doc/device-tree-bindings/bus/simple-pm-bus.txt b/doc/device-tree-bindings/bus/simple-pm-bus.txt
new file mode 100644
index 0000000000..6f15037131
--- /dev/null
+++ b/doc/device-tree-bindings/bus/simple-pm-bus.txt
@@ -0,0 +1,44 @@
+Simple Power-Managed Bus
+========================
+
+A Simple Power-Managed Bus is a transparent bus that doesn't need a real
+driver, as it's typically initialized by the boot loader.
+
+However, its bus controller is part of a PM domain, or under the control of a
+functional clock.  Hence, the bus controller's PM domain and/or clock must be
+enabled for child devices connected to the bus (either on-SoC or externally)
+to function.
+
+While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
+in the Devicetree Specification, it is not an extension of "simple-bus".
+
+
+Required properties:
+  - compatible: Must contain at least "simple-pm-bus".
+		Must not contain "simple-bus".
+		It's recommended to let this be preceded by one or more
+		vendor-specific compatible values.
+  - #address-cells, #size-cells, ranges: Must describe the mapping between
+		parent address and child address spaces.
+
+Optional platform-specific properties for clock or PM domain control (at least
+one of them is required):
+  - clocks: Must contain a reference to the functional clock(s),
+  - power-domains: Must contain a reference to the PM domain.
+Please refer to the binding documentation for the clock and/or PM domain
+providers for more details.
+
+
+Example:
+
+	bsc: bus at fec10000 {
+		compatible = "renesas,bsc-sh73a0", "renesas,bsc",
+			     "simple-pm-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x20000000>;
+		reg = <0xfec10000 0x400>;
+		interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&zb_clk>;
+		power-domains = <&pd_a4s>;
+	};
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 3b95b5387b..0cd687526e 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -195,6 +195,13 @@ config SPL_SIMPLE_BUS
 	  Supports the 'simple-bus' driver, which is used on some systems
 	  in SPL.
 
+config SIMPLE_PM_BUS
+	bool "Support simple-pm-bus driver"
+	depends on DM && OF_CONTROL && CLK && POWER_DOMAIN
+	help
+	  Supports the 'simple-pm-bus' driver, which is used for busses that
+	  have power domains and/or clocks which need to be enabled before use.
+
 config OF_TRANSLATE
 	bool "Translate addresses using fdt_translate_address"
 	depends on DM && OF_CONTROL
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index bce7467da1..284af7caaa 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -6,6 +6,7 @@ obj-y	+= device.o fdtaddr.o lists.o root.o uclass.o util.o
 obj-$(CONFIG_DEVRES) += devres.o
 obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE)	+= device-remove.o
 obj-$(CONFIG_$(SPL_)SIMPLE_BUS)	+= simple-bus.o
+obj-$(CONFIG_SIMPLE_PM_BUS)	+= simple-pm-bus.o
 obj-$(CONFIG_DM)	+= dump.o
 obj-$(CONFIG_$(SPL_TPL_)REGMAP)	+= regmap.o
 obj-$(CONFIG_$(SPL_TPL_)SYSCON)	+= syscon-uclass.o
diff --git a/drivers/core/simple-pm-bus.c b/drivers/core/simple-pm-bus.c
new file mode 100644
index 0000000000..3ee54531d1
--- /dev/null
+++ b/drivers/core/simple-pm-bus.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <dm.h>
+#include <clk.h>
+
+/*
+ * Power domains are taken care of by driver_probe, so we just have to enable
+ * clocks
+ */
+static const int simple_pm_bus_probe(struct udevice *dev)
+{
+	int ret;
+	struct clk_bulk *bulk = dev_get_priv(dev);
+
+	ret = clk_get_bulk(dev, bulk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(bulk);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+		clk_release_bulk(bulk);
+		return ret;
+	}
+	return 0;
+}
+
+static const int simple_pm_bus_remove(struct udevice *dev)
+{
+	int ret;
+	struct clk_bulk *bulk = dev_get_priv(dev);
+
+	ret = clk_release_bulk(bulk);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+		return ret;
+	else
+		return 0;
+}
+
+static const struct udevice_id simple_pm_bus_ids[] = {
+	{ .compatible = "simple-pm-bus" },
+	{ }
+};
+
+U_BOOT_DRIVER(simple_pm_bus_drv) = {
+	.name	= "simple_pm_bus",
+	.id	= UCLASS_SIMPLE_BUS,
+	.of_match = simple_pm_bus_ids,
+	.probe = simple_pm_bus_probe,
+	.remove = simple_pm_bus_remove,
+	.priv_auto_alloc_size = sizeof(struct clk_bulk),
+	.flags	= DM_FLAG_PRE_RELOC,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 1f0e0febb4..a760ab8b14 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -71,4 +71,5 @@ obj-$(CONFIG_DM_MDIO) += mdio.o
 obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
 obj-$(CONFIG_DM_RNG) += rng.o
 obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
+obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
 endif
diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c
new file mode 100644
index 0000000000..1b42415ccd
--- /dev/null
+++ b/test/dm/simple-pm-bus.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <asm/clk.h>
+#include <asm/power-domain.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <dm/device-internal.h>
+#include <test/ut.h>
+
+/* These must match the ids in the device tree */
+#define TEST_CLOCK_ID 4
+#define TEST_POWER_ID 1
+
+static int dm_test_simple_pm_bus(struct unit_test_state *uts)
+{
+	struct udevice *power;
+	struct udevice *clock;
+	struct udevice *bus;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN,
+					      "power-domain", &power));
+	ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
+					      &clock));
+	ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID));
+	ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, "pm-bus-test",
+					      &bus));
+	ut_asserteq(1, sandbox_power_domain_query(power, TEST_POWER_ID));
+	ut_asserteq(1, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
+
+	ut_assertok(device_remove(bus, DM_REMOVE_NORMAL));
+	/* must re-probe since device_remove also removes the power domain */
+	ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN,
+					      "power-domain", &power));
+	ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID));
+	ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
+
+	return 0;
+}
+DM_TEST(dm_test_simple_pm_bus, DM_TESTF_SCAN_FDT);
-- 
2.25.0

[PATCH v4 06/17] spi: dw: Add device tree properties for fields in CTRL1

[Sean Anderson]

Some devices have different layouts for the fields in CTRL1 (e.g. the
Kendryte K210). Allow this layout to be configurable from the device tree.
The documentation has been taken from Linux.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- New

 .../spi/snps,dw-apb-ssi.txt                   | 43 +++++++++++++++++++
 drivers/spi/designware_spi.c                  | 40 ++++++++++-------
 2 files changed, 68 insertions(+), 15 deletions(-)
 create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt

diff --git a/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
new file mode 100644
index 0000000000..4b6152f6b7
--- /dev/null
+++ b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
@@ -0,0 +1,43 @@
+Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
+
+Required properties:
+- compatible : "snps,dw-apb-ssi"
+- reg : The register base for the controller. For "mscc,<soc>-spi", a second
+  register set is required (named ICPU_CFG:SPI_MST)
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+- clocks : phandles for the clocks, see the description of clock-names below.
+   The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
+   is optional. If a single clock is specified but no clock-name, it is the
+   "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
+
+Optional properties:
+- clock-names : Contains the names of the clocks:
+    "ssi_clk", for the core clock used to generate the external SPI clock.
+    "pclk", the interface clock, required for register access.
+- cs-gpios : Specifies the gpio pins to be used for chipselects.
+- num-cs : The number of chipselects. If omitted, this will default to 4.
+- reg-io-width : The I/O register width (in bytes) implemented by this
+  device.  Supported values are 2 or 4 (the default).
+- snps,dfs-offset The offset in bits of the DFS field in CTRL0, defaulting to 0
+- snps,frf-offset The offset in bits of the FRF field in CTRL0, defaulting to 4
+- snps,tmod-offset The offset in bits of the tmode field in CTRL0, defaulting
+  to 6
+- snps,mode-offset The offset in bits of the work mode field in CTRL0,
+  defaulting to 8
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+	spi at fff00000 {
+		compatible = "snps,dw-apb-ssi";
+		reg = <0xfff00000 0x1000>;
+		interrupts = <0 154 4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&spi_m_clk>;
+		num-cs = <2>;
+		cs-gpios = <&gpio0 13 0>,
+			   <&gpio0 14 0>;
+	};
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 66ff8eeccd..04cc873754 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -3,6 +3,7 @@
  * Designware master SPI core controller driver
  *
  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
  *
  * Very loosely based on the Linux driver:
  * drivers/spi/spi-dw.c, which is:
@@ -50,20 +51,14 @@
 #define DW_SPI_DR			0x60
 
 /* Bit fields in CTRLR0 */
-#define SPI_DFS_OFFSET			0
-
-#define SPI_FRF_OFFSET			4
 #define SPI_FRF_SPI			0x0
 #define SPI_FRF_SSP			0x1
 #define SPI_FRF_MICROWIRE		0x2
 #define SPI_FRF_RESV			0x3
 
-#define SPI_MODE_OFFSET			6
-#define SPI_SCPH_OFFSET			6
-#define SPI_SCOL_OFFSET			7
+#define SPI_MODE_SCPH			0x1
+#define SPI_MODE_SCOL			0x2
 
-#define SPI_TMOD_OFFSET			8
-#define SPI_TMOD_MASK			(0x3 << SPI_TMOD_OFFSET)
 #define	SPI_TMOD_TR			0x0		/* xmit & recv */
 #define SPI_TMOD_TO			0x1		/* xmit only */
 #define SPI_TMOD_RO			0x2		/* recv only */
@@ -88,6 +83,12 @@
 struct dw_spi_platdata {
 	s32 frequency;		/* Default clock frequency, -1 for none */
 	void __iomem *regs;
+
+	/* Offsets in CTRL0 */
+	u8 dfs_off;
+	u8 frf_off;
+	u8 tmod_off;
+	u8 mode_off;
 };
 
 struct dw_spi_priv {
@@ -114,6 +115,15 @@ struct dw_spi_priv {
 	struct reset_ctl_bulk	resets;
 };
 
+static inline u32 GEN_CTRL0(struct dw_spi_priv *priv,
+			    struct dw_spi_platdata *plat)
+{
+	return ((priv->bits_per_word - 1) << plat->dfs_off |
+	      (priv->type << plat->frf_off) |
+	      (priv->mode << plat->mode_off) |
+	      (priv->tmode << plat->tmod_off));
+}
+
 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
 {
 	return __raw_readl(priv->regs + offset);
@@ -159,6 +169,10 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
 	/* Use 500KHz as a suitable default */
 	plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
 					       500000);
+	plat->dfs_off = dev_read_u32_default(bus, "snps,dfs-offset", 0);
+	plat->frf_off = dev_read_u32_default(bus, "snps,frf-offset", 4);
+	plat->mode_off = dev_read_u32_default(bus, "snps,mode-offset", 6);
+	plat->tmod_off = dev_read_u32_default(bus, "snps,tmod-offset", 8);
 	debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
 	      plat->frequency);
 
@@ -387,6 +401,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		       const void *dout, void *din, unsigned long flags)
 {
 	struct udevice *bus = dev->parent;
+	struct dw_spi_platdata *plat = dev_get_platdata(bus);
 	struct dw_spi_priv *priv = dev_get_priv(bus);
 	const u8 *tx = dout;
 	u8 *rx = din;
@@ -405,10 +420,6 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	if (flags & SPI_XFER_BEGIN)
 		external_cs_manage(dev, false);
 
-	cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
-		(priv->mode << SPI_MODE_OFFSET) |
-		(priv->tmode << SPI_TMOD_OFFSET);
-
 	if (rx && tx)
 		priv->tmode = SPI_TMOD_TR;
 	else if (rx)
@@ -420,8 +431,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		 */
 		priv->tmode = SPI_TMOD_TR;
 
-	cr0 &= ~SPI_TMOD_MASK;
-	cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
+	cr0 = GEN_CTRL0(priv, plat);
 
 	priv->len = bitlen >> 3;
 	debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
@@ -475,7 +485,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
 static int dw_spi_set_speed(struct udevice *bus, uint speed)
 {
-	struct dw_spi_platdata *plat = bus->platdata;
+	struct dw_spi_platdata *plat = dev_get_platdata(bus);
 	struct dw_spi_priv *priv = dev_get_priv(bus);
 	u16 clk_div;
 
-- 
2.25.0

[PATCH v4 07/17] spi: dw: Add mem_ops

[Sean Anderson]

The dw spi devices on the Kendryte K210 must be operated in a specific
fasion which cannot be achived through multiple writes to via dw_spi_xfer
(as it is currently written). This patch adds an implementation of exec_op,
which gives correct behaviour when reading/writing spi flash.

I would like to be able to modify the existing dw_spi_xfer function such
that it works properly (e.g. with the mmc_spi driver). However, the only
example code I have to work off is Kendryte's sdk (which is written in the
exec_op style), and I do not have access to the datasheet (if anyone does,
I would love to have a look!).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- New

 drivers/spi/designware_spi.c | 123 +++++++++++++++++++++++++++++++++--
 1 file changed, 119 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 04cc873754..277eb19a0b 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -17,6 +17,7 @@
 #include <errno.h>
 #include <malloc.h>
 #include <spi.h>
+#include <spi-mem.h>
 #include <fdtdec.h>
 #include <reset.h>
 #include <linux/compat.h>
@@ -107,8 +108,8 @@ struct dw_spi_priv {
 	int len;
 
 	u32 fifo_len;		/* depth of the FIFO buffer */
-	void *tx;
-	void *tx_end;
+	const void *tx;
+	const void *tx_end;
 	void *rx;
 	void *rx_end;
 
@@ -344,7 +345,7 @@ static void dw_writer(struct dw_spi_priv *priv)
 				txw = *(u16 *)(priv->tx);
 		}
 		dw_write(priv, DW_SPI_DR, txw);
-		debug("%s: tx=0x%02x\n", __func__, txw);
+		log_io("tx=0x%02x\n", txw);
 		priv->tx += priv->bits_per_word >> 3;
 	}
 }
@@ -356,7 +357,7 @@ static void dw_reader(struct dw_spi_priv *priv)
 
 	while (max--) {
 		rxw = dw_read(priv, DW_SPI_DR);
-		debug("%s: rx=0x%02x\n", __func__, rxw);
+		log_io("rx=0x%02x\n", rxw);
 
 		/* Care about rx if the transfer's original "rx" is not null */
 		if (priv->rx_end - priv->len) {
@@ -483,6 +484,115 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	return ret;
 }
 
+static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+	bool read = op->data.dir == SPI_MEM_DATA_IN;
+	int pos, i, ret = 0;
+	struct udevice *bus = slave->dev->parent;
+	struct dw_spi_platdata *plat = dev_get_platdata(bus);
+	struct dw_spi_priv *priv = dev_get_priv(bus);
+	u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+	u8 op_buf[op_len];
+	u32 cr0;
+
+	if (read)
+		priv->tmode = SPI_TMOD_EPROMREAD;
+	else
+		priv->tmode = SPI_TMOD_TO;
+
+	debug("%s: buf=%p len=%u [bytes]\n",
+	      __func__, op->data.buf.in, op->data.nbytes);
+
+	cr0 = GEN_CTRL0(priv, plat);
+	debug("%s: cr0=%08x\n", __func__, cr0);
+
+	spi_enable_chip(priv, 0);
+	dw_write(priv, DW_SPI_CTRL0, cr0);
+	if (read)
+		dw_write(priv, DW_SPI_CTRL1, op->data.nbytes - 1);
+	spi_enable_chip(priv, 1);
+
+	/* From spi_mem_exec_op */
+	pos = 0;
+	op_buf[pos++] = op->cmd.opcode;
+	if (op->addr.nbytes) {
+		for (i = 0; i < op->addr.nbytes; i++)
+			op_buf[pos + i] = op->addr.val >>
+				(8 * (op->addr.nbytes - i - 1));
+
+		pos += op->addr.nbytes;
+	}
+	if (op->dummy.nbytes)
+		memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+	priv->tx = &op_buf;
+	priv->tx_end = priv->tx + op_len;
+	while (priv->tx != priv->tx_end)
+		dw_writer(priv);
+
+	/*
+	 * XXX: The following are tight loops! Enabling debug messages may cause
+	 * them to fail because we are not reading/writing the fifo fast enough.
+	 *
+	 * We heuristically break out of the loop when we stop getting data.
+	 * This is to stop us from hanging if the device doesn't send any data
+	 * (either at all, or after sending a response). For example, one flash
+	 * chip I tested did not send anything back after the first 64K of data.
+	 */
+	if (read) {
+		/* If we have gotten any data back yet */
+		bool got_data = false;
+		/* How many times we have looped without reading anything */
+		int loops_since_read = 0;
+		struct spi_mem_op *mut_op = (struct spi_mem_op *)op;
+
+		priv->rx = op->data.buf.in;
+		priv->rx_end = priv->rx + op->data.nbytes;
+
+		dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
+		while (priv->rx != priv->rx_end) {
+			void *last_rx = priv->rx;
+
+			dw_reader(priv);
+			if (priv->rx == last_rx) {
+				loops_since_read++;
+				/* Thresholds are arbitrary */
+				if (loops_since_read > 256)
+					break;
+				else if (got_data && loops_since_read > 32)
+					break;
+			} else {
+				got_data = true;
+				loops_since_read = 0;
+			}
+		}
+
+		/* Update with the actual amount of data read */
+		mut_op->data.nbytes -= priv->rx_end - priv->rx;
+	} else {
+		u32 val;
+
+		priv->tx = op->data.buf.out;
+		priv->tx_end = priv->tx + op->data.nbytes;
+
+		/* Fill up the write fifo before starting the transfer */
+		dw_writer(priv);
+		dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
+		while (priv->tx != priv->tx_end)
+			dw_writer(priv);
+
+		if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
+				       (val & SR_TF_EMPT) && !(val & SR_BUSY),
+				       RX_TIMEOUT * 1000)) {
+			ret = -ETIMEDOUT;
+		}
+	}
+
+	dw_write(priv, DW_SPI_SER, 0);
+	debug("%s: %u bytes xfered\n", __func__, op->data.nbytes);
+	return ret;
+}
+
 static int dw_spi_set_speed(struct udevice *bus, uint speed)
 {
 	struct dw_spi_platdata *plat = dev_get_platdata(bus);
@@ -546,8 +656,13 @@ static int dw_spi_remove(struct udevice *bus)
 	return 0;
 }
 
+static const struct spi_controller_mem_ops dw_spi_mem_ops = {
+	.exec_op = dw_spi_exec_op,
+};
+
 static const struct dm_spi_ops dw_spi_ops = {
 	.xfer		= dw_spi_xfer,
+	.mem_ops	= &dw_spi_mem_ops,
 	.set_speed	= dw_spi_set_speed,
 	.set_mode	= dw_spi_set_mode,
 	/*
-- 
2.25.0

[PATCH v4 08/17] riscv: Add headers for asm/global_data.h

[Sean Anderson]

This header depended on bd_t and ulong, but did not include the appropriate
headers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- Include compiler.h not linux/compiler.h

 arch/riscv/include/asm/global_data.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index b74bd7e738..7276d9763f 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -11,6 +11,8 @@
 #define __ASM_GBL_DATA_H
 
 #include <asm/smp.h>
+#include <asm/u-boot.h>
+#include <compiler.h>
 
 /* Architecture-specific global data */
 struct arch_global_data {
-- 
2.25.0

[PATCH v4 09/17] riscv: Add option to support RISC-V privileged spec 1.9.1

[Sean Anderson]

Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs.  Using the new CSR on an old processor causes an illegal
instruction exception.  This patch adds an option to use the old CSRs
instead of the new one.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- Fixed CSRs not being defined properly (thanks bmeng)
- Added ifdefs for all changed CSRs (e.g. for VM)
- Also properly disable VM on boot

Changes in v3:
- Renamed from "riscv: Add option to disable writes to mcounteren"
- Added original functionality back for older priv specs.

Changes in v2:
- Moved forward in the patch series

 arch/riscv/Kconfig           | 10 +++++++++
 arch/riscv/cpu/cpu.c         |  9 ++++++++
 arch/riscv/include/asm/csr.h | 40 ++++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3338b788f8..659d98e33d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -225,6 +225,16 @@ config XIP
 config SHOW_REGS
 	bool "Show registers on unhandled exception"
 
+config RISCV_PRIV_1_9_1
+	bool "Use version 1.9.1 of the RISC-V priviledged specification"
+	help
+	  Older versions of the RISC-V priviledged specification had
+	  separate counter enable CSRs for each privilege mode. Writing
+	  to the unified mcounteren CSR on a processor implementing the
+	  old specification will result in an illegal instruction
+	  exception. In addition to counter CSR changes, the way virtual
+	  memory is configured was also changed.
+
 config STACK_SIZE_SHIFT
 	int
 	default 14
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e457f6acbf..1df2753edb 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -89,11 +89,20 @@ int arch_cpu_init_dm(void)
 		 * Enable perf counters for cycle, time,
 		 * and instret counters only
 		 */
+#ifdef CONFIG_RISCV_PRIV_1_9_1
+		csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+		csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
 		csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
 
 		/* Disable paging */
 		if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9_1
+			csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
 			csr_write(CSR_SATP, 0);
+#endif
 	}
 
 	return 0;
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index d1520743a2..b02accdc34 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -15,7 +15,11 @@
 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
+#ifdef CONFIG_RISCV_PRIV_1_9_1
+#define SR_PUM		_AC(0x00040000, UL) /* Protect User Memory Access */
+#else
 #define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
+#endif
 
 #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
 #define SR_FS_OFF	_AC(0x00000000, UL)
@@ -29,6 +33,22 @@
 #define SR_XS_CLEAN	_AC(0x00010000, UL)
 #define SR_XS_DIRTY	_AC(0x00018000, UL)
 
+#ifdef CONFIG_RISCV_PRIV_1_9_1
+#define SR_VM		_AC(0x1F000000, UL) /* Virtualization Management */
+#define SR_VM_MODE_BARE	_AC(0x00000000, UL) /* No translation or protection */
+#define SR_VM_MODE_BB	_AC(0x01000000, UL) /* Single base-and-bound */
+#define SR_VM_MODE_BBID	_AC(0x02000000, UL) /* Separate instruction and
+					       data base-and-bound */
+#ifndef CONFIG_64BIT
+#define SR_VM_MODE_32	_AC(0x08000000, UL)
+#define SR_VM_MODE	SR_VM_MODE_32
+#else
+#define SR_VM_MODE_39	_AC(0x09000000, UL)
+#define SR_VM_MODE_48	_AC(0x0A000000, UL)
+#define SR_VM_MODE	SR_VM_MODE_39
+#endif
+#endif
+
 #ifndef CONFIG_64BIT
 #define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
 #else
@@ -36,6 +56,7 @@
 #endif
 
 /* SATP flags */
+#ifndef CONFIG_RISCV_PRIV_1_9_1
 #ifndef CONFIG_64BIT
 #define SATP_PPN	_AC(0x003FFFFF, UL)
 #define SATP_MODE_32	_AC(0x80000000, UL)
@@ -45,6 +66,7 @@
 #define SATP_MODE_39	_AC(0x8000000000000000, UL)
 #define SATP_MODE	SATP_MODE_39
 #endif
+#endif
 
 /* SCAUSE */
 #define SCAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
@@ -88,17 +110,35 @@
 #define CSR_SCAUSE		0x142
 #define CSR_STVAL		0x143
 #define CSR_SIP			0x144
+#ifdef CONFIG_RISCV_PRIV_1_9_1
+#define CSR_SPTBR		0x180
+#else
 #define CSR_SATP		0x180
+#endif
 #define CSR_MSTATUS		0x300
 #define CSR_MISA		0x301
 #define CSR_MIE			0x304
 #define CSR_MTVEC		0x305
+#ifdef CONFIG_RISCV_PRIV_1_9_1
+#define CSR_MUCOUNTEREN         0x320
+#define CSR_MSCOUNTEREN         0x321
+#define CSR_MHCOUNTEREN         0x322
+#else
 #define CSR_MCOUNTEREN		0x306
+#endif
 #define CSR_MSCRATCH		0x340
 #define CSR_MEPC		0x341
 #define CSR_MCAUSE		0x342
 #define CSR_MTVAL		0x343
 #define CSR_MIP			0x344
+#ifdef CONFIG_RISCV_PRIV_1_9_1
+#define CSR_MBASE		0x380
+#define CSR_MBOUND		0x381
+#define CSR_MIBASE		0x382
+#define CSR_MIBOUND		0x383
+#define CSR_MDBASE		0x384
+#define CSR_MDBOUND		0x385
+#endif
 #define CSR_CYCLEH		0xc80
 #define CSR_TIMEH		0xc81
 #define CSR_INSTRETH		0xc82
-- 
2.25.0

[PATCH v4 10/17] riscv: Allow use of reset drivers

[Sean Anderson]

Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- New

 arch/riscv/lib/reset.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
index b8cecb309d..6cf6387f10 100644
--- a/arch/riscv/lib/reset.c
+++ b/arch/riscv/lib/reset.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <command.h>
 
+#ifndef CONFIG_SYSRESET
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	printf("resetting ...\n");
@@ -15,3 +16,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	return 0;
 }
+#endif
-- 
2.25.0

[PATCH v4 11/17] riscv: Add K210 pll support

[Sean Anderson]

This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_params is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- Rename the reference clock to "divider clock", and input clock to "reference
  clock" to match the upstream documentation.
- Add a test for calc_params. This currently resides in test/dm, but perhaps it
  should be moved to its own directory.
- Update MAINTAINERS
- Update copyright
- Lint

Changes in v3:
- Add an option to not include support for setting the pll rate. This saves
  around 1K in the final executable.
- Remove udelays to suppress warnings
- Bypass PLL after enabling, instead of before
- Check if the PLL is enabled already before doing a reset
- Fix bug with locked mask

Changes in v2:
- Rename driver to "k210_clk_pll"
- Add additional in-line documentation on algorithm and PLLs
- Restrict the range of internal VCO and reference frequencies
- Don't load driver before relocation
- Remove spurious references to mach-k210

 MAINTAINERS                   |   6 +
 drivers/clk/Kconfig           |   1 +
 drivers/clk/Makefile          |   1 +
 drivers/clk/kendryte/Kconfig  |  12 +
 drivers/clk/kendryte/Makefile |   1 +
 drivers/clk/kendryte/pll.c    | 604 ++++++++++++++++++++++++++++++++++
 include/kendryte/pll.h        |  57 ++++
 include/test/export.h         |  16 +
 test/dm/Makefile              |   1 +
 test/dm/k210_pll.c            |  95 ++++++
 10 files changed, 794 insertions(+)
 create mode 100644 drivers/clk/kendryte/Kconfig
 create mode 100644 drivers/clk/kendryte/Makefile
 create mode 100644 drivers/clk/kendryte/pll.c
 create mode 100644 include/kendryte/pll.h
 create mode 100644 include/test/export.h
 create mode 100644 test/dm/k210_pll.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 438fb225ab..60bdf41ab7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -781,6 +781,12 @@ F:	arch/riscv/
 F:	cmd/riscv/
 F:	tools/prelink-riscv.c
 
+RISC-V KENDRYTE
+M:	Sean Anderson <seanga2@gmail.com>
+S:	Maintained
+F:	drivers/clk/kendryte/
+F:	include/kendryte/
+
 ROCKUSB
 M:	Eddie Cai <eddie.cai.linux@gmail.com>
 S:	Maintained
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 16d4237f89..af75c7c4cf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -145,6 +145,7 @@ source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/imx/Kconfig"
+source "drivers/clk/kendryte/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 06131edb9f..4f3893f6fc 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_K210) += kendryte/
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
new file mode 100644
index 0000000000..7b69c8afaf
--- /dev/null
+++ b/drivers/clk/kendryte/Kconfig
@@ -0,0 +1,12 @@
+config CLK_K210
+	bool "Clock support for Kendryte K210"
+	depends on CLK && CLK_CCF
+	help
+	  This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+	bool "Enable setting the Kendryte K210 PLL rate"
+	depends on CLK_K210
+	help
+	  Add functionality to calculate new rates for K210 PLLs. Enabling this
+	  feature adds around 1K to U-Boot's final size.
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
new file mode 100644
index 0000000000..c56d93ea1c
--- /dev/null
+++ b/drivers/clk/kendryte/Makefile
@@ -0,0 +1 @@
+obj-y += pll.o
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
new file mode 100644
index 0000000000..c554f9c419
--- /dev/null
+++ b/drivers/clk/kendryte/pll.c
@@ -0,0 +1,604 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+#include <kendryte/pll.h>
+
+#define LOG_CATEGORY UCLASS_CLK
+#include <asm/io.h>
+/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
+#include <div64.h>
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <log.h>
+#include <serial.h>
+
+#define CLK_K210_PLL "k210_clk_pll"
+
+#ifdef CONFIG_CLK_K210_SET_RATE
+static int k210_pll_enable(struct clk *clk);
+static int k210_pll_disable(struct clk *clk);
+
+/*
+ * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
+ * General-Purpose PLL. The logical layout of the PLL with internal feedback is
+ * approximately the following:
+ *
+ *  +---------------+
+ *  |reference clock|
+ *  +---------------+
+ *          |
+ *          v
+ *        +--+
+ *        |/r|
+ *        +--+
+ *          |
+ *          v
+ *   +-------------+
+ *   |divided clock|
+ *   +-------------+
+ *          |
+ *          v
+ *  +--------------+
+ *  |phase detector|<---+
+ *  +--------------+    |
+ *          |           |
+ *          v   +--------------+
+ *        +---+ |feedback clock|
+ *        |VCO| +--------------+
+ *        +---+         ^
+ *          |    +--+   |
+ *          +--->|/f|---+
+ *          |    +--+
+ *          v
+ *        +---+
+ *        |/od|
+ *        +---+
+ *          |
+ *          v
+ *       +------+
+ *       |output|
+ *       +------+
+ *
+ * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
+ * the effect of the division by f is to multiply the input frequency. The
+ * equation for the output rate is
+ *   rate = (rate_in * f) / (r * od).
+ * Moving knowns to one side of the equation, we get
+ *   rate / rate_in = f / (r * od)
+ * Rearranging slightly,
+ *   abs_error = abs((rate / rate_in) - (f / (r * od))).
+ * To get relative, error, we divide by the expected ratio
+ *   error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
+ * Simplifying,
+ *   error = abs(1 - f / (r * od)) / (rate / rate_in)
+ *   error = abs(1 - (f * rate_in) / (r * od * rate))
+ * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
+ *   error = abs((f * inv_ratio) / (r * od) - 1)
+ * This is the error used in evaluating parameters.
+ *
+ * r and od are four bits each, while f is six bits. Because r and od are
+ * multiplied together, instead of the full 256 values possible if both bits
+ * were used fully, there are only 97 distinct products. Combined with f, there
+ * are 6208 theoretical settings for the PLL. However, most of these settings
+ * can be ruled out immediately because they do not have the correct ratio.
+ *
+ * In addition to the constraint of approximating the desired ratio, parameters
+ * must also keep internal pll frequencies within acceptable ranges. The divided
+ * clock's minimum and maximum frequencies have a ratio of around 128.  This
+ * leaves fairly substantial room to work with, especially since the only
+ * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
+ * of 5, which is considerably more restrictive.
+ *
+ * The r and od factors are stored in a table. This is to make it easy to find
+ * the next-largest product. Some products have multiple factorizations, but
+ * only when one factor has at least a 2.5x ratio to the factors of the other
+ * factorization. This is because any smaller ratio would not make a difference
+ * when ensuring the VCO's frequency is within spec.
+ *
+ * Throughout the calculation function, fixed point arithmetic is used. Because
+ * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
+ * 32.32 fixed-point numbers are used to represent ratios. In general, to
+ * implement division, the numerator is first multiplied by 2^32. This gives a
+ * result where the whole number part is in the upper 32 bits, and the fraction
+ * is in the lower 32 bits.
+ *
+ * In general, rounding is done to the closest integer. This helps find the best
+ * approximation for the ratio. Rounding in one direction (e.g down) could cause
+ * the function to miss a better ratio with one of the parameters increased by
+ * one.
+ */
+
+/*
+ * The factors table was generated with the following python code:
+ *
+ * def p(x, y):
+ *    return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
+ *
+ * factors = {}
+ * for i in range(1, 17):
+ *    for j in range(1, 17):
+ *       fs = factors.get(i*j) or []
+ *       if fs == [] or all([
+ *             (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
+ *             for (x, y) in fs]):
+ *          fs.append((i, j))
+ *          factors[i*j] = fs
+ *
+ * for k, l in sorted(factors.items()):
+ *    for v in l:
+ *       print("PACK(%s, %s)," % v)
+ */
+#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
+#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
+#define UNPACK_OD(val) (((val) & 0xF) + 1)
+static const u8 factors[] = {
+	PACK(1, 1),
+	PACK(1, 2),
+	PACK(1, 3),
+	PACK(1, 4),
+	PACK(1, 5),
+	PACK(1, 6),
+	PACK(1, 7),
+	PACK(1, 8),
+	PACK(1, 9),
+	PACK(3, 3),
+	PACK(1, 10),
+	PACK(1, 11),
+	PACK(1, 12),
+	PACK(3, 4),
+	PACK(1, 13),
+	PACK(1, 14),
+	PACK(1, 15),
+	PACK(3, 5),
+	PACK(1, 16),
+	PACK(4, 4),
+	PACK(2, 9),
+	PACK(2, 10),
+	PACK(3, 7),
+	PACK(2, 11),
+	PACK(2, 12),
+	PACK(5, 5),
+	PACK(2, 13),
+	PACK(3, 9),
+	PACK(2, 14),
+	PACK(2, 15),
+	PACK(2, 16),
+	PACK(3, 11),
+	PACK(5, 7),
+	PACK(3, 12),
+	PACK(3, 13),
+	PACK(4, 10),
+	PACK(3, 14),
+	PACK(4, 11),
+	PACK(3, 15),
+	PACK(3, 16),
+	PACK(7, 7),
+	PACK(5, 10),
+	PACK(4, 13),
+	PACK(6, 9),
+	PACK(5, 11),
+	PACK(4, 14),
+	PACK(4, 15),
+	PACK(7, 9),
+	PACK(4, 16),
+	PACK(5, 13),
+	PACK(6, 11),
+	PACK(5, 14),
+	PACK(6, 12),
+	PACK(5, 15),
+	PACK(7, 11),
+	PACK(6, 13),
+	PACK(5, 16),
+	PACK(9, 9),
+	PACK(6, 14),
+	PACK(8, 11),
+	PACK(6, 15),
+	PACK(7, 13),
+	PACK(6, 16),
+	PACK(7, 14),
+	PACK(9, 11),
+	PACK(10, 10),
+	PACK(8, 13),
+	PACK(7, 15),
+	PACK(9, 12),
+	PACK(10, 11),
+	PACK(7, 16),
+	PACK(9, 13),
+	PACK(8, 15),
+	PACK(11, 11),
+	PACK(9, 14),
+	PACK(8, 16),
+	PACK(10, 13),
+	PACK(11, 12),
+	PACK(9, 15),
+	PACK(10, 14),
+	PACK(11, 13),
+	PACK(9, 16),
+	PACK(10, 15),
+	PACK(11, 14),
+	PACK(12, 13),
+	PACK(10, 16),
+	PACK(11, 15),
+	PACK(12, 14),
+	PACK(13, 13),
+	PACK(11, 16),
+	PACK(12, 15),
+	PACK(13, 14),
+	PACK(12, 16),
+	PACK(13, 15),
+	PACK(14, 14),
+	PACK(13, 16),
+	PACK(14, 15),
+	PACK(14, 16),
+	PACK(15, 15),
+	PACK(15, 16),
+	PACK(16, 16),
+};
+
+TEST_STATIC int k210_pll_calc_params(u32 rate, u32 rate_in,
+				     struct k210_pll_params *best)
+{
+	int i;
+	s64 error, best_error;
+	u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
+	u64 max_r;
+	u64 r, f, od;
+
+	/*
+	 * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
+	 * VCO frequency. These are not the same limits as below because od can
+	 * reduce the output frequency by 16.
+	 */
+	if (rate > 1750000000 || rate < 21250000)
+		return -EINVAL;
+
+	/* Similar restrictions on the input rate */
+	if (rate_in > 1750000000 || rate_in < 13300000)
+		return -EINVAL;
+
+	ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
+	inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
+	/* Can't increase by more than 64 or reduce by more than 256 */
+	if (rate > rate_in && ratio > (64ULL << 32))
+		return -EINVAL;
+	else if (rate <= rate_in && inv_ratio > (256ULL << 32))
+		return -EINVAL;
+
+	/*
+	 * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
+	 * MHz. There is no minimum, since the only way to get a higher input
+	 * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
+	 * cannot output frequencies greater than 1.75 GHz, the minimum would
+	 * never be greater than one.
+	 */
+	max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
+
+	/* Variables get immediately incremented, so start at -1th iteration */
+	i = -1;
+	f = 0;
+	r = 0;
+	od = 0;
+	error = best_error = S64_MAX;
+	/* do-while here so we always try@least one ratio */
+	do {
+		/*
+		 * Whether we swapped r and od while enforcing frequency limits
+		 */
+		bool swapped = false;
+		u64 last_od = od;
+		u64 last_r = r;
+
+		/*
+		 * Try the next largest value for f (or r and od) and
+		 * recalculate the other parameters based on that
+		 */
+		if (rate > rate_in) {
+			/*
+			 * Skip factors of the same product if we already tried
+			 * out that product
+			 */
+			do {
+				i++;
+				r = UNPACK_R(factors[i]);
+				od = UNPACK_OD(factors[i]);
+			} while (i + 1 < ARRAY_SIZE(factors) &&
+				 r * od == last_r * last_od);
+
+			/* Round close */
+			f = (r * od * ratio + BIT(31)) >> 32;
+			if (f > 64)
+				f = 64;
+		} else {
+			u64 tmp = ++f * inv_ratio;
+			bool round_up = !!(tmp & BIT(31));
+			u32 goal = (tmp >> 32) + round_up;
+			u32 err, last_err;
+
+			/* Get the next r/od pair in factors */
+			while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
+				i++;
+				r = UNPACK_R(factors[i]);
+				od = UNPACK_OD(factors[i]);
+			}
+
+			/*
+			 * This is a case of double rounding. If we rounded up
+			 * above, we need to round down (in cases of ties) here.
+			 * This prevents off-by-one errors resulting from
+			 * choosing X+2 over X when X.Y rounds up to X+1 and
+			 * there is no r * od = X+1. For the converse, when X.Y
+			 * is rounded down to X, we should choose X+1 over X-1.
+			 */
+			err = abs(r * od - goal);
+			last_err = abs(last_r * last_od - goal);
+			if (last_err < err || (round_up && last_err == err)) {
+				i--;
+				r = last_r;
+				od = last_od;
+			}
+		}
+
+		/*
+		 * Enforce limits on internal clock frequencies. If we
+		 * aren't in spec, try swapping r and od. If everything is
+		 * in-spec, calculate the relative error.
+		 */
+		while (true) {
+			/*
+			 * Whether the intermediate frequencies are out-of-spec
+			 */
+			bool out_of_spec = false;
+
+			if (r > max_r) {
+				out_of_spec = true;
+			} else {
+				/*
+				 * There is no way to only divide once; we need
+				 * to examine the frequency with and without the
+				 * effect of od.
+				 */
+				u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
+
+				if (vco > 1750000000 || vco < 340000000)
+					out_of_spec = true;
+			}
+
+			if (out_of_spec) {
+				if (!swapped) {
+					u64 tmp = r;
+
+					r = od;
+					od = tmp;
+					swapped = true;
+					continue;
+				} else {
+					/*
+					 * Try looking ahead to see if there are
+					 * additional factors for the same
+					 * product.
+					 */
+					if (i + 1 < ARRAY_SIZE(factors)) {
+						u64 new_r, new_od;
+
+						i++;
+						new_r = UNPACK_R(factors[i]);
+						new_od = UNPACK_OD(factors[i]);
+						if (r * od == new_r * new_od) {
+							r = new_r;
+							od = new_od;
+							swapped = false;
+							continue;
+						}
+						i--;
+					}
+					break;
+				}
+			}
+
+			error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
+			/* The lower 16 bits are spurious */
+			error = abs((error - BIT(32))) >> 16;
+
+			if (error < best_error) {
+				best->r = r;
+				best->f = f;
+				best->od = od;
+				best_error = error;
+			}
+			break;
+		}
+	} while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
+
+	if (best_error == S64_MAX)
+		return -EINVAL;
+
+	log_debug("best error %lld\n", best_error);
+	return 0;
+}
+
+static ulong k210_pll_set_rate(struct clk *clk, ulong rate)
+{
+	int err;
+	long long rate_in = clk_get_parent_rate(clk);
+	struct k210_pll_params params = {};
+	struct k210_pll *pll = to_k210_pll(clk);
+	u32 reg;
+
+	if (rate_in < 0)
+		return rate_in;
+
+	log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n",
+		  rate, rate_in);
+	err = k210_pll_calc_params(rate, rate_in, &params);
+	if (err)
+		return err;
+	log_debug("Got r=%u f=%u od=%u\n", params.r, params.f, params.od);
+
+	/*
+	 * Don't use clk_disable as it might not actually disable the pll due to
+	 * refcounting
+	 */
+	k210_pll_disable(clk);
+
+	reg = readl(pll->reg);
+	reg &= ~K210_PLL_CLKR
+	    &  ~K210_PLL_CLKF
+	    &  ~K210_PLL_CLKOD
+	    &  ~K210_PLL_BWADJ;
+	reg |= FIELD_PREP(K210_PLL_CLKR, params.r - 1)
+	    |  FIELD_PREP(K210_PLL_CLKF, params.f - 1)
+	    |  FIELD_PREP(K210_PLL_CLKOD, params.od - 1)
+	    |  FIELD_PREP(K210_PLL_BWADJ, params.f - 1);
+	writel(reg, pll->reg);
+
+	err = k210_pll_enable(clk);
+	if (err)
+		return err;
+
+	serial_setbrg();
+	return clk_get_rate(clk);
+}
+#endif /* CONFIG_CLK_K210_SET_RATE */
+
+static ulong k210_pll_get_rate(struct clk *clk)
+{
+	long long rate_in = clk_get_parent_rate(clk);
+	struct k210_pll *pll = to_k210_pll(clk);
+	u64 r, f, od;
+	u32 reg = readl(pll->reg);
+
+	if (rate_in < 0 || (reg & K210_PLL_BYPASS))
+		return rate_in;
+
+	if (!(reg & K210_PLL_PWRD))
+		return 0;
+
+	r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
+	f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
+	od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
+
+	return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
+}
+
+/* Check if the PLL is locked */
+static inline int k210_pll_locked(struct k210_pll *pll)
+{
+	u32 reg = readl(pll->lock);
+
+	return (reg & pll->lock_mask) == pll->lock_mask;
+}
+
+/*
+ * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
+ * slip before retrying
+ */
+static void k210_pll_waitfor_lock(struct k210_pll *pll)
+{
+	while (!k210_pll_locked(pll)) {
+		u32 reg = readl(pll->lock);
+
+		reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
+		writel(reg, pll->lock);
+	}
+}
+
+/* Adapted from sysctl_pll_enable */
+static int k210_pll_enable(struct clk *clk)
+{
+	struct k210_pll *pll = to_k210_pll(clk);
+	u32 reg = readl(pll->reg);
+
+	if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET))
+		return 0;
+
+	reg |= K210_PLL_PWRD;
+	writel(reg, pll->reg);
+
+	/* Ensure reset is low before asserting it */
+	reg &= ~K210_PLL_RESET;
+	writel(reg, pll->reg);
+	reg |= K210_PLL_RESET;
+	writel(reg, pll->reg);
+	nop();
+	nop();
+	reg &= ~K210_PLL_RESET;
+	writel(reg, pll->reg);
+
+	k210_pll_waitfor_lock(pll);
+
+	reg &= ~K210_PLL_BYPASS;
+	writel(reg, pll->reg);
+
+	return 0;
+}
+
+static int k210_pll_disable(struct clk *clk)
+{
+	struct k210_pll *pll = to_k210_pll(clk);
+	u32 reg = readl(pll->reg);
+
+	/*
+	 * Bypassing before powering off is important so child clocks don't stop
+	 * working. This is especially important for pll0, the indirect parent
+	 * of the cpu clock.
+	 */
+	reg |= K210_PLL_BYPASS;
+	writel(reg, pll->reg);
+
+	reg &= ~K210_PLL_PWRD;
+	writel(reg, pll->reg);
+	return 0;
+}
+
+const struct clk_ops k210_pll_ops = {
+	.get_rate = k210_pll_get_rate,
+#ifdef CONFIG_CLK_K210_SET_RATE
+	.set_rate = k210_pll_set_rate,
+#endif
+	.enable = k210_pll_enable,
+	.disable = k210_pll_disable,
+};
+
+struct k210_pll *k210_clk_comp_pll(void __iomem *reg, void __iomem *lock,
+				   u8 shift, u8 width)
+{
+	struct k210_pll *pll;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return pll;
+	pll->reg = reg;
+	pll->lock = lock;
+	pll->shift = shift;
+	pll->lock_mask = GENMASK(width - 1, 0) << shift;
+	return pll;
+}
+
+struct clk *k210_clk_pll(const char *name, const char *parent_name,
+			 void __iomem *reg, void __iomem *lock, u8 shift,
+			 u8 width)
+{
+	int err;
+	struct k210_pll *pll;
+
+	pll = k210_clk_comp_pll(reg, lock, shift, width);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	err = clk_register(&pll->clk, CLK_K210_PLL, name, parent_name);
+	if (err) {
+		kfree(pll);
+		return ERR_PTR(err);
+	}
+	return &pll->clk;
+}
+
+U_BOOT_DRIVER(k210_pll) = {
+	.name	= CLK_K210_PLL,
+	.id	= UCLASS_CLK,
+	.ops	= &k210_pll_ops,
+};
diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h
new file mode 100644
index 0000000000..32991b3ea0
--- /dev/null
+++ b/include/kendryte/pll.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+#ifndef K210_PLL_H
+#define K210_PLL_H
+
+#include <clk.h>
+#include <test/export.h>
+
+#define K210_PLL_CLKR GENMASK(3, 0)
+#define K210_PLL_CLKF GENMASK(9, 4)
+#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
+#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
+#define K210_PLL_RESET BIT(20)
+#define K210_PLL_PWRD BIT(21) /* PoWeReD */
+#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
+#define K210_PLL_BYPASS BIT(23)
+#define K210_PLL_TEST BIT(24)
+#define K210_PLL_EN BIT(25)
+#define K210_PLL_TEST_EN BIT(26)
+
+#define K210_PLL_LOCK 0
+#define K210_PLL_CLEAR_SLIP 2
+#define K210_PLL_TEST_OUT 3
+
+struct k210_pll {
+	struct clk clk;
+	void __iomem *reg; /* Base PLL register */
+	void __iomem *lock; /* Common PLL lock register */
+	u8 shift; /* Offset of bits in lock register */
+	u8 lock_mask; /* Mask of lock bits to test against, pre-shifted */
+};
+
+#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk)
+
+struct k210_pll_params {
+	u8 r;
+	u8 f;
+	u8 od;
+};
+
+#ifdef CONFIG_UNIT_TEST
+TEST_STATIC int k210_pll_calc_params(u32 rate, u32 rate_in,
+				     struct k210_pll_params *best);
+#define nop()
+#endif
+
+extern const struct clk_ops k210_pll_ops;
+
+struct k210_pll *k210_clk_comp_pll(void __iomem *reg, void __iomem *lock,
+				   u8 shift, u8 width);
+struct clk *k210_clk_pll(const char *name, const char *parent_name,
+			 void __iomem *reg, void __iomem *lock, u8 shift,
+			 u8 width);
+
+#endif /* K210_PLL_H */
diff --git a/include/test/export.h b/include/test/export.h
new file mode 100644
index 0000000000..afc755a8ff
--- /dev/null
+++ b/include/test/export.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef TEST_EXPORT_H
+#define TEST_EXPORT_H
+
+/* Declare something static, unless we are doing unit tests */
+#ifdef CONFIG_UNIT_TEST
+#define TEST_STATIC
+#else
+#define TEST_STATIC static
+#endif
+
+#endif /* TEST_EXPORT_H */
diff --git a/test/dm/Makefile b/test/dm/Makefile
index a760ab8b14..82b175560c 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -72,4 +72,5 @@ obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
 obj-$(CONFIG_DM_RNG) += rng.o
 obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
 obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
+obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
 endif
diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c
new file mode 100644
index 0000000000..3ddd12d991
--- /dev/null
+++ b/test/dm/k210_pll.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
+#include <div64.h>
+#include <dm/test.h>
+#include <kendryte/pll.h>
+#include <test/ut.h>
+
+static int dm_test_k210_pll_calc_params(u32 rate, u32 rate_in,
+					struct k210_pll_params *best)
+{
+	u64 f, r, od, max_r, inv_ratio;
+	s64 error, best_error;
+
+	error = best_error = S64_MAX;
+	max_r = min(16ULL, DIV_ROUND_DOWN_ULL(rate_in, 13300000));
+	inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
+
+	/* Brute force it */
+	for (r = 1; r <= max_r; r++) {
+		for (f = 1; f <= 64; f++) {
+			for (od = 1; od <= 16; od++) {
+				u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
+
+				if (vco > 1750000000 || vco < 340000000)
+					continue;
+
+				error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio,
+							      r * od);
+				/* The lower 16 bits are spurious */
+				error = abs((error - BIT(32))) >> 16;
+				if (error < best_error) {
+					best->r = r;
+					best->f = f;
+					best->od = od;
+					best_error = error;
+				}
+			}
+		}
+	}
+
+	if (best_error == S64_MAX)
+		return -EINVAL;
+	return 0;
+}
+
+static int dm_test_k210_pll_compare(struct k210_pll_params *ours,
+				    struct k210_pll_params *theirs)
+{
+	return (u32)ours->f * theirs->r * theirs->od !=
+	       (u32)theirs->f * ours->r * ours->od;
+}
+
+static int dm_test_k210_pll(struct unit_test_state *uts)
+{
+	struct k210_pll_params ours, theirs;
+
+	/* General range checks */
+	ut_asserteq(-EINVAL, k210_pll_calc_params(0, 26000000, &theirs));
+	ut_asserteq(-EINVAL, k210_pll_calc_params(390000000, 0, &theirs));
+	ut_asserteq(-EINVAL, k210_pll_calc_params(2000000000, 26000000,
+						  &theirs));
+	ut_asserteq(-EINVAL, k210_pll_calc_params(390000000, 2000000000,
+						  &theirs));
+	ut_asserteq(-EINVAL, k210_pll_calc_params(1500000000, 20000000,
+						  &theirs));
+
+	/* Verify we get the same output with brute-force */
+	ut_assertok(dm_test_k210_pll_calc_params(390000000, 26000000, &ours));
+	ut_assertok(k210_pll_calc_params(390000000, 26000000, &theirs));
+	ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+	ut_assertok(dm_test_k210_pll_calc_params(26000000, 390000000, &ours));
+	ut_assertok(k210_pll_calc_params(26000000, 390000000, &theirs));
+	ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+	ut_assertok(dm_test_k210_pll_calc_params(400000000, 26000000, &ours));
+	ut_assertok(k210_pll_calc_params(400000000, 26000000, &theirs));
+	ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+	ut_assertok(dm_test_k210_pll_calc_params(27000000, 26000000, &ours));
+	ut_assertok(k210_pll_calc_params(27000000, 26000000, &theirs));
+	ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+	ut_assertok(dm_test_k210_pll_calc_params(26000000, 27000000, &ours));
+	ut_assertok(k210_pll_calc_params(26000000, 27000000, &theirs));
+	ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+
+	return 0;
+}
+DM_TEST(dm_test_k210_pll, 0);
-- 
2.25.0

[PATCH v4 12/17] riscv: Add a bypass clock for K210

[Sean Anderson]

This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- New

 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/bypass.c | 268 ++++++++++++++++++++++++++++++++++
 include/kendryte/bypass.h     |  28 ++++
 3 files changed, 297 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 include/kendryte/bypass.h

diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index c56d93ea1c..47f682fce3 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += pll.o
+obj-y += bypass.o pll.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
new file mode 100644
index 0000000000..5276591bfd
--- /dev/null
+++ b/drivers/clk/kendryte/bypass.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <kendryte/bypass.h>
+
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#define LOG_CATEGORY UCLASS_CLK
+#include <log.h>
+#include <serial.h>
+
+#define CLK_K210_BYPASS "k210_clk_bypass"
+
+/*
+ * This is a small driver to do a software bypass of a clock if hardware bypass
+ * is not working. I have tried to write this in a generic fashion, so that it
+ * could be potentially broken out of the kendryte code at some future date.
+ *
+ * Say you have the following clock configuration
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ *         ^
+ *        /|
+ *       / |
+ *      /  |
+ *     /   |
+ *    /    |
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * But the pll does not have a bypass, so when you configure the pll, the
+ * configuration needs to change to look like
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ *   ^
+ *   |\
+ *   | \
+ *   |  \
+ *   |   \
+ *   |    \
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
+ * creating the child clocks, set their parent to the bypass clock. After
+ * creating all the children, call k210_bypass_setchildren().
+ */
+
+static int k210_bypass_dobypass(struct k210_bypass *bypass)
+{
+	int ret, i;
+
+	/*
+	 * If we already have saved parents, then the children are already
+	 * bypassed
+	 */
+	if (bypass->child_count && bypass->saved_parents[0])
+		return 0;
+
+	for (i = 0; i < bypass->child_count; i++) {
+		struct clk *child = bypass->children[i];
+		struct clk *parent = clk_get_parent(child);
+
+		if (IS_ERR(parent)) {
+			for (; i; i--)
+				bypass->saved_parents[i] = NULL;
+			return PTR_ERR(parent);
+		}
+		bypass->saved_parents[i] = parent;
+	}
+
+	for (i = 0; i < bypass->child_count; i++) {
+		struct clk *child = bypass->children[i];
+
+		ret = clk_set_parent(child, bypass->alt);
+		if (ret) {
+			for (; i; i--)
+				clk_set_parent(bypass->children[i],
+					       bypass->saved_parents[i]);
+			for (i = 0; i < bypass->child_count; i++)
+				bypass->saved_parents[i] = NULL;
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int k210_bypass_unbypass(struct k210_bypass *bypass)
+{
+	int err, ret, i;
+
+	if (!bypass->child_count && !bypass->saved_parents[0]) {
+		log_warning("Cannot unbypass children; dobypass not called first\n");
+		return 0;
+	}
+
+	ret = 0;
+	for (i = 0; i < bypass->child_count; i++) {
+		err = clk_set_parent(bypass->children[i],
+				     bypass->saved_parents[i]);
+		if (err)
+			ret = err;
+		bypass->saved_parents[i] = NULL;
+	}
+	return ret;
+}
+
+static ulong k210_bypass_get_rate(struct clk *clk)
+{
+	struct k210_bypass *bypass = to_k210_bypass(clk);
+	const struct clk_ops *ops = bypass->bypassee_ops;
+
+	if (ops->get_rate)
+		return ops->get_rate(bypass->bypassee);
+	else
+		return clk_get_parent_rate(bypass->bypassee);
+}
+
+static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret;
+	struct k210_bypass *bypass = to_k210_bypass(clk);
+	const struct clk_ops *ops = bypass->bypassee_ops;
+
+	/* Don't bother bypassing if we aren't going to set the rate */
+	if (!ops->set_rate)
+		return k210_bypass_get_rate(clk);
+
+	ret = k210_bypass_dobypass(bypass);
+	if (ret)
+		return ret;
+
+	ret = ops->set_rate(bypass->bypassee, rate);
+	if (ret < 0)
+		return ret;
+
+	return k210_bypass_unbypass(bypass);
+}
+
+static int k210_bypass_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct k210_bypass *bypass = to_k210_bypass(clk);
+	const struct clk_ops *ops = bypass->bypassee_ops;
+
+	if (ops->set_parent)
+		return ops->set_parent(bypass->bypassee, parent);
+	else
+		return -ENOTSUPP;
+}
+
+/*
+ * For these next two functions, do the bypassing even if there is no
+ * en-/-disable function, since the bypassing itself can be observed in between
+ * calls.
+ */
+static int k210_bypass_enable(struct clk *clk)
+{
+	int ret;
+	struct k210_bypass *bypass = to_k210_bypass(clk);
+	const struct clk_ops *ops = bypass->bypassee_ops;
+
+	ret = k210_bypass_dobypass(bypass);
+	if (ret)
+		return ret;
+
+	if (ops->enable)
+		ret = ops->enable(bypass->bypassee);
+	else
+		ret = 0;
+	if (ret)
+		return ret;
+
+	return k210_bypass_unbypass(bypass);
+}
+
+static int k210_bypass_disable(struct clk *clk)
+{
+	int ret;
+	struct k210_bypass *bypass = to_k210_bypass(clk);
+	const struct clk_ops *ops = bypass->bypassee_ops;
+
+	ret = k210_bypass_dobypass(bypass);
+	if (ret)
+		return ret;
+
+	if (ops->disable)
+		return ops->disable(bypass->bypassee);
+	else
+		return 0;
+}
+
+static const struct clk_ops k210_bypass_ops = {
+	.get_rate = k210_bypass_get_rate,
+	.set_rate = k210_bypass_set_rate,
+	.set_parent = k210_bypass_set_parent,
+	.enable = k210_bypass_enable,
+	.disable = k210_bypass_disable,
+};
+
+int k210_bypass_set_children(struct clk *clk, struct clk **children,
+			     size_t child_count)
+{
+	struct k210_bypass *bypass = to_k210_bypass(clk);
+
+	kfree(bypass->saved_parents);
+	if (child_count) {
+		bypass->saved_parents =
+			kcalloc(child_count, sizeof(struct clk *), GFP_KERNEL);
+		if (!bypass->saved_parents)
+			return -ENOMEM;
+	}
+	bypass->child_count = child_count;
+	bypass->children = children;
+
+	return 0;
+}
+
+static struct k210_bypass *k210_clk_comp_bypass(struct clk *bypassee,
+						const struct clk_ops *bypassee_ops,
+						struct clk *alt)
+{
+	struct k210_bypass *bypass;
+
+	bypass = kzalloc(sizeof(*bypass), GFP_KERNEL);
+	if (!bypass)
+		return bypass;
+
+	bypass->bypassee = bypassee;
+	bypass->bypassee_ops = bypassee_ops;
+	bypass->alt = alt;
+	return bypass;
+}
+
+struct clk *k210_clk_bypass(const char *name, const char *parent_name,
+			    struct clk *bypassee,
+			    const struct clk_ops *bypassee_ops, struct clk *alt)
+{
+	int err;
+	struct k210_bypass *bypass;
+
+	bypass = k210_clk_comp_bypass(bypassee, bypassee_ops, alt);
+	if (!bypass)
+		return ERR_PTR(-ENOMEM);
+
+	err = clk_register(&bypass->clk, CLK_K210_BYPASS, name, parent_name);
+	if (err) {
+		kfree(bypass);
+		return ERR_PTR(err);
+	}
+	bypassee->dev = bypass->clk.dev;
+	return &bypass->clk;
+}
+
+U_BOOT_DRIVER(k210_bypass) = {
+	.name	= CLK_K210_BYPASS,
+	.id	= UCLASS_CLK,
+	.ops	= &k210_bypass_ops,
+};
diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h
new file mode 100644
index 0000000000..3093057324
--- /dev/null
+++ b/include/kendryte/bypass.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+#ifndef K210_BYPASS_H
+#define K210_BYPASS_H
+
+#include <clk.h>
+
+struct k210_bypass {
+	struct clk clk;
+	struct clk **children; /* Clocks to reparent */
+	struct clk **saved_parents; /* Parents saved over en-/dis-able */
+	struct clk *bypassee; /* Clock to bypass */
+	const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */
+	struct clk *alt; /* Clock to set children to when bypassing */
+	size_t child_count;
+};
+
+#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk)
+
+int k210_bypass_set_children(struct clk *clk, struct clk **children,
+			     size_t child_count);
+struct clk *k210_clk_bypass(const char *name, const char *parent_name,
+			    struct clk *bypassee,
+			    const struct clk_ops *bypassee_ops,
+			    struct clk *alt);
+#endif /* K210_BYPASS_H */
-- 
2.25.0

[PATCH v4 13/17] riscv: Add K210 clock support

[Sean Anderson]

Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. A common pattern is to create a
composite clock composed of several component clocks. For these component
clocks, the clk_register_* functions are not used, since they will be
registered as part of the composite clock. To create these component
clocks, several helper k210_clk_comp_* functions are used. This
functionality seems like it would be useful to other drivers also creating
composite clocks, so perhaps some general versions should be created. I am
not particularly attached to the naming convention, suggestions are
welcome.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- Reparent aclk before configuring pll0
- Update copyright
- Lint

Changes in v3:
- Removed sysctl struct, replacing it with defines. This is to have the same
  interface to sysctl from C as from the device tree.
- Fixed clocks having the same id
- Fixed clocks not using the correct register/bits
- Aligned the defines in headers

Changes in v2:
- Add clk.o to obj-y
- Don't probe before relocation

 drivers/clk/kendryte/Kconfig            |   2 +-
 drivers/clk/kendryte/Makefile           |   2 +-
 drivers/clk/kendryte/clk.c              | 409 ++++++++++++++++++++++++
 include/dt-bindings/clock/k210-sysctl.h |  53 +++
 include/dt-bindings/mfd/k210-sysctl.h   |  38 +++
 include/kendryte/clk.h                  |  27 ++
 6 files changed, 529 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/kendryte/clk.c
 create mode 100644 include/dt-bindings/clock/k210-sysctl.h
 create mode 100644 include/dt-bindings/mfd/k210-sysctl.h
 create mode 100644 include/kendryte/clk.h

diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
index 7b69c8afaf..073fca0781 100644
--- a/drivers/clk/kendryte/Kconfig
+++ b/drivers/clk/kendryte/Kconfig
@@ -1,6 +1,6 @@
 config CLK_K210
 	bool "Clock support for Kendryte K210"
-	depends on CLK && CLK_CCF
+	depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF
 	help
 	  This enables support clock driver for Kendryte K210 platforms.
 
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index 47f682fce3..6fb68253ae 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += bypass.o pll.o
+obj-y += bypass.o clk.o pll.o
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
new file mode 100644
index 0000000000..bfc4896dfe
--- /dev/null
+++ b/drivers/clk/kendryte/clk.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+#include <kendryte/clk.h>
+
+#include <asm/io.h>
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <dt-bindings/mfd/k210-sysctl.h>
+#include <dm.h>
+#include <log.h>
+#include <mapmem.h>
+
+#include <kendryte/bypass.h>
+#include <kendryte/pll.h>
+
+static ulong k210_clk_get_rate(struct clk *clk)
+{
+	struct clk *c;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+	return clk_get_rate(c);
+}
+
+static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *c;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+	return clk_set_rate(c, rate);
+}
+
+static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *c, *p;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+
+	err = clk_get_by_id(parent->id, &p);
+	if (err)
+		return err;
+
+	return clk_set_parent(c, p);
+}
+
+static int k210_clk_endisable(struct clk *clk, bool enable)
+{
+	struct clk *c;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+	return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int k210_clk_enable(struct clk *clk)
+{
+	return k210_clk_endisable(clk, true);
+}
+
+static int k210_clk_disable(struct clk *clk)
+{
+	return k210_clk_endisable(clk, false);
+}
+
+static const struct clk_ops k210_clk_ops = {
+	.set_rate = k210_clk_set_rate,
+	.get_rate = k210_clk_get_rate,
+	.set_parent = k210_clk_set_parent,
+	.enable = k210_clk_enable,
+	.disable = k210_clk_disable,
+};
+
+/* The first clock is in0, which is filled in by k210_clk_probe */
+static const char * const generic_sels[] = { "in0_half", "pll0_half" };
+static const char *pll2_sels[] = { NULL, "pll0", "pll1" };
+
+static struct clk_divider *k210_clk_comp_div_flags(void __iomem *reg, u8 shift,
+						   u8 width, u8 flags)
+{
+	struct clk_divider *div;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		return div;
+	div->reg = reg;
+	div->shift = shift;
+	div->width = width;
+	div->flags = flags;
+	return div;
+}
+
+static inline struct clk_divider *k210_clk_comp_div(void __iomem *reg, u8 shift,
+						    u8 width)
+{
+	return k210_clk_comp_div_flags(reg, shift, width, 0);
+}
+
+static struct clk_gate *k210_clk_comp_gate(void __iomem *reg, u8 bit_idx)
+{
+	struct clk_gate *gate;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return gate;
+	gate->reg = reg;
+	gate->bit_idx = bit_idx;
+	return gate;
+}
+
+static struct clk_mux *k210_clk_comp_mux(const char * const parent_names[],
+					 u8 num_parents, void __iomem *reg,
+					 u8 shift, u8 width)
+{
+	struct clk_mux *mux;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return mux;
+	mux->reg = reg;
+	mux->mask = BIT(width) - 1;
+	mux->shift = shift;
+	mux->parent_names = parent_names;
+	mux->num_parents = num_parents;
+	return mux;
+}
+
+static struct clk *k210_clk_comp_nomux(const char *name, const char *parent,
+				       struct clk_divider *div,
+				       struct clk_gate *gate)
+{
+	if (!div || !gate) {
+		kfree(div);
+		kfree(gate);
+		return ERR_PTR(-ENOMEM);
+	}
+	return clk_register_composite(NULL, name, &parent, 1,
+				      NULL, NULL,
+				      &div->clk, &clk_divider_ops,
+				      &gate->clk, &clk_gate_ops, 0);
+}
+
+static struct clk *k210_clk_comp(const char *name, struct clk_divider *div,
+				 struct clk_gate *gate, struct clk_mux *mux)
+{
+	if (!div || !gate || !mux) {
+		kfree(div);
+		kfree(gate);
+		kfree(mux);
+		return ERR_PTR(-ENOMEM);
+	}
+	return clk_register_composite(NULL, name, generic_sels,
+				      ARRAY_SIZE(generic_sels),
+				      &mux->clk, &clk_mux_ops,
+				      &div->clk, &clk_divider_ops,
+				      &gate->clk, &clk_gate_ops, 0);
+}
+
+static int k210_clk_probe(struct udevice *dev)
+{
+	int err;
+	const char *in0;
+	struct clk **children;
+	struct clk *aclk;
+	struct clk *bypass;
+	struct clk in0_clk;
+	struct clk *in0_half;
+	struct clk_divider *div;
+	struct clk_gate *gate;
+	struct clk_mux *mux;
+	struct k210_pll *pll;
+	void *base;
+
+	base = dev_read_addr_ptr(dev_get_parent(dev));
+	if (!base)
+		return -EINVAL;
+
+	err = clk_get_by_index(dev, 0, &in0_clk);
+	if (err)
+		goto cleanup_base;
+	in0 = in0_clk.dev->name;
+	pll2_sels[0] = in0;
+
+	in0_half = k210_clk_half("in0_half", in0);
+
+	/* PLLs */
+	pll = k210_clk_comp_pll(base + K210_SYSCTL_PLL0,
+				base + K210_SYSCTL_PLL_LOCK, 0, 2);
+	/*
+	 * All PLLs have a broken bypass, but pll0 has the CPU downstream, so we
+	 * need to manually reparent it whenever we configure pll0
+	 */
+	bypass = k210_clk_bypass("pll0", in0, &pll->clk, &k210_pll_ops,
+				 in0_half);
+	clk_dm(K210_CLK_PLL0, bypass);
+	clk_dm(K210_CLK_PLL1, k210_clk_pll("pll1", in0, base + K210_SYSCTL_PLL1,
+					   base + K210_SYSCTL_PLL_LOCK, 8, 1));
+	/* PLL2 is muxed, so set up a composite clock */
+	mux = k210_clk_comp_mux(pll2_sels, ARRAY_SIZE(pll2_sels),
+				base + K210_SYSCTL_PLL2, 26, 2);
+	pll = k210_clk_comp_pll(base + K210_SYSCTL_PLL2,
+				base + K210_SYSCTL_PLL_LOCK, 16, 1);
+	if (!mux || !pll) {
+		kfree(mux);
+		kfree(pll);
+	} else {
+		clk_dm(K210_CLK_PLL2,
+		       clk_register_composite(NULL, "pll2", pll2_sels,
+					      ARRAY_SIZE(pll2_sels),
+					      &mux->clk, &clk_mux_ops,
+					      &pll->clk, &k210_pll_ops,
+					      &pll->clk, &k210_pll_ops, 0));
+	}
+
+	/* Half-frequency clocks for "even" dividers */
+	k210_clk_half("pll0_half", "pll0");
+	k210_clk_half("pll2_half", "pll2");
+
+	/* Muxed clocks */
+	div = k210_clk_comp_div_flags(base + K210_SYSCTL_SEL0, 1, 2,
+				      CLK_DIVIDER_POWER_OF_TWO);
+	mux = k210_clk_comp_mux(generic_sels, ARRAY_SIZE(generic_sels),
+				base + K210_SYSCTL_SEL0, 0, 1);
+	/*
+	 * aclk is the direct parent of the cpu clock, and needs to be
+	 * reparented when pll0 is configured.
+	 */
+	children = kzalloc(sizeof(*children), GFP_KERNEL);
+	if (!div || !mux || !children) {
+		kfree(div);
+		kfree(mux);
+		kfree(children);
+	} else {
+		aclk = clk_register_composite(NULL, "aclk", generic_sels,
+					      ARRAY_SIZE(generic_sels),
+					      &mux->clk, &clk_mux_ops,
+					      &div->clk, &clk_divider_ops,
+					      NULL, NULL, 0);
+		children[0] = aclk;
+		err = k210_bypass_set_children(bypass, children, 1);
+		if (!err)
+			clk_dm(K210_CLK_ACLK, aclk);
+	}
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_SEL0, 1, 2);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 9);
+	mux = k210_clk_comp_mux(generic_sels, ARRAY_SIZE(generic_sels),
+				base + K210_SYSCTL_SEL0, 12, 1);
+	clk_dm(K210_CLK_SPI3, k210_clk_comp("spi3", div, gate, mux));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR2, 8, 0);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 21);
+	mux = k210_clk_comp_mux(generic_sels, ARRAY_SIZE(generic_sels),
+				base + K210_SYSCTL_SEL0, 13, 1);
+	clk_dm(K210_CLK_TIMER0, k210_clk_comp("timer0", div, gate, mux));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR2, 8, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 22);
+	mux = k210_clk_comp_mux(generic_sels, ARRAY_SIZE(generic_sels),
+				base + K210_SYSCTL_SEL0, 14, 1);
+	clk_dm(K210_CLK_TIMER1, k210_clk_comp("timer1", div, gate, mux));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR2, 8, 16);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 23);
+	mux = k210_clk_comp_mux(generic_sels, ARRAY_SIZE(generic_sels),
+				base + K210_SYSCTL_SEL0, 15, 1);
+	clk_dm(K210_CLK_TIMER2, k210_clk_comp("timer2", div, gate, mux));
+
+	/* Dividing clocks, no mux */
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR0, 0, 4);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_CENT, 1);
+	clk_dm(K210_CLK_SRAM0, k210_clk_comp_nomux("sram0", "aclk", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR0, 4, 4);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_CENT, 2);
+	clk_dm(K210_CLK_SRAM1, k210_clk_comp_nomux("sram1", "aclk", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR0, 16, 4);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 0);
+	clk_dm(K210_CLK_ROM, k210_clk_comp_nomux("rom", "aclk", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR0, 12, 4);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 3);
+	clk_dm(K210_CLK_DVP, k210_clk_comp_nomux("dvp", "aclk", div, gate));
+
+	/*
+	 * XXX: the next three clocks may be using an even divider
+	 * c.f. <https://github.com/kendryte/kendryte-standalone-sdk/issues/99>
+	 */
+	div = k210_clk_comp_div(base + K210_SYSCTL_SEL0, 3, 3);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_CENT, 3);
+	clk_dm(K210_CLK_APB0, k210_clk_comp_nomux("apb0", "aclk", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_SEL0, 6, 3);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_CENT, 4);
+	clk_dm(K210_CLK_APB1, k210_clk_comp_nomux("apb1", "aclk", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_SEL0, 9, 3);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_CENT, 5);
+	clk_dm(K210_CLK_APB2, k210_clk_comp_nomux("apb2", "aclk", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR0, 8, 4);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 2);
+	clk_dm(K210_CLK_AI, k210_clk_comp_nomux("ai", "pll1", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR3, 0, 16);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 10);
+	clk_dm(K210_CLK_I2S0,
+	       k210_clk_comp_nomux("i2s0", "pll2_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR3, 16, 16);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 11);
+	clk_dm(K210_CLK_I2S1,
+	       k210_clk_comp_nomux("i2s1", "pll2_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR4, 0, 16);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 12);
+	clk_dm(K210_CLK_I2S2,
+	       k210_clk_comp_nomux("i2s2", "pll2_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR6, 0, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 24);
+	clk_dm(K210_CLK_WDT0,
+	       k210_clk_comp_nomux("wdt0", "in0_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR6, 8, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 25);
+	clk_dm(K210_CLK_WDT1,
+	       k210_clk_comp_nomux("wdt1", "in0_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR1, 0, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 6);
+	clk_dm(K210_CLK_SPI0,
+	       k210_clk_comp_nomux("spi0", "pll0_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR1, 8, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 7);
+	clk_dm(K210_CLK_SPI1,
+	       k210_clk_comp_nomux("spi1", "pll0_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR1, 16, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 8);
+	clk_dm(K210_CLK_SPI2,
+	       k210_clk_comp_nomux("spi2", "pll0_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR5, 8, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 13);
+	clk_dm(K210_CLK_I2C0,
+	       k210_clk_comp_nomux("i2c0", "pll0_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR5, 16, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 14);
+	clk_dm(K210_CLK_I2C1,
+	       k210_clk_comp_nomux("i2c1", "pll0_half", div, gate));
+
+	div = k210_clk_comp_div(base + K210_SYSCTL_THR5, 24, 8);
+	gate = k210_clk_comp_gate(base + K210_SYSCTL_EN_PERI, 15);
+	clk_dm(K210_CLK_I2C2,
+	       k210_clk_comp_nomux("i2c2", "pll0_half", div, gate));
+
+	/* Gated clocks */
+	clk_dm(K210_CLK_CPU,
+	       k210_clk_gate("cpu", "aclk", base + K210_SYSCTL_EN_CENT, 0));
+	clk_dm(K210_CLK_DMA,
+	       k210_clk_gate("dma", "aclk", base + K210_SYSCTL_EN_PERI, 1));
+	clk_dm(K210_CLK_FFT,
+	       k210_clk_gate("fft", "aclk", base + K210_SYSCTL_EN_PERI, 4));
+	clk_dm(K210_CLK_GPIO,
+	       k210_clk_gate("gpio", "apb0", base + K210_SYSCTL_EN_PERI, 5));
+	clk_dm(K210_CLK_UART1,
+	       k210_clk_gate("uart1", "apb0", base + K210_SYSCTL_EN_PERI, 16));
+	clk_dm(K210_CLK_UART2,
+	       k210_clk_gate("uart2", "apb0", base + K210_SYSCTL_EN_PERI, 17));
+	clk_dm(K210_CLK_UART3,
+	       k210_clk_gate("uart3", "apb0", base + K210_SYSCTL_EN_PERI, 18));
+	clk_dm(K210_CLK_FPIOA,
+	       k210_clk_gate("fpioa", "apb0", base + K210_SYSCTL_EN_PERI, 20));
+	clk_dm(K210_CLK_SHA,
+	       k210_clk_gate("sha", "apb0", base + K210_SYSCTL_EN_PERI, 26));
+	clk_dm(K210_CLK_AES,
+	       k210_clk_gate("aes", "apb1", base + K210_SYSCTL_EN_PERI, 19));
+	clk_dm(K210_CLK_OTP,
+	       k210_clk_gate("otp", "apb1", base + K210_SYSCTL_EN_PERI, 27));
+	clk_dm(K210_CLK_RTC,
+	       k210_clk_gate("rtc", in0, base + K210_SYSCTL_EN_PERI, 29));
+
+cleanup_base:
+	unmap_sysmem(base);
+	return err;
+}
+
+static const struct udevice_id k210_clk_ids[] = {
+	{ .compatible = "kendryte,k210-clk" },
+	{ },
+};
+
+U_BOOT_DRIVER(k210_clk) = {
+	.name = "k210_clk",
+	.id = UCLASS_CLK,
+	.of_match = k210_clk_ids,
+	.ops = &k210_clk_ops,
+	.probe = k210_clk_probe,
+};
diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h
new file mode 100644
index 0000000000..7c471f9893
--- /dev/null
+++ b/include/dt-bindings/clock/k210-sysctl.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef CLOCK_K210_SYSCTL_H
+#define CLOCK_K210_SYSCTL_H
+
+/*
+ * Arbitrary identifiers for clocks. 0 is unused since clk_enable thinks it
+ * means "no clock".
+ */
+#define K210_CLK_PLL0   1
+#define K210_CLK_PLL1   2
+#define K210_CLK_PLL2   3
+#define K210_CLK_CPU    4
+#define K210_CLK_SRAM0  5
+#define K210_CLK_SRAM1  6
+#define K210_CLK_APB0   7
+#define K210_CLK_APB1   8
+#define K210_CLK_APB2   9
+#define K210_CLK_ROM    10
+#define K210_CLK_DMA    11
+#define K210_CLK_AI     12
+#define K210_CLK_DVP    13
+#define K210_CLK_FFT    14
+#define K210_CLK_GPIO   15
+#define K210_CLK_SPI0   16
+#define K210_CLK_SPI1   17
+#define K210_CLK_SPI2   18
+#define K210_CLK_SPI3   19
+#define K210_CLK_I2S0   20
+#define K210_CLK_I2S1   21
+#define K210_CLK_I2S2   22
+#define K210_CLK_I2C0   23
+#define K210_CLK_I2C1   24
+#define K210_CLK_I2C2   25
+#define K210_CLK_UART1  26
+#define K210_CLK_UART2  27
+#define K210_CLK_UART3  28
+#define K210_CLK_AES    29
+#define K210_CLK_FPIOA  30
+#define K210_CLK_TIMER0 31
+#define K210_CLK_TIMER1 32
+#define K210_CLK_TIMER2 33
+#define K210_CLK_WDT0   34
+#define K210_CLK_WDT1   35
+#define K210_CLK_SHA    36
+#define K210_CLK_OTP    37
+#define K210_CLK_RTC    40
+#define K210_CLK_ACLK   41
+
+#endif /* CLOCK_K210_SYSCTL_H */
diff --git a/include/dt-bindings/mfd/k210-sysctl.h b/include/dt-bindings/mfd/k210-sysctl.h
new file mode 100644
index 0000000000..e16d7302cd
--- /dev/null
+++ b/include/dt-bindings/mfd/k210-sysctl.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef K210_SYSCTL_H
+#define K210_SYSCTL_H
+
+/* Taken from kendryte-standalone-sdk/lib/drivers/include/sysctl.h */
+#define K210_SYSCTL_GIT_ID     0x00 /* Git short commit id */
+#define K210_SYSCTL_CLK_FREQ   0x04 /* System clock base frequency */
+#define K210_SYSCTL_PLL0       0x08 /* PLL0 controller */
+#define K210_SYSCTL_PLL1       0x0C /* PLL1 controller */
+#define K210_SYSCTL_PLL2       0x10 /* PLL2 controller */
+#define K210_SYSCTL_PLL_LOCK   0x18 /* PLL lock tester */
+#define K210_SYSCTL_ROM_ERROR  0x1C /* AXI ROM detector */
+#define K210_SYSCTL_SEL0       0x20 /* Clock select controller0 */
+#define K210_SYSCTL_SEL1       0x24 /* Clock select controller1 */
+#define K210_SYSCTL_EN_CENT    0x28 /* Central clock enable */
+#define K210_SYSCTL_EN_PERI    0x2C /* Peripheral clock enable */
+#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */
+#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */
+#define K210_SYSCTL_THR0       0x38 /* Clock threshold controller 0 */
+#define K210_SYSCTL_THR1       0x3C /* Clock threshold controller 1 */
+#define K210_SYSCTL_THR2       0x40 /* Clock threshold controller 2 */
+#define K210_SYSCTL_THR3       0x44 /* Clock threshold controller 3 */
+#define K210_SYSCTL_THR4       0x48 /* Clock threshold controller 4 */
+#define K210_SYSCTL_THR5       0x4C /* Clock threshold controller 5 */
+#define K210_SYSCTL_THR6       0x50 /* Clock threshold controller 6 */
+#define K210_SYSCTL_MISC       0x54 /* Miscellaneous controller */
+#define K210_SYSCTL_PERI       0x58 /* Peripheral controller */
+#define K210_SYSCTL_SPI_SLEEP  0x5C /* SPI sleep controller */
+#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */
+#define K210_SYSCTL_DMA_SEL0   0x64 /* DMA handshake selector */
+#define K210_SYSCTL_DMA_SEL1   0x68 /* DMA handshake selector */
+#define K210_SYSCTL_POWER_SEL  0x6C /* IO Power Mode Select controller */
+
+#endif /* K210_SYSCTL_H */
diff --git a/include/kendryte/clk.h b/include/kendryte/clk.h
new file mode 100644
index 0000000000..d1078c3014
--- /dev/null
+++ b/include/kendryte/clk.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef K210_CLK_H
+#define K210_CLK_H
+
+#define LOG_CATEGORY UCLASS_CLK
+#include <linux/types.h>
+#include <linux/clk-provider.h>
+
+static inline struct clk *k210_clk_gate(const char *name,
+					const char *parent_name,
+					void __iomem *reg, u8 bit_idx)
+{
+	return clk_register_gate(NULL, name, parent_name, 0, reg, bit_idx, 0,
+				 NULL);
+}
+
+static inline struct clk *k210_clk_half(const char *name,
+					const char *parent_name)
+{
+	return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 2);
+}
+
+#endif /* K210_CLK_H */
-- 
2.25.0

[PATCH v4 14/17] riscv: Try to get cpu frequency from device tree

[Sean Anderson]

Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
This patch was previously sumbitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

This patch is the combination of the patches
https://patchwork.ozlabs.org/patch/1223933/
https://patchwork.ozlabs.org/patch/1224957/
"riscv: Fix incorrect cpu frequency on RV64"
"riscv: Try to get cpu frequency from device tree"

Changes in v4:
- New

 drivers/cpu/riscv_cpu.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 28ad0aa30f..5309a49e60 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
+#include <clk.h>
 #include <common.h>
 #include <cpu.h>
 #include <dm.h>
@@ -27,9 +28,24 @@ static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
 
 static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 {
+	int ret;
+	struct clk clk;
 	const char *mmu;
 
-	dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
+	/* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */
+	info->cpu_freq = 0;
+
+	/* First try getting the frequency from the assigned clock */
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (!ret) {
+		ret = clk_get_rate(&clk);
+		if (!IS_ERR_VALUE(ret))
+			info->cpu_freq = ret;
+		clk_free(&clk);
+	}
+
+	if (!info->cpu_freq)
+		dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
 
 	mmu = dev_read_string(dev, "mmu-type");
 	if (!mmu)
-- 
2.25.0

[PATCH v4 15/17] riscv: Enable cpu clock if it is present

[Sean Anderson]

The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
This patch was previously submitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

Changes in v4:
- New

 drivers/cpu/riscv_cpu.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 5309a49e60..52b74d9e69 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  */
 
 #include <clk.h>
@@ -116,6 +117,24 @@ static int riscv_cpu_bind(struct udevice *dev)
 	return 0;
 }
 
+static int riscv_cpu_probe(struct udevice *dev)
+{
+	int ret = 0;
+	struct clk clk;
+
+	/* Get a clock if it exists */
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return 0;
+
+	ret = clk_enable(&clk);
+	clk_free(&clk);
+	if (ret == -ENOSYS || ret == -ENOTSUPP)
+		return 0;
+	else
+		return ret;
+}
+
 static const struct cpu_ops riscv_cpu_ops = {
 	.get_desc	= riscv_cpu_get_desc,
 	.get_info	= riscv_cpu_get_info,
@@ -132,6 +151,7 @@ U_BOOT_DRIVER(riscv_cpu) = {
 	.id = UCLASS_CPU,
 	.of_match = riscv_cpu_ids,
 	.bind = riscv_cpu_bind,
+	.probe = riscv_cpu_probe,
 	.ops = &riscv_cpu_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
2.25.0

[PATCH v4 16/17] riscv: Add device tree for K210

[Sean Anderson]

The cache-line size is undocumented. Emphirical tests suggest that it is 32
bytes, but I've used 64-bytes to be on the safe side.

Where possible, I have tried to find compatible drivers based on the layout
of registers. However, I have not tested most of this functionality, and
most devices should be considered descriptive at best. I would appreciate
if anyone could help identify possibly compatible devices, especially for
the timers, watchdogs, and rtc.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v4:
- Set regs sizes to full address range
- Remove clock-frequency property from cpus
- Add spi-max-frequency to spi devices from documentation
- Add more compatible strings for each device
- Add AI ram as a separate memory bank. Its clock is disabled on boot, and
  it cannot be accessed
- Reorder memory banks so u-boot relocates higher, leaving more room to
  load boot images
- Add designware ssi CTRL0 field shifts to spi devices
- Don't enable the MMC slot
- Update copyright
- Lint

Changes in v3:
- Move this patch to the end of the series
- Add a max frequency for spi3
- Remov unused compatible strings from spi-flash at 0
- Add s and u to isa string
- Fix mmu-type
- Remove cache-line size since it is unused (in u-boot) and undocumented
  (upstream)
- Add timer interrupts to clint0
- Round up various registers
- Add riscv,max-priority to plic
- Add apb* busses, since they have clocks which need to be enabled to
  access their devices
- Change uart compatible strings to "snps,dw-apb-uart", since that appears
  to match their registers
- Add compatible string for wdt*
- Add system reset device under sysctl
- Add reset device under sysctl

Changes in v2:
- Model changed to "Sipeed Maix Bit" to match file name
- Value of stdout-path fixed
- SD card slot compatible changed to "mmc-spi-slot"
- "jedec,spi-nor" added to spi flash compatible list
- Aliases for spi busses added
- timebase-frequency divided by 50 to match timer speed
- cpu-frequency renamed to clock-frequency
- CPUX_intc restyled to cpuX_intc
- "kendryte,k210-soc" added to soc compatible list for future-proofing
- PLIC handle renamed to plic0 from pic0
- K210_RST_SOC removed from sysrst, due to not being located in the reset
  register
- K210_RST_* numbers changed to match their bit offset within the reset
  register
- gpio_controller restyled to gpio-controller
- Added a second clock to the dma binding to match what the driver expects
- Changed "snps,designware-spi" compatible string to "snps,dw-apb-ssi" to
  match the correct driver
- Added a name to the spi clocks
- Added reg-io-width property to spi bindings
- Assigned a default parent to K210_CLK_SPI3
- Removed assigned clocks for ACLK and PLLs
- Removed u-boot,dm-pre-reloc bindings

 arch/riscv/dts/Makefile                 |   1 +
 arch/riscv/dts/k210-maix-bit.dts        |  41 ++
 arch/riscv/dts/k210.dtsi                | 568 ++++++++++++++++++++++++
 include/dt-bindings/clock/k210-sysctl.h |   2 +-
 include/dt-bindings/reset/k210-sysctl.h |  38 ++
 5 files changed, 649 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/dts/k210-maix-bit.dts
 create mode 100644 arch/riscv/dts/k210.dtsi
 create mode 100644 include/dt-bindings/reset/k210-sysctl.h

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 4f30e6936f..3a6f96c67d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
new file mode 100644
index 0000000000..33c4da96f3
--- /dev/null
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "k210.dtsi"
+
+/ {
+	model = "Sipeed Maix Bit";
+	compatible = "sipeed,maix-bit", "kendryte,k210";
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+};
+
+&uarths0 {
+	status = "okay";
+};
+
+&spi0 {
+	//status = "okay";
+	slot at 0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		broken-cd;
+		disable-wp;
+	};
+};
+
+&spi3 {
+	status = "okay";
+	spi-flash at 0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <120000000>;
+		m25p,fast-read;
+	};
+};
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
new file mode 100644
index 0000000000..a3c7be72ce
--- /dev/null
+++ b/arch/riscv/dts/k210.dtsi
@@ -0,0 +1,568 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <dt-bindings/mfd/k210-sysctl.h>
+#include <dt-bindings/reset/k210-sysctl.h>
+
+/ {
+	/*
+	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
+	 * wide, and the upper half of all addresses is ignored.
+	 */
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "kendryte,k210";
+
+	aliases {
+		serial0 = &uarths0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+	};
+
+	clocks {
+		in0: osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <26000000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <7800000>;
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			reg = <0>;
+			compatible = "riscv";
+			riscv,isa = "rv64acdfimsu";
+			mmu-type = "sv39";
+			i-cache-size = <0x8000>;
+			d-cache-size = <0x8000>;
+			clocks = <&sysclk K210_CLK_CPU>;
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			reg = <1>;
+			compatible = "riscv";
+			riscv,isa = "rv64acdfimsu";
+			mmu-type = "sv39";
+			i-cache-size = <0x8000>;
+			d-cache-size = <0x8000>;
+			clocks = <&sysclk K210_CLK_CPU>;
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	/* Out-of-order so we relocate higher */
+	sram1: memory at 80400000 {
+		device_type = "memory";
+		reg = <0x80400000 0x200000>;
+		clocks = <&sysclk K210_CLK_SRAM1>;
+	};
+
+	sram0: memory at 80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x400000>;
+		clocks = <&sysclk K210_CLK_SRAM0>;
+	};
+
+	airam: memory at 80600000 {
+		device_type = "memory";
+		reg = <0x80600000 0x200000>;
+		clocks = <&sysclk K210_CLK_AI>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		ai_reserved: ai at 80600000 {
+			reg = <0x80600000 0x200000>;
+			reusable;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "kendryte,k210-soc", "simple-bus";
+		ranges;
+		interrupt-parent = <&plic0>;
+
+		debug0: debug at 0 {
+			compatible = "kendryte,k210-debug", "riscv,debug";
+			reg = <0x0 0x1000>;
+		};
+
+		rom0: nvmem at 1000 {
+			reg = <0x1000 0x1000>;
+			read-only;
+		};
+
+		clint0: interrupt-controller at 2000000 {
+			compatible = "kendryte,k210-clint", "riscv,clint0";
+			reg = <0x2000000 0x1000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>;
+			clocks = <&sysclk K210_CLK_CPU>;
+		};
+
+		plic0: interrupt-controller at c000000 {
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			compatible = "kendryte,k210-plic", "riscv,plic0";
+			reg = <0xC000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
+					      <&cpu1_intc 9>, <&cpu1_intc 11>;
+			riscv,ndev = <65>;
+			riscv,max-priority = <7>;
+		};
+
+		uarths0: serial at 38000000 {
+			compatible = "sifive,uart0";
+			reg = <0x38000000 0x1000>;
+			interrupts = <33>;
+			clocks = <&sysclk K210_CLK_CPU>;
+			status = "disabled";
+		};
+
+		gpiohs0: gpio-controller at 38001000 {
+			#gpio-cells = <2>;
+			compatible = "kendryte,k210-gpiohs";
+			reg = <0x38001000 0x1000>;
+			gpio-controller;
+			interrupts = <34 35 36 37 38 39 40 41
+				      42 43 44 45 46 47 48 49
+				      50 51 52 53 54 55 56 57
+				      58 59 60 61 62 63 64 65>;
+			clocks = <&sysclk K210_CLK_CPU>;
+			status = "disabled";
+		};
+
+		kpu0: kpu at 40800000 {
+			compatible = "kendryte,k210-kpu";
+			reg = <0x40800000 0xc00000>;
+			interrupts = <25>;
+			clocks = <&sysclk K210_CLK_AI>;
+			memory-region = <&ai_reserved>;
+			status = "disabled";
+		};
+
+		fft0: fft at 42000000 {
+			compatible = "kendryte,k210-fft";
+			reg = <0x42000000 0x400000>;
+			interrupts = <26>;
+			clocks = <&sysclk K210_CLK_FFT>;
+			resets = <&sysrst K210_RST_FFT>;
+			status = "disabled";
+		};
+
+		dmac0: dma-controller at 50000000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0x50000000 0x1000>;
+			interrupts = <27 28 29 30 31 32>;
+			clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
+			clock-names = "core-clk", "cfgr-clk";
+			resets = <&sysrst K210_RST_DMA>;
+			dma-channels = <6>;
+			snps,dma-masters = <2>;
+			snps,data-width = <5>;
+			snps,block-size = <0x400000 0x400000 0x400000
+					   0x400000 0x400000 0x400000>;
+			snps,axi-max-burst-len = <256>;
+			status = "disabled";
+		};
+
+		apb0: bus at 50200000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "kendryte,k210-apb", "simple-pm-bus";
+			ranges;
+			clocks = <&sysclk K210_CLK_APB0>;
+
+			gpio1: gpio-controller at 50200000 {
+				#gpio-cells = <2>;
+				compatible = "kendryte,k210-gpio";
+				reg = <0x50200000 0x80>;
+				gpio-controller;
+				interrupts = <23>;
+				clocks = <&sysclk K210_CLK_GPIO>;
+				resets = <&sysrst K210_RST_GPIO>;
+				status = "disabled";
+			};
+
+			uart1: serial at 50210000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <50210000 0x100>;
+				interrupts = <11>;
+				clocks = <&sysclk K210_CLK_UART1>;
+				resets = <&sysrst K210_RST_UART1>;
+				reg-io-width = <4>;
+				dcd-override;
+				dsr-override;
+				cts-override;
+				ri-override;
+				status = "disabled";
+			};
+
+			uart2: serial at 50220000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <50220000 0x100>;
+				interrupts = <12>;
+				clocks = <&sysclk K210_CLK_UART2>;
+				resets = <&sysrst K210_RST_UART2>;
+				reg-io-width = <4>;
+				dcd-override;
+				dsr-override;
+				cts-override;
+				ri-override;
+				status = "disabled";
+			};
+
+			uart3: serial at 50230000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <50230000 0x100>;
+				interrupts = <13>;
+				clocks = <&sysclk K210_CLK_UART3>;
+				resets = <&sysrst K210_RST_UART3>;
+				reg-io-width = <4>;
+				dcd-override;
+				dsr-override;
+				cts-override;
+				ri-override;
+				status = "disabled";
+			};
+
+			spi2: spi at 50240000 {
+				compatible = "kendryte,k120-spislave",
+					     "snps,dw-apb-ssi";
+				spi-slave;
+				reg = <0x50240000 0x100>;
+				interrupts = <2>;
+				clocks = <&sysclk K210_CLK_SPI2>;
+				resets = <&sysrst K210_RST_SPI2>;
+				spi-max-frequency = <25000000>;
+				snps,tmod-offset = <8>;
+				status = "disabled";
+			};
+
+			i2s0: i2s at 50250000 {
+				compatible = "snps,designware-i2s";
+				reg = <0x50250000 0x200>;
+				interrupts = <5>;
+				clocks = <&sysclk K210_CLK_I2S0>;
+				resets = <&sysrst K210_RST_I2S0>;
+				status = "disabled";
+			};
+
+			apu0: sound at 520250200 {
+				compatible = "unknown";
+				reg = <0x50250200 0x200>;
+				status = "disabled";
+			};
+
+			i2s1: i2s at 50260000 {
+				compatible = "snps,designware-i2s";
+				reg = <0x50260000 0x200>;
+				interrupts = <6>;
+				clocks = <&sysclk K210_CLK_I2S1>;
+				resets = <&sysrst K210_RST_I2S1>;
+				status = "disabled";
+			};
+
+			i2s2: i2s at 50270000 {
+				compatible = "snps,designware-i2s";
+				reg = <0x50270000 0x200>;
+				interrupts = <7>;
+				clocks = <&sysclk K210_CLK_I2S2>;
+				resets = <&sysrst K210_RST_I2S2>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at 50280000 {
+				compatible = "snps,designware-i2c";
+				reg = <0x50280000 0x100>;
+				interrupts = <8>;
+				clocks = <&sysclk K210_CLK_I2C0>;
+				resets = <&sysrst K210_RST_I2C0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 50290000 {
+				compatible = "snps,designware-i2c";
+				reg = <0x50290000 0x100>;
+				interrupts = <9>;
+				clocks = <&sysclk K210_CLK_I2C1>;
+				resets = <&sysrst K210_RST_I2C1>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 502A0000 {
+				compatible = "snps,designware-i2c";
+				reg = <0x502A0000 0x100>;
+				interrupts = <10>;
+				clocks = <&sysclk K210_CLK_I2C2>;
+				resets = <&sysrst K210_RST_I2C2>;
+				status = "disabled";
+			};
+
+			fpioa: pinmux at 502B0000 {
+				#pinctrl-cells = <1>;
+				compatible = "kendryte,k210-fpioa";
+				reg = <0x502B0000 0x100>;
+				clocks = <&sysclk K210_CLK_FPIOA>;
+				resets = <&sysrst K210_RST_FPIOA>;
+				status = "disabled";
+			};
+
+			sha256: sha256 at 502C0000 {
+				compatible = "kendryte,k210-sha256";
+				reg = <0x502C0000 0x100>;
+				clocks = <&sysclk K210_CLK_SHA>;
+				resets = <&sysrst K210_RST_SHA>;
+				status = "disabled";
+			};
+
+			timer0: timer at 502D0000 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x502D0000 0x100>;
+				interrupts = <14 15>;
+				clocks = <&sysclk K210_CLK_TIMER0>;
+				clock-names = "timer";
+				resets = <&sysrst K210_RST_TIMER0>;
+				status = "disabled";
+			};
+
+			timer1: timer at 502E0000 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x502E0000 0x100>;
+				interrupts = <16 17>;
+				clocks = <&sysclk K210_CLK_TIMER1>;
+				clock-names = "timer";
+				resets = <&sysrst K210_RST_TIMER1>;
+				status = "disabled";
+			};
+
+			timer2: timer at 502F0000 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x502F0000 0x100>;
+				interrupts = <18 19>;
+				clocks = <&sysclk K210_CLK_TIMER2>;
+				clock-names = "timer";
+				resets = <&sysrst K210_RST_TIMER2>;
+				status = "disabled";
+			};
+		};
+
+		apb1: bus at 50400000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "kendryte,k210-apb", "simple-pm-bus";
+			ranges;
+			clocks = <&sysclk K210_CLK_APB1>;
+
+			wdt0: watchdog at 50400000 {
+				compatible = "snps,dw-wdt";
+				reg = <0x50400000 0x100>;
+				interrupts = <21>;
+				clocks = <&sysclk K210_CLK_WDT0>;
+				resets = <&sysrst K210_RST_WDT0>;
+				status = "disabled";
+			};
+
+			wdt1: watchdog at 50410000 {
+				compatible = "snps,dw-wdt";
+				reg = <0x50410000 0x100>;
+				interrupts = <22>;
+				clocks = <&sysclk K210_CLK_WDT1>;
+				resets = <&sysrst K210_RST_WDT1>;
+				status = "disabled";
+			};
+
+			otp0: nvmem at 50420000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "kendryte,k210-otp";
+				reg = <0x50420000 0x100>,
+				      <0x88000000 0x20000>;
+				reg-names = "reg", "mem";
+				clocks = <&sysclk K210_CLK_ROM>;
+				resets = <&sysrst K210_RST_ROM>;
+				read-only;
+				status = "disabled";
+
+				/* Bootloader */
+				firmware at 00000 {
+					reg = <0x00000 0xc200>;
+				};
+
+				/*
+				 * Some kind of hardware description
+				 * 0x100c has a pointer to here, preceded by the
+				 * magic bytes "MInuX". This probably referrs to
+				 * a person named "minux" c.f. credits at 1f000
+				 */
+				minux at 1c000 {
+					reg = <0x1c000 0x1000>;
+				};
+
+				/*
+				 * Device tree containing only registers,
+				 * interrupts, and cpus
+				 */
+				fdt at 1d000 {
+					reg = <0x1d000 0x2000>;
+				};
+
+				/* CPU/ROM credits */
+				credits at 1f000 {
+					reg = <0x1f000 0x1000>;
+				};
+			};
+
+			dvp0: camera at 50430000 {
+				compatible = "none";
+				reg = <0x50430000 0x100>;
+				interrupts = <24>;
+				clocks = <&sysclk K210_CLK_DVP>;
+				resets = <&sysrst K210_RST_DVP>;
+				status = "disabled";
+			};
+
+			sysctl: syscon at 50440000 {
+				compatible = "kendryte,k210-sysctl",
+					     "syscon", "simple-mfd";
+				reg = <0x50440000 0x100>;
+				reg-io-width = <4>;
+
+				sysclk: clock-controller {
+					compatible = "kendryte,k210-clk";
+					clocks = <&in0>;
+					#clock-cells = <1>;
+				};
+
+				sysrst: reset-controller {
+					compatible = "kendryte,k210-rst",
+						     "syscon-reset";
+					#reset-cells = <1>;
+					regmap = <&sysctl>;
+					offset = <K210_SYSCTL_PERI_RESET>;
+					mask = <0x27FFFFFF>;
+					assert-high = <1>;
+				};
+
+				reboot {
+					compatible = "syscon-reboot";
+					regmap = <&sysctl>;
+					offset = <K210_SYSCTL_SOFT_RESET>;
+					mask = <1>;
+					value = <1>;
+				};
+			};
+
+			aes0: aes at 50450000 {
+				compatible = "kendryte,k210-aes";
+				reg = <0x50450000 0x100>;
+				clocks = <&sysclk K210_CLK_AES>;
+				resets = <&sysrst K210_RST_AES>;
+				status = "disabled";
+			};
+
+			rtc: rts at 50460000 {
+				compatible = "unknown";
+				reg = <0x50460000 0x100>;
+				clocks = <&in0>;
+				resets = <&sysrst K210_RST_RTC>;
+				interrupts = <20>;
+				status = "disabled";
+			};
+		};
+
+		apb2: bus at 52000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "kendryte,k210-apb", "simple-pm-bus";
+			ranges;
+			clocks = <&sysclk K210_CLK_APB2>;
+
+			spi0: spi at 52000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "kendryte,k210-spi",
+					     "snps,dw-apb-ssi";
+				reg = <0x52000000 0x100>;
+				interrupts = <1>;
+				clocks = <&sysclk K210_CLK_SPI0>;
+				clock-names = "ssi_clk";
+				resets = <&sysrst K210_RST_SPI0>;
+				spi-max-frequency = <25000000>;
+				num-cs = <4>;
+				reg-io-width = <4>;
+				snps,dfs-offset = <16>;
+				snps,frf-offset = <21>;
+				snps,tmod-offset = <8>;
+				snps,mode-offset = <6>;
+				status = "disabled";
+			};
+
+			spi1: spi at 53000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "kendryte,k210-spi",
+					     "snps,dw-apb-ssi";
+				reg = <0x53000000 0x100>;
+				interrupts = <2>;
+				clocks = <&sysclk K210_CLK_SPI1>;
+				clock-names = "ssi_clk";
+				resets = <&sysrst K210_RST_SPI1>;
+				spi-max-frequency = <25000000>;
+				num-cs = <4>;
+				reg-io-width = <4>;
+				snps,dfs-offset = <16>;
+				snps,frf-offset = <21>;
+				snps,tmod-offset = <8>;
+				snps,mode-offset = <6>;
+				status = "disabled";
+			};
+
+			spi3: spi at 54000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "kendryte,k210-spi",
+					     "snps,dw-apb-ssi";
+				reg = <0x54000000 0x200>;
+				interrupts = <4>;
+				clocks = <&sysclk K210_CLK_SPI3>;
+				clock-names = "ssi_clk";
+				resets = <&sysrst K210_RST_SPI3>;
+				spi-max-frequency = <100000000>;
+				num-cs = <4>;
+				reg-io-width = <4>;
+				snps,dfs-offset = <0>;
+				snps,frf-offset = <22>;
+				snps,tmod-offset = <10>;
+				snps,mode-offset = <8>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h
index 7c471f9893..79460fb5b6 100644
--- a/include/dt-bindings/clock/k210-sysctl.h
+++ b/include/dt-bindings/clock/k210-sysctl.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
  */
 
 #ifndef CLOCK_K210_SYSCTL_H
diff --git a/include/dt-bindings/reset/k210-sysctl.h b/include/dt-bindings/reset/k210-sysctl.h
new file mode 100644
index 0000000000..12bb3880d9
--- /dev/null
+++ b/include/dt-bindings/reset/k210-sysctl.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef RESET_K210_SYSCTL_H
+#define RESET_K210_SYSCTL_H
+
+#define K210_RST_ROM    0
+#define K210_RST_DMA    1
+#define K210_RST_AI     2
+#define K210_RST_DVP    3
+#define K210_RST_FFT    4
+#define K210_RST_GPIO   5
+#define K210_RST_SPI0   6
+#define K210_RST_SPI1   7
+#define K210_RST_SPI2   8
+#define K210_RST_SPI3   9
+#define K210_RST_I2S0   10
+#define K210_RST_I2S1   11
+#define K210_RST_I2S2   12
+#define K210_RST_I2C0   13
+#define K210_RST_I2C1   14
+#define K210_RST_I2C2   15
+#define K210_RST_UART1  16
+#define K210_RST_UART2  17
+#define K210_RST_UART3  18
+#define K210_RST_AES    19
+#define K210_RST_FPIOA  20
+#define K210_RST_TIMER0 21
+#define K210_RST_TIMER1 22
+#define K210_RST_TIMER2 23
+#define K210_RST_WDT0   24
+#define K210_RST_WDT1   25
+#define K210_RST_SHA    26
+#define K210_RST_RTC    29
+
+#endif /* RESET_K210_SYSCTL_H */
-- 
2.25.0

[PATCH v4 17/17] riscv: Add Sipeed Maix support

[Sean Anderson]

The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.

Documentation for Maix boards is located at
<http://dl.sipeed.com/MAIX/HDK/>.  Documentation for the Kendryte K210 is
located at <https://kendryte.com/downloads/>. However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
<https://github.com/kendryte/kendryte-standalone-sdk>.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
asdf

---

Changes in v4:
- Rework documentation to be organized by board mfg not cpu mfg
- Update docs to reflect working SPI support
- Add proper spi support
- Don't define unneecessary macros in config.h
- Lower the default stack so it isn't clobbered on relocation
- Update MAINTAINERS
- Update copyright

Changes in v3:
- Reorder to be last in the patch series
- Add documentation for the board
- Generate defconfig with "make savedefconfig"
- Update Kconfig to imply most features we need
- Update MAINTAINERS

Changes in v2:
- Select CONFIG_SYS_RISCV_NOCOUNTER
- Imply CONFIG_CLK_K210
- Remove spurious references to CONFIG_ARCH_K210
- Remove many configs from defconfig where the defaults were fine
- Add a few "not set" lines to suppress unneeded defaults
- Reduce pre-reloc malloc space, now that clocks initialization happens
  later

 arch/riscv/Kconfig                 |  4 ++
 board/sipeed/maix/Kconfig          | 56 ++++++++++++++++++
 board/sipeed/maix/MAINTAINERS      | 11 ++++
 board/sipeed/maix/Makefile         |  5 ++
 board/sipeed/maix/maix.c           |  9 +++
 configs/sipeed_maix_bitm_defconfig | 10 ++++
 doc/board/index.rst                |  1 +
 doc/board/sipeed/index.rst         |  9 +++
 doc/board/sipeed/maix.rst          | 94 ++++++++++++++++++++++++++++++
 include/configs/sipeed-maix.h      | 17 ++++++
 10 files changed, 216 insertions(+)
 create mode 100644 board/sipeed/maix/Kconfig
 create mode 100644 board/sipeed/maix/MAINTAINERS
 create mode 100644 board/sipeed/maix/Makefile
 create mode 100644 board/sipeed/maix/maix.c
 create mode 100644 configs/sipeed_maix_bitm_defconfig
 create mode 100644 doc/board/sipeed/index.rst
 create mode 100644 doc/board/sipeed/maix.rst
 create mode 100644 include/configs/sipeed-maix.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 659d98e33d..709a44759c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
 config TARGET_SIFIVE_FU540
 	bool "Support SiFive FU540 Board"
 
+config TARGET_SIPEED_MAIX
+	bool "Support Sipeed Maix Board"
+
 endchoice
 
 config SYS_ICACHE_OFF
@@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
new file mode 100644
index 0000000000..580c7f06ba
--- /dev/null
+++ b/board/sipeed/maix/Kconfig
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+	default "maix"
+
+config SYS_VENDOR
+	default "sipeed"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "sipeed-maix"
+
+config SYS_TEXT_BASE
+	default 0x80000000
+
+config DEFAULT_DEVICE_TREE
+	default "k210-maix-bit"
+
+config NR_CPUS
+	default 2
+
+config NR_DRAM_BANKS
+	default 3
+
+config SF_DEFAULT_BUS
+	default 3
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select GENERIC_RISCV
+	select RISCV_PRIV_1_9_1
+	imply DM_SERIAL
+	imply SIFIVE_SERIAL
+	imply SIFIVE_CLINT
+	imply POWER_DOMAIN
+	imply SIMPLE_PM_BUS
+	imply CLK_CCF
+	imply CLK_COMPOSITE_CCF
+	imply CLK_K210
+	imply DM_RESET
+	imply RESET_SYSCON
+	imply SYSRESET
+	imply SYSRESET_SYSCON
+	imply SPI
+	imply DESIGNWARE_SPI
+	imply SPI_FLASH_WINBOND
+	imply MMC
+	imply MMC_SPI
+	imply MMC_BROKEN_CD
+	imply CMD_MMC
+endif
diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS
new file mode 100644
index 0000000000..1f33882e1e
--- /dev/null
+++ b/board/sipeed/maix/MAINTAINERS
@@ -0,0 +1,11 @@
+Sipeed Maix BOARD
+M:	Sean Anderson <seanga2@gmail.com>
+S:	Maintained
+F:	arch/riscv/dts/k210.dtsi
+F:	arch/riscv/dts/k210-maix-bit.dts
+F:	board/sipeed/maix/
+F:	configs/sipeed_maix_defconfig
+F:	doc/board/sipeed/
+F:	include/configs/sipeed-maix.h
+F:	include/dt-bindings/*/k210-sysctl.h
+F:	test/dm/k210_pll.c
diff --git a/board/sipeed/maix/Makefile b/board/sipeed/maix/Makefile
new file mode 100644
index 0000000000..4acff5b31e
--- /dev/null
+++ b/board/sipeed/maix/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y += maix.o
diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c
new file mode 100644
index 0000000000..f8e773acf7
--- /dev/null
+++ b/board/sipeed/maix/maix.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
new file mode 100644
index 0000000000..22d814ec7f
--- /dev/null
+++ b/configs/sipeed_maix_bitm_defconfig
@@ -0,0 +1,10 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_SIPEED_MAIX=y
+CONFIG_ARCH_RV64I=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+# CONFIG_AUTOBOOT is not set
+# CONFIG_NET is not set
+# CONFIG_INPUT is not set
+# CONFIG_MTD is not set
+# CONFIG_DM_ETH is not set
+# CONFIG_EFI_LOADER is not set
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 00e72f57cd..1b3abc82f5 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,4 +15,5 @@ Board-specific doc
    intel/index
    renesas/index
    sifive/index
+   sipeed/index
    xilinx/index
diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst
new file mode 100644
index 0000000000..92da47fddd
--- /dev/null
+++ b/doc/board/sipeed/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kendryte
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   maix
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
new file mode 100644
index 0000000000..d31da05f73
--- /dev/null
+++ b/doc/board/sipeed/maix.rst
@@ -0,0 +1,94 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+
+Maix Bit
+========
+
+Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
+a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
+neural network processing and other "ai" tasks. This includes a "KPU" neural
+network processor, an audio processor supporting beamforming reception, and a
+digital video port supporting capture and output at VGA resolution. Other
+peripherals include 8M of SRAM (accessible with and without caching); remappable
+pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
+and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash;
+on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
+ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but
+the boards are fairly similar.
+
+Documentation for Maix boards is available from
+`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
+Documentation for the Kendryte K210 is available from
+`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware
+details are rather lacking, so most technical reference has been taken from the
+`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_.
+
+Build and boot steps
+--------------------
+
+To build u-boot, run
+
+.. code-block:: none
+
+    make sipeed_maix_bitm_defconfig
+    make CROSS_COMPILE=<your cross compile prefix>
+
+To flash u-boot to a maix bit, run
+
+.. code-block:: none
+
+    kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin
+
+Boot output should look like the following:
+
+.. code-block:: none
+
+    
+    U-Boot 2020.01-00465-g1da52c6c9a (Feb 10 2020 - 20:26:50 -0500)
+    
+    DRAM:  8 MiB
+    MMC:
+    In:    serial at 38000000
+    Out:   serial at 38000000
+    Err:   serial at 38000000
+    =>
+
+To boot a payload, first flash it to the board. This can be done by passing the
+``-a <ADDRESS>`` option to kflash. After flashing your payload, load it by
+running
+
+.. code-block:: none
+
+    => sf probe
+    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    => sf read 80000000 <ADDRESS + 5> <SIZE>
+    device 0 offset <ADDRESS + 5>, size <SIZE>
+    SF: <SIZE> bytes @ <ADDRESS + 5> Read: OK
+    => go 80000000
+    ## Starting application at 0x80000000 ...
+
+**NB:** kflash adds a 5-byte header to payloads (and a 32-byte trailer) to all
+payloads it flashes. To load your payload properly, you will need to add 5 bytes
+to the address that you gave to kflash.
+
+The MMC (SD-card reader) does not work yet.
+
+Over- and Under-clocking
+------------------------
+
+To change the clock speed of the K210, you will need to enable
+``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a
+section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following:
+
+.. code-block:: dts
+
+    &sysclk {
+ 	assigned-clocks = <&sysclk K210_CLK_PLL0>;
+ 	assigned-clock-rates = <780000000>;
+    };
+
+There are three PLLs on the K210: PLL0 is the parent of most of the components,
+including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
+PLL2 is the parent of the sound processing devices. Note that child clocks of
+PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is
+running at 800 MHz, then the CPU will run at 400 MHz.
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
new file mode 100644
index 0000000000..ee69a6f22e
--- /dev/null
+++ b/include/configs/sipeed-maix.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef CONFIGS_SIPEED_MAIX_H
+#define CONFIGS_SIPEED_MAIX_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+/* Start just below the second bank */
+#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
+#define CONFIG_SYS_MALLOC_LEN SZ_8K
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#endif /* CONFIGS_SIPEED_MAIX_H */
-- 
2.25.0

[PATCH v4 05/17] dm: Add support for simple-pm-bus

[Simon Glass]

Hi Sean,

On Mon, 10 Feb 2020 at 23:05, Sean Anderson <seanga2@gmail.com> wrote:
>
> This type of bus is used in Linux to designate busses which have power

buses

> domains and/or clocks which need to be enabled before their child devices
> can be used.  Because power domains are automatically enabled before
> probing in u-boot, we just need to enable any clocks present.

U-Boot

>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---

With the above and below fixed:

Reviewed-by: Simon Glass <sjg@chromium.org>

>
> Changes in v4:
> - Split the bus off into its own driver
> - Add test
> - Fix line spacing in Kconfig
> - Lint
>
> Changes in v3:
> - New
>
>  arch/sandbox/dts/test.dts                     |  6 ++
>  arch/sandbox/include/asm/clk.h                |  1 +
>  configs/sandbox_defconfig                     |  1 +
>  .../bus/simple-pm-bus.txt                     | 44 +++++++++++++++
>  drivers/core/Kconfig                          |  7 +++
>  drivers/core/Makefile                         |  1 +
>  drivers/core/simple-pm-bus.c                  | 55 +++++++++++++++++++
>  test/dm/Makefile                              |  1 +
>  test/dm/simple-pm-bus.c                       | 44 +++++++++++++++
>  9 files changed, 160 insertions(+)
>  create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt
>  create mode 100644 drivers/core/simple-pm-bus.c
>  create mode 100644 test/dm/simple-pm-bus.c
>
> diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
> index 23f2aefd43..648f21239a 100644
> --- a/arch/sandbox/dts/test.dts
> +++ b/arch/sandbox/dts/test.dts
> @@ -929,6 +929,12 @@
>                 compatible = "sandbox,mdio";
>         };
>
> +       pm-bus-test {
> +               compatible = "simple-pm-bus";
> +               clocks = <&clk_sandbox 4>;
> +               power-domains = <&pwrdom 1>;
> +       };
> +
>         resetc2: syscon-reset {
>                 compatible = "syscon-reset";
>                 #reset-cells = <1>;
> diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
> index 1573e4a134..c184c4bffc 100644
> --- a/arch/sandbox/include/asm/clk.h
> +++ b/arch/sandbox/include/asm/clk.h
> @@ -21,6 +21,7 @@ enum sandbox_clk_id {
>         SANDBOX_CLK_ID_I2C,
>         SANDBOX_CLK_ID_UART1,
>         SANDBOX_CLK_ID_UART2,
> +       SANDBOX_CLK_ID_BUS,
>
>         SANDBOX_CLK_ID_COUNT,
>  };
> diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> index 19970f1db5..c637b39b96 100644
> --- a/configs/sandbox_defconfig
> +++ b/configs/sandbox_defconfig
> @@ -89,6 +89,7 @@ CONFIG_REGMAP=y
>  CONFIG_SYSCON=y
>  CONFIG_DEVRES=y
>  CONFIG_DEBUG_DEVRES=y
> +CONFIG_SIMPLE_PM_BUS=y
>  CONFIG_ADC=y
>  CONFIG_ADC_SANDBOX=y
>  CONFIG_AXI=y
> diff --git a/doc/device-tree-bindings/bus/simple-pm-bus.txt b/doc/device-tree-bindings/bus/simple-pm-bus.txt
> new file mode 100644
> index 0000000000..6f15037131
> --- /dev/null
> +++ b/doc/device-tree-bindings/bus/simple-pm-bus.txt
> @@ -0,0 +1,44 @@
> +Simple Power-Managed Bus
> +========================
> +
> +A Simple Power-Managed Bus is a transparent bus that doesn't need a real
> +driver, as it's typically initialized by the boot loader.
> +
> +However, its bus controller is part of a PM domain, or under the control of a
> +functional clock.  Hence, the bus controller's PM domain and/or clock must be
> +enabled for child devices connected to the bus (either on-SoC or externally)
> +to function.
> +
> +While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
> +in the Devicetree Specification, it is not an extension of "simple-bus".
> +
> +
> +Required properties:
> +  - compatible: Must contain at least "simple-pm-bus".
> +               Must not contain "simple-bus".
> +               It's recommended to let this be preceded by one or more
> +               vendor-specific compatible values.
> +  - #address-cells, #size-cells, ranges: Must describe the mapping between
> +               parent address and child address spaces.
> +
> +Optional platform-specific properties for clock or PM domain control (at least
> +one of them is required):
> +  - clocks: Must contain a reference to the functional clock(s),
> +  - power-domains: Must contain a reference to the PM domain.
> +Please refer to the binding documentation for the clock and/or PM domain
> +providers for more details.
> +
> +
> +Example:
> +
> +       bsc: bus at fec10000 {
> +               compatible = "renesas,bsc-sh73a0", "renesas,bsc",
> +                            "simple-pm-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges = <0 0 0x20000000>;
> +               reg = <0xfec10000 0x400>;
> +               interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
> +               clocks = <&zb_clk>;
> +               power-domains = <&pd_a4s>;
> +       };
> diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
> index 3b95b5387b..0cd687526e 100644
> --- a/drivers/core/Kconfig
> +++ b/drivers/core/Kconfig
> @@ -195,6 +195,13 @@ config SPL_SIMPLE_BUS
>           Supports the 'simple-bus' driver, which is used on some systems
>           in SPL.
>
> +config SIMPLE_PM_BUS
> +       bool "Support simple-pm-bus driver"
> +       depends on DM && OF_CONTROL && CLK && POWER_DOMAIN
> +       help
> +         Supports the 'simple-pm-bus' driver, which is used for busses that
> +         have power domains and/or clocks which need to be enabled before use.
> +
>  config OF_TRANSLATE
>         bool "Translate addresses using fdt_translate_address"
>         depends on DM && OF_CONTROL
> diff --git a/drivers/core/Makefile b/drivers/core/Makefile
> index bce7467da1..284af7caaa 100644
> --- a/drivers/core/Makefile
> +++ b/drivers/core/Makefile
> @@ -6,6 +6,7 @@ obj-y   += device.o fdtaddr.o lists.o root.o uclass.o util.o
>  obj-$(CONFIG_DEVRES) += devres.o
>  obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE)  += device-remove.o
>  obj-$(CONFIG_$(SPL_)SIMPLE_BUS)        += simple-bus.o
> +obj-$(CONFIG_SIMPLE_PM_BUS)    += simple-pm-bus.o
>  obj-$(CONFIG_DM)       += dump.o
>  obj-$(CONFIG_$(SPL_TPL_)REGMAP)        += regmap.o
>  obj-$(CONFIG_$(SPL_TPL_)SYSCON)        += syscon-uclass.o
> diff --git a/drivers/core/simple-pm-bus.c b/drivers/core/simple-pm-bus.c
> new file mode 100644
> index 0000000000..3ee54531d1
> --- /dev/null
> +++ b/drivers/core/simple-pm-bus.c
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
> + */
> +

common.h

> +#include <dm.h>
> +#include <clk.h>

clk.h above dm.h

> +
> +/*
> + * Power domains are taken care of by driver_probe, so we just have to enable
> + * clocks
> + */
> +static const int simple_pm_bus_probe(struct udevice *dev)
> +{
> +       int ret;
> +       struct clk_bulk *bulk = dev_get_priv(dev);
> +
> +       ret = clk_get_bulk(dev, bulk);
> +       if (ret)
> +               return ret;
> +
> +       ret = clk_enable_bulk(bulk);
> +       if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
> +               clk_release_bulk(bulk);
> +               return ret;
> +       }
> +       return 0;
> +}
> +
> +static const int simple_pm_bus_remove(struct udevice *dev)
> +{
> +       int ret;
> +       struct clk_bulk *bulk = dev_get_priv(dev);
> +
> +       ret = clk_release_bulk(bulk);
> +       if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
> +               return ret;
> +       else
> +               return 0;
> +}
> +
> +static const struct udevice_id simple_pm_bus_ids[] = {
> +       { .compatible = "simple-pm-bus" },
> +       { }
> +};
> +
> +U_BOOT_DRIVER(simple_pm_bus_drv) = {
> +       .name   = "simple_pm_bus",
> +       .id     = UCLASS_SIMPLE_BUS,
> +       .of_match = simple_pm_bus_ids,
> +       .probe = simple_pm_bus_probe,
> +       .remove = simple_pm_bus_remove,
> +       .priv_auto_alloc_size = sizeof(struct clk_bulk),
> +       .flags  = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/test/dm/Makefile b/test/dm/Makefile
> index 1f0e0febb4..a760ab8b14 100644
> --- a/test/dm/Makefile
> +++ b/test/dm/Makefile
> @@ -71,4 +71,5 @@ obj-$(CONFIG_DM_MDIO) += mdio.o
>  obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
>  obj-$(CONFIG_DM_RNG) += rng.o
>  obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
> +obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
>  endif
> diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c
> new file mode 100644
> index 0000000000..1b42415ccd
> --- /dev/null
> +++ b/test/dm/simple-pm-bus.c
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
> + */
> +

Please fix include ordering

https://www.denx.de/wiki/U-Boot/CodingStyle

> +#include <asm/clk.h>
> +#include <asm/power-domain.h>
> +#include <dm.h>
> +#include <dm/test.h>
> +#include <dm/device-internal.h>
> +#include <test/ut.h>
> +
> +/* These must match the ids in the device tree */
> +#define TEST_CLOCK_ID 4
> +#define TEST_POWER_ID 1
> +
> +static int dm_test_simple_pm_bus(struct unit_test_state *uts)
> +{
> +       struct udevice *power;
> +       struct udevice *clock;
> +       struct udevice *bus;
> +
> +       ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN,
> +                                             "power-domain", &power));
> +       ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
> +                                             &clock));
> +       ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID));
> +       ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
> +
> +       ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, "pm-bus-test",
> +                                             &bus));
> +       ut_asserteq(1, sandbox_power_domain_query(power, TEST_POWER_ID));
> +       ut_asserteq(1, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
> +
> +       ut_assertok(device_remove(bus, DM_REMOVE_NORMAL));
> +       /* must re-probe since device_remove also removes the power domain */
> +       ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN,
> +                                             "power-domain", &power));
> +       ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID));
> +       ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID));
> +
> +       return 0;
> +}
> +DM_TEST(dm_test_simple_pm_bus, DM_TESTF_SCAN_FDT);
> --
> 2.25.0
>

Regards,
Simon

[PATCH v4 04/17] reset: Add generic reset driver

[Simon Glass]

On Mon, 10 Feb 2020 at 23:05, Sean Anderson <seanga2@gmail.com> wrote:
>
> This patch adds a generic reset driver. It is designed to be useful when
> one has a register in a regmap which contains bits that reset other
> devices. I thought this seemed like a very generic use, so here is a
> generic driver. The overall structure has been modeled on the syscon-reboot
> driver.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v4:
> - Added basic test
> - Fix incorrect usage of regmap_update_bits
>
> Changes in v3:
> - New
>
>  arch/sandbox/dts/test.dts                     | 15 ++++
>  configs/sandbox_defconfig                     |  1 +
>  .../reset/syscon-reset.txt                    | 36 +++++++++
>  drivers/reset/Kconfig                         |  5 ++
>  drivers/reset/Makefile                        |  1 +
>  drivers/reset/reset-syscon.c                  | 79 +++++++++++++++++++
>  test/dm/Makefile                              |  1 +
>  test/dm/syscon-reset.c                        | 58 ++++++++++++++
>  8 files changed, 196 insertions(+)
>  create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt
>  create mode 100644 drivers/reset/reset-syscon.c
>  create mode 100644 test/dm/syscon-reset.c

Please fix the include-file ordering fixed in the two .c files in this
patch. Then:

Reviewed-by: Simon Glass <sjg@chromium.org>

[PATCH v4 06/17] spi: dw: Add device tree properties for fields in CTRL1

[Simon Glass]

On Mon, 10 Feb 2020 at 23:05, Sean Anderson <seanga2@gmail.com> wrote:
>
> Some devices have different layouts for the fields in CTRL1 (e.g. the
> Kendryte K210). Allow this layout to be configurable from the device tree.
> The documentation has been taken from Linux.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v4:
> - New
>
>  .../spi/snps,dw-apb-ssi.txt                   | 43 +++++++++++++++++++
>  drivers/spi/designware_spi.c                  | 40 ++++++++++-------
>  2 files changed, 68 insertions(+), 15 deletions(-)
>  create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[PATCH v4 05/17] dm: Add support for simple-pm-bus

[Sean Anderson]

Hi Simon,

On 2/11/20 12:14 PM, Simon Glass wrote:
> Hi Sean,
> 
> On Mon, 10 Feb 2020 at 23:05, Sean Anderson <seanga2@gmail.com> wrote:
>>
>> This type of bus is used in Linux to designate busses which have power
> 
> buses
> 
>> domains and/or clocks which need to be enabled before their child devices
>> can be used.  Because power domains are automatically enabled before
>> probing in u-boot, we just need to enable any clocks present.
> 
> U-Boot
> 
>>
>> Signed-off-by: Sean Anderson <seanga2@gmail.com>
>> ---
> 
> With the above and below fixed:
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 

Will do, thanks.

>> diff --git a/drivers/core/simple-pm-bus.c b/drivers/core/simple-pm-bus.c
>> new file mode 100644
>> index 0000000000..3ee54531d1
>> --- /dev/null
>> +++ b/drivers/core/simple-pm-bus.c
>> @@ -0,0 +1,55 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
>> + */
>> +
> 
> common.h
> 
>> +#include <dm.h>
>> +#include <clk.h>
> 
> clk.h above dm.h
> 
>> diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c
>> new file mode 100644
>> index 0000000000..1b42415ccd
>> --- /dev/null
>> +++ b/test/dm/simple-pm-bus.c
>> @@ -0,0 +1,44 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
>> + */
>> +
> 
> Please fix include ordering
> 
> https://www.denx.de/wiki/U-Boot/CodingStyle

Ah, I wasn't aware that there was a specific ordering; I had been doing
it alphabetically.

--Sean

[PATCH v4 06/17] spi: dw: Add device tree properties for fields in CTRL1

[Rick Chen]

Hi Sean

> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Sean Anderson
> Sent: Tuesday, February 11, 2020 2:04 PM
> To: u-boot at lists.denx.de
> Cc: Rick Chen; Eugeniy Paltsev
> Subject: [PATCH v4 06/17] spi: dw: Add device tree properties for fields in CTRL1
>
> Some devices have different layouts for the fields in CTRL1 (e.g. the Kendryte K210). Allow this layout to be configurable from the device tree.

The description of CTRL1 here don't match with the below content of CTRL0.
Is it a typo ?

Thanks
Rick

> The documentation has been taken from Linux.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v4:
> - New
>
>  .../spi/snps,dw-apb-ssi.txt                   | 43 +++++++++++++++++++
>  drivers/spi/designware_spi.c                  | 40 ++++++++++-------
>  2 files changed, 68 insertions(+), 15 deletions(-)  create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
>
> diff --git a/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
> new file mode 100644
> index 0000000000..4b6152f6b7
> --- /dev/null
> +++ b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
> @@ -0,0 +1,43 @@
> +Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
> +
> +Required properties:
> +- compatible : "snps,dw-apb-ssi"
> +- reg : The register base for the controller. For "mscc,<soc>-spi", a
> +second
> +  register set is required (named ICPU_CFG:SPI_MST)
> +- #address-cells : <1>, as required by generic SPI binding.
> +- #size-cells : <0>, also as required by generic SPI binding.
> +- clocks : phandles for the clocks, see the description of clock-names below.
> +   The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
> +   is optional. If a single clock is specified but no clock-name, it is the
> +   "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
> +
> +Optional properties:
> +- clock-names : Contains the names of the clocks:
> +    "ssi_clk", for the core clock used to generate the external SPI clock.
> +    "pclk", the interface clock, required for register access.
> +- cs-gpios : Specifies the gpio pins to be used for chipselects.
> +- num-cs : The number of chipselects. If omitted, this will default to 4.
> +- reg-io-width : The I/O register width (in bytes) implemented by this
> +  device.  Supported values are 2 or 4 (the default).
> +- snps,dfs-offset The offset in bits of the DFS field in CTRL0,
> +defaulting to 0
> +- snps,frf-offset The offset in bits of the FRF field in CTRL0,
> +defaulting to 4
> +- snps,tmod-offset The offset in bits of the tmode field in CTRL0,
> +defaulting
> +  to 6
> +- snps,mode-offset The offset in bits of the work mode field in CTRL0,
> +  defaulting to 8
> +
> +Child nodes as per the generic SPI binding.
> +
> +Example:
> +
> +       spi at fff00000 {
> +               compatible = "snps,dw-apb-ssi";
> +               reg = <0xfff00000 0x1000>;
> +               interrupts = <0 154 4>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               clocks = <&spi_m_clk>;
> +               num-cs = <2>;
> +               cs-gpios = <&gpio0 13 0>,
> +                          <&gpio0 14 0>;
> +       };
> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 66ff8eeccd..04cc873754 100644
> --- a/drivers/spi/designware_spi.c
> +++ b/drivers/spi/designware_spi.c
> @@ -3,6 +3,7 @@
>   * Designware master SPI core controller driver
>   *
>   * Copyright (C) 2014 Stefan Roese <sr@denx.de>
> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
>   *
>   * Very loosely based on the Linux driver:
>   * drivers/spi/spi-dw.c, which is:
> @@ -50,20 +51,14 @@
>  #define DW_SPI_DR                      0x60
>
>  /* Bit fields in CTRLR0 */
> -#define SPI_DFS_OFFSET                 0
> -
> -#define SPI_FRF_OFFSET                 4
>  #define SPI_FRF_SPI                    0x0
>  #define SPI_FRF_SSP                    0x1
>  #define SPI_FRF_MICROWIRE              0x2
>  #define SPI_FRF_RESV                   0x3
>
> -#define SPI_MODE_OFFSET                        6
> -#define SPI_SCPH_OFFSET                        6
> -#define SPI_SCOL_OFFSET                        7
> +#define SPI_MODE_SCPH                  0x1
> +#define SPI_MODE_SCOL                  0x2
>
> -#define SPI_TMOD_OFFSET                        8
> -#define SPI_TMOD_MASK                  (0x3 << SPI_TMOD_OFFSET)
>  #define        SPI_TMOD_TR                     0x0             /* xmit & recv */
>  #define SPI_TMOD_TO                    0x1             /* xmit only */
>  #define SPI_TMOD_RO                    0x2             /* recv only */
> @@ -88,6 +83,12 @@
>  struct dw_spi_platdata {
>         s32 frequency;          /* Default clock frequency, -1 for none */
>         void __iomem *regs;
> +
> +       /* Offsets in CTRL0 */
> +       u8 dfs_off;
> +       u8 frf_off;
> +       u8 tmod_off;
> +       u8 mode_off;
>  };
>
>  struct dw_spi_priv {
> @@ -114,6 +115,15 @@ struct dw_spi_priv {
>         struct reset_ctl_bulk   resets;
>  };
>
> +static inline u32 GEN_CTRL0(struct dw_spi_priv *priv,
> +                           struct dw_spi_platdata *plat)
> +{
> +       return ((priv->bits_per_word - 1) << plat->dfs_off |
> +             (priv->type << plat->frf_off) |
> +             (priv->mode << plat->mode_off) |
> +             (priv->tmode << plat->tmod_off)); }
> +
>  static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)  {
>         return __raw_readl(priv->regs + offset); @@ -159,6 +169,10 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
>         /* Use 500KHz as a suitable default */
>         plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
>                                                500000);
> +       plat->dfs_off = dev_read_u32_default(bus, "snps,dfs-offset", 0);
> +       plat->frf_off = dev_read_u32_default(bus, "snps,frf-offset", 4);
> +       plat->mode_off = dev_read_u32_default(bus, "snps,mode-offset", 6);
> +       plat->tmod_off = dev_read_u32_default(bus, "snps,tmod-offset", 8);
>         debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
>               plat->frequency);
>
> @@ -387,6 +401,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
>                        const void *dout, void *din, unsigned long flags)  {
>         struct udevice *bus = dev->parent;
> +       struct dw_spi_platdata *plat = dev_get_platdata(bus);
>         struct dw_spi_priv *priv = dev_get_priv(bus);
>         const u8 *tx = dout;
>         u8 *rx = din;
> @@ -405,10 +420,6 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
>         if (flags & SPI_XFER_BEGIN)
>                 external_cs_manage(dev, false);
>
> -       cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
> -               (priv->mode << SPI_MODE_OFFSET) |
> -               (priv->tmode << SPI_TMOD_OFFSET);
> -
>         if (rx && tx)
>                 priv->tmode = SPI_TMOD_TR;
>         else if (rx)
> @@ -420,8 +431,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
>                  */
>                 priv->tmode = SPI_TMOD_TR;
>
> -       cr0 &= ~SPI_TMOD_MASK;
> -       cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
> +       cr0 = GEN_CTRL0(priv, plat);
>
>         priv->len = bitlen >> 3;
>         debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len); @@ -475,7 +485,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
>
>  static int dw_spi_set_speed(struct udevice *bus, uint speed)  {
> -       struct dw_spi_platdata *plat = bus->platdata;
> +       struct dw_spi_platdata *plat = dev_get_platdata(bus);
>         struct dw_spi_priv *priv = dev_get_priv(bus);
>         u16 clk_div;
>
> --
> 2.25.0
>

[PATCH v4 12/17] riscv: Add a bypass clock for K210

[Rick Chen]

Hi Sean

This patch is relative about clock driver.
It shall be named as clk instead of riscv
Thanks
Rick

> This is a small driver to do a software bypass of a clock if hardware
> bypass is not working. I have tried to write this in a generic fashion, so
> that it could be potentially broken out of the kendryte code at some future
> date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
> so that the CPU keeps on working.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v4:
> - New
>
>  drivers/clk/kendryte/Makefile |   2 +-
>  drivers/clk/kendryte/bypass.c | 268 ++++++++++++++++++++++++++++++++++
>  include/kendryte/bypass.h     |  28 ++++
>  3 files changed, 297 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/kendryte/bypass.c
>  create mode 100644 include/kendryte/bypass.h
>
> diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
> index c56d93ea1c..47f682fce3 100644
> --- a/drivers/clk/kendryte/Makefile
> +++ b/drivers/clk/kendryte/Makefile
> @@ -1 +1 @@
> -obj-y += pll.o
> +obj-y += bypass.o pll.o
> diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
> new file mode 100644
> index 0000000000..5276591bfd
> --- /dev/null
> +++ b/drivers/clk/kendryte/bypass.c
> @@ -0,0 +1,268 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
> + */
> +
> +#include <kendryte/bypass.h>
> +
> +#include <clk-uclass.h>
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#define LOG_CATEGORY UCLASS_CLK
> +#include <log.h>
> +#include <serial.h>
> +
> +#define CLK_K210_BYPASS "k210_clk_bypass"
> +
> +/*
> + * This is a small driver to do a software bypass of a clock if hardware bypass
> + * is not working. I have tried to write this in a generic fashion, so that it
> + * could be potentially broken out of the kendryte code at some future date.
> + *
> + * Say you have the following clock configuration
> + *
> + * +---+ +---+
> + * |osc| |pll|
> + * +---+ +---+
> + *         ^
> + *        /|
> + *       / |
> + *      /  |
> + *     /   |
> + *    /    |
> + * +---+ +---+
> + * |clk| |clk|
> + * +---+ +---+
> + *
> + * But the pll does not have a bypass, so when you configure the pll, the
> + * configuration needs to change to look like
> + *
> + * +---+ +---+
> + * |osc| |pll|
> + * +---+ +---+
> + *   ^
> + *   |\
> + *   | \
> + *   |  \
> + *   |   \
> + *   |    \
> + * +---+ +---+
> + * |clk| |clk|
> + * +---+ +---+
> + *
> + * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
> + * creating the child clocks, set their parent to the bypass clock. After
> + * creating all the children, call k210_bypass_setchildren().
> + */
> +
> +static int k210_bypass_dobypass(struct k210_bypass *bypass)
> +{
> +       int ret, i;
> +
> +       /*
> +        * If we already have saved parents, then the children are already
> +        * bypassed
> +        */
> +       if (bypass->child_count && bypass->saved_parents[0])
> +               return 0;
> +
> +       for (i = 0; i < bypass->child_count; i++) {
> +               struct clk *child = bypass->children[i];
> +               struct clk *parent = clk_get_parent(child);
> +
> +               if (IS_ERR(parent)) {
> +                       for (; i; i--)
> +                               bypass->saved_parents[i] = NULL;
> +                       return PTR_ERR(parent);
> +               }
> +               bypass->saved_parents[i] = parent;
> +       }
> +
> +       for (i = 0; i < bypass->child_count; i++) {
> +               struct clk *child = bypass->children[i];
> +
> +               ret = clk_set_parent(child, bypass->alt);
> +               if (ret) {
> +                       for (; i; i--)
> +                               clk_set_parent(bypass->children[i],
> +                                              bypass->saved_parents[i]);
> +                       for (i = 0; i < bypass->child_count; i++)
> +                               bypass->saved_parents[i] = NULL;
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int k210_bypass_unbypass(struct k210_bypass *bypass)
> +{
> +       int err, ret, i;
> +
> +       if (!bypass->child_count && !bypass->saved_parents[0]) {
> +               log_warning("Cannot unbypass children; dobypass not called first\n");
> +               return 0;
> +       }
> +
> +       ret = 0;
> +       for (i = 0; i < bypass->child_count; i++) {
> +               err = clk_set_parent(bypass->children[i],
> +                                    bypass->saved_parents[i]);
> +               if (err)
> +                       ret = err;
> +               bypass->saved_parents[i] = NULL;
> +       }
> +       return ret;
> +}
> +
> +static ulong k210_bypass_get_rate(struct clk *clk)
> +{
> +       struct k210_bypass *bypass = to_k210_bypass(clk);
> +       const struct clk_ops *ops = bypass->bypassee_ops;
> +
> +       if (ops->get_rate)
> +               return ops->get_rate(bypass->bypassee);
> +       else
> +               return clk_get_parent_rate(bypass->bypassee);
> +}
> +
> +static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
> +{
> +       int ret;
> +       struct k210_bypass *bypass = to_k210_bypass(clk);
> +       const struct clk_ops *ops = bypass->bypassee_ops;
> +
> +       /* Don't bother bypassing if we aren't going to set the rate */
> +       if (!ops->set_rate)
> +               return k210_bypass_get_rate(clk);
> +
> +       ret = k210_bypass_dobypass(bypass);
> +       if (ret)
> +               return ret;
> +
> +       ret = ops->set_rate(bypass->bypassee, rate);
> +       if (ret < 0)
> +               return ret;
> +
> +       return k210_bypass_unbypass(bypass);
> +}
> +
> +static int k210_bypass_set_parent(struct clk *clk, struct clk *parent)
> +{
> +       struct k210_bypass *bypass = to_k210_bypass(clk);
> +       const struct clk_ops *ops = bypass->bypassee_ops;
> +
> +       if (ops->set_parent)
> +               return ops->set_parent(bypass->bypassee, parent);
> +       else
> +               return -ENOTSUPP;
> +}
> +
> +/*
> + * For these next two functions, do the bypassing even if there is no
> + * en-/-disable function, since the bypassing itself can be observed in between
> + * calls.
> + */
> +static int k210_bypass_enable(struct clk *clk)
> +{
> +       int ret;
> +       struct k210_bypass *bypass = to_k210_bypass(clk);
> +       const struct clk_ops *ops = bypass->bypassee_ops;
> +
> +       ret = k210_bypass_dobypass(bypass);
> +       if (ret)
> +               return ret;
> +
> +       if (ops->enable)
> +               ret = ops->enable(bypass->bypassee);
> +       else
> +               ret = 0;
> +       if (ret)
> +               return ret;
> +
> +       return k210_bypass_unbypass(bypass);
> +}
> +
> +static int k210_bypass_disable(struct clk *clk)
> +{
> +       int ret;
> +       struct k210_bypass *bypass = to_k210_bypass(clk);
> +       const struct clk_ops *ops = bypass->bypassee_ops;
> +
> +       ret = k210_bypass_dobypass(bypass);
> +       if (ret)
> +               return ret;
> +
> +       if (ops->disable)
> +               return ops->disable(bypass->bypassee);
> +       else
> +               return 0;
> +}
> +
> +static const struct clk_ops k210_bypass_ops = {
> +       .get_rate = k210_bypass_get_rate,
> +       .set_rate = k210_bypass_set_rate,
> +       .set_parent = k210_bypass_set_parent,
> +       .enable = k210_bypass_enable,
> +       .disable = k210_bypass_disable,
> +};
> +
> +int k210_bypass_set_children(struct clk *clk, struct clk **children,
> +                            size_t child_count)
> +{
> +       struct k210_bypass *bypass = to_k210_bypass(clk);
> +
> +       kfree(bypass->saved_parents);
> +       if (child_count) {
> +               bypass->saved_parents =
> +                       kcalloc(child_count, sizeof(struct clk *), GFP_KERNEL);
> +               if (!bypass->saved_parents)
> +                       return -ENOMEM;
> +       }
> +       bypass->child_count = child_count;
> +       bypass->children = children;
> +
> +       return 0;
> +}
> +
> +static struct k210_bypass *k210_clk_comp_bypass(struct clk *bypassee,
> +                                               const struct clk_ops *bypassee_ops,
> +                                               struct clk *alt)
> +{
> +       struct k210_bypass *bypass;
> +
> +       bypass = kzalloc(sizeof(*bypass), GFP_KERNEL);
> +       if (!bypass)
> +               return bypass;
> +
> +       bypass->bypassee = bypassee;
> +       bypass->bypassee_ops = bypassee_ops;
> +       bypass->alt = alt;
> +       return bypass;
> +}
> +
> +struct clk *k210_clk_bypass(const char *name, const char *parent_name,
> +                           struct clk *bypassee,
> +                           const struct clk_ops *bypassee_ops, struct clk *alt)
> +{
> +       int err;
> +       struct k210_bypass *bypass;
> +
> +       bypass = k210_clk_comp_bypass(bypassee, bypassee_ops, alt);
> +       if (!bypass)
> +               return ERR_PTR(-ENOMEM);
> +
> +       err = clk_register(&bypass->clk, CLK_K210_BYPASS, name, parent_name);
> +       if (err) {
> +               kfree(bypass);
> +               return ERR_PTR(err);
> +       }
> +       bypassee->dev = bypass->clk.dev;
> +       return &bypass->clk;
> +}
> +
> +U_BOOT_DRIVER(k210_bypass) = {
> +       .name   = CLK_K210_BYPASS,
> +       .id     = UCLASS_CLK,
> +       .ops    = &k210_bypass_ops,
> +};
> diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h
> new file mode 100644
> index 0000000000..3093057324
> --- /dev/null
> +++ b/include/kendryte/bypass.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
> + */
> +#ifndef K210_BYPASS_H
> +#define K210_BYPASS_H
> +
> +#include <clk.h>
> +
> +struct k210_bypass {
> +       struct clk clk;
> +       struct clk **children; /* Clocks to reparent */
> +       struct clk **saved_parents; /* Parents saved over en-/dis-able */
> +       struct clk *bypassee; /* Clock to bypass */
> +       const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */
> +       struct clk *alt; /* Clock to set children to when bypassing */
> +       size_t child_count;
> +};
> +
> +#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk)
> +
> +int k210_bypass_set_children(struct clk *clk, struct clk **children,
> +                            size_t child_count);
> +struct clk *k210_clk_bypass(const char *name, const char *parent_name,
> +                           struct clk *bypassee,
> +                           const struct clk_ops *bypassee_ops,
> +                           struct clk *alt);
> +#endif /* K210_BYPASS_H */
> --
> 2.25.0
>

[PATCH v4 06/17] spi: dw: Add device tree properties for fields in CTRL1

[Sean Anderson]

On 2/18/20 1:05 AM, Rick Chen wrote:
> Hi Sean
> 
>> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Sean Anderson
>> Sent: Tuesday, February 11, 2020 2:04 PM
>> To: u-boot at lists.denx.de
>> Cc: Rick Chen; Eugeniy Paltsev
>> Subject: [PATCH v4 06/17] spi: dw: Add device tree properties for fields in CTRL1
>>
>> Some devices have different layouts for the fields in CTRL1 (e.g. the Kendryte K210). Allow this layout to be configurable from the device tree.
> 
> The description of CTRL1 here don't match with the below content of CTRL0.
> Is it a typo ?

Yes. I will fix the message in the next revision.

--Sean

[PATCH v4 12/17] riscv: Add a bypass clock for K210

[Sean Anderson]

On 2/18/20 1:35 AM, Rick Chen wrote:
> Hi Sean
> 
> This patch is relative about clock driver.
> It shall be named as clk instead of riscv
> Thanks
> Rick

Should the other clock patches adding k210 clock support be prefixed
"clk:" as well?

--Sean

[PATCH v4 12/17] riscv: Add a bypass clock for K210

[Rick Chen]

Hi Sean

> On 2/18/20 1:35 AM, Rick Chen wrote:
> > Hi Sean
> >
> > This patch is relative about clock driver.
> > It shall be named as clk instead of riscv
> > Thanks
> > Rick
>
> Should the other clock patches adding k210 clock support be prefixed
> "clk:" as well?

Sure, patch 11 and 13 as well

Thanks
Rick

>
> --Sean

[PATCH v4 03/17] clk: Unconditionally recursively en-/dis-able clocks

[Rick Chen]

Hi Sean

> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> just enable them as normal. The enable count is local to the struct clk,
> but this will never result in the actual en-/dis-able op being called
> (unless the same struct clk is enabled twice).
>
> For clocks in the CCF, we always traverse up the tree when enabling.
> Previously, CCF clocks without id set would be skipped, stopping the
> traversal too early.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> Acked-by: Lukasz Majewski <lukma@denx.de>
> ---
>
> Changes in v4:
> - Lint
>
> Changes in v3:
> - New
>
>  drivers/clk/clk-uclass.c | 59 ++++++++++++++++++----------------------
>  1 file changed, 26 insertions(+), 33 deletions(-)
>

When I tried to apply this patch-set, there occur a conflict as below:

Applying: clk: Always use the supplied struct clk
Applying: clk: Check that ops of composite clock components exist before calling
Applying: clk: Unconditionally recursively en-/dis-able clocks
error: patch failed: drivers/clk/clk-uclass.c:491
error: drivers/clk/clk-uclass.c: patch does not apply
Patch failed at 0003 clk: Unconditionally recursively en-/dis-able clocks

Thanks
Rick

> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index 246b9c0ab8..c5f87fee72 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -491,7 +491,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
>  int clk_enable(struct clk *clk)
>  {
>         const struct clk_ops *ops;
> -       struct clk *clkp = NULL;
>         int ret;
>
>         debug("%s(clk=%p \"%s\")\n", __func__, clk, clk->dev->name);
> @@ -500,32 +499,29 @@ int clk_enable(struct clk *clk)
>         ops = clk_dev_ops(clk->dev);
>
>         if (CONFIG_IS_ENABLED(CLK_CCF)) {
> -               /* Take id 0 as a non-valid clk, such as dummy */
> -               if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
> -                       if (clkp->enable_count) {
> -                               clkp->enable_count++;
> -                               return 0;
> -                       }
> -                       if (clkp->dev->parent &&
> -                           device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
> -                               ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
> -                               if (ret) {
> -                                       printf("Enable %s failed\n",
> -                                              clkp->dev->parent->name);
> -                                       return ret;
> -                               }
> +               if (clk->enable_count) {
> +                       clk->enable_count++;
> +                       return 0;
> +               }
> +               if (clk->dev->parent &&
> +                   device_get_uclass_id(clk->dev->parent) == UCLASS_CLK) {
> +                       ret = clk_enable(dev_get_clk_ptr(clk->dev->parent));
> +                       if (ret) {
> +                               printf("Enable %s failed\n",
> +                                      clk->dev->parent->name);
> +                               return ret;
>                         }
>                 }
>
>                 if (ops->enable) {
>                         ret = ops->enable(clk);
>                         if (ret) {
> -                               printf("Enable %s failed\n", clk->dev->name);
> +                               printf("Enable %s failed (error %d)\n",
> +                                      clk->dev->name, ret);
>                                 return ret;
>                         }
>                 }
> -               if (clkp)
> -                       clkp->enable_count++;
> +               clk->enable_count++;
>         } else {
>                 if (!ops->enable)
>                         return -ENOSYS;
> @@ -551,7 +547,6 @@ int clk_enable_bulk(struct clk_bulk *bulk)
>  int clk_disable(struct clk *clk)
>  {
>         const struct clk_ops *ops;
> -       struct clk *clkp = NULL;
>         int ret;
>
>         debug("%s(clk=%p)\n", __func__, clk);
> @@ -560,29 +555,27 @@ int clk_disable(struct clk *clk)
>         ops = clk_dev_ops(clk->dev);
>
>         if (CONFIG_IS_ENABLED(CLK_CCF)) {
> -               if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
> -                       if (clkp->enable_count == 0) {
> -                               printf("clk %s already disabled\n",
> -                                      clkp->dev->name);
> -                               return 0;
> -                       }
> -
> -                       if (--clkp->enable_count > 0)
> -                               return 0;
> +               if (clk->enable_count == 0) {
> +                       printf("clk %s already disabled\n",
> +                              clk->dev->name);
> +                       return 0;
>                 }
>
> +               if (--clk->enable_count > 0)
> +                       return 0;
> +
>                 if (ops->disable) {
>                         ret = ops->disable(clk);
>                         if (ret)
>                                 return ret;
>                 }
>
> -               if (clkp && clkp->dev->parent &&
> -                   device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
> -                       ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
> +               if (clk->dev->parent &&
> +                   device_get_uclass_id(clk->dev) == UCLASS_CLK) {
> +                       ret = clk_disable(dev_get_clk_ptr(clk->dev->parent));
>                         if (ret) {
> -                               printf("Disable %s failed\n",
> -                                      clkp->dev->parent->name);
> +                               printf("Disable %s failed (error %d)\n",
> +                                      clk->dev->parent->name, ret);
>                                 return ret;
>                         }
>                 }
> --
> 2.25.0
>

[PATCH v4 07/17] spi: dw: Add mem_ops

[Rick Chen]

Hi Sean

> The dw spi devices on the Kendryte K210 must be operated in a specific
> fasion which cannot be achived through multiple writes to via dw_spi_xfer
> (as it is currently written). This patch adds an implementation of exec_op,
> which gives correct behaviour when reading/writing spi flash.
>
> I would like to be able to modify the existing dw_spi_xfer function such
> that it works properly (e.g. with the mmc_spi driver). However, the only
> example code I have to work off is Kendryte's sdk (which is written in the
> exec_op style), and I do not have access to the datasheet (if anyone does,
> I would love to have a look!).
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v4:
> - New
>
>  drivers/spi/designware_spi.c | 123 +++++++++++++++++++++++++++++++++--
>  1 file changed, 119 insertions(+), 4 deletions(-)
>

Patch 6 and 7 shall be applied via spi tree.
You mix them together, the patchwork will become complicated.
It will be better for me to wait for a period of time to get the
approval(Reviewed-by or Acked-by) of SPI MAINTAINER.

Thanks
Rick

> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> index 04cc873754..277eb19a0b 100644
> --- a/drivers/spi/designware_spi.c
> +++ b/drivers/spi/designware_spi.c
> @@ -17,6 +17,7 @@
>  #include <errno.h>
>  #include <malloc.h>
>  #include <spi.h>
> +#include <spi-mem.h>
>  #include <fdtdec.h>
>  #include <reset.h>
>  #include <linux/compat.h>
> @@ -107,8 +108,8 @@ struct dw_spi_priv {
>         int len;
>
>         u32 fifo_len;           /* depth of the FIFO buffer */
> -       void *tx;
> -       void *tx_end;
> +       const void *tx;
> +       const void *tx_end;
>         void *rx;
>         void *rx_end;
>
> @@ -344,7 +345,7 @@ static void dw_writer(struct dw_spi_priv *priv)
>                                 txw = *(u16 *)(priv->tx);
>                 }
>                 dw_write(priv, DW_SPI_DR, txw);
> -               debug("%s: tx=0x%02x\n", __func__, txw);
> +               log_io("tx=0x%02x\n", txw);
>                 priv->tx += priv->bits_per_word >> 3;
>         }
>  }
> @@ -356,7 +357,7 @@ static void dw_reader(struct dw_spi_priv *priv)
>
>         while (max--) {
>                 rxw = dw_read(priv, DW_SPI_DR);
> -               debug("%s: rx=0x%02x\n", __func__, rxw);
> +               log_io("rx=0x%02x\n", rxw);
>
>                 /* Care about rx if the transfer's original "rx" is not null */
>                 if (priv->rx_end - priv->len) {
> @@ -483,6 +484,115 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
>         return ret;
>  }
>
> +static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
> +{
> +       bool read = op->data.dir == SPI_MEM_DATA_IN;
> +       int pos, i, ret = 0;
> +       struct udevice *bus = slave->dev->parent;
> +       struct dw_spi_platdata *plat = dev_get_platdata(bus);
> +       struct dw_spi_priv *priv = dev_get_priv(bus);
> +       u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
> +       u8 op_buf[op_len];
> +       u32 cr0;
> +
> +       if (read)
> +               priv->tmode = SPI_TMOD_EPROMREAD;
> +       else
> +               priv->tmode = SPI_TMOD_TO;
> +
> +       debug("%s: buf=%p len=%u [bytes]\n",
> +             __func__, op->data.buf.in, op->data.nbytes);
> +
> +       cr0 = GEN_CTRL0(priv, plat);
> +       debug("%s: cr0=%08x\n", __func__, cr0);
> +
> +       spi_enable_chip(priv, 0);
> +       dw_write(priv, DW_SPI_CTRL0, cr0);
> +       if (read)
> +               dw_write(priv, DW_SPI_CTRL1, op->data.nbytes - 1);
> +       spi_enable_chip(priv, 1);
> +
> +       /* From spi_mem_exec_op */
> +       pos = 0;
> +       op_buf[pos++] = op->cmd.opcode;
> +       if (op->addr.nbytes) {
> +               for (i = 0; i < op->addr.nbytes; i++)
> +                       op_buf[pos + i] = op->addr.val >>
> +                               (8 * (op->addr.nbytes - i - 1));
> +
> +               pos += op->addr.nbytes;
> +       }
> +       if (op->dummy.nbytes)
> +               memset(op_buf + pos, 0xff, op->dummy.nbytes);
> +
> +       priv->tx = &op_buf;
> +       priv->tx_end = priv->tx + op_len;
> +       while (priv->tx != priv->tx_end)
> +               dw_writer(priv);
> +
> +       /*
> +        * XXX: The following are tight loops! Enabling debug messages may cause
> +        * them to fail because we are not reading/writing the fifo fast enough.
> +        *
> +        * We heuristically break out of the loop when we stop getting data.
> +        * This is to stop us from hanging if the device doesn't send any data
> +        * (either at all, or after sending a response). For example, one flash
> +        * chip I tested did not send anything back after the first 64K of data.
> +        */
> +       if (read) {
> +               /* If we have gotten any data back yet */
> +               bool got_data = false;
> +               /* How many times we have looped without reading anything */
> +               int loops_since_read = 0;
> +               struct spi_mem_op *mut_op = (struct spi_mem_op *)op;
> +
> +               priv->rx = op->data.buf.in;
> +               priv->rx_end = priv->rx + op->data.nbytes;
> +
> +               dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
> +               while (priv->rx != priv->rx_end) {
> +                       void *last_rx = priv->rx;
> +
> +                       dw_reader(priv);
> +                       if (priv->rx == last_rx) {
> +                               loops_since_read++;
> +                               /* Thresholds are arbitrary */
> +                               if (loops_since_read > 256)
> +                                       break;
> +                               else if (got_data && loops_since_read > 32)
> +                                       break;
> +                       } else {
> +                               got_data = true;
> +                               loops_since_read = 0;
> +                       }
> +               }
> +
> +               /* Update with the actual amount of data read */
> +               mut_op->data.nbytes -= priv->rx_end - priv->rx;
> +       } else {
> +               u32 val;
> +
> +               priv->tx = op->data.buf.out;
> +               priv->tx_end = priv->tx + op->data.nbytes;
> +
> +               /* Fill up the write fifo before starting the transfer */
> +               dw_writer(priv);
> +               dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
> +               while (priv->tx != priv->tx_end)
> +                       dw_writer(priv);
> +
> +               if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
> +                                      (val & SR_TF_EMPT) && !(val & SR_BUSY),
> +                                      RX_TIMEOUT * 1000)) {
> +                       ret = -ETIMEDOUT;
> +               }
> +       }
> +
> +       dw_write(priv, DW_SPI_SER, 0);
> +       debug("%s: %u bytes xfered\n", __func__, op->data.nbytes);
> +       return ret;
> +}
> +
>  static int dw_spi_set_speed(struct udevice *bus, uint speed)
>  {
>         struct dw_spi_platdata *plat = dev_get_platdata(bus);
> @@ -546,8 +656,13 @@ static int dw_spi_remove(struct udevice *bus)
>         return 0;
>  }
>
> +static const struct spi_controller_mem_ops dw_spi_mem_ops = {
> +       .exec_op = dw_spi_exec_op,
> +};
> +
>  static const struct dm_spi_ops dw_spi_ops = {
>         .xfer           = dw_spi_xfer,
> +       .mem_ops        = &dw_spi_mem_ops,
>         .set_speed      = dw_spi_set_speed,
>         .set_mode       = dw_spi_set_mode,
>         /*
> --
> 2.25.0
>

[PATCH v4 03/17] clk: Unconditionally recursively en-/dis-able clocks

[Sean Anderson]

On 2/18/20 2:20 AM, Rick Chen wrote:
> Hi Sean
> 
>> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
>> just enable them as normal. The enable count is local to the struct clk,
>> but this will never result in the actual en-/dis-able op being called
>> (unless the same struct clk is enabled twice).
>>
>> For clocks in the CCF, we always traverse up the tree when enabling.
>> Previously, CCF clocks without id set would be skipped, stopping the
>> traversal too early.
>>
>> Signed-off-by: Sean Anderson <seanga2@gmail.com>
>> Acked-by: Lukasz Majewski <lukma@denx.de>
>> ---
>>
>> Changes in v4:
>> - Lint
>>
>> Changes in v3:
>> - New
>>
>>  drivers/clk/clk-uclass.c | 59 ++++++++++++++++++----------------------
>>  1 file changed, 26 insertions(+), 33 deletions(-)
>>
> 
> When I tried to apply this patch-set, there occur a conflict as below:
> 
> Applying: clk: Always use the supplied struct clk
> Applying: clk: Check that ops of composite clock components exist before calling
> Applying: clk: Unconditionally recursively en-/dis-able clocks
> error: patch failed: drivers/clk/clk-uclass.c:491
> error: drivers/clk/clk-uclass.c: patch does not apply
> Patch failed at 0003 clk: Unconditionally recursively en-/dis-able clocks
> 
> Thanks
> Rick

Hm, perhaps you are applying it on a different commit. My series is
based off of

c00bd81ae0 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx

What are you applying to?

--Sean

[PATCH v4 07/17] spi: dw: Add mem_ops

[Sean Anderson]

On 2/18/20 3:34 AM, Rick Chen wrote:
> Hi Sean
> 
>> The dw spi devices on the Kendryte K210 must be operated in a specific
>> fasion which cannot be achived through multiple writes to via dw_spi_xfer
>> (as it is currently written). This patch adds an implementation of exec_op,
>> which gives correct behaviour when reading/writing spi flash.
>>
>> I would like to be able to modify the existing dw_spi_xfer function such
>> that it works properly (e.g. with the mmc_spi driver). However, the only
>> example code I have to work off is Kendryte's sdk (which is written in the
>> exec_op style), and I do not have access to the datasheet (if anyone does,
>> I would love to have a look!).
>>
>> Signed-off-by: Sean Anderson <seanga2@gmail.com>
>> ---
>>
>> Changes in v4:
>> - New
>>
>>  drivers/spi/designware_spi.c | 123 +++++++++++++++++++++++++++++++++--
>>  1 file changed, 119 insertions(+), 4 deletions(-)
>>
> 
> Patch 6 and 7 shall be applied via spi tree.
> You mix them together, the patchwork will become complicated.
> It will be better for me to wait for a period of time to get the
> approval(Reviewed-by or Acked-by) of SPI MAINTAINER.
> 
> Thanks
> Rick

So is this just waiting for approval, or is there a change I should make
on my end?

--Sean

[PATCH v4 07/17] spi: dw: Add mem_ops

[Rick Chen]

Hi Sean

> >> The dw spi devices on the Kendryte K210 must be operated in a specific
> >> fasion which cannot be achived through multiple writes to via dw_spi_xfer
> >> (as it is currently written). This patch adds an implementation of exec_op,
> >> which gives correct behaviour when reading/writing spi flash.
> >>
> >> I would like to be able to modify the existing dw_spi_xfer function such
> >> that it works properly (e.g. with the mmc_spi driver). However, the only
> >> example code I have to work off is Kendryte's sdk (which is written in the
> >> exec_op style), and I do not have access to the datasheet (if anyone does,
> >> I would love to have a look!).
> >>
> >> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> >> ---
> >>
> >> Changes in v4:
> >> - New
> >>
> >>  drivers/spi/designware_spi.c | 123 +++++++++++++++++++++++++++++++++--
> >>  1 file changed, 119 insertions(+), 4 deletions(-)
> >>
> >
> > Patch 6 and 7 shall be applied via spi tree.
> > You mix them together, the patchwork will become complicated.
> > It will be better for me to wait for a period of time to get the
> > approval(Reviewed-by or Acked-by) of SPI MAINTAINER.
> >
> > Thanks
> > Rick
>
> So is this just waiting for approval, or is there a change I should make
> on my end?

If they are not highly dependent, you shall separate and send them individually.
But we can wait for few days and see, if it still no response.
You can consider separate them.

Thanks
Rick

>
> --Sean

[PATCH v4 03/17] clk: Unconditionally recursively en-/dis-able clocks

[Rick Chen]

Hi Sean

> On 2/18/20 2:20 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> >> just enable them as normal. The enable count is local to the struct clk,
> >> but this will never result in the actual en-/dis-able op being called
> >> (unless the same struct clk is enabled twice).
> >>
> >> For clocks in the CCF, we always traverse up the tree when enabling.
> >> Previously, CCF clocks without id set would be skipped, stopping the
> >> traversal too early.
> >>
> >> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> >> Acked-by: Lukasz Majewski <lukma@denx.de>
> >> ---
> >>
> >> Changes in v4:
> >> - Lint
> >>
> >> Changes in v3:
> >> - New
> >>
> >>  drivers/clk/clk-uclass.c | 59 ++++++++++++++++++----------------------
> >>  1 file changed, 26 insertions(+), 33 deletions(-)
> >>
> >
> > When I tried to apply this patch-set, there occur a conflict as below:
> >
> > Applying: clk: Always use the supplied struct clk
> > Applying: clk: Check that ops of composite clock components exist before calling
> > Applying: clk: Unconditionally recursively en-/dis-able clocks
> > error: patch failed: drivers/clk/clk-uclass.c:491
> > error: drivers/clk/clk-uclass.c: patch does not apply
> > Patch failed at 0003 clk: Unconditionally recursively en-/dis-able clocks
> >
> > Thanks
> > Rick
>
> Hm, perhaps you are applying it on a different commit. My series is
> based off of
>
> c00bd81ae0 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx
>
> What are you applying to?

I applied to u-boot/master

Thanks
Rick

>
> --Sean

[PATCH v4 07/17] spi: dw: Add mem_ops

[Sean Anderson]

On 2/18/20 8:39 PM, Rick Chen wrote:
>>>
>>> Patch 6 and 7 shall be applied via spi tree.
>>> You mix them together, the patchwork will become complicated.
>>> It will be better for me to wait for a period of time to get the
>>> approval(Reviewed-by or Acked-by) of SPI MAINTAINER.
>>>
>>> Thanks
>>> Rick
>>
>> So is this just waiting for approval, or is there a change I should make
>> on my end?
> 
> If they are not highly dependent, you shall separate and send them individually.
> But we can wait for few days and see, if it still no response.
> You can consider separate them.

These patches add support for the on-board spi flash. In the past I have
separated out some unrelated patches, and have been told to keep them in
a series where they are used.

--Sean

[PATCH v4 09/17] riscv: Add option to support RISC-V privileged spec 1.9.1

[Bin Meng]

On Tue, Feb 11, 2020 at 2:05 PM Sean Anderson <seanga2@gmail.com> wrote:
>
> Some older processors (notably the Kendryte K210) use an older version of
> the RISC-V privileged specification. The primary changes between the old
> and new are in virtual memory, and in the merging of three separate counter
> enable CSRs.  Using the new CSR on an old processor causes an illegal
> instruction exception.  This patch adds an option to use the old CSRs
> instead of the new one.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v4:
> - Fixed CSRs not being defined properly (thanks bmeng)
> - Added ifdefs for all changed CSRs (e.g. for VM)
> - Also properly disable VM on boot
>
> Changes in v3:
> - Renamed from "riscv: Add option to disable writes to mcounteren"
> - Added original functionality back for older priv specs.
>
> Changes in v2:
> - Moved forward in the patch series
>
>  arch/riscv/Kconfig           | 10 +++++++++
>  arch/riscv/cpu/cpu.c         |  9 ++++++++
>  arch/riscv/include/asm/csr.h | 40 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 59 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v4 07/17] spi: dw: Add mem_ops

[Bin Meng]

On Wed, Feb 19, 2020 at 11:51 AM Sean Anderson <seanga2@gmail.com> wrote:
>
> On 2/18/20 8:39 PM, Rick Chen wrote:
> >>>
> >>> Patch 6 and 7 shall be applied via spi tree.
> >>> You mix them together, the patchwork will become complicated.
> >>> It will be better for me to wait for a period of time to get the
> >>> approval(Reviewed-by or Acked-by) of SPI MAINTAINER.
> >>>
> >>> Thanks
> >>> Rick
> >>
> >> So is this just waiting for approval, or is there a change I should make
> >> on my end?
> >
> > If they are not highly dependent, you shall separate and send them individually.
> > But we can wait for few days and see, if it still no response.
> > You can consider separate them.
>
> These patches add support for the on-board spi flash. In the past I have
> separated out some unrelated patches, and have been told to keep them in
> a series where they are used.

Yes, keeping all related patch in one series help maintainers in some
way. I would prefer all patches in this series go via the riscv tree.

However as Rick pointed out, we do need the SPI maintainer's review comments.

So Jagan, are you able to give some review? Thanks!

Regards,
Bin

[PATCH v4 08/17] riscv: Add headers for asm/global_data.h

[Bin Meng]

On Tue, Feb 11, 2020 at 2:05 PM Sean Anderson <seanga2@gmail.com> wrote:
>
> This header depended on bd_t and ulong, but did not include the appropriate
> headers.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v4:
> - Include compiler.h not linux/compiler.h
>
>  arch/riscv/include/asm/global_data.h | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v4 14/17] riscv: Try to get cpu frequency from device tree

[Bin Meng]

Hi Sean,

On Tue, Feb 11, 2020 at 2:05 PM Sean Anderson <seanga2@gmail.com> wrote:
>
> Instead of always using the "clock-frequency" property to determine cpu
> frequency, try using a clock in "clocks" if it exists. This patch also
> fixes a bug where there could be spurious higher frequencies if sizeof(u32)
> != sizeof(ulong).
>

I just realized the commit title looked a little bit confusing.

I think it could be more specific like:

riscv: Try to get cpu frequency from a "clocks" node if it exists

?

Regards,
Bin

[PATCH v4 14/17] riscv: Try to get cpu frequency from device tree

[Sean Anderson]

On 2/19/20 11:12 AM, Bin Meng wrote:
> Hi Sean,
> 
> On Tue, Feb 11, 2020 at 2:05 PM Sean Anderson <seanga2@gmail.com> wrote:
>>
>> Instead of always using the "clock-frequency" property to determine cpu
>> frequency, try using a clock in "clocks" if it exists. This patch also
>> fixes a bug where there could be spurious higher frequencies if sizeof(u32)
>> != sizeof(ulong).
>>
> 
> I just realized the commit title looked a little bit confusing.
> 
> I think it could be more specific like:
> 
> riscv: Try to get cpu frequency from a "clocks" node if it exists
> 
> ?
> 
> Regards,
> Bin
> 

That makes sense to me.

--Sean