* [PATCH v2 0/7] clk: sunxi-ng: sun8i-de2: Multiple fixes
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
In current sun8i-de2 clock driver, rotation core related clocks and
reset weren't considered properly. All SoC which have that core don't
have those definitions. Even worse, the only SoC which have rotation
core related definitions doesn't have that core at all.
This series fixes this mess.
Please take a look.
Best regards,
Jernej
Changes from v1:
- fix "fixes" tags
- move sort patch at the end
- update several commit logs
Jernej Skrabec (7):
clk: sunxi-ng: sun8i-de2: Split out H5 definitions
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
clk: sunxi-ng: sun8i-de2: Sort structures
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 127 +++++++++++++++++----------
1 file changed, 80 insertions(+), 47 deletions(-)
--
2.25.0
_______________________________________________
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 1/7] clk: sunxi-ng: sun8i-de2: Split out H5 definitions
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-11 18:59 ` Jernej Skrabec
-1 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: mturquette, sboyd, icenowy, jernej.skrabec, linux-arm-kernel,
linux-clk, linux-kernel
H5 has less clocks and resets than A64. Currently that's not obvious
because A64 is missing rotation core related clocks and reset.
Split out H5 definition. A64 structures will be fixed in subsequent
commit.
Note that this patch depends on commit 19368d99746e ("clk: sunxi-ng:
add support for Allwinner H3 DE2 CCU") for the H3 clock list.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index d9668493c3f9..2478ae314d0f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -192,6 +192,12 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
+static struct ccu_reset_map sun50i_h5_de2_resets[] = {
+ [RST_MIXER0] = { 0x08, BIT(0) },
+ [RST_MIXER1] = { 0x08, BIT(1) },
+ [RST_WB] = { 0x08, BIT(2) },
+};
+
static struct ccu_reset_map sun50i_h6_de3_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
@@ -229,6 +235,16 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
};
+static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
+ .ccu_clks = sun8i_h3_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
+
+ .hw_clks = &sun8i_h3_de2_hw_clks,
+
+ .resets = sun50i_h5_de2_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
+};
+
static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
.ccu_clks = sun50i_h6_de3_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
@@ -347,7 +363,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
},
{
.compatible = "allwinner,sun50i-h5-de2-clk",
- .data = &sun50i_a64_de2_clk_desc,
+ .data = &sun50i_h5_de2_clk_desc,
},
{
.compatible = "allwinner,sun50i-h6-de3-clk",
--
2.25.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 1/7] clk: sunxi-ng: sun8i-de2: Split out H5 definitions
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
H5 has less clocks and resets than A64. Currently that's not obvious
because A64 is missing rotation core related clocks and reset.
Split out H5 definition. A64 structures will be fixed in subsequent
commit.
Note that this patch depends on commit 19368d99746e ("clk: sunxi-ng:
add support for Allwinner H3 DE2 CCU") for the H3 clock list.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index d9668493c3f9..2478ae314d0f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -192,6 +192,12 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
+static struct ccu_reset_map sun50i_h5_de2_resets[] = {
+ [RST_MIXER0] = { 0x08, BIT(0) },
+ [RST_MIXER1] = { 0x08, BIT(1) },
+ [RST_WB] = { 0x08, BIT(2) },
+};
+
static struct ccu_reset_map sun50i_h6_de3_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
@@ -229,6 +235,16 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
};
+static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
+ .ccu_clks = sun8i_h3_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
+
+ .hw_clks = &sun8i_h3_de2_hw_clks,
+
+ .resets = sun50i_h5_de2_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
+};
+
static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
.ccu_clks = sun50i_h6_de3_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
@@ -347,7 +363,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
},
{
.compatible = "allwinner,sun50i-h5-de2-clk",
- .data = &sun50i_a64_de2_clk_desc,
+ .data = &sun50i_h5_de2_clk_desc,
},
{
.compatible = "allwinner,sun50i-h6-de3-clk",
--
2.25.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 2/7] clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-11 18:59 ` Jernej Skrabec
-1 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: mturquette, sboyd, icenowy, jernej.skrabec, linux-arm-kernel,
linux-clk, linux-kernel
A64 has rotation core which needs clocks and reset. Because there is no
appropriate structures available, make a separate, A64 specific
structures.
Fixes: cf4881c12935 ("clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 45 ++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 2478ae314d0f..c6220be8e205 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -108,6 +108,24 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {
&wb_div_clk.common,
};
+static struct ccu_common *sun50i_a64_de2_clks[] = {
+ &mixer0_clk.common,
+ &mixer1_clk.common,
+ &wb_clk.common,
+
+ &bus_mixer0_clk.common,
+ &bus_mixer1_clk.common,
+ &bus_wb_clk.common,
+
+ &mixer0_div_clk.common,
+ &mixer1_div_clk.common,
+ &wb_div_clk.common,
+
+ &bus_rot_clk.common,
+ &rot_clk.common,
+ &rot_div_clk.common,
+};
+
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
@@ -156,6 +174,26 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
.num = CLK_NUMBER_WITHOUT_ROT,
};
+static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
+ .hws = {
+ [CLK_MIXER0] = &mixer0_clk.common.hw,
+ [CLK_MIXER1] = &mixer1_clk.common.hw,
+ [CLK_WB] = &wb_clk.common.hw,
+ [CLK_ROT] = &rot_clk.common.hw,
+
+ [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
+ [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
+ [CLK_BUS_WB] = &bus_wb_clk.common.hw,
+ [CLK_BUS_ROT] = &bus_rot_clk.common.hw,
+
+ [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
+ [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
+ [CLK_WB_DIV] = &wb_div_clk.common.hw,
+ [CLK_ROT_DIV] = &rot_div_clk.common.hw,
+ },
+ .num = CLK_NUMBER_WITH_ROT,
+};
+
static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
@@ -190,6 +228,7 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
+ [RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
@@ -226,10 +265,10 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
};
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
- .ccu_clks = sun8i_h3_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
+ .ccu_clks = sun50i_a64_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
- .hw_clks = &sun8i_h3_de2_hw_clks,
+ .hw_clks = &sun50i_a64_de2_hw_clks,
.resets = sun50i_a64_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
--
2.25.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 2/7] clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
A64 has rotation core which needs clocks and reset. Because there is no
appropriate structures available, make a separate, A64 specific
structures.
Fixes: cf4881c12935 ("clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 45 ++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 2478ae314d0f..c6220be8e205 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -108,6 +108,24 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {
&wb_div_clk.common,
};
+static struct ccu_common *sun50i_a64_de2_clks[] = {
+ &mixer0_clk.common,
+ &mixer1_clk.common,
+ &wb_clk.common,
+
+ &bus_mixer0_clk.common,
+ &bus_mixer1_clk.common,
+ &bus_wb_clk.common,
+
+ &mixer0_div_clk.common,
+ &mixer1_div_clk.common,
+ &wb_div_clk.common,
+
+ &bus_rot_clk.common,
+ &rot_clk.common,
+ &rot_div_clk.common,
+};
+
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
@@ -156,6 +174,26 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
.num = CLK_NUMBER_WITHOUT_ROT,
};
+static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
+ .hws = {
+ [CLK_MIXER0] = &mixer0_clk.common.hw,
+ [CLK_MIXER1] = &mixer1_clk.common.hw,
+ [CLK_WB] = &wb_clk.common.hw,
+ [CLK_ROT] = &rot_clk.common.hw,
+
+ [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
+ [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
+ [CLK_BUS_WB] = &bus_wb_clk.common.hw,
+ [CLK_BUS_ROT] = &bus_rot_clk.common.hw,
+
+ [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
+ [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
+ [CLK_WB_DIV] = &wb_div_clk.common.hw,
+ [CLK_ROT_DIV] = &rot_div_clk.common.hw,
+ },
+ .num = CLK_NUMBER_WITH_ROT,
+};
+
static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
@@ -190,6 +228,7 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
+ [RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
@@ -226,10 +265,10 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
};
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
- .ccu_clks = sun8i_h3_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
+ .ccu_clks = sun50i_a64_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
- .hw_clks = &sun8i_h3_de2_hw_clks,
+ .hw_clks = &sun50i_a64_de2_hw_clks,
.resets = sun50i_a64_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
--
2.25.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 3/7] clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-11 18:59 ` Jernej Skrabec
-1 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: mturquette, sboyd, icenowy, jernej.skrabec, linux-arm-kernel,
linux-clk, linux-kernel
DE3 documentation regarding presence of rotate core in H6 is a bit
confusing. Register descriptions mention bits for enabling rotate core
clocks and reset, but general overview doesn't list it as feature of H6
display engine, BSP kernel doesn't support it and there is no interrupt
listed for it. Manual poking registers also didn't reveal presence of
rotate core.
Let's assume there isn't any rotate core on H6 present and remove
related clocks. With that done, structures are same as those for H5, so
just reuse H5 structure.
Fixes: 56808da9f97f ("clk: sunxi-ng: Add support for H6 DE3 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 57 +---------------------------
1 file changed, 1 insertion(+), 56 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index c6220be8e205..87a30d072ae9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -51,24 +51,6 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
-static struct ccu_common *sun50i_h6_de3_clks[] = {
- &mixer0_clk.common,
- &mixer1_clk.common,
- &wb_clk.common,
-
- &bus_mixer0_clk.common,
- &bus_mixer1_clk.common,
- &bus_wb_clk.common,
-
- &mixer0_div_clk.common,
- &mixer1_div_clk.common,
- &wb_div_clk.common,
-
- &bus_rot_clk.common,
- &rot_clk.common,
- &rot_div_clk.common,
-};
-
static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
@@ -194,26 +176,6 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
.num = CLK_NUMBER_WITH_ROT,
};
-static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
- .hws = {
- [CLK_MIXER0] = &mixer0_clk.common.hw,
- [CLK_MIXER1] = &mixer1_clk.common.hw,
- [CLK_WB] = &wb_clk.common.hw,
- [CLK_ROT] = &rot_clk.common.hw,
-
- [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
- [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
- [CLK_BUS_WB] = &bus_wb_clk.common.hw,
- [CLK_BUS_ROT] = &bus_rot_clk.common.hw,
-
- [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
- [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
- [CLK_WB_DIV] = &wb_div_clk.common.hw,
- [CLK_ROT_DIV] = &rot_div_clk.common.hw,
- },
- .num = CLK_NUMBER_WITH_ROT,
-};
-
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
@@ -237,13 +199,6 @@ static struct ccu_reset_map sun50i_h5_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
-static struct ccu_reset_map sun50i_h6_de3_resets[] = {
- [RST_MIXER0] = { 0x08, BIT(0) },
- [RST_MIXER1] = { 0x08, BIT(1) },
- [RST_WB] = { 0x08, BIT(2) },
- [RST_ROT] = { 0x08, BIT(3) },
-};
-
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
.ccu_clks = sun8i_a83t_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
@@ -284,16 +239,6 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
};
-static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
- .ccu_clks = sun50i_h6_de3_clks,
- .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
-
- .hw_clks = &sun50i_h6_de3_hw_clks,
-
- .resets = sun50i_h6_de3_resets,
- .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
-};
-
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
.ccu_clks = sun8i_v3s_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
@@ -406,7 +351,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
},
{
.compatible = "allwinner,sun50i-h6-de3-clk",
- .data = &sun50i_h6_de3_clk_desc,
+ .data = &sun50i_h5_de2_clk_desc,
},
{ }
};
--
2.25.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 3/7] clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
DE3 documentation regarding presence of rotate core in H6 is a bit
confusing. Register descriptions mention bits for enabling rotate core
clocks and reset, but general overview doesn't list it as feature of H6
display engine, BSP kernel doesn't support it and there is no interrupt
listed for it. Manual poking registers also didn't reveal presence of
rotate core.
Let's assume there isn't any rotate core on H6 present and remove
related clocks. With that done, structures are same as those for H5, so
just reuse H5 structure.
Fixes: 56808da9f97f ("clk: sunxi-ng: Add support for H6 DE3 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 57 +---------------------------
1 file changed, 1 insertion(+), 56 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index c6220be8e205..87a30d072ae9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -51,24 +51,6 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
-static struct ccu_common *sun50i_h6_de3_clks[] = {
- &mixer0_clk.common,
- &mixer1_clk.common,
- &wb_clk.common,
-
- &bus_mixer0_clk.common,
- &bus_mixer1_clk.common,
- &bus_wb_clk.common,
-
- &mixer0_div_clk.common,
- &mixer1_div_clk.common,
- &wb_div_clk.common,
-
- &bus_rot_clk.common,
- &rot_clk.common,
- &rot_div_clk.common,
-};
-
static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
@@ -194,26 +176,6 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
.num = CLK_NUMBER_WITH_ROT,
};
-static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
- .hws = {
- [CLK_MIXER0] = &mixer0_clk.common.hw,
- [CLK_MIXER1] = &mixer1_clk.common.hw,
- [CLK_WB] = &wb_clk.common.hw,
- [CLK_ROT] = &rot_clk.common.hw,
-
- [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
- [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
- [CLK_BUS_WB] = &bus_wb_clk.common.hw,
- [CLK_BUS_ROT] = &bus_rot_clk.common.hw,
-
- [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
- [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
- [CLK_WB_DIV] = &wb_div_clk.common.hw,
- [CLK_ROT_DIV] = &rot_div_clk.common.hw,
- },
- .num = CLK_NUMBER_WITH_ROT,
-};
-
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
@@ -237,13 +199,6 @@ static struct ccu_reset_map sun50i_h5_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
-static struct ccu_reset_map sun50i_h6_de3_resets[] = {
- [RST_MIXER0] = { 0x08, BIT(0) },
- [RST_MIXER1] = { 0x08, BIT(1) },
- [RST_WB] = { 0x08, BIT(2) },
- [RST_ROT] = { 0x08, BIT(3) },
-};
-
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
.ccu_clks = sun8i_a83t_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
@@ -284,16 +239,6 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
};
-static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
- .ccu_clks = sun50i_h6_de3_clks,
- .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
-
- .hw_clks = &sun50i_h6_de3_hw_clks,
-
- .resets = sun50i_h6_de3_resets,
- .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
-};
-
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
.ccu_clks = sun8i_v3s_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
@@ -406,7 +351,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
},
{
.compatible = "allwinner,sun50i-h6-de3-clk",
- .data = &sun50i_h6_de3_clk_desc,
+ .data = &sun50i_h5_de2_clk_desc,
},
{ }
};
--
2.25.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 4/7] clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-11 18:59 ` Jernej Skrabec
-1 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: mturquette, sboyd, icenowy, jernej.skrabec, linux-arm-kernel,
linux-clk, linux-kernel
Currently, V3s and H3 reuse A83T reset structure. However, A83T contains
additional core for rotation, which is not present in V3s and H3.
Make new reset structure for H3 and let V3s reuse it. A83T reset
structure will be amended in subsequent commit.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 87a30d072ae9..bbbe1ed7aba1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -179,9 +179,18 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
- * For A83T, H3 and R40, mixer1 reset line is shared with wb, so
- * only RST_WB is exported here.
- * For V3s there's just no mixer1, so it also shares this struct.
+ * Mixer1 reset line is shared with wb, so only RST_WB is
+ * exported here.
+ */
+ [RST_WB] = { 0x08, BIT(2) },
+};
+
+static struct ccu_reset_map sun8i_h3_de2_resets[] = {
+ [RST_MIXER0] = { 0x08, BIT(0) },
+ /*
+ * Mixer1 reset line is shared with wb, so only RST_WB is
+ * exported here.
+ * V3s doesn't have mixer1, so it also shares this struct.
*/
[RST_WB] = { 0x08, BIT(2) },
};
@@ -215,8 +224,8 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
.hw_clks = &sun8i_h3_de2_hw_clks,
- .resets = sun8i_a83t_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ .resets = sun8i_h3_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
@@ -245,8 +254,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
.hw_clks = &sun8i_v3s_de2_hw_clks,
- .resets = sun8i_a83t_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ .resets = sun8i_h3_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
static int sunxi_de2_clk_probe(struct platform_device *pdev)
--
2.25.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 4/7] clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
Currently, V3s and H3 reuse A83T reset structure. However, A83T contains
additional core for rotation, which is not present in V3s and H3.
Make new reset structure for H3 and let V3s reuse it. A83T reset
structure will be amended in subsequent commit.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 87a30d072ae9..bbbe1ed7aba1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -179,9 +179,18 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
- * For A83T, H3 and R40, mixer1 reset line is shared with wb, so
- * only RST_WB is exported here.
- * For V3s there's just no mixer1, so it also shares this struct.
+ * Mixer1 reset line is shared with wb, so only RST_WB is
+ * exported here.
+ */
+ [RST_WB] = { 0x08, BIT(2) },
+};
+
+static struct ccu_reset_map sun8i_h3_de2_resets[] = {
+ [RST_MIXER0] = { 0x08, BIT(0) },
+ /*
+ * Mixer1 reset line is shared with wb, so only RST_WB is
+ * exported here.
+ * V3s doesn't have mixer1, so it also shares this struct.
*/
[RST_WB] = { 0x08, BIT(2) },
};
@@ -215,8 +224,8 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
.hw_clks = &sun8i_h3_de2_hw_clks,
- .resets = sun8i_a83t_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ .resets = sun8i_h3_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
@@ -245,8 +254,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
.hw_clks = &sun8i_v3s_de2_hw_clks,
- .resets = sun8i_a83t_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ .resets = sun8i_h3_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
static int sunxi_de2_clk_probe(struct platform_device *pdev)
--
2.25.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 5/7] clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-11 18:59 ` Jernej Skrabec
-1 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: mturquette, sboyd, icenowy, jernej.skrabec, linux-arm-kernel,
linux-clk, linux-kernel
A83T structures don't have clocks and reset for rotation core. Add them.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index bbbe1ed7aba1..9656553c01f3 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -50,6 +50,8 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
+ CLK_SET_RATE_PARENT);
static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_clk.common,
@@ -63,6 +65,10 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_div_a83_clk.common,
&mixer1_div_a83_clk.common,
&wb_div_a83_clk.common,
+
+ &bus_rot_clk.common,
+ &rot_clk.common,
+ &rot_div_a83_clk.common,
};
static struct ccu_common *sun8i_h3_de2_clks[] = {
@@ -113,16 +119,19 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_MIXER1] = &mixer1_clk.common.hw,
[CLK_WB] = &wb_clk.common.hw,
+ [CLK_ROT] = &rot_clk.common.hw,
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
+ [CLK_BUS_ROT] = &bus_rot_clk.common.hw,
[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
+ [CLK_ROT_DIV] = &rot_div_a83_clk.common.hw,
},
- .num = CLK_NUMBER_WITHOUT_ROT,
+ .num = CLK_NUMBER_WITH_ROT,
};
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
@@ -183,6 +192,7 @@ static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
* exported here.
*/
[RST_WB] = { 0x08, BIT(2) },
+ [RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
--
2.25.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 5/7] clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
A83T structures don't have clocks and reset for rotation core. Add them.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index bbbe1ed7aba1..9656553c01f3 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -50,6 +50,8 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
+ CLK_SET_RATE_PARENT);
static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_clk.common,
@@ -63,6 +65,10 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_div_a83_clk.common,
&mixer1_div_a83_clk.common,
&wb_div_a83_clk.common,
+
+ &bus_rot_clk.common,
+ &rot_clk.common,
+ &rot_div_a83_clk.common,
};
static struct ccu_common *sun8i_h3_de2_clks[] = {
@@ -113,16 +119,19 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_MIXER1] = &mixer1_clk.common.hw,
[CLK_WB] = &wb_clk.common.hw,
+ [CLK_ROT] = &rot_clk.common.hw,
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
+ [CLK_BUS_ROT] = &bus_rot_clk.common.hw,
[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
+ [CLK_ROT_DIV] = &rot_div_a83_clk.common.hw,
},
- .num = CLK_NUMBER_WITHOUT_ROT,
+ .num = CLK_NUMBER_WITH_ROT,
};
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
@@ -183,6 +192,7 @@ static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
* exported here.
*/
[RST_WB] = { 0x08, BIT(2) },
+ [RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
--
2.25.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 6/7] clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-11 18:59 ` Jernej Skrabec
-1 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: mturquette, sboyd, icenowy, jernej.skrabec, linux-arm-kernel,
linux-clk, linux-kernel
R40 is actually very similar to A64, but it doesn't have mixer1 reset.
This means it's clocks and resets combination is unique and R40 specific
quirks are needed.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 9656553c01f3..5a278c391f1d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -238,6 +238,16 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
+static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
+ .ccu_clks = sun50i_a64_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
+
+ .hw_clks = &sun50i_a64_de2_hw_clks,
+
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+};
+
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks = sun50i_a64_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
@@ -356,6 +366,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.compatible = "allwinner,sun8i-h3-de2-clk",
.data = &sun8i_h3_de2_clk_desc,
},
+ {
+ .compatible = "allwinner,sun8i-r40-de2-clk",
+ .data = &sun8i_r40_de2_clk_desc,
+ },
{
.compatible = "allwinner,sun8i-v3s-de2-clk",
.data = &sun8i_v3s_de2_clk_desc,
--
2.25.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 6/7] clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
R40 is actually very similar to A64, but it doesn't have mixer1 reset.
This means it's clocks and resets combination is unique and R40 specific
quirks are needed.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 9656553c01f3..5a278c391f1d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -238,6 +238,16 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
+static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
+ .ccu_clks = sun50i_a64_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
+
+ .hw_clks = &sun50i_a64_de2_hw_clks,
+
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+};
+
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks = sun50i_a64_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
@@ -356,6 +366,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.compatible = "allwinner,sun8i-h3-de2-clk",
.data = &sun8i_h3_de2_clk_desc,
},
+ {
+ .compatible = "allwinner,sun8i-r40-de2-clk",
+ .data = &sun8i_r40_de2_clk_desc,
+ },
{
.compatible = "allwinner,sun8i-v3s-de2-clk",
.data = &sun8i_v3s_de2_clk_desc,
--
2.25.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 7/7] clk: sunxi-ng: sun8i-de2: Sort structures
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-11 18:59 ` Jernej Skrabec
-1 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: mturquette, sboyd, icenowy, jernej.skrabec, linux-arm-kernel,
linux-clk, linux-kernel
V3s quirks are not in right place. Move it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5a278c391f1d..524f33275bc7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -248,6 +248,16 @@ static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
+static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
+ .ccu_clks = sun8i_v3s_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
+
+ .hw_clks = &sun8i_v3s_de2_hw_clks,
+
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+};
+
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks = sun50i_a64_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
@@ -268,16 +278,6 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
};
-static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
- .ccu_clks = sun8i_v3s_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
-
- .hw_clks = &sun8i_v3s_de2_hw_clks,
-
- .resets = sun8i_h3_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
-};
-
static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
struct resource *res;
--
2.25.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 7/7] clk: sunxi-ng: sun8i-de2: Sort structures
@ 2020-02-11 18:59 ` Jernej Skrabec
0 siblings, 0 replies; 18+ messages in thread
From: Jernej Skrabec @ 2020-02-11 18:59 UTC (permalink / raw)
To: mripard, wens
Cc: jernej.skrabec, sboyd, mturquette, linux-kernel, linux-clk,
linux-arm-kernel, icenowy
V3s quirks are not in right place. Move it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5a278c391f1d..524f33275bc7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -248,6 +248,16 @@ static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
+static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
+ .ccu_clks = sun8i_v3s_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
+
+ .hw_clks = &sun8i_v3s_de2_hw_clks,
+
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+};
+
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks = sun50i_a64_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
@@ -268,16 +278,6 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
};
-static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
- .ccu_clks = sun8i_v3s_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
-
- .hw_clks = &sun8i_v3s_de2_hw_clks,
-
- .resets = sun8i_h3_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
-};
-
static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
struct resource *res;
--
2.25.0
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/7] clk: sunxi-ng: sun8i-de2: Multiple fixes
2020-02-11 18:59 ` Jernej Skrabec
@ 2020-02-12 18:01 ` Maxime Ripard
-1 siblings, 0 replies; 18+ messages in thread
From: Maxime Ripard @ 2020-02-12 18:01 UTC (permalink / raw)
To: Jernej Skrabec
Cc: wens, mturquette, sboyd, icenowy, linux-arm-kernel, linux-clk,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 405 bytes --]
On Tue, Feb 11, 2020 at 07:59:29PM +0100, Jernej Skrabec wrote:
> In current sun8i-de2 clock driver, rotation core related clocks and
> reset weren't considered properly. All SoC which have that core don't
> have those definitions. Even worse, the only SoC which have rotation
> core related definitions doesn't have that core at all.
>
> This series fixes this mess.
Applied all of them, thanks!
Maxime
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/7] clk: sunxi-ng: sun8i-de2: Multiple fixes
@ 2020-02-12 18:01 ` Maxime Ripard
0 siblings, 0 replies; 18+ messages in thread
From: Maxime Ripard @ 2020-02-12 18:01 UTC (permalink / raw)
To: Jernej Skrabec
Cc: sboyd, mturquette, linux-kernel, wens, linux-clk,
linux-arm-kernel, icenowy
[-- Attachment #1.1: Type: text/plain, Size: 405 bytes --]
On Tue, Feb 11, 2020 at 07:59:29PM +0100, Jernej Skrabec wrote:
> In current sun8i-de2 clock driver, rotation core related clocks and
> reset weren't considered properly. All SoC which have that core don't
> have those definitions. Even worse, the only SoC which have rotation
> core related definitions doesn't have that core at all.
>
> This series fixes this mess.
Applied all of them, thanks!
Maxime
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread