* [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180
@ 2020-02-12 11:21 Sandeep Maheswaram
2020-02-12 11:21 ` [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml Sandeep Maheswaram
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Sandeep Maheswaram @ 2020-02-12 11:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Add QMP V3 USB3 PHY entries for SC7180 in phy driver and
device tree bindings.
changes in v3:
*Addressed Rob's comments in yaml file.
*Sepearated the SC7180 support in yaml patch.
*corrected the phy reset entries in device tree.
changes in v2:
*Remove global phy reset in QMP phy.
*Convert QMP phy bindings to yaml.
Sandeep Maheswaram (4):
dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml
dt-bindings: phy: qcom,qmp: Add support for SC7180
phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
arm64: dts: qcom: sc7180: Correct qmp phy reset entries
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 287 +++++++++++++++++++++
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 227 ----------------
arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 +-
drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++
4 files changed, 327 insertions(+), 229 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml
2020-02-12 11:21 [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
@ 2020-02-12 11:21 ` Sandeep Maheswaram
2020-02-12 20:16 ` Matthias Kaehlcke
2020-02-13 20:42 ` Rob Herring
2020-02-12 11:21 ` [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180 Sandeep Maheswaram
` (3 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Sandeep Maheswaram @ 2020-02-12 11:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Convert QMP phy bindings to DT schema format using json-schema.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 283 +++++++++++++++++++++
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 227 -----------------
2 files changed, 283 insertions(+), 227 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
new file mode 100644
index 0000000..b39a594
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -0,0 +1,283 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QMP PHY controller
+
+maintainers:
+ - Manu Gautam <mgautam@codeaurora.org>
+
+description:
+ QMP phy controller supports physical layer functionality for a number of
+ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ - qcom,msm8996-qmp-pcie-phy
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+
+ reg:
+ minItems: 1
+ items:
+ - description: Address and length of PHY's common serdes block.
+ - description: Address and length of the DP_COM control block.
+
+ reg-names:
+ items:
+ - const: reg-base
+ - const: dp_com
+
+ "#clock-cells":
+ enum: [ 1, 2 ]
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ clocks:
+ maxItems: 4
+ minItems: 1
+
+ clock-names:
+ maxItems: 4
+ minItems: 1
+
+ resets:
+ maxItems: 3
+ minItems: 1
+
+ reset-names:
+ maxItems: 3
+ minItems: 1
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vddp-ref-clk-supply:
+ description:
+ Phandle to a regulator supply to any specific refclk
+ pll block.
+
+#Required nodes:
+patternProperties:
+ "^lanes@[0-9a-f]+$":
+ type: object
+ description:
+ Each device node of QMP phy is required to have as many child nodes as
+ the number of lanes the PHY has.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy common block aux clock.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ - description: phy's ahb cfg block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - const: cfg
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-pcie-phy
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,msm8998-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 19.2 MHz ref clk.
+ - description: Phy reference aux clock.
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+ resets:
+ items:
+ - description: PHY reset in the UFS controller.
+ reset-names:
+ items:
+ - const: ufsphy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: pipe clk.
+ clock-names:
+ items:
+ - const: pipe_clk
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sdm845-qmp-usb3-phy
+ then:
+ required:
+ - reg-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ usb_1_qmpphy: phy@88e9000 {
+ compatible = "qcom,sdm845-qmp-usb3-phy";
+ reg = <0 0x088e9000 0 0x18c>,
+ <0 0x088e8000 0 0x10>;
+ reg-names = "reg-base", "dp_com";
+ #clock-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ usb_1_ssphy: lanes@88e9200 {
+ reg = <0 0x088e9200 0 0x128>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x218>,
+ <0 0x088e9600 0 0x128>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
deleted file mode 100644
index eac9ad3..0000000
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ /dev/null
@@ -1,227 +0,0 @@
-Qualcomm QMP PHY controller
-===========================
-
-QMP phy controller supports physical layer functionality for a number of
-controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
-
-Required properties:
- - compatible: compatible list, contains:
- "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
- "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
- "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
- "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
- "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
- "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
- "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
- "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
- "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
- "qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150.
-
-- reg:
- - index 0: address and length of register set for PHY's common
- serdes block.
- - index 1: address and length of the DP_COM control block (for
- "qcom,sdm845-qmp-usb3-phy" only).
-
-- reg-names:
- - For "qcom,sdm845-qmp-usb3-phy":
- - Should be: "reg-base", "dp_com"
- - For all others:
- - The reg-names property shouldn't be defined.
-
- - #address-cells: must be 1
- - #size-cells: must be 1
- - ranges: must be present
-
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: "cfg_ahb" for phy config clock,
- "aux" for phy aux clock,
- "ref" for 19.2 MHz ref clk,
- "com_aux" for phy common block aux clock,
- "ref_aux" for phy reference aux clock,
-
- For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8996-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,sm8150-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
-
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: "phy" for reset of phy block,
- "common" for phy common block reset,
- "cfg" for phy's ahb cfg block reset,
- "ufsphy" for the PHY reset in the UFS controller.
-
- For "qcom,ipq8074-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "phy", "common", "cfg".
- For "qcom,msm8996-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,sm8150-qmp-ufs-phy": must contain:
- "ufsphy".
-
- - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
-
-Optional properties:
- - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
- pll block.
-
-Required nodes:
- - Each device node of QMP phy is required to have as many child nodes as
- the number of lanes the PHY has.
-
-Required properties for child nodes of PCIe PHYs (one child per lane):
- - reg: list of offset and length pairs of register sets for PHY blocks -
- tx, rx, pcs, and pcs_misc (optional).
- - #phy-cells: must be 0
-
-Required properties for a single "lanes" child node of non-PCIe PHYs:
- - reg: list of offset and length pairs of register sets for PHY blocks
- For 1-lane devices:
- tx, rx, pcs, and (optionally) pcs_misc
- For 2-lane devices:
- tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
- - #phy-cells: must be 0
-
-Required properties for child node of PCIe and USB3 qmp phys:
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: Must contain following:
- "pipe<lane-number>" for pipe clock specific to each lane.
- - clock-output-names: Name of the PHY clock that will be the parent for
- the above pipe clock.
- For "qcom,ipq8074-qmp-pcie-phy":
- - "pcie20_phy0_pipe_clk" Pipe Clock parent
- (or)
- "pcie20_phy1_pipe_clk"
- - #clock-cells: must be 0
- - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
- gate-controlled by the gcc.
-
-Required properties for child node of PHYs with lane reset, AKA:
- "qcom,msm8996-qmp-pcie-phy"
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: Must contain following:
- "lane<lane-number>" for reset specific to each lane.
-
-Example:
- phy@34000 {
- compatible = "qcom,msm8996-qmp-pcie-phy";
- reg = <0x34000 0x488>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
-
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
- resets = <&gcc GCC_PCIE_PHY_BCR>,
- <&gcc GCC_PCIE_PHY_COM_BCR>,
- <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
- reset-names = "phy", "common", "cfg";
-
- pciephy_0: lane@35000 {
- reg = <0x35000 0x130>,
- <0x35200 0x200>,
- <0x35400 0x1dc>;
- #clock-cells = <0>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie_0_pipe_clk_src";
- resets = <&gcc GCC_PCIE_0_PHY_BCR>;
- reset-names = "lane0";
- };
-
- pciephy_1: lane@36000 {
- ...
- ...
- };
-
- phy@88eb000 {
- compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0x88eb000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
-
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
-
- lane@88eb200 {
- reg = <0x88eb200 0x128>,
- <0x88eb400 0x1fc>,
- <0x88eb800 0x218>,
- <0x88eb600 0x70>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
- };
-
- phy@1d87000 {
- compatible = "qcom,sdm845-qmp-ufs-phy";
- reg = <0x1d87000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- lanes@1d87400 {
- reg = <0x1d87400 0x108>,
- <0x1d87600 0x1e0>,
- <0x1d87c00 0x1dc>,
- <0x1d87800 0x108>,
- <0x1d87a00 0x1e0>;
- #phy-cells = <0>;
- };
- };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180
2020-02-12 11:21 [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
2020-02-12 11:21 ` [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml Sandeep Maheswaram
@ 2020-02-12 11:21 ` Sandeep Maheswaram
2020-02-12 20:30 ` Matthias Kaehlcke
2020-02-18 23:05 ` Rob Herring
2020-02-12 11:21 ` [PATCH v3 3/4] phy: qcom-qmp: Add QMP V3 USB3 PHY " Sandeep Maheswaram
` (2 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Sandeep Maheswaram @ 2020-02-12 11:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Add compatible for SC7180 in qmp phy bindings.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index b39a594..8c153e3 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -23,6 +23,7 @@ properties:
- qcom,msm8998-qmp-usb3-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,msm8998-qmp-pcie-phy
+ - qcom,sc7180-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sdm845-qmp-ufs-phy
@@ -105,9 +106,10 @@ allOf:
properties:
compatible:
contains:
- enum:
- - qcom,sdm845-qmp-usb3-phy
- - qcom,sdm845-qmp-usb3-uni-phy
+ enum:
+ - qcom,sc7180-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
then:
properties:
clocks:
@@ -238,7 +240,9 @@ allOf:
properties:
compatible:
contains:
- const: qcom,sdm845-qmp-usb3-phy
+ enum:
+ - qcom,sc7180-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-phy
then:
required:
- reg-names
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 3/4] phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
2020-02-12 11:21 [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
2020-02-12 11:21 ` [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml Sandeep Maheswaram
2020-02-12 11:21 ` [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180 Sandeep Maheswaram
@ 2020-02-12 11:21 ` Sandeep Maheswaram
2020-02-12 20:52 ` Matthias Kaehlcke
2020-02-12 11:21 ` [PATCH v3 4/4] arm64: dts: qcom: sc7180: Correct qmp phy reset entries Sandeep Maheswaram
2020-03-05 18:57 ` [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Matthias Kaehlcke
4 siblings, 1 reply; 13+ messages in thread
From: Sandeep Maheswaram @ 2020-02-12 11:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Adding QMP v3 USB3 phy support for SC7180.
Adding only usb phy reset in the list to avoid
reset of DP block.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 7db2a94..dc300a9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1139,6 +1139,10 @@ static const char * const msm8996_usb3phy_reset_l[] = {
"phy", "common",
};
+static const char * const sc7180_usb3phy_reset_l[] = {
+ "phy",
+};
+
/* list of regulators */
static const char * const qmp_phy_vreg_l[] = {
"vdda-phy", "vdda-pll",
@@ -1265,6 +1269,37 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.is_dual_lane_phy = true,
};
+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+
+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
+ .tx_tbl = qmp_v3_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
+ .rx_tbl = qmp_v3_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
+ .clk_list = qmp_v3_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+ .reset_list = sc7180_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v3_usb3phy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+
+ .has_phy_dp_com_ctrl = true,
+ .is_dual_lane_phy = true,
+};
+
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -2103,6 +2138,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
}, {
+ .compatible = "qcom,sc7180-qmp-usb3-phy",
+ .data = &sc7180_usb3phy_cfg,
+ }, {
.compatible = "qcom,sdm845-qmp-usb3-phy",
.data = &qmp_v3_usb3phy_cfg,
}, {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 4/4] arm64: dts: qcom: sc7180: Correct qmp phy reset entries
2020-02-12 11:21 [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
` (2 preceding siblings ...)
2020-02-12 11:21 ` [PATCH v3 3/4] phy: qcom-qmp: Add QMP V3 USB3 PHY " Sandeep Maheswaram
@ 2020-02-12 11:21 ` Sandeep Maheswaram
2020-02-12 20:56 ` Matthias Kaehlcke
2020-03-05 18:57 ` [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Matthias Kaehlcke
4 siblings, 1 reply; 13+ messages in thread
From: Sandeep Maheswaram @ 2020-02-12 11:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
The phy reset entries were incorrect.so swapped them.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 8011c5f..63bd7f1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1081,8 +1081,8 @@
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: phy@88e9200 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml
2020-02-12 11:21 ` [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml Sandeep Maheswaram
@ 2020-02-12 20:16 ` Matthias Kaehlcke
2020-02-13 20:42 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Matthias Kaehlcke @ 2020-02-12 20:16 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
Hi Sandeep,
On Wed, Feb 12, 2020 at 04:51:25PM +0530, Sandeep Maheswaram wrote:
> Convert QMP phy bindings to DT schema format using json-schema.
nit: s/phy bindings/PHY bindings/
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 283 +++++++++++++++++++++
> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 227 -----------------
> 2 files changed, 283 insertions(+), 227 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> new file mode 100644
> index 0000000..b39a594
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> @@ -0,0 +1,283 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm QMP PHY controller
> +
> +maintainers:
> + - Manu Gautam <mgautam@codeaurora.org>
> +
> +description:
> + QMP phy controller supports physical layer functionality for a number of
> + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq8074-qmp-pcie-phy
> + - qcom,msm8996-qmp-pcie-phy
> + - qcom,msm8996-qmp-usb3-phy
> + - qcom,msm8998-qmp-usb3-phy
> + - qcom,msm8998-qmp-ufs-phy
> + - qcom,msm8998-qmp-pcie-phy
> + - qcom,sdm845-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-uni-phy
> + - qcom,sdm845-qmp-ufs-phy
> + - qcom,sm8150-qmp-ufs-phy
nit: sort in alphabetical order (i.e. -pcie, -ufs, -usb3)?
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Address and length of PHY's common serdes block.
> + - description: Address and length of the DP_COM control block.
> +
> + reg-names:
> + items:
> + - const: reg-base
> + - const: dp_com
> +
> + "#clock-cells":
> + enum: [ 1, 2 ]
> +
> + "#address-cells":
> + enum: [ 1, 2 ]
> +
> + "#size-cells":
> + enum: [ 1, 2 ]
> +
> + clocks:
> + maxItems: 4
> + minItems: 1
nit: minItems before maxItems, which is the order humans expect, also
it is the prevalent order in other .yaml bindings.
Do we actually need min/maxItems? I would expect the below rules for each
compatible string to take care of it, however I'm not a schema expert.
> +
> + clock-names:
> + maxItems: 4
> + minItems: 1
> + resets:
> + maxItems: 3
> + minItems: 1
> +
> + reset-names:
> + maxItems: 3
> + minItems: 1
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> + vddp-ref-clk-supply:
> + description:
> + Phandle to a regulator supply to any specific refclk
> + pll block.
> +
> +#Required nodes:
> +patternProperties:
> + "^lanes@[0-9a-f]+$":
> + type: object
> + description:
> + Each device node of QMP phy is required to have as many child nodes as
> + the number of lanes the PHY has.
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#address-cells"
> + - "#size-cells"
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> +additionalProperties: false
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
fix indentation (2 blanks, not 3)
> + - qcom,sdm845-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-uni-phy
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Phy aux clock.
> + - description: Phy config clock.
> + - description: 19.2 MHz ref clk.
> + - description: Phy common block aux clock.
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: com_aux
> + resets:
> + items:
> + - description: reset of phy block.
> + - description: phy common block reset.
> + reset-names:
> + items:
> + - const: phy
> + - const: common
fix indentation (3 -> 2)
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
fix indentation (3 -> 2)
> + - qcom,msm8996-qmp-pcie-phy
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Phy aux clock.
> + - description: Phy config clock.
> + - description: 19.2 MHz ref clk.
> +
nit: remove empty line or add it everywhere.
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + resets:
> + items:
> + - description: reset of phy block.
> + - description: phy common block reset.
> + - description: phy's ahb cfg block reset.
> + reset-names:
> + items:
> + - const: phy
> + - const: common
> + - const: cfg
fix indentation (3 -> 2)
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
fix indentation (3 -> 2)
> + - qcom,msm8996-qmp-pcie-phy
> + - qcom,msm8996-qmp-usb3-phy
> + - qcom,msm8998-qmp-pcie-phy
> + - qcom,msm8998-qmp-usb3-phy
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Phy aux clock.
> + - description: Phy config clock.
> + - description: 19.2 MHz ref clk.
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + resets:
> + items:
> + - description: reset of phy block.
> + - description: phy common block reset.
> + reset-names:
> + items:
> + - const: phy
> + - const: common
According to the .txt binding this is not correct for
'qcom,msm8996-qmp-pcie-phy':
For "qcom,msm8996-qmp-pcie-phy" must contain:
"phy", "common", "cfg".
This also matches the actual use in arch/arm64/boot/dts/qcom/msm8996.dtsi
Also the indentation needs to be fixed (3 -> 2)
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
fix indentation (3 -> 2)
> + - qcom,msm8998-qmp-ufs-phy
> + - qcom,sdm845-qmp-ufs-phy
> + - qcom,sm8150-qmp-ufs-phy
> + then:
> + properties:
> + clocks:
> + items:
> + - description: 19.2 MHz ref clk.
> + - description: Phy reference aux clock.
> + clock-names:
> + items:
> + - const: ref
> + - const: ref_aux
> + resets:
> + items:
> + - description: PHY reset in the UFS controller.
> + reset-names:
> + items:
> + - const: ufsphy
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
fix indentation (3 -> 2)
Thanks
Matthias
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180
2020-02-12 11:21 ` [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180 Sandeep Maheswaram
@ 2020-02-12 20:30 ` Matthias Kaehlcke
2020-02-18 23:05 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Matthias Kaehlcke @ 2020-02-12 20:30 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
On Wed, Feb 12, 2020 at 04:51:26PM +0530, Sandeep Maheswaram wrote:
> Add compatible for SC7180 in qmp phy bindings.
nit: QMP PHY
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> index b39a594..8c153e3 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> @@ -23,6 +23,7 @@ properties:
> - qcom,msm8998-qmp-usb3-phy
> - qcom,msm8998-qmp-ufs-phy
> - qcom,msm8998-qmp-pcie-phy
> + - qcom,sc7180-qmp-usb3-phy
> - qcom,sdm845-qmp-usb3-phy
> - qcom,sdm845-qmp-usb3-uni-phy
> - qcom,sdm845-qmp-ufs-phy
> @@ -105,9 +106,10 @@ allOf:
> properties:
> compatible:
> contains:
> - enum:
> - - qcom,sdm845-qmp-usb3-phy
> - - qcom,sdm845-qmp-usb3-uni-phy
> + enum:
> + - qcom,sc7180-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-uni-phy
There is some extra churn from fixing the indentation, but that's the
fault of the parent patch and will go away when $parent is fixed.
> then:
> properties:
> clocks:
> @@ -238,7 +240,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: qcom,sdm845-qmp-usb3-phy
> + enum:
> + - qcom,sc7180-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-phy
> then:
> required:
> - reg-names
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/4] phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
2020-02-12 11:21 ` [PATCH v3 3/4] phy: qcom-qmp: Add QMP V3 USB3 PHY " Sandeep Maheswaram
@ 2020-02-12 20:52 ` Matthias Kaehlcke
0 siblings, 0 replies; 13+ messages in thread
From: Matthias Kaehlcke @ 2020-02-12 20:52 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
On Wed, Feb 12, 2020 at 04:51:27PM +0530, Sandeep Maheswaram wrote:
> Adding QMP v3 USB3 phy support for SC7180.
> Adding only usb phy reset in the list to avoid
> reset of DP block.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 7db2a94..dc300a9 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -1139,6 +1139,10 @@ static const char * const msm8996_usb3phy_reset_l[] = {
> "phy", "common",
> };
>
> +static const char * const sc7180_usb3phy_reset_l[] = {
> + "phy",
> +};
> +
> /* list of regulators */
> static const char * const qmp_phy_vreg_l[] = {
> "vdda-phy", "vdda-pll",
> @@ -1265,6 +1269,37 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
> .is_dual_lane_phy = true,
> };
>
> +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
> .type = PHY_TYPE_USB3,
> .nlanes = 1,
> @@ -2103,6 +2138,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> .compatible = "qcom,ipq8074-qmp-pcie-phy",
> .data = &ipq8074_pciephy_cfg,
> }, {
> + .compatible = "qcom,sc7180-qmp-usb3-phy",
> + .data = &sc7180_usb3phy_cfg,
> + }, {
> .compatible = "qcom,sdm845-qmp-usb3-phy",
> .data = &qmp_v3_usb3phy_cfg,
> }, {
I don't claim to be really knowledgable about this driver, but I confirmed
that this matches qmp_v3_usb3phy_cfg, except for the resets, since we don't
want to reset DP from the USB driver.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 4/4] arm64: dts: qcom: sc7180: Correct qmp phy reset entries
2020-02-12 11:21 ` [PATCH v3 4/4] arm64: dts: qcom: sc7180: Correct qmp phy reset entries Sandeep Maheswaram
@ 2020-02-12 20:56 ` Matthias Kaehlcke
0 siblings, 0 replies; 13+ messages in thread
From: Matthias Kaehlcke @ 2020-02-12 20:56 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
On Wed, Feb 12, 2020 at 04:51:28PM +0530, Sandeep Maheswaram wrote:
> The phy reset entries were incorrect.so swapped them.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 8011c5f..63bd7f1 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1081,8 +1081,8 @@
> <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> clock-names = "aux", "cfg_ahb", "ref", "com_aux";
>
> - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> - <&gcc GCC_USB3_PHY_PRIM_BCR>;
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> reset-names = "phy", "common";
>
> usb_1_ssphy: phy@88e9200 {
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml
2020-02-12 11:21 ` [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml Sandeep Maheswaram
2020-02-12 20:16 ` Matthias Kaehlcke
@ 2020-02-13 20:42 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-02-13 20:42 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke,
linux-arm-msm, linux-kernel, devicetree, Manu Gautam,
Sandeep Maheswaram
On Wed, 12 Feb 2020 16:51:25 +0530, Sandeep Maheswaram wrote:
> Convert QMP phy bindings to DT schema format using json-schema.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 283 +++++++++++++++++++++
> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 227 -----------------
> 2 files changed, 283 insertions(+), 227 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/qcom,qmp-phy.example.dt.yaml: phy@88e9000: '#phy-cells' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/qcom,qmp-phy.example.dt.yaml: lanes@88e9200: '#clock-cells' is a dependency of 'clock-output-names'
See https://patchwork.ozlabs.org/patch/1236789
Please check and re-submit.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180
2020-02-12 11:21 ` [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180 Sandeep Maheswaram
2020-02-12 20:30 ` Matthias Kaehlcke
@ 2020-02-18 23:05 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-02-18 23:05 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke,
linux-arm-msm, linux-kernel, devicetree, Manu Gautam,
Sandeep Maheswaram
On Wed, 12 Feb 2020 16:51:26 +0530, Sandeep Maheswaram wrote:
> Add compatible for SC7180 in qmp phy bindings.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180
2020-02-12 11:21 [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
` (3 preceding siblings ...)
2020-02-12 11:21 ` [PATCH v3 4/4] arm64: dts: qcom: sc7180: Correct qmp phy reset entries Sandeep Maheswaram
@ 2020-03-05 18:57 ` Matthias Kaehlcke
2020-03-06 11:21 ` Sandeep Maheswaram (Temp)
4 siblings, 1 reply; 13+ messages in thread
From: Matthias Kaehlcke @ 2020-03-05 18:57 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
Hi Sandeep,
this series has a few minor outstanding comments that prevent it from
landing. Do you plan to respin it soon?
Thanks
Matthias
On Wed, Feb 12, 2020 at 04:51:24PM +0530, Sandeep Maheswaram wrote:
> Add QMP V3 USB3 PHY entries for SC7180 in phy driver and
> device tree bindings.
>
> changes in v3:
> *Addressed Rob's comments in yaml file.
> *Sepearated the SC7180 support in yaml patch.
> *corrected the phy reset entries in device tree.
>
> changes in v2:
> *Remove global phy reset in QMP phy.
> *Convert QMP phy bindings to yaml.
>
> Sandeep Maheswaram (4):
> dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml
> dt-bindings: phy: qcom,qmp: Add support for SC7180
> phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
> arm64: dts: qcom: sc7180: Correct qmp phy reset entries
>
> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 287 +++++++++++++++++++++
> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 227 ----------------
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 +-
> drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++
> 4 files changed, 327 insertions(+), 229 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180
2020-03-05 18:57 ` [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Matthias Kaehlcke
@ 2020-03-06 11:21 ` Sandeep Maheswaram (Temp)
0 siblings, 0 replies; 13+ messages in thread
From: Sandeep Maheswaram (Temp) @ 2020-03-06 11:21 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
Hi Matthias,
Will do it by 3/9.
Regards
Sandeep
On 3/6/2020 12:27 AM, Matthias Kaehlcke wrote:
> Hi Sandeep,
>
> this series has a few minor outstanding comments that prevent it from
> landing. Do you plan to respin it soon?
>
> Thanks
>
> Matthias
>
> On Wed, Feb 12, 2020 at 04:51:24PM +0530, Sandeep Maheswaram wrote:
>> Add QMP V3 USB3 PHY entries for SC7180 in phy driver and
>> device tree bindings.
>>
>> changes in v3:
>> *Addressed Rob's comments in yaml file.
>> *Sepearated the SC7180 support in yaml patch.
>> *corrected the phy reset entries in device tree.
>>
>> changes in v2:
>> *Remove global phy reset in QMP phy.
>> *Convert QMP phy bindings to yaml.
>>
>> Sandeep Maheswaram (4):
>> dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml
>> dt-bindings: phy: qcom,qmp: Add support for SC7180
>> phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
>> arm64: dts: qcom: sc7180: Correct qmp phy reset entries
>>
>> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 287 +++++++++++++++++++++
>> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 227 ----------------
>> arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 +-
>> drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++
>> 4 files changed, 327 insertions(+), 229 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
>> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>>
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation
>>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-03-06 11:21 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-12 11:21 [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
2020-02-12 11:21 ` [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Convert QMP phy bindings to yaml Sandeep Maheswaram
2020-02-12 20:16 ` Matthias Kaehlcke
2020-02-13 20:42 ` Rob Herring
2020-02-12 11:21 ` [PATCH v3 2/4] dt-bindings: phy: qcom,qmp: Add support for SC7180 Sandeep Maheswaram
2020-02-12 20:30 ` Matthias Kaehlcke
2020-02-18 23:05 ` Rob Herring
2020-02-12 11:21 ` [PATCH v3 3/4] phy: qcom-qmp: Add QMP V3 USB3 PHY " Sandeep Maheswaram
2020-02-12 20:52 ` Matthias Kaehlcke
2020-02-12 11:21 ` [PATCH v3 4/4] arm64: dts: qcom: sc7180: Correct qmp phy reset entries Sandeep Maheswaram
2020-02-12 20:56 ` Matthias Kaehlcke
2020-03-05 18:57 ` [PATCH v3 0/4] Add QMP V3 USB3 PHY support for SC7180 Matthias Kaehlcke
2020-03-06 11:21 ` Sandeep Maheswaram (Temp)
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