[PATCH 1/3] gpu/drm: ingenic: Add trick to support 16bpp on 24-bit panels

[PATCH 1/3] gpu/drm: ingenic: Add trick to support 16bpp on 24-bit panels

[Paul Cercueil]

If the panel interface is 24-bit but our primary plane is 16bpp,
configure as if the panel was 18-bit. This tricks permits the display
of 16bpp data on a 24-bit panel by wiring each color component to the
MSBs of the 24-bit interface.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/gpu/drm/ingenic/ingenic-drm.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 6d47ef7b148c..034961a40e98 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -400,6 +400,8 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 	struct drm_connector *conn = conn_state->connector;
 	struct drm_display_info *info = &conn->display_info;
+	struct drm_plane_state *plane_state = crtc_state->crtc->primary->state;
+	const struct drm_format_info *finfo = NULL;
 	unsigned int cfg;
 
 	priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
@@ -435,7 +437,22 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 				cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
 				break;
 			case MEDIA_BUS_FMT_RGB888_1X24:
-				cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
+				if (plane_state && plane_state->fb)
+					finfo = plane_state->fb->format;
+
+				/*
+				 * If the panel interface is 24-bit but our
+				 * primary plane is 16bpp, configure as if the
+				 * panel was 18-bit. This tricks permits the
+				 * display of 16bpp data on a 24-bit panel by
+				 * wiring each color component to the MSBs of
+				 * the 24-bit interface.
+				 */
+				if (finfo &&
+				    finfo->format != DRM_FORMAT_XRGB8888)
+					cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
+				else
+					cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
 				break;
 			case MEDIA_BUS_FMT_RGB888_3X8:
 				cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
-- 
2.25.0

[PATCH 1/3] gpu/drm: ingenic: Add trick to support 16bpp on 24-bit panels

[Paul Cercueil]

If the panel interface is 24-bit but our primary plane is 16bpp,
configure as if the panel was 18-bit. This tricks permits the display
of 16bpp data on a 24-bit panel by wiring each color component to the
MSBs of the 24-bit interface.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/gpu/drm/ingenic/ingenic-drm.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 6d47ef7b148c..034961a40e98 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -400,6 +400,8 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 	struct drm_connector *conn = conn_state->connector;
 	struct drm_display_info *info = &conn->display_info;
+	struct drm_plane_state *plane_state = crtc_state->crtc->primary->state;
+	const struct drm_format_info *finfo = NULL;
 	unsigned int cfg;
 
 	priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
@@ -435,7 +437,22 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 				cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
 				break;
 			case MEDIA_BUS_FMT_RGB888_1X24:
-				cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
+				if (plane_state && plane_state->fb)
+					finfo = plane_state->fb->format;
+
+				/*
+				 * If the panel interface is 24-bit but our
+				 * primary plane is 16bpp, configure as if the
+				 * panel was 18-bit. This tricks permits the
+				 * display of 16bpp data on a 24-bit panel by
+				 * wiring each color component to the MSBs of
+				 * the 24-bit interface.
+				 */
+				if (finfo &&
+				    finfo->format != DRM_FORMAT_XRGB8888)
+					cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
+				else
+					cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
 				break;
 			case MEDIA_BUS_FMT_RGB888_3X8:
 				cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
-- 
2.25.0

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[PATCH 2/3] gpu/drm: ingenic: Switch emulated fbdev to 16bpp

[Paul Cercueil]

The fbdev emulation is only ever used on Ingenic SoCs to run old SDL1
based games at 16bpp (rgb565). Recent applications generally talk to
DRM directly, and can request their favourite pixel format; so we can
make everybody happy by switching the emulated fbdev to 16bpp.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 034961a40e98..9aa88fabbd2a 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -808,7 +808,7 @@ static int ingenic_drm_probe(struct platform_device *pdev)
 		goto err_devclk_disable;
 	}
 
-	ret = drm_fbdev_generic_setup(drm, 32);
+	ret = drm_fbdev_generic_setup(drm, 16);
 	if (ret)
 		dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
 
-- 
2.25.0

[PATCH 2/3] gpu/drm: ingenic: Switch emulated fbdev to 16bpp

[Paul Cercueil]

The fbdev emulation is only ever used on Ingenic SoCs to run old SDL1
based games at 16bpp (rgb565). Recent applications generally talk to
DRM directly, and can request their favourite pixel format; so we can
make everybody happy by switching the emulated fbdev to 16bpp.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 034961a40e98..9aa88fabbd2a 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -808,7 +808,7 @@ static int ingenic_drm_probe(struct platform_device *pdev)
 		goto err_devclk_disable;
 	}
 
-	ret = drm_fbdev_generic_setup(drm, 32);
+	ret = drm_fbdev_generic_setup(drm, 16);
 	if (ret)
 		dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
 
-- 
2.25.0

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[PATCH 3/3] gpu/drm: ingenic: Add option to mmap GEM buffers cached

[Paul Cercueil]

Ingenic SoCs are most notably used in cheap chinese handheld gaming
consoles. There, the games and applications generally render in software
directly in the emulated framebuffer using SDL1.

Since the emulated framebuffer is mapped as write-combine by default,
these applications start to run really slow as soon as alpha-blending is
used.

Add a 'cached_gem_buffers' option to the ingenic-drm driver to mmap the
GEM buffers as fully cached to address this issue.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/gpu/drm/ingenic/ingenic-drm.c | 41 +++++++++++++++++++++++++--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 9aa88fabbd2a..31f0346b55f0 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -6,6 +6,7 @@
 
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
@@ -30,6 +31,11 @@
 #include <drm/drm_probe_helper.h>
 #include <drm/drm_vblank.h>
 
+static bool ingenic_drm_cached_gem_buf;
+module_param_named(cached_gem_buffers, ingenic_drm_cached_gem_buf, bool, 0400);
+MODULE_PARM_DESC(cached_gem_buffers,
+		 "Enable fully cached GEM buffers [default=false]");
+
 #define JZ_REG_LCD_CFG				0x00
 #define JZ_REG_LCD_VSYNC			0x04
 #define JZ_REG_LCD_HSYNC			0x08
@@ -378,16 +384,25 @@ static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
 	struct ingenic_drm *priv = drm_plane_get_priv(plane);
 	struct drm_plane_state *state = plane->state;
 	unsigned int width, height, cpp;
+	unsigned long virt_addr;
 	dma_addr_t addr;
+	uint32_t len;
 
 	if (state && state->fb) {
 		addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
+
 		width = state->src_w >> 16;
 		height = state->src_h >> 16;
 		cpp = state->fb->format->cpp[plane->index];
+		len = width * height * cpp;
+
+		if (ingenic_drm_cached_gem_buf) {
+			virt_addr = (unsigned long)phys_to_virt(addr);
+			dma_cache_wback_inv(virt_addr, len);
+		}
 
 		priv->dma_hwdesc->addr = addr;
-		priv->dma_hwdesc->cmd = width * height * cpp / 4;
+		priv->dma_hwdesc->cmd = len / 4;
 		priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
 	}
 }
@@ -533,6 +548,28 @@ static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
 
 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
 
+static int ingenic_drm_gem_mmap(struct drm_gem_object *obj,
+				struct vm_area_struct *vma)
+{
+	unsigned long start, off;
+
+	if (!ingenic_drm_cached_gem_buf)
+		return drm_gem_cma_prime_mmap(obj, vma);
+
+	off = vma->vm_pgoff << PAGE_SHIFT;
+	start = to_drm_gem_cma_obj(obj)->paddr;
+
+	off += start;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
+	pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
+
+	return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
+				  vma->vm_end - vma->vm_start,
+				  vma->vm_page_prot);
+}
+
 static struct drm_driver ingenic_drm_driver_data = {
 	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 	.name			= "ingenic-drm",
@@ -554,7 +591,7 @@ static struct drm_driver ingenic_drm_driver_data = {
 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
 	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
-	.gem_prime_mmap		= drm_gem_cma_prime_mmap,
+	.gem_prime_mmap		= ingenic_drm_gem_mmap,
 
 	.irq_handler		= ingenic_drm_irq_handler,
 	.release		= ingenic_drm_release,
-- 
2.25.0

[PATCH 3/3] gpu/drm: ingenic: Add option to mmap GEM buffers cached

[Paul Cercueil]

Ingenic SoCs are most notably used in cheap chinese handheld gaming
consoles. There, the games and applications generally render in software
directly in the emulated framebuffer using SDL1.

Since the emulated framebuffer is mapped as write-combine by default,
these applications start to run really slow as soon as alpha-blending is
used.

Add a 'cached_gem_buffers' option to the ingenic-drm driver to mmap the
GEM buffers as fully cached to address this issue.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/gpu/drm/ingenic/ingenic-drm.c | 41 +++++++++++++++++++++++++--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 9aa88fabbd2a..31f0346b55f0 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -6,6 +6,7 @@
 
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
@@ -30,6 +31,11 @@
 #include <drm/drm_probe_helper.h>
 #include <drm/drm_vblank.h>
 
+static bool ingenic_drm_cached_gem_buf;
+module_param_named(cached_gem_buffers, ingenic_drm_cached_gem_buf, bool, 0400);
+MODULE_PARM_DESC(cached_gem_buffers,
+		 "Enable fully cached GEM buffers [default=false]");
+
 #define JZ_REG_LCD_CFG				0x00
 #define JZ_REG_LCD_VSYNC			0x04
 #define JZ_REG_LCD_HSYNC			0x08
@@ -378,16 +384,25 @@ static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
 	struct ingenic_drm *priv = drm_plane_get_priv(plane);
 	struct drm_plane_state *state = plane->state;
 	unsigned int width, height, cpp;
+	unsigned long virt_addr;
 	dma_addr_t addr;
+	uint32_t len;
 
 	if (state && state->fb) {
 		addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
+
 		width = state->src_w >> 16;
 		height = state->src_h >> 16;
 		cpp = state->fb->format->cpp[plane->index];
+		len = width * height * cpp;
+
+		if (ingenic_drm_cached_gem_buf) {
+			virt_addr = (unsigned long)phys_to_virt(addr);
+			dma_cache_wback_inv(virt_addr, len);
+		}
 
 		priv->dma_hwdesc->addr = addr;
-		priv->dma_hwdesc->cmd = width * height * cpp / 4;
+		priv->dma_hwdesc->cmd = len / 4;
 		priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
 	}
 }
@@ -533,6 +548,28 @@ static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
 
 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
 
+static int ingenic_drm_gem_mmap(struct drm_gem_object *obj,
+				struct vm_area_struct *vma)
+{
+	unsigned long start, off;
+
+	if (!ingenic_drm_cached_gem_buf)
+		return drm_gem_cma_prime_mmap(obj, vma);
+
+	off = vma->vm_pgoff << PAGE_SHIFT;
+	start = to_drm_gem_cma_obj(obj)->paddr;
+
+	off += start;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
+	pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
+
+	return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
+				  vma->vm_end - vma->vm_start,
+				  vma->vm_page_prot);
+}
+
 static struct drm_driver ingenic_drm_driver_data = {
 	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 	.name			= "ingenic-drm",
@@ -554,7 +591,7 @@ static struct drm_driver ingenic_drm_driver_data = {
 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
 	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
-	.gem_prime_mmap		= drm_gem_cma_prime_mmap,
+	.gem_prime_mmap		= ingenic_drm_gem_mmap,
 
 	.irq_handler		= ingenic_drm_irq_handler,
 	.release		= ingenic_drm_release,
-- 
2.25.0

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Re: [PATCH 2/3] gpu/drm: ingenic: Switch emulated fbdev to 16bpp

[Daniel Vetter]

On Sun, Feb 16, 2020 at 12:58:10PM -0300, Paul Cercueil wrote:
> The fbdev emulation is only ever used on Ingenic SoCs to run old SDL1
> based games at 16bpp (rgb565). Recent applications generally talk to
> DRM directly, and can request their favourite pixel format; so we can
> make everybody happy by switching the emulated fbdev to 16bpp.
> 
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>  drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
> index 034961a40e98..9aa88fabbd2a 100644
> --- a/drivers/gpu/drm/ingenic/ingenic-drm.c
> +++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
> @@ -808,7 +808,7 @@ static int ingenic_drm_probe(struct platform_device *pdev)
>  		goto err_devclk_disable;
>  	}
>  
> -	ret = drm_fbdev_generic_setup(drm, 32);
> +	ret = drm_fbdev_generic_setup(drm, 16);

If you're really bored, could we make everyone even more happy by exposing
format switching in the drm fbdev emulation? Only for the drivers which
have a full format list on the primary plane (gets too tricky otherwise).
And obviously only formats that have lower bpp than the one we booted with
(can't reallocate the framebuffer because fbdev).

Just as an idea, this shouldn't be too horrible amounts of work to wire
up. But ofc more than this oneliner :-)

Cheers, Daniel

>  	if (ret)
>  		dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
>  
> -- 
> 2.25.0
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [PATCH 2/3] gpu/drm: ingenic: Switch emulated fbdev to 16bpp

[Daniel Vetter]

On Sun, Feb 16, 2020 at 12:58:10PM -0300, Paul Cercueil wrote:
> The fbdev emulation is only ever used on Ingenic SoCs to run old SDL1
> based games at 16bpp (rgb565). Recent applications generally talk to
> DRM directly, and can request their favourite pixel format; so we can
> make everybody happy by switching the emulated fbdev to 16bpp.
> 
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>  drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
> index 034961a40e98..9aa88fabbd2a 100644
> --- a/drivers/gpu/drm/ingenic/ingenic-drm.c
> +++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
> @@ -808,7 +808,7 @@ static int ingenic_drm_probe(struct platform_device *pdev)
>  		goto err_devclk_disable;
>  	}
>  
> -	ret = drm_fbdev_generic_setup(drm, 32);
> +	ret = drm_fbdev_generic_setup(drm, 16);

If you're really bored, could we make everyone even more happy by exposing
format switching in the drm fbdev emulation? Only for the drivers which
have a full format list on the primary plane (gets too tricky otherwise).
And obviously only formats that have lower bpp than the one we booted with
(can't reallocate the framebuffer because fbdev).

Just as an idea, this shouldn't be too horrible amounts of work to wire
up. But ofc more than this oneliner :-)

Cheers, Daniel

>  	if (ret)
>  		dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
>  
> -- 
> 2.25.0
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 3/3] gpu/drm: ingenic: Add option to mmap GEM buffers cached

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 9463 bytes --]

Hi Paul,

I love your patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on linus/master v5.6-rc2 next-20200218]
[cannot apply to tegra-drm/drm/tegra/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Paul-Cercueil/gpu-drm-ingenic-Add-trick-to-support-16bpp-on-24-bit-panels/20200218-234500
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: alpha-allmodconfig (attached as .config)
compiler: alpha-linux-gcc (GCC) 7.5.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.5.0 make.cross ARCH=alpha 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/ingenic/ingenic-drm.c: In function 'ingenic_drm_plane_atomic_update':
>> drivers/gpu/drm/ingenic/ingenic-drm.c:401:4: error: implicit declaration of function 'dma_cache_wback_inv'; did you mean 'dma_cache_sync'? [-Werror=implicit-function-declaration]
       dma_cache_wback_inv(virt_addr, len);
       ^~~~~~~~~~~~~~~~~~~
       dma_cache_sync
   drivers/gpu/drm/ingenic/ingenic-drm.c: In function 'ingenic_drm_gem_mmap':
>> drivers/gpu/drm/ingenic/ingenic-drm.c:565:36: error: '_CACHE_MASK' undeclared (first use in this function); did you mean 'VMACACHE_MASK'?
     pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
                                       ^~~~~~~~~~~
                                       VMACACHE_MASK
   drivers/gpu/drm/ingenic/ingenic-drm.c:565:36: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/ingenic/ingenic-drm.c:566:35: error: '_CACHE_CACHABLE_NONCOHERENT' undeclared (first use in this function); did you mean 'ACPI_CACHABLE_MEMORY'?
     pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~
                                      ACPI_CACHABLE_MEMORY
   cc1: some warnings being treated as errors

vim +401 drivers/gpu/drm/ingenic/ingenic-drm.c

   380	
   381	static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
   382						    struct drm_plane_state *oldstate)
   383	{
   384		struct ingenic_drm *priv = drm_plane_get_priv(plane);
   385		struct drm_plane_state *state = plane->state;
   386		unsigned int width, height, cpp;
   387		unsigned long virt_addr;
   388		dma_addr_t addr;
   389		uint32_t len;
   390	
   391		if (state && state->fb) {
   392			addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
   393	
   394			width = state->src_w >> 16;
   395			height = state->src_h >> 16;
   396			cpp = state->fb->format->cpp[plane->index];
   397			len = width * height * cpp;
   398	
   399			if (ingenic_drm_cached_gem_buf) {
   400				virt_addr = (unsigned long)phys_to_virt(addr);
 > 401				dma_cache_wback_inv(virt_addr, len);
   402			}
   403	
   404			priv->dma_hwdesc->addr = addr;
   405			priv->dma_hwdesc->cmd = len / 4;
   406			priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
   407		}
   408	}
   409	
   410	static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
   411							struct drm_crtc_state *crtc_state,
   412							struct drm_connector_state *conn_state)
   413	{
   414		struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
   415		struct drm_display_mode *mode = &crtc_state->adjusted_mode;
   416		struct drm_connector *conn = conn_state->connector;
   417		struct drm_display_info *info = &conn->display_info;
   418		struct drm_plane_state *plane_state = crtc_state->crtc->primary->state;
   419		const struct drm_format_info *finfo = NULL;
   420		unsigned int cfg;
   421	
   422		priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
   423	
   424		if (priv->panel_is_sharp) {
   425			cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
   426		} else {
   427			cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
   428			    | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
   429		}
   430	
   431		if (mode->flags & DRM_MODE_FLAG_NHSYNC)
   432			cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
   433		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
   434			cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
   435		if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
   436			cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
   437		if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
   438			cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
   439	
   440		if (!priv->panel_is_sharp) {
   441			if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
   442				if (mode->flags & DRM_MODE_FLAG_INTERLACE)
   443					cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
   444				else
   445					cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
   446			} else {
   447				switch (*info->bus_formats) {
   448				case MEDIA_BUS_FMT_RGB565_1X16:
   449					cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
   450					break;
   451				case MEDIA_BUS_FMT_RGB666_1X18:
   452					cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
   453					break;
   454				case MEDIA_BUS_FMT_RGB888_1X24:
   455					if (plane_state && plane_state->fb)
   456						finfo = plane_state->fb->format;
   457	
   458					/*
   459					 * If the panel interface is 24-bit but our
   460					 * primary plane is 16bpp, configure as if the
   461					 * panel was 18-bit. This tricks permits the
   462					 * display of 16bpp data on a 24-bit panel by
   463					 * wiring each color component to the MSBs of
   464					 * the 24-bit interface.
   465					 */
   466					if (finfo &&
   467					    finfo->format != DRM_FORMAT_XRGB8888)
   468						cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
   469					else
   470						cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
   471					break;
   472				case MEDIA_BUS_FMT_RGB888_3X8:
   473					cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
   474					break;
   475				default:
   476					break;
   477				}
   478			}
   479		}
   480	
   481		regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
   482	}
   483	
   484	static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
   485						    struct drm_crtc_state *crtc_state,
   486						    struct drm_connector_state *conn_state)
   487	{
   488		struct drm_display_info *info = &conn_state->connector->display_info;
   489	
   490		if (info->num_bus_formats != 1)
   491			return -EINVAL;
   492	
   493		if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
   494			return 0;
   495	
   496		switch (*info->bus_formats) {
   497		case MEDIA_BUS_FMT_RGB565_1X16:
   498		case MEDIA_BUS_FMT_RGB666_1X18:
   499		case MEDIA_BUS_FMT_RGB888_1X24:
   500		case MEDIA_BUS_FMT_RGB888_3X8:
   501			return 0;
   502		default:
   503			return -EINVAL;
   504		}
   505	}
   506	
   507	static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
   508	{
   509		struct ingenic_drm *priv = arg;
   510		unsigned int state;
   511	
   512		regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
   513	
   514		regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
   515				   JZ_LCD_STATE_EOF_IRQ, 0);
   516	
   517		if (state & JZ_LCD_STATE_EOF_IRQ)
   518			drm_crtc_handle_vblank(&priv->crtc);
   519	
   520		return IRQ_HANDLED;
   521	}
   522	
   523	static void ingenic_drm_release(struct drm_device *drm)
   524	{
   525		struct ingenic_drm *priv = drm_device_get_priv(drm);
   526	
   527		drm_mode_config_cleanup(drm);
   528		drm_dev_fini(drm);
   529		kfree(priv);
   530	}
   531	
   532	static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
   533	{
   534		struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
   535	
   536		regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
   537				   JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
   538	
   539		return 0;
   540	}
   541	
   542	static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
   543	{
   544		struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
   545	
   546		regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
   547	}
   548	
   549	DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
   550	
   551	static int ingenic_drm_gem_mmap(struct drm_gem_object *obj,
   552					struct vm_area_struct *vma)
   553	{
   554		unsigned long start, off;
   555	
   556		if (!ingenic_drm_cached_gem_buf)
   557			return drm_gem_cma_prime_mmap(obj, vma);
   558	
   559		off = vma->vm_pgoff << PAGE_SHIFT;
   560		start = to_drm_gem_cma_obj(obj)->paddr;
   561	
   562		off += start;
   563	
   564		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 > 565		pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
 > 566		pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
   567	
   568		return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
   569					  vma->vm_end - vma->vm_start,
   570					  vma->vm_page_prot);
   571	}
   572	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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Re: [PATCH 3/3] gpu/drm: ingenic: Add option to mmap GEM buffers cached

[kbuild test robot]

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Hi Paul,

I love your patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next linus/master v5.6-rc2 next-20200218]
[cannot apply to tegra-drm/drm/tegra/for-next drm/drm-next]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Paul-Cercueil/gpu-drm-ingenic-Add-trick-to-support-16bpp-on-24-bit-panels/20200218-234500
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: s390-allmodconfig (attached as .config)
compiler: s390-linux-gcc (GCC) 7.5.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.5.0 make.cross ARCH=s390 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu//drm/ingenic/ingenic-drm.c: In function 'ingenic_drm_plane_atomic_update':
   drivers/gpu//drm/ingenic/ingenic-drm.c:401:4: error: implicit declaration of function 'dma_cache_wback_inv'; did you mean 'dma_cache_sync'? [-Werror=implicit-function-declaration]
       dma_cache_wback_inv(virt_addr, len);
       ^~~~~~~~~~~~~~~~~~~
       dma_cache_sync
   drivers/gpu//drm/ingenic/ingenic-drm.c: In function 'ingenic_drm_gem_mmap':
>> drivers/gpu//drm/ingenic/ingenic-drm.c:565:36: error: '_CACHE_MASK' undeclared (first use in this function); did you mean '_PAGE_MASK'?
     pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
                                       ^~~~~~~~~~~
                                       _PAGE_MASK
   drivers/gpu//drm/ingenic/ingenic-drm.c:565:36: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu//drm/ingenic/ingenic-drm.c:566:35: error: '_CACHE_CACHABLE_NONCOHERENT' undeclared (first use in this function); did you mean 'ACPI_CACHABLE_MEMORY'?
     pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~
                                      ACPI_CACHABLE_MEMORY
   cc1: some warnings being treated as errors

vim +565 drivers/gpu//drm/ingenic/ingenic-drm.c

   380	
   381	static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
   382						    struct drm_plane_state *oldstate)
   383	{
   384		struct ingenic_drm *priv = drm_plane_get_priv(plane);
   385		struct drm_plane_state *state = plane->state;
   386		unsigned int width, height, cpp;
   387		unsigned long virt_addr;
   388		dma_addr_t addr;
   389		uint32_t len;
   390	
   391		if (state && state->fb) {
   392			addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
   393	
   394			width = state->src_w >> 16;
   395			height = state->src_h >> 16;
   396			cpp = state->fb->format->cpp[plane->index];
   397			len = width * height * cpp;
   398	
   399			if (ingenic_drm_cached_gem_buf) {
   400				virt_addr = (unsigned long)phys_to_virt(addr);
 > 401				dma_cache_wback_inv(virt_addr, len);
   402			}
   403	
   404			priv->dma_hwdesc->addr = addr;
   405			priv->dma_hwdesc->cmd = len / 4;
   406			priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
   407		}
   408	}
   409	
   410	static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
   411							struct drm_crtc_state *crtc_state,
   412							struct drm_connector_state *conn_state)
   413	{
   414		struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
   415		struct drm_display_mode *mode = &crtc_state->adjusted_mode;
   416		struct drm_connector *conn = conn_state->connector;
   417		struct drm_display_info *info = &conn->display_info;
   418		struct drm_plane_state *plane_state = crtc_state->crtc->primary->state;
   419		const struct drm_format_info *finfo = NULL;
   420		unsigned int cfg;
   421	
   422		priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
   423	
   424		if (priv->panel_is_sharp) {
   425			cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
   426		} else {
   427			cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
   428			    | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
   429		}
   430	
   431		if (mode->flags & DRM_MODE_FLAG_NHSYNC)
   432			cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
   433		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
   434			cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
   435		if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
   436			cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
   437		if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
   438			cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
   439	
   440		if (!priv->panel_is_sharp) {
   441			if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
   442				if (mode->flags & DRM_MODE_FLAG_INTERLACE)
   443					cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
   444				else
   445					cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
   446			} else {
   447				switch (*info->bus_formats) {
   448				case MEDIA_BUS_FMT_RGB565_1X16:
   449					cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
   450					break;
   451				case MEDIA_BUS_FMT_RGB666_1X18:
   452					cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
   453					break;
   454				case MEDIA_BUS_FMT_RGB888_1X24:
   455					if (plane_state && plane_state->fb)
   456						finfo = plane_state->fb->format;
   457	
   458					/*
   459					 * If the panel interface is 24-bit but our
   460					 * primary plane is 16bpp, configure as if the
   461					 * panel was 18-bit. This tricks permits the
   462					 * display of 16bpp data on a 24-bit panel by
   463					 * wiring each color component to the MSBs of
   464					 * the 24-bit interface.
   465					 */
   466					if (finfo &&
   467					    finfo->format != DRM_FORMAT_XRGB8888)
   468						cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
   469					else
   470						cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
   471					break;
   472				case MEDIA_BUS_FMT_RGB888_3X8:
   473					cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
   474					break;
   475				default:
   476					break;
   477				}
   478			}
   479		}
   480	
   481		regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
   482	}
   483	
   484	static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
   485						    struct drm_crtc_state *crtc_state,
   486						    struct drm_connector_state *conn_state)
   487	{
   488		struct drm_display_info *info = &conn_state->connector->display_info;
   489	
   490		if (info->num_bus_formats != 1)
   491			return -EINVAL;
   492	
   493		if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
   494			return 0;
   495	
   496		switch (*info->bus_formats) {
   497		case MEDIA_BUS_FMT_RGB565_1X16:
   498		case MEDIA_BUS_FMT_RGB666_1X18:
   499		case MEDIA_BUS_FMT_RGB888_1X24:
   500		case MEDIA_BUS_FMT_RGB888_3X8:
   501			return 0;
   502		default:
   503			return -EINVAL;
   504		}
   505	}
   506	
   507	static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
   508	{
   509		struct ingenic_drm *priv = arg;
   510		unsigned int state;
   511	
   512		regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
   513	
   514		regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
   515				   JZ_LCD_STATE_EOF_IRQ, 0);
   516	
   517		if (state & JZ_LCD_STATE_EOF_IRQ)
   518			drm_crtc_handle_vblank(&priv->crtc);
   519	
   520		return IRQ_HANDLED;
   521	}
   522	
   523	static void ingenic_drm_release(struct drm_device *drm)
   524	{
   525		struct ingenic_drm *priv = drm_device_get_priv(drm);
   526	
   527		drm_mode_config_cleanup(drm);
   528		drm_dev_fini(drm);
   529		kfree(priv);
   530	}
   531	
   532	static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
   533	{
   534		struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
   535	
   536		regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
   537				   JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
   538	
   539		return 0;
   540	}
   541	
   542	static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
   543	{
   544		struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
   545	
   546		regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
   547	}
   548	
   549	DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
   550	
   551	static int ingenic_drm_gem_mmap(struct drm_gem_object *obj,
   552					struct vm_area_struct *vma)
   553	{
   554		unsigned long start, off;
   555	
   556		if (!ingenic_drm_cached_gem_buf)
   557			return drm_gem_cma_prime_mmap(obj, vma);
   558	
   559		off = vma->vm_pgoff << PAGE_SHIFT;
   560		start = to_drm_gem_cma_obj(obj)->paddr;
   561	
   562		off += start;
   563	
   564		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 > 565		pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
   566		pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
   567	
   568		return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
   569					  vma->vm_end - vma->vm_start,
   570					  vma->vm_page_prot);
   571	}
   572	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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