* [PATCH 0/3] target/arm: Implement v8.3-RCPC and v8.4-RCPC
@ 2020-02-24 17:28 Peter Maydell
2020-02-24 17:28 ` [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Peter Maydell @ 2020-02-24 17:28 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
This patchset implements the Arm architectural features
ARMv8.3-RCPC and ARMv8.4-RCPC. These provide a handful of
new load and store instructions which have "LoadAcquirePC"
semantics. These are slightly weaker than standard
"LoadAcquire", so we choose to implement them in QEMU as
LoadAcquire.
Patch 1 is a trivial fix to the PMU isar function which
I managed to cut-n-paste with the wrong FIELD_EX* macro.
I've tested these using risu against an Arm AEM FVP model:
this doesn't do anything to test the memory barrier semantics
but does work as a check that the decode is correct and
that the various signed/unsigned/extend/etc operations
are being done correctly.
thanks
-- PMM
Peter Maydell (3):
target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
target/arm: Implement v8.3-RCPC
target/arm: Implement v8.4-RCPC
target/arm/cpu.h | 14 ++++-
linux-user/elfload.c | 2 +
target/arm/cpu64.c | 1 +
target/arm/translate-a64.c | 114 +++++++++++++++++++++++++++++++++++++
4 files changed, 129 insertions(+), 2 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 2020-02-24 17:28 [PATCH 0/3] target/arm: Implement v8.3-RCPC and v8.4-RCPC Peter Maydell @ 2020-02-24 17:28 ` Peter Maydell 2020-02-24 17:48 ` Philippe Mathieu-Daudé 2020-02-24 18:23 ` Richard Henderson 2020-02-24 17:28 ` [PATCH 2/3] target/arm: Implement v8.3-RCPC Peter Maydell 2020-02-24 17:28 ` [PATCH 3/3] target/arm: Implement v8.4-RCPC Peter Maydell 2 siblings, 2 replies; 9+ messages in thread From: Peter Maydell @ 2020-02-24 17:28 UTC (permalink / raw) To: qemu-arm, qemu-devel; +Cc: Richard Henderson We missed an instance of using FIELD_EX32 on a 64-bit ID register, in isar_feature_aa64_pmu_8_4(). Fix it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30ee..b647d8df916 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3723,8 +3723,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) { - return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && - FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } /* -- 2.20.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 2020-02-24 17:28 ` [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell @ 2020-02-24 17:48 ` Philippe Mathieu-Daudé 2020-02-24 18:23 ` Richard Henderson 1 sibling, 0 replies; 9+ messages in thread From: Philippe Mathieu-Daudé @ 2020-02-24 17:48 UTC (permalink / raw) To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Richard Henderson On 2/24/20 6:28 PM, Peter Maydell wrote: > We missed an instance of using FIELD_EX32 on a 64-bit ID > register, in isar_feature_aa64_pmu_8_4(). Fix it. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/cpu.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 65171cb30ee..b647d8df916 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3723,8 +3723,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) > > static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) > { > - return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && > - FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; > + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && > + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; > } > > /* > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 2020-02-24 17:28 ` [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell 2020-02-24 17:48 ` Philippe Mathieu-Daudé @ 2020-02-24 18:23 ` Richard Henderson 1 sibling, 0 replies; 9+ messages in thread From: Richard Henderson @ 2020-02-24 18:23 UTC (permalink / raw) To: Peter Maydell, qemu-arm, qemu-devel On 2/24/20 9:28 AM, Peter Maydell wrote: > We missed an instance of using FIELD_EX32 on a 64-bit ID > register, in isar_feature_aa64_pmu_8_4(). Fix it. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/cpu.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] target/arm: Implement v8.3-RCPC 2020-02-24 17:28 [PATCH 0/3] target/arm: Implement v8.3-RCPC and v8.4-RCPC Peter Maydell 2020-02-24 17:28 ` [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell @ 2020-02-24 17:28 ` Peter Maydell 2020-02-24 18:31 ` Richard Henderson 2020-02-24 17:28 ` [PATCH 3/3] target/arm: Implement v8.4-RCPC Peter Maydell 2 siblings, 1 reply; 9+ messages in thread From: Peter Maydell @ 2020-02-24 17:28 UTC (permalink / raw) To: qemu-arm, qemu-devel; +Cc: Richard Henderson The v8.3-RCPC extension implements three new load instructions which provide slightly weaker consistency guarantees than the existing load-acquire operations. For QEMU we choose to simply implement them with a full LDAQ barrier. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 5 +++++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 24 ++++++++++++++++++++++++ 4 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b647d8df916..59b467a44bf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3727,6 +3727,11 @@ static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } +static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b1a895f24ce..a0ffbc8861d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -658,6 +658,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); + GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); return hwcaps; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0929401a4dd..59b7c574e35 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -657,6 +657,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ cpu->isar.id_aa64isar1 = t; t = cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 596bf4cf734..7a066fb7cb2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3142,6 +3142,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, int rs = extract32(insn, 16, 5); int rn = extract32(insn, 5, 5); int o3_opc = extract32(insn, 12, 4); + bool r = extract32(insn, 22, 1); + bool a = extract32(insn, 23, 1); TCGv_i64 tcg_rs, clean_addr; AtomicThreeOpFn *fn; @@ -3177,6 +3179,13 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, case 010: /* SWP */ fn = tcg_gen_atomic_xchg_i64; break; + case 014: /* LDAPR, LDAPRH, LDAPRB */ + if (!dc_isar_feature(aa64_rcpc_8_3, s) || + rs != 31 || a != 1 || r != 0) { + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -3186,6 +3195,21 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, gen_check_sp_alignment(s); } clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + + if (o3_opc == 014) { + /* + * LDAPR* are a special case because they are a simple load, not a + * fetch-and-do-something op. + * The architectural consistency requirements here are weaker than + * full load-acquire (we only need "load-acquire processor consistent"), + * but we choose to implement them as full LDAQ. + */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, + true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return; + } + tcg_rs = read_cpu_reg(s, rs, true); if (o3_opc == 1) { /* LDCLR */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] target/arm: Implement v8.3-RCPC 2020-02-24 17:28 ` [PATCH 2/3] target/arm: Implement v8.3-RCPC Peter Maydell @ 2020-02-24 18:31 ` Richard Henderson 0 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2020-02-24 18:31 UTC (permalink / raw) To: Peter Maydell, qemu-arm, qemu-devel On 2/24/20 9:28 AM, Peter Maydell wrote: > The v8.3-RCPC extension implements three new load instructions > which provide slightly weaker consistency guarantees than the > existing load-acquire operations. For QEMU we choose to simply > implement them with a full LDAQ barrier. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/cpu.h | 5 +++++ > linux-user/elfload.c | 1 + > target/arm/cpu64.c | 1 + > target/arm/translate-a64.c | 24 ++++++++++++++++++++++++ > 4 files changed, 31 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] target/arm: Implement v8.4-RCPC 2020-02-24 17:28 [PATCH 0/3] target/arm: Implement v8.3-RCPC and v8.4-RCPC Peter Maydell 2020-02-24 17:28 ` [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell 2020-02-24 17:28 ` [PATCH 2/3] target/arm: Implement v8.3-RCPC Peter Maydell @ 2020-02-24 17:28 ` Peter Maydell 2020-02-24 18:39 ` Richard Henderson 2 siblings, 1 reply; 9+ messages in thread From: Peter Maydell @ 2020-02-24 17:28 UTC (permalink / raw) To: qemu-arm, qemu-devel; +Cc: Richard Henderson The v8.4-RCPC extension implements some new instructions: * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW * STLUR, STLURB, STLURH These are all in a new subgroup of encodings that sits below the top-level "Loads and Stores" group in the Arm ARM. The STLUR* instructions have standard store-release semantics; the LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose to implement them as the slightly stronger Load-Acquire. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 5 +++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 2 +- target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 59b467a44bf..3ce453f1e01 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3732,6 +3732,11 @@ static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; } +static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a0ffbc8861d..94ec3dcab8f 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -659,6 +659,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); + GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); return hwcaps; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 59b7c574e35..6aace57e4e2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -657,7 +657,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ cpu->isar.id_aa64isar1 = t; t = cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7a066fb7cb2..579180af0a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3283,6 +3283,88 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, } } +/* + * LDAPR/STLR (unscaled immediate) + * + * 31 30 24 22 21 12 10 5 0 + * +------+-------------+-----+---+--------+-----+----+-----+ + * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | + * +------+-------------+-----+---+--------+-----+----+-----+ + * + * Rt: source or destination register + * Rn: base register + * imm9: unscaled immediate offset + * opc: 00: STLUR*, 01/10/11: various LDAPUR* + * size: size of load/store + */ +static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) +{ + int rt = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + int offset = sextract32(insn, 12, 9); + int opc = extract32(insn, 22, 2); + int size = extract32(insn, 30, 2); + TCGv_i64 clean_addr, dirty_addr; + bool is_store = false; + bool is_signed = false; + bool extend = false; + bool iss_sf; + + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { + unallocated_encoding(s); + return; + } + + switch (opc) { + case 0: /* STLURB */ + is_store = true; + break; + case 1: /* LDAPUR* */ + break; + case 2: /* LDAPURS* 64-bit variant */ + if (size == 3) { + unallocated_encoding(s); + return; + } + is_signed = true; + break; + case 3: /* LDAPURS* 32-bit variant */ + if (size > 1) { + unallocated_encoding(s); + return; + } + is_signed = true; + extend = true; /* zero-extend 32->64 after signed load */ + break; + default: + g_assert_not_reached(); + } + + iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); + + if (rn == 31) { + gen_check_sp_alignment(s); + } + + dirty_addr = read_cpu_reg_sp(s, rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + clean_addr = clean_data_tbi(s, dirty_addr); + + if (is_store) { + /* Store-Release semantics */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); + } else { + /* + * Load-AcquirePC semantics; we implement as the slightly more + * restrictive Load-Acquire. + */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, + true, rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3634,6 +3716,14 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* LDAPR/STLR (unscaled immediate) */ + if (extract32(insn, 10, 2) != 0 || + extract32(insn, 21, 1) != 0) { + unallocated_encoding(s); + break; + } + disas_ldst_ldapr_stlr(s, insn); + break; default: unallocated_encoding(s); break; -- 2.20.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] target/arm: Implement v8.4-RCPC 2020-02-24 17:28 ` [PATCH 3/3] target/arm: Implement v8.4-RCPC Peter Maydell @ 2020-02-24 18:39 ` Richard Henderson 2020-02-24 18:42 ` Peter Maydell 0 siblings, 1 reply; 9+ messages in thread From: Richard Henderson @ 2020-02-24 18:39 UTC (permalink / raw) To: Peter Maydell, qemu-arm, qemu-devel On 2/24/20 9:28 AM, Peter Maydell wrote: > The v8.4-RCPC extension implements some new instructions: > * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW > * STLUR, STLURB, STLURH > > These are all in a new subgroup of encodings that sits below the > top-level "Loads and Stores" group in the Arm ARM. > > The STLUR* instructions have standard store-release semantics; the > LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose > to implement them as the slightly stronger Load-Acquire. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/cpu.h | 5 +++ > linux-user/elfload.c | 1 + > target/arm/cpu64.c | 2 +- > target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++ > 4 files changed, 97 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] target/arm: Implement v8.4-RCPC 2020-02-24 18:39 ` Richard Henderson @ 2020-02-24 18:42 ` Peter Maydell 0 siblings, 0 replies; 9+ messages in thread From: Peter Maydell @ 2020-02-24 18:42 UTC (permalink / raw) To: Richard Henderson; +Cc: qemu-arm, QEMU Developers On Mon, 24 Feb 2020 at 18:39, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 2/24/20 9:28 AM, Peter Maydell wrote: > > The v8.4-RCPC extension implements some new instructions: > > * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW > > * STLUR, STLURB, STLURH > > > > These are all in a new subgroup of encodings that sits below the > > top-level "Loads and Stores" group in the Arm ARM. > > > > The STLUR* instructions have standard store-release semantics; the > > LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose > > to implement them as the slightly stronger Load-Acquire. > > > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > > --- > > target/arm/cpu.h | 5 +++ > > linux-user/elfload.c | 1 + > > target/arm/cpu64.c | 2 +- > > target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++ > > 4 files changed, 97 insertions(+), 1 deletion(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> I guess your memtag series will need to account for the extra loads/stores added by this series, incidentally. thanks -- PMM ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-02-24 18:43 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-24 17:28 [PATCH 0/3] target/arm: Implement v8.3-RCPC and v8.4-RCPC Peter Maydell 2020-02-24 17:28 ` [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell 2020-02-24 17:48 ` Philippe Mathieu-Daudé 2020-02-24 18:23 ` Richard Henderson 2020-02-24 17:28 ` [PATCH 2/3] target/arm: Implement v8.3-RCPC Peter Maydell 2020-02-24 18:31 ` Richard Henderson 2020-02-24 17:28 ` [PATCH 3/3] target/arm: Implement v8.4-RCPC Peter Maydell 2020-02-24 18:39 ` Richard Henderson 2020-02-24 18:42 ` Peter Maydell
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