* [igt-dev] [PATCH i-g-t v5 0/1] Support to assemble CB kernel for gen7
@ 2020-02-24 17:42 Akeem G Abodunrin
2020-02-24 17:42 ` [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel Akeem G Abodunrin
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Akeem G Abodunrin @ 2020-02-24 17:42 UTC (permalink / raw)
To: akeem.g.abodunrin, jon.bloomfield, sudeep.dutt, daniel.vetter,
joonas.lahtinen, jani.nikula, chris.p.wilson,
prathap.kumar.valsan, mika.kuoppala, francesco.balestrieri,
ville.syrjala, petri.latvala, igt-dev
Summary
-------
This is patch adds support to assemble CB kernel for gen7 and gen7.5
devices. It is needed for "Security mitigation for Intel Gen7/7.5 HWs"
Intel ID: PSIRT-TA-201910-001/CVEID: CVE-2019-14615.
Additional Note
---------------
The changes in the IGT GPU tool require latest Mesa tool to work
correctly. Generated CB kernel are imported to i915 driver, without need
for additional modifications. Users can use assembly sources provided
with this patch, and Mesa/igt to assemble CB kernel for verifications.
Akeem G Abodunrin (1):
tools/generate_cb_buffer: Add script to assemble CB kernel
scripts/asm_eu_kernel.sh | 158 ++++++++++++++++++++++++
tools/assembly_source/hsw_clear_buf.asm | 141 +++++++++++++++++++++
tools/assembly_source/ivb_clear_buf.asm | 139 +++++++++++++++++++++
3 files changed, 438 insertions(+)
create mode 100755 scripts/asm_eu_kernel.sh
create mode 100644 tools/assembly_source/hsw_clear_buf.asm
create mode 100644 tools/assembly_source/ivb_clear_buf.asm
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel
2020-02-24 17:42 [igt-dev] [PATCH i-g-t v5 0/1] Support to assemble CB kernel for gen7 Akeem G Abodunrin
@ 2020-02-24 17:42 ` Akeem G Abodunrin
2020-02-26 8:58 ` Petri Latvala
2020-02-25 2:06 ` [igt-dev] ✓ Fi.CI.BAT: success for Support to assemble CB kernel for gen7 Patchwork
2020-02-26 10:53 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Akeem G Abodunrin @ 2020-02-24 17:42 UTC (permalink / raw)
To: akeem.g.abodunrin, jon.bloomfield, sudeep.dutt, daniel.vetter,
joonas.lahtinen, jani.nikula, chris.p.wilson,
prathap.kumar.valsan, mika.kuoppala, francesco.balestrieri,
ville.syrjala, petri.latvala, igt-dev
This patch adds script and applicable assembly sources, so that we can use
igt to assemble Clear Batch Buffer kernel for gen7 and gen7.5 devices -
Resultant header files would be imported to i915, and used as they are...
With this patch, user need to have mesa configured on their platform,
before igt could be used to achieve the purpose of assembling the kernel
from source.
This is needed for "Security mitigation for Intel Gen7/7.5 HWs"
Intel ID: PSIRT-TA-201910-001/CVEID: CVE-2019-14615
v2: Addressed formatting, -g option and other minor issues (Petri)
v3: Update script due to suggested changes in i915, and Mesa tool
v4: Update help comment with Mesa build option with meson (Petri)
v5: Modify how user specify i965_asm - script now takes binary, instead
of Mesa tool source directory (Ville).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Bloomfield Jon <jon.bloomfield@intel.com>
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
---
scripts/asm_eu_kernel.sh | 158 ++++++++++++++++++++++++
tools/assembly_source/hsw_clear_buf.asm | 141 +++++++++++++++++++++
tools/assembly_source/ivb_clear_buf.asm | 139 +++++++++++++++++++++
3 files changed, 438 insertions(+)
create mode 100755 scripts/asm_eu_kernel.sh
create mode 100644 tools/assembly_source/hsw_clear_buf.asm
create mode 100644 tools/assembly_source/ivb_clear_buf.asm
diff --git a/scripts/asm_eu_kernel.sh b/scripts/asm_eu_kernel.sh
new file mode 100755
index 00000000..ddf44b38
--- /dev/null
+++ b/scripts/asm_eu_kernel.sh
@@ -0,0 +1,158 @@
+#!/bin/bash
+#
+# SPDX-License-Identifier: MIT
+#
+# Copyright © 2020 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+# IN THE SOFTWARE.
+
+export ASSEMBLY_SOURCE=./tools/assembly_source
+
+function get_help {
+ echo "Usage: asm_eu_kernel.sh [options]"
+ echo "Note: hsw_clear_kernel.c/ivb_clear_kernel.c automatically generated by this script should never be modified - it would be imported to i915, to use as it is..."
+ echo " "
+ echo "Please make sure your Mesa tool is compiled with "-Dtools=intel" and "-Ddri-drivers=i965", and run this script from IGT source root directory"
+ echo " "
+ echo "Options are:"
+ echo " -h display this help message, and exit"
+ echo " -g=platform generation of device: use "hsw" for gen7.5, and "ivb" for gen7 devices"
+ echo " -o=name_of_file output file to store Mesa assembled c-literal for the device - If none specified, default file will be used - ivb/hsw-cb_assembled"
+ echo " -m=mesa Path to Mesa i965_asm binary"
+ echo " "
+ echo " Usage example: \"scripts/asm_eu_kernel.sh -g hsw -o hsw_clear_buffer.h -m /path/to/Mesa/i965_asm/binary\""
+}
+
+function include_array # $1=array_name
+{
+ echo "static const u32 $(basename $1)_clear_kernel[] = {"
+}
+function prefix_header # $1=filename $2=comment
+{
+ array_name=$(include_array $1)
+
+ cat <<EOF
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Generated by: IGT Gpu Tools on $(date)
+ */
+
+$array_name
+EOF
+}
+
+function postfix_footer # filename
+{
+ cat <<EOF
+};
+EOF
+}
+
+function check_output_file #check output file
+{
+ if [ "x$output_file" != "x" ]; then
+ if [ -f "$output_file" ]; then
+ echo -e "Warning: The \"$output_file\" file already exist - choose another file\n"
+ get_help
+ exit 1
+ fi
+ else
+ # It is okay to overwrite default file created
+ echo -e "Output file not specified - using default file \"$gen_device-cb_assembled\"\n"
+ output_file="$gen_device-cb_assembled"
+ fi
+}
+function asm_cb_kernel # as-root <args>
+{
+ check_output_file
+
+ # Using i965_asm tool to assemble hex file from assembly source
+ $mesa_i965_asm -g $gen_device -t c_literal $input_asm_source -o $output_file
+
+ if [ ! -f ${output_file} ]; then
+ echo -e "Failed to assemble CB Kernel with Mesa tool\n"
+ get_help
+ exit 1
+ fi
+
+ # Generate header file
+ if [ "$gen_device" == "hsw" ]; then
+ echo "Generating gen7.5 CB Kernel assembled file \"hsw_clear_kernel.c\" for i915 driver..."
+
+ i915_filename=hsw_clear_kernel.c
+ prefix_header $gen_device > $i915_filename
+ cat $output_file >> $i915_filename
+ postfix_footer $i915_filename >> $i915_filename
+
+ elif [ "$gen_device" == "ivb" ]; then
+ echo "Generating gen7 CB Kernel assembled file \"ivb_clear_kernel.c\" for i915 driver..."
+
+ i915_filename=ivb_clear_kernel.c
+ prefix_header $gen_device > $i915_filename
+ cat $output_file >> $i915_filename
+ postfix_footer $i915_filename >> $i915_filename
+ fi
+}
+
+while getopts "hg:o:m:" opt; do
+ case $opt in
+ h) get_help; exit 0;;
+ g) gen_device="$OPTARG" ;;
+ o) output_file="$OPTARG" ;;
+ m) mesa_i965_asm="$OPTARG" ;;
+ \?)
+ echo -e "Unknown option: -$OPTARG\n"
+ get_help
+ exit 1
+ ;;
+ esac
+done
+shift $(($OPTIND-1))
+
+if [ "x$1" != "x" ]; then
+ echo -e "Unknown option: $1\n"
+ get_help
+ exit 1
+fi
+
+if [ "x$mesa_i965_asm" == "x" ]; then
+ echo -e "i965_asm binary not found\n"
+ get_help
+ exit 1
+fi
+
+if [ "x$gen_device" != "x" ]; then
+ if [ "$gen_device" == "hsw" ]; then
+ input_asm_source="${ASSEMBLY_SOURCE}/hsw_clear_buf.asm"
+ elif [ "$gen_device" == "ivb" ]; then
+ input_asm_source="${ASSEMBLY_SOURCE}/ivb_clear_buf.asm"
+ else
+ echo -e "Unknown platform specified\n"
+ get_help
+ exit 1
+ fi
+ asm_cb_kernel
+else
+ echo -e "Platform generation not specified\n"
+ get_help
+ exit 1
+fi
diff --git a/tools/assembly_source/hsw_clear_buf.asm b/tools/assembly_source/hsw_clear_buf.asm
new file mode 100644
index 00000000..bc29baf2
--- /dev/null
+++ b/tools/assembly_source/hsw_clear_buf.asm
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/**
+ * Kernel name: hsw_clear_buf.asm
+ *
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout:
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
diff --git a/tools/assembly_source/ivb_clear_buf.asm b/tools/assembly_source/ivb_clear_buf.asm
new file mode 100644
index 00000000..b21bc948
--- /dev/null
+++ b/tools/assembly_source/ivb_clear_buf.asm
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/**
+ * Kernel name: ivb_clear_buf.asm
+ *
+ * Kernel for PAVP buffer clear.
+ *
+ * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
+ * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
+ * 512 bytes of Render Cache.
+ */
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/**
+ * Curbe Format
+ *
+ * DW 1.0 - Block Offset to write Render Cache
+ * DW 1.1 [15:0] - Clear Word
+ * DW 1.2 - Delay iterations
+ * DW 1.3 - Enable Instrumentation (only for debug)
+ * DW 1.4 - Rsvd (intended for context ID)
+ * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
+ * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
+ * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
+ *
+ * Binding Table
+ *
+ * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
+ * BTI 1: Wait/Instrumentation Buffer
+ * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
+ * Expected to be initialized to 0 by driver/another kernel
+ * Layout :
+ * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
+ * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
+ */
+add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
+cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
+(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
+
+/**
+ * State Register has info on where this thread is running
+ * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
+ */
+mov(8) g3<1>UD 0x00000000UD { align1 1Q };
+shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
+and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
+shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
+and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
+mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
+add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
+shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
+and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
+mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
+add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
+
+mov(8) g5<1>UD 0x00000000UD { align1 1Q };
+and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
+mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
+
+mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
+mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
+mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
+and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
+
+/* Media block read to fetch current value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
+ render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
+add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
+
+/* Media block write for updated value at specified location in instrumentation buffer */
+sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
+/* Delay thread for specified parameter */
+add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
+(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
+
+/* Store designated "clear GRF" value */
+mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
+
+/* Initialize looping parameters */
+mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
+mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
+
+/* Write 32x16 all "0" block */
+mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
+mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
+mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
+mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
+and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
+mov(16) g3<1>UD 0x00000000UD { align1 1H };
+mov(16) g4<1>UD 0x00000000UD { align1 1H };
+mov(16) g5<1>UD 0x00000000UD { align1 1H };
+mov(16) g6<1>UD 0x00000000UD { align1 1H };
+mov(16) g7<1>UD 0x00000000UD { align1 1H };
+mov(16) g8<1>UD 0x00000000UD { align1 1H };
+mov(16) g9<1>UD 0x00000000UD { align1 1H };
+mov(16) g10<1>UD 0x00000000UD { align1 1H };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
+sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
+ render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
+
+/* Now, clear all GRF registers */
+add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
+mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
+add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
+(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
+
+/* Terminante the thread */
+sendc(8) null<1>UD g127<8,8,1>F 0x82000010
+ thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Support to assemble CB kernel for gen7
2020-02-24 17:42 [igt-dev] [PATCH i-g-t v5 0/1] Support to assemble CB kernel for gen7 Akeem G Abodunrin
2020-02-24 17:42 ` [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel Akeem G Abodunrin
@ 2020-02-25 2:06 ` Patchwork
2020-02-26 10:53 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-25 2:06 UTC (permalink / raw)
To: Akeem G Abodunrin; +Cc: igt-dev
== Series Details ==
Series: Support to assemble CB kernel for gen7
URL : https://patchwork.freedesktop.org/series/73880/
State : success
== Summary ==
CI Bug Log - changes from IGT_5464 -> IGTPW_4220
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/index.html
Known issues
------------
Here are the changes found in IGTPW_4220 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [PASS][1] -> [FAIL][2] ([CI#94])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#106070] / [i915#424])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@prime_vgem@basic-busy-default:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/fi-tgl-y/igt@prime_vgem@basic-busy-default.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/fi-tgl-y/igt@prime_vgem@basic-busy-default.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-byt-n2820: [INCOMPLETE][9] ([i915#45]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/fi-byt-n2820/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/fi-byt-n2820/igt@i915_module_load@reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-cml-s: [DMESG-FAIL][11] ([i915#877]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
* igt@vgem_basic@create:
- fi-tgl-y: [DMESG-WARN][13] ([CI#94] / [i915#402]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/fi-tgl-y/igt@vgem_basic@create.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/fi-tgl-y/igt@vgem_basic@create.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
Participating hosts (51 -> 43)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-glk-dsi fi-bsw-cyan fi-gdg-551 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5464 -> IGTPW_4220
CI-20190529: 20190529
CI_DRM_8000: e231691d89abd1b3fff01e75f142e435b44b522f @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4220: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/index.html
IGT_5464: 8cf2f8684992052ab89de1cf328c418224c0c2a7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel
2020-02-24 17:42 ` [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel Akeem G Abodunrin
@ 2020-02-26 8:58 ` Petri Latvala
2020-02-26 23:55 ` Abodunrin, Akeem G
0 siblings, 1 reply; 6+ messages in thread
From: Petri Latvala @ 2020-02-26 8:58 UTC (permalink / raw)
To: Akeem G Abodunrin
Cc: jani.nikula, chris.p.wilson, igt-dev, jon.bloomfield,
daniel.vetter, mika.kuoppala
On Mon, Feb 24, 2020 at 09:42:17AM -0800, Akeem G Abodunrin wrote:
> This patch adds script and applicable assembly sources, so that we can use
> igt to assemble Clear Batch Buffer kernel for gen7 and gen7.5 devices -
> Resultant header files would be imported to i915, and used as they are...
>
> With this patch, user need to have mesa configured on their platform,
> before igt could be used to achieve the purpose of assembling the kernel
> from source.
>
> This is needed for "Security mitigation for Intel Gen7/7.5 HWs"
> Intel ID: PSIRT-TA-201910-001/CVEID: CVE-2019-14615
>
> v2: Addressed formatting, -g option and other minor issues (Petri)
> v3: Update script due to suggested changes in i915, and Mesa tool
> v4: Update help comment with Mesa build option with meson (Petri)
> v5: Modify how user specify i965_asm - script now takes binary, instead
> of Mesa tool source directory (Ville).
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> ---
> scripts/asm_eu_kernel.sh | 158 ++++++++++++++++++++++++
> tools/assembly_source/hsw_clear_buf.asm | 141 +++++++++++++++++++++
> tools/assembly_source/ivb_clear_buf.asm | 139 +++++++++++++++++++++
> 3 files changed, 438 insertions(+)
> create mode 100755 scripts/asm_eu_kernel.sh
> create mode 100644 tools/assembly_source/hsw_clear_buf.asm
> create mode 100644 tools/assembly_source/ivb_clear_buf.asm
>
> diff --git a/scripts/asm_eu_kernel.sh b/scripts/asm_eu_kernel.sh
> new file mode 100755
> index 00000000..ddf44b38
> --- /dev/null
> +++ b/scripts/asm_eu_kernel.sh
> @@ -0,0 +1,158 @@
> +#!/bin/bash
> +#
> +# SPDX-License-Identifier: MIT
> +#
> +# Copyright © 2020 Intel Corporation
> +#
> +# Permission is hereby granted, free of charge, to any person obtaining a
> +# copy of this software and associated documentation files (the "Software"),
> +# to deal in the Software without restriction, including without limitation
> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> +# and/or sell copies of the Software, and to permit persons to whom the
> +# Software is furnished to do so, subject to the following conditions:
> +#
> +# The above copyright notice and this permission notice (including the next
> +# paragraph) shall be included in all copies or substantial portions of the
> +# Software.
> +#
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> +# IN THE SOFTWARE.
> +
> +export ASSEMBLY_SOURCE=./tools/assembly_source
> +
> +function get_help {
> + echo "Usage: asm_eu_kernel.sh [options]"
> + echo "Note: hsw_clear_kernel.c/ivb_clear_kernel.c automatically generated by this script should never be modified - it would be imported to i915, to use as it is..."
> + echo " "
> + echo "Please make sure your Mesa tool is compiled with "-Dtools=intel" and "-Ddri-drivers=i965", and run this script from IGT source root directory"
> + echo " "
> + echo "Options are:"
> + echo " -h display this help message, and exit"
> + echo " -g=platform generation of device: use "hsw" for gen7.5, and "ivb" for gen7 devices"
> + echo " -o=name_of_file output file to store Mesa assembled c-literal for the device - If none specified, default file will be used - ivb/hsw-cb_assembled"
> + echo " -m=mesa Path to Mesa i965_asm binary"
What Ville said was that the name of the build directory can be
something other than 'build'. Within that build directory the path to
i965_asm binary is always src/intel/tools/i965_asm. But that's just
bikeshedding at this point.
I was able to test the script now, thanks Akeem for the Mesa side
changes link.
There's only the cosmetic things left to fix on IGT's side and then
this can be merged as soon as the Mesa side is merged. Namely, names:
The patch subject talks about tools/generate_cb_buffer but no such
file is created with it. The name asm_eu_kernel.sh sounds a bit too
generic when this is for very particular shaders to assemble. Speaking
of shaders, we already have a directory for shader sources where they
should go.
Suggestions for naming:
The assembly sources could go to lib/i915/shaders/clear_buffer/hsw.asm
and lib/i915/shaders/clear_buffer/ivb.asm
The script itself could be called scripts/generate_cb_shader.sh or
something. Not sure what the correct terminology is for these shaders.
Opinions, people who are better at naming than me?
--
Petri Latvala
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Support to assemble CB kernel for gen7
2020-02-24 17:42 [igt-dev] [PATCH i-g-t v5 0/1] Support to assemble CB kernel for gen7 Akeem G Abodunrin
2020-02-24 17:42 ` [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel Akeem G Abodunrin
2020-02-25 2:06 ` [igt-dev] ✓ Fi.CI.BAT: success for Support to assemble CB kernel for gen7 Patchwork
@ 2020-02-26 10:53 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-26 10:53 UTC (permalink / raw)
To: Akeem G Abodunrin; +Cc: igt-dev
== Series Details ==
Series: Support to assemble CB kernel for gen7
URL : https://patchwork.freedesktop.org/series/73880/
State : success
== Summary ==
CI Bug Log - changes from IGT_5464_full -> IGTPW_4220_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/index.html
Known issues
------------
Here are the changes found in IGTPW_4220_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb2/igt@gem_exec_balancer@smoke.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb8/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#677]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb3/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@pi-shared-iova-blt:
- shard-kbl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103665] / [i915#1193])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-kbl6/igt@gem_exec_schedule@pi-shared-iova-blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-kbl6/igt@gem_exec_schedule@pi-shared-iova-blt.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +14 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#413])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb8/igt@i915_pm_rps@waitboost.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb2/igt@i915_pm_rps@waitboost.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#899])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][19] -> [FAIL][20] ([i915#31])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-hsw4/igt@kms_setmode@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-hsw8/igt@kms_setmode@basic.html
- shard-kbl: [PASS][21] -> [FAIL][22] ([i915#31])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-kbl7/igt@kms_setmode@basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-kbl6/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#112080]) +13 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb2/igt@perf_pmu@busy-no-semaphores-vcs1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb5/igt@perf_pmu@busy-no-semaphores-vcs1.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][27] ([fdo#112080]) -> [PASS][28] +14 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb3/igt@gem_busy@busy-vcs1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb2/igt@gem_busy@busy-vcs1.html
* {igt@gem_ctx_persistence@engines-mixed-process@vcs0}:
- shard-apl: [FAIL][29] ([i915#679]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-apl1/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-apl3/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
* {igt@gem_ctx_persistence@engines-mixed-process@vecs0}:
- shard-apl: [INCOMPLETE][31] ([fdo#103927] / [i915#1197] / [i915#1239]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-apl1/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-apl3/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
* {igt@gem_exec_schedule@implicit-read-write-bsd1}:
- shard-iclb: [SKIP][33] ([fdo#109276] / [i915#677]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb8/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb2/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][35] ([fdo#112146]) -> [PASS][36] +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb2/igt@gem_exec_schedule@in-order-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb8/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [SKIP][37] ([fdo#109276]) -> [PASS][38] +17 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][41] ([i915#716]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-glk9/igt@gen9_exec_parse@allowed-all.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_rpm@pm-tiling:
- shard-hsw: [SKIP][43] ([fdo#109271]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-hsw4/igt@i915_pm_rpm@pm-tiling.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-hsw6/igt@i915_pm_rpm@pm-tiling.html
- shard-glk: [SKIP][45] ([fdo#109271]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-glk3/igt@i915_pm_rpm@pm-tiling.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-glk8/igt@i915_pm_rpm@pm-tiling.html
- shard-iclb: [SKIP][47] -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb7/igt@i915_pm_rpm@pm-tiling.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb3/igt@i915_pm_rpm@pm-tiling.html
* igt@kms_cursor_crc@pipe-a-cursor-size-change:
- shard-apl: [FAIL][49] ([i915#54]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-size-change.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-size-change.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@sw_sync@sync_multi_producer_single_consumer:
- shard-hsw: [TIMEOUT][55] ([fdo#112271]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-hsw5/igt@sw_sync@sync_multi_producer_single_consumer.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-hsw8/igt@sw_sync@sync_multi_producer_single_consumer.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][57] ([fdo#112080]) -> [FAIL][58] ([IGT#28])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][59] ([fdo#111870] / [i915#478]) -> [DMESG-WARN][60] ([fdo#110789] / [fdo#111870] / [i915#478])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-snb2/igt@gem_userptr_blits@sync-unmap.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
- shard-hsw: [DMESG-WARN][61] ([fdo#111870]) -> [DMESG-WARN][62] ([fdo#110789] / [fdo#111870])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-hsw7/igt@gem_userptr_blits@sync-unmap.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-hsw6/igt@gem_userptr_blits@sync-unmap.html
* igt@kms_content_protection@lic:
- shard-kbl: [TIMEOUT][63] ([fdo#112271] / [i915#1319]) -> [TIMEOUT][64] ([fdo#112271] / [i915#1319] / [i915#727])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5464/shard-kbl4/igt@kms_content_protection@lic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/shard-kbl4/igt@kms_content_protection@lic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1193]: https://gitlab.freedesktop.org/drm/intel/issues/1193
[i915#1197]: https://gitlab.freedesktop.org/drm/intel/issues/1197
[i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#727]: https://gitlab.freedesktop.org/drm/intel/issues/727
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5464 -> IGTPW_4220
CI-20190529: 20190529
CI_DRM_8000: e231691d89abd1b3fff01e75f142e435b44b522f @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4220: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/index.html
IGT_5464: 8cf2f8684992052ab89de1cf328c418224c0c2a7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4220/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel
2020-02-26 8:58 ` Petri Latvala
@ 2020-02-26 23:55 ` Abodunrin, Akeem G
0 siblings, 0 replies; 6+ messages in thread
From: Abodunrin, Akeem G @ 2020-02-26 23:55 UTC (permalink / raw)
To: Latvala, Petri
Cc: Nikula, Jani, Wilson, Chris P, igt-dev, Bloomfield, Jon, Vetter,
Daniel, Kuoppala, Mika
> -----Original Message-----
> From: Latvala, Petri <petri.latvala@intel.com>
> Sent: Wednesday, February 26, 2020 12:59 AM
> To: Abodunrin, Akeem G <akeem.g.abodunrin@intel.com>
> Cc: Bloomfield, Jon <jon.bloomfield@intel.com>; Dutt, Sudeep
> <sudeep.dutt@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>;
> joonas.lahtinen@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>; Wilson,
> Chris P <chris.p.wilson@intel.com>; Kumar Valsan, Prathap
> <prathap.kumar.valsan@intel.com>; Kuoppala, Mika
> <mika.kuoppala@intel.com>; Balestrieri, Francesco
> <francesco.balestrieri@intel.com>; ville.syrjala@linux.intel.com; igt-
> dev@lists.freedesktop.org
> Subject: Re: [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to
> assemble CB kernel
>
> On Mon, Feb 24, 2020 at 09:42:17AM -0800, Akeem G Abodunrin wrote:
> > This patch adds script and applicable assembly sources, so that we can
> > use igt to assemble Clear Batch Buffer kernel for gen7 and gen7.5
> > devices - Resultant header files would be imported to i915, and used as they
> are...
> >
> > With this patch, user need to have mesa configured on their platform,
> > before igt could be used to achieve the purpose of assembling the
> > kernel from source.
> >
> > This is needed for "Security mitigation for Intel Gen7/7.5 HWs"
> > Intel ID: PSIRT-TA-201910-001/CVEID: CVE-2019-14615
> >
> > v2: Addressed formatting, -g option and other minor issues (Petri)
> > v3: Update script due to suggested changes in i915, and Mesa tool
> > v4: Update help comment with Mesa build option with meson (Petri)
> > v5: Modify how user specify i965_asm - script now takes binary,
> > instead of Mesa tool source directory (Ville).
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > ---
> > scripts/asm_eu_kernel.sh | 158 ++++++++++++++++++++++++
> > tools/assembly_source/hsw_clear_buf.asm | 141 +++++++++++++++++++++
> > tools/assembly_source/ivb_clear_buf.asm | 139 +++++++++++++++++++++
> > 3 files changed, 438 insertions(+)
> > create mode 100755 scripts/asm_eu_kernel.sh create mode 100644
> > tools/assembly_source/hsw_clear_buf.asm
> > create mode 100644 tools/assembly_source/ivb_clear_buf.asm
> >
> > diff --git a/scripts/asm_eu_kernel.sh b/scripts/asm_eu_kernel.sh new
> > file mode 100755 index 00000000..ddf44b38
> > --- /dev/null
> > +++ b/scripts/asm_eu_kernel.sh
> > @@ -0,0 +1,158 @@
> > +#!/bin/bash
> > +#
> > +# SPDX-License-Identifier: MIT
> > +#
> > +# Copyright © 2020 Intel Corporation
> > +#
> > +# Permission is hereby granted, free of charge, to any person
> > +obtaining a # copy of this software and associated documentation
> > +files (the "Software"), # to deal in the Software without
> > +restriction, including without limitation # the rights to use, copy,
> > +modify, merge, publish, distribute, sublicense, # and/or sell copies
> > +of the Software, and to permit persons to whom the # Software is furnished
> to do so, subject to the following conditions:
> > +#
> > +# The above copyright notice and this permission notice (including
> > +the next # paragraph) shall be included in all copies or substantial
> > +portions of the # Software.
> > +#
> > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > +EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> OF
> > +MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND
> > +NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT
> > +HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY,
> > +WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING #
> FROM,
> > +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS # IN THE SOFTWARE.
> > +
> > +export ASSEMBLY_SOURCE=./tools/assembly_source
> > +
> > +function get_help {
> > + echo "Usage: asm_eu_kernel.sh [options]"
> > + echo "Note: hsw_clear_kernel.c/ivb_clear_kernel.c automatically
> generated by this script should never be modified - it would be imported to i915,
> to use as it is..."
> > + echo " "
> > + echo "Please make sure your Mesa tool is compiled with "-Dtools=intel"
> and "-Ddri-drivers=i965", and run this script from IGT source root directory"
> > + echo " "
> > + echo "Options are:"
> > + echo " -h display this help message, and exit"
> > + echo " -g=platform generation of device: use "hsw" for gen7.5,
> and "ivb" for gen7 devices"
> > + echo " -o=name_of_file output file to store Mesa assembled c-
> literal for the device - If none specified, default file will be used - ivb/hsw-
> cb_assembled"
> > + echo " -m=mesa Path to Mesa i965_asm binary"
>
> What Ville said was that the name of the build directory can be something other
> than 'build'. Within that build directory the path to i965_asm binary is always
> src/intel/tools/i965_asm. But that's just bikeshedding at this point.
>
> I was able to test the script now, thanks Akeem for the Mesa side changes link.
>
> There's only the cosmetic things left to fix on IGT's side and then this can be
> merged as soon as the Mesa side is merged. Namely, names:
>
> The patch subject talks about tools/generate_cb_buffer but no such file is
> created with it. The name asm_eu_kernel.sh sounds a bit too generic when this
> is for very particular shaders to assemble. Speaking of shaders, we already have
> a directory for shader sources where they should go.
>
> Suggestions for naming:
>
> The assembly sources could go to lib/i915/shaders/clear_buffer/hsw.asm
> and lib/i915/shaders/clear_buffer/ivb.asm
>
> The script itself could be called scripts/generate_cb_shader.sh or something.
> Not sure what the correct terminology is for these shaders.
>
> Opinions, people who are better at naming than me?
All changes in Mesa have been merged... and I addressed naming issue mentioned here, and updated script to reflect Mesa new c-literal output format - automated files (hsw_clear_kernel.c and ivb_clear_kernel.c) generated for i915 still the same, no difference, except of course date...
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-02-26 23:55 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-24 17:42 [igt-dev] [PATCH i-g-t v5 0/1] Support to assemble CB kernel for gen7 Akeem G Abodunrin
2020-02-24 17:42 ` [igt-dev] [PATCH i-g-t v5 1/1] tools/generate_cb_buffer: Add script to assemble CB kernel Akeem G Abodunrin
2020-02-26 8:58 ` Petri Latvala
2020-02-26 23:55 ` Abodunrin, Akeem G
2020-02-25 2:06 ` [igt-dev] ✓ Fi.CI.BAT: success for Support to assemble CB kernel for gen7 Patchwork
2020-02-26 10:53 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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