From: kbuild test robot <lkp@intel.com> To: Dhananjay Kangude <dkangude@cadence.com> Cc: kbuild-all@lists.01.org, clang-built-linux@googlegroups.com, linux-edac@vger.kernel.org Subject: Re: [PATCH 1/2] EDAC/Cadence:Add EDAC driver for cadence memory controller Date: Wed, 26 Feb 2020 11:26:45 +0800 [thread overview] Message-ID: <202002261105.7GbpkGuO%lkp@intel.com> (raw) In-Reply-To: <20200225093856.7328-2-dkangude@cadence.com> [-- Attachment #1: Type: text/plain, Size: 3824 bytes --] Hi Dhananjay, Thank you for the patch! Yet something to improve: [auto build test ERROR on ras/edac-for-next] [also build test ERROR on next-20200225] [cannot apply to v5.6-rc3] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Dhananjay-Kangude/Add-EDAC-support-for-Cadence-ddr-controller/20200225-185633 base: https://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next config: arm64-allyesconfig (attached as .config) compiler: clang version 11.0.0 (git://gitmirror/llvm_project 7f9f027c62623bff79730cd30d1a8a534e2ddb06) reproduce: # FIXME the reproduce steps for clang is not ready yet If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@intel.com> All error/warnings (new ones prefixed by >>): >> drivers/edac/cadence_edac.c:179:9: error: implicit declaration of function 'EDAC_DIMM_PTR' [-Werror,-Wimplicit-function-declaration] dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); ^ >> drivers/edac/cadence_edac.c:179:7: warning: incompatible integer to pointer conversion assigning to 'struct dimm_info *' from 'int' [-Wint-conversion] dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/edac/cadence_edac.c:476:17: warning: unused variable 'root' [-Wunused-variable] struct dentry *root; ^ 2 warnings and 1 error generated. vim +/EDAC_DIMM_PTR +179 drivers/edac/cadence_edac.c 159 160 /** 161 * init_mem_layout - Set address Map as per the mc design. 162 * @mci: memory controller information. 163 * 164 * Set Address Map as per mc instance . 165 * 166 * Return: none. 167 */ 168 static void init_mem_layout(struct mem_ctl_info *mci) 169 { 170 struct cdns_edac_priv_data *priv = mci->pvt_info; 171 struct csrow_info *csi; 172 struct dimm_info *dimm; 173 struct sysinfo inf; 174 enum mem_type mtype; 175 u32 val, width; 176 u32 size, row; 177 u8 j; 178 > 179 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); 180 181 si_meminfo(&inf); 182 for (row = 0; row < mci->nr_csrows; row++) { 183 csi = mci->csrows[row]; 184 size = inf.totalram * inf.mem_unit; 185 186 for (j = 0; j < csi->nr_channels; j++) { 187 dimm = csi->channels[j]->dimm; 188 dimm->edac_mode = EDAC_FLAG_SECDED; 189 /* Get memory type by reading hw registers*/ 190 val = readl(priv->reg + DDR_CTL_MEM_TYPE_REG); 191 mtype = val & ECC_CTL_MTYPE_MASK; 192 193 if (mtype == MEM_TYPE_DDR4) 194 dimm->mtype = MEM_DDR4; 195 else 196 dimm->mtype = MEM_EMPTY; 197 198 /*Get EDAC devtype width for the current mc*/ 199 width = (readl(priv->reg + DDR_CTL_MEM_WIDTH_REG) & 200 CTL_MEM_MAX_WIDTH_MASK); 201 switch (width) { 202 case WDTH_16: 203 dimm->dtype = DEV_X2; 204 break; 205 case WDTH_32: 206 dimm->dtype = DEV_X4; 207 break; 208 case WDTH_64: 209 dimm->dtype = DEV_X8; 210 break; 211 default: 212 dimm->dtype = DEV_UNKNOWN; 213 } 214 215 dimm->nr_pages = (size >> PAGE_SHIFT) / 216 csi->nr_channels; 217 dimm->grain = CDNS_EDAC_ERR_GRAIN; 218 } 219 } 220 } 221 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 70475 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: kbuild test robot <lkp@intel.com> To: kbuild-all@lists.01.org Subject: Re: [PATCH 1/2] EDAC/Cadence:Add EDAC driver for cadence memory controller Date: Wed, 26 Feb 2020 11:26:45 +0800 [thread overview] Message-ID: <202002261105.7GbpkGuO%lkp@intel.com> (raw) In-Reply-To: <20200225093856.7328-2-dkangude@cadence.com> [-- Attachment #1: Type: text/plain, Size: 3929 bytes --] Hi Dhananjay, Thank you for the patch! Yet something to improve: [auto build test ERROR on ras/edac-for-next] [also build test ERROR on next-20200225] [cannot apply to v5.6-rc3] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Dhananjay-Kangude/Add-EDAC-support-for-Cadence-ddr-controller/20200225-185633 base: https://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next config: arm64-allyesconfig (attached as .config) compiler: clang version 11.0.0 (git://gitmirror/llvm_project 7f9f027c62623bff79730cd30d1a8a534e2ddb06) reproduce: # FIXME the reproduce steps for clang is not ready yet If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@intel.com> All error/warnings (new ones prefixed by >>): >> drivers/edac/cadence_edac.c:179:9: error: implicit declaration of function 'EDAC_DIMM_PTR' [-Werror,-Wimplicit-function-declaration] dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); ^ >> drivers/edac/cadence_edac.c:179:7: warning: incompatible integer to pointer conversion assigning to 'struct dimm_info *' from 'int' [-Wint-conversion] dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/edac/cadence_edac.c:476:17: warning: unused variable 'root' [-Wunused-variable] struct dentry *root; ^ 2 warnings and 1 error generated. vim +/EDAC_DIMM_PTR +179 drivers/edac/cadence_edac.c 159 160 /** 161 * init_mem_layout - Set address Map as per the mc design. 162 * @mci: memory controller information. 163 * 164 * Set Address Map as per mc instance . 165 * 166 * Return: none. 167 */ 168 static void init_mem_layout(struct mem_ctl_info *mci) 169 { 170 struct cdns_edac_priv_data *priv = mci->pvt_info; 171 struct csrow_info *csi; 172 struct dimm_info *dimm; 173 struct sysinfo inf; 174 enum mem_type mtype; 175 u32 val, width; 176 u32 size, row; 177 u8 j; 178 > 179 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); 180 181 si_meminfo(&inf); 182 for (row = 0; row < mci->nr_csrows; row++) { 183 csi = mci->csrows[row]; 184 size = inf.totalram * inf.mem_unit; 185 186 for (j = 0; j < csi->nr_channels; j++) { 187 dimm = csi->channels[j]->dimm; 188 dimm->edac_mode = EDAC_FLAG_SECDED; 189 /* Get memory type by reading hw registers*/ 190 val = readl(priv->reg + DDR_CTL_MEM_TYPE_REG); 191 mtype = val & ECC_CTL_MTYPE_MASK; 192 193 if (mtype == MEM_TYPE_DDR4) 194 dimm->mtype = MEM_DDR4; 195 else 196 dimm->mtype = MEM_EMPTY; 197 198 /*Get EDAC devtype width for the current mc*/ 199 width = (readl(priv->reg + DDR_CTL_MEM_WIDTH_REG) & 200 CTL_MEM_MAX_WIDTH_MASK); 201 switch (width) { 202 case WDTH_16: 203 dimm->dtype = DEV_X2; 204 break; 205 case WDTH_32: 206 dimm->dtype = DEV_X4; 207 break; 208 case WDTH_64: 209 dimm->dtype = DEV_X8; 210 break; 211 default: 212 dimm->dtype = DEV_UNKNOWN; 213 } 214 215 dimm->nr_pages = (size >> PAGE_SHIFT) / 216 csi->nr_channels; 217 dimm->grain = CDNS_EDAC_ERR_GRAIN; 218 } 219 } 220 } 221 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org [-- Attachment #2: config.gz --] [-- Type: application/gzip, Size: 70475 bytes --]
next prev parent reply other threads:[~2020-02-26 3:27 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-25 9:38 [PATCH 0/2] Add EDAC support for Cadence ddr controller Dhananjay Kangude 2020-02-25 9:38 ` [PATCH 1/2] EDAC/Cadence:Add EDAC driver for cadence memory controller Dhananjay Kangude 2020-02-25 22:04 ` kbuild test robot 2020-02-25 22:04 ` kbuild test robot 2020-02-26 2:11 ` [RFC PATCH] EDAC/Cadence: data_synd[] can be static kbuild test robot 2020-02-26 2:11 ` kbuild test robot 2020-02-26 3:26 ` kbuild test robot [this message] 2020-02-26 3:26 ` [PATCH 1/2] EDAC/Cadence:Add EDAC driver for cadence memory controller kbuild test robot 2020-02-25 9:38 ` [PATCH 2/2] dt-bindings: edac: Add cadence ddr mc support Dhananjay Kangude 2020-02-25 16:58 ` Rob Herring
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