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* [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
@ 2020-02-26 13:02 sai gowtham
  2020-02-26 13:13 ` Chris Wilson
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: sai gowtham @ 2020-02-26 13:02 UTC (permalink / raw)
  To: sai.gowtham.ch, igt-dev

Replaced the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Used  gem_context_clone_with_engines
to make sure that engine index was potentially created
based on a  default context with engine map configured.

Added gem_reopen_driver and gem_context_copy_engines
to transfer the engine map from parent fd default
context.

Cc: Dec Katarzyna <katarzyna.dec@intel.com>
Cc: Ursulin Tvrtko <tvrtko.ursulin@intel.com>
Signed-off-by: sai gowtham <sai.gowtham.ch@intel.com>
---
 tests/i915/gem_sync.c | 559 ++++++++++++++++++++++++------------------
 1 file changed, 324 insertions(+), 235 deletions(-)

diff --git a/tests/i915/gem_sync.c b/tests/i915/gem_sync.c
index 2ef55ecc..a500c445 100644
--- a/tests/i915/gem_sync.c
+++ b/tests/i915/gem_sync.c
@@ -79,52 +79,55 @@ out:
 }
 
 static void
-sync_ring(int fd, unsigned ring, int num_children, int timeout)
+sync_ring(int fd, const struct intel_execution_engine2 *e, int num_children, int timeout)
 {
+	const struct intel_execution_engine2 *e2;
 	unsigned engines[16];
 	const char *names[16];
 	int num_engines = 0;
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			names[num_engines] = e->name;
-			engines[num_engines++] = eb_ring(e);
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			names[num_engines] = e2->name;
+			engines[num_engines++] = e2->flags;
 			if (num_engines == ARRAY_SIZE(engines))
 				break;
 		}
 
 		num_children *= num_engines;
 	} else {
-		gem_require_ring(fd, ring);
 		names[num_engines] = NULL;
-		engines[num_engines++] = ring;
+		engines[num_engines++] = e->flags;
 	}
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_children) {
+		int i915;
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 object;
 		struct drm_i915_gem_execbuffer2 execbuf;
 		double start, elapsed;
 		unsigned long cycles;
 
+		i915 = gem_reopen_driver(fd);
+		gem_context_copy_engines(fd, 0, i915, 0);
 		memset(&object, 0, sizeof(object));
-		object.handle = gem_create(fd, 4096);
-		gem_write(fd, object.handle, 0, &bbe, sizeof(bbe));
+		object.handle = gem_create(i915, 4096);
+		gem_write(i915, object.handle, 0, &bbe, sizeof(bbe));
 
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		execbuf.flags = engines[child % num_engines];
-		gem_execbuf(fd, &execbuf);
-		gem_sync(fd, object.handle);
+		gem_execbuf(i915, &execbuf);
+		gem_sync(i915, object.handle);
 
 		start = gettime();
 		cycles = 0;
 		do {
 			do {
-				gem_execbuf(fd, &execbuf);
-				gem_sync(fd, object.handle);
+				gem_execbuf(i915, &execbuf);
+				gem_sync(i915, object.handle);
 			} while (++cycles & 1023);
 		} while ((elapsed = gettime() - start) < timeout);
 		igt_info("%s%sompleted %ld cycles: %.3f us\n",
@@ -132,14 +135,14 @@ sync_ring(int fd, unsigned ring, int num_children, int timeout)
 			 names[child % num_engines] ? " c" : "C",
 			 cycles, elapsed*1e6/cycles);
 
-		gem_close(fd, object.handle);
+		gem_close(i915, object.handle);
 	}
 	igt_waitchildren_timeout(timeout+10, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
 static void
-idle_ring(int fd, unsigned ring, int timeout)
+idle_ring(int fd, const struct intel_execution_engine2 *e, int timeout)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_exec_object2 object;
@@ -147,7 +150,6 @@ idle_ring(int fd, unsigned ring, int timeout)
 	double start, elapsed;
 	unsigned long cycles;
 
-	gem_require_ring(fd, ring);
 
 	memset(&object, 0, sizeof(object));
 	object.handle = gem_create(fd, 4096);
@@ -156,7 +158,7 @@ idle_ring(int fd, unsigned ring, int timeout)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&object);
 	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	gem_execbuf(fd, &execbuf);
 	gem_sync(fd, object.handle);
 
@@ -178,32 +180,33 @@ idle_ring(int fd, unsigned ring, int timeout)
 }
 
 static void
-wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
+wakeup_ring(int fd, const struct intel_execution_engine2 *e, int timeout, int wlen)
 {
+	const struct intel_execution_engine2 *e2;
 	unsigned engines[16];
 	const char *names[16];
 	int num_engines = 0;
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			if (!gem_can_store_dword(fd, eb_ring(e)))
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			if (!gem_class_can_store_dword(fd, e2->class))
 				continue;
 
-			names[num_engines] = e->name;
-			engines[num_engines++] = eb_ring(e);
+			names[num_engines] = e2->name;
+			engines[num_engines++] = e2->flags;
 			if (num_engines == ARRAY_SIZE(engines))
 				break;
 		}
 		igt_require(num_engines);
 	} else {
-		gem_require_ring(fd, ring);
-		igt_require(gem_can_store_dword(fd, ring));
+		igt_require(gem_class_can_store_dword(fd, e->class));
 		names[num_engines] = NULL;
-		engines[num_engines++] = ring;
+		engines[num_engines++] = e->flags;
 	}
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_engines) {
+		int i915;
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 object;
 		struct drm_i915_gem_execbuffer2 execbuf;
@@ -211,9 +214,11 @@ wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 		unsigned long cycles;
 		igt_spin_t *spin;
 
+		i915 = gem_reopen_driver(fd);
+		gem_context_copy_engines(fd, 0, i915, 0);
 		memset(&object, 0, sizeof(object));
-		object.handle = gem_create(fd, 4096);
-		gem_write(fd, object.handle, 0, &bbe, sizeof(bbe));
+		object.handle = gem_create(i915, 4096);
+		gem_write(i915, object.handle, 0, &bbe, sizeof(bbe));
 
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(&object);
@@ -226,10 +231,10 @@ wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 						IGT_SPIN_FAST));
 		igt_assert(igt_spin_has_poll(spin));
 
-		gem_execbuf(fd, &execbuf);
+		gem_execbuf(i915, &execbuf);
 
 		igt_spin_end(spin);
-		gem_sync(fd, object.handle);
+		gem_sync(i915, object.handle);
 
 		for (int warmup = 0; warmup <= 1; warmup++) {
 			end = gettime() + timeout/10.;
@@ -238,12 +243,12 @@ wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 			do {
 				igt_spin_reset(spin);
 
-				gem_execbuf(fd, &spin->execbuf);
+				gem_execbuf(i915, &spin->execbuf);
 				igt_spin_busywait_until_started(spin);
 
 				this = gettime();
 				igt_spin_end(spin);
-				gem_sync(fd, spin->handle);
+				gem_sync(i915, spin->handle);
 				now = gettime();
 
 				elapsed += now - this;
@@ -262,15 +267,15 @@ wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 		do {
 			igt_spin_reset(spin);
 
-			gem_execbuf(fd, &spin->execbuf);
+			gem_execbuf(i915, &spin->execbuf);
 			igt_spin_busywait_until_started(spin);
 
 			for (int n = 0; n < wlen; n++)
-				gem_execbuf(fd, &execbuf);
+				gem_execbuf(i915, &execbuf);
 
 			this = gettime();
 			igt_spin_end(spin);
-			gem_sync(fd, object.handle);
+			gem_sync(i915, object.handle);
 			now = gettime();
 
 			elapsed += now - this;
@@ -283,49 +288,52 @@ wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 			 names[child % num_engines] ? " c" : "C",
 			 cycles, 1e6*baseline, elapsed*1e6/cycles);
 
-		igt_spin_free(fd, spin);
-		gem_close(fd, object.handle);
+		igt_spin_free(i915, spin);
+		gem_close(i915, object.handle);
 	}
 	igt_waitchildren_timeout(2*timeout, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
-static void active_ring(int fd, unsigned ring, int timeout)
+static void active_ring(int fd, const struct intel_execution_engine2 *e, int timeout)
 {
+	const struct intel_execution_engine2 *e2;
 	unsigned engines[16];
 	const char *names[16];
 	int num_engines = 0;
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			if (!gem_can_store_dword(fd, eb_ring(e)))
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			if (!gem_class_can_store_dword(fd, e2->class))
 				continue;
 
-			names[num_engines] = e->name;
-			engines[num_engines++] = eb_ring(e);
+			names[num_engines] = e2->name;
+			engines[num_engines++] = e2->flags;
 			if (num_engines == ARRAY_SIZE(engines))
 				break;
 		}
 		igt_require(num_engines);
 	} else {
-		gem_require_ring(fd, ring);
-		igt_require(gem_can_store_dword(fd, ring));
+		igt_require(gem_class_can_store_dword(fd, e->class));
 		names[num_engines] = NULL;
-		engines[num_engines++] = ring;
+		engines[num_engines++] = e->flags;
 	}
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_engines) {
+		int i915;
 		double start, end, elapsed;
 		unsigned long cycles;
 		igt_spin_t *spin[2];
 
-		spin[0] = __igt_spin_new(fd,
-					 .engine = ring,
+		i915 = gem_reopen_driver(fd);
+		gem_context_copy_engines(fd, 0, i915, 0);
+		spin[0] = __igt_spin_new(i915,
+					 .engine = e->flags,
 					 .flags = IGT_SPIN_FAST);
 
-		spin[1] = __igt_spin_new(fd,
-					 .engine = ring,
+		spin[1] = __igt_spin_new(i915,
+					 .engine = e->flags,
 					 .flags = IGT_SPIN_FAST);
 
 		start = gettime();
@@ -336,16 +344,16 @@ static void active_ring(int fd, unsigned ring, int timeout)
 				igt_spin_t *s = spin[loop & 1];
 
 				igt_spin_end(s);
-				gem_sync(fd, s->handle);
+				gem_sync(i915, s->handle);
 
 				igt_spin_reset(s);
 
-				gem_execbuf(fd, &s->execbuf);
+				gem_execbuf(i915, &s->execbuf);
 			}
 			cycles += 1024;
 		} while ((elapsed = gettime()) < end);
-		igt_spin_free(fd, spin[1]);
-		igt_spin_free(fd, spin[0]);
+		igt_spin_free(i915, spin[1]);
+		igt_spin_free(i915, spin[0]);
 
 		igt_info("%s%sompleted %ld cycles: %.3f us\n",
 			 names[child % num_engines] ?: "",
@@ -357,32 +365,33 @@ static void active_ring(int fd, unsigned ring, int timeout)
 }
 
 static void
-active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
+active_wakeup_ring(int fd, const struct intel_execution_engine2 *e, int timeout, int wlen)
 {
+	const struct intel_execution_engine2 *e2;
 	unsigned engines[16];
 	const char *names[16];
 	int num_engines = 0;
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			if (!gem_can_store_dword(fd, eb_ring(e)))
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			if (!gem_class_can_store_dword(fd, e2->class))
 				continue;
 
-			names[num_engines] = e->name;
-			engines[num_engines++] = eb_ring(e);
+			names[num_engines] = e2->name;
+			engines[num_engines++] = e2->flags;
 			if (num_engines == ARRAY_SIZE(engines))
 				break;
 		}
 		igt_require(num_engines);
 	} else {
-		gem_require_ring(fd, ring);
-		igt_require(gem_can_store_dword(fd, ring));
+		igt_require(gem_class_can_store_dword(fd, e->class));
 		names[num_engines] = NULL;
-		engines[num_engines++] = ring;
+		engines[num_engines++] = e->flags;
 	}
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_engines) {
+		int i915;
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 object;
 		struct drm_i915_gem_execbuffer2 execbuf;
@@ -390,36 +399,38 @@ active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 		unsigned long cycles;
 		igt_spin_t *spin[2];
 
+		i915 = gem_reopen_driver(fd);
+		gem_context_copy_engines(fd, 0, i915, 0);
 		memset(&object, 0, sizeof(object));
-		object.handle = gem_create(fd, 4096);
-		gem_write(fd, object.handle, 0, &bbe, sizeof(bbe));
+		object.handle = gem_create(i915, 4096);
+		gem_write(i915, object.handle, 0, &bbe, sizeof(bbe));
 
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		execbuf.flags = engines[child % num_engines];
 
-		spin[0] = __igt_spin_new(fd,
+		spin[0] = __igt_spin_new(i915,
 					 .engine = execbuf.flags,
 					 .flags = (IGT_SPIN_POLL_RUN |
 						   IGT_SPIN_FAST));
 		igt_assert(igt_spin_has_poll(spin[0]));
 
-		spin[1] = __igt_spin_new(fd,
+		spin[1] = __igt_spin_new(i915,
 					 .engine = execbuf.flags,
 					 .flags = (IGT_SPIN_POLL_RUN |
 						   IGT_SPIN_FAST));
 
-		gem_execbuf(fd, &execbuf);
+		gem_execbuf(i915, &execbuf);
 
 		igt_spin_end(spin[1]);
 		igt_spin_end(spin[0]);
-		gem_sync(fd, object.handle);
+		gem_sync(i915, object.handle);
 
 		for (int warmup = 0; warmup <= 1; warmup++) {
 			igt_spin_reset(spin[0]);
 
-			gem_execbuf(fd, &spin[0]->execbuf);
+			gem_execbuf(i915, &spin[0]->execbuf);
 
 			end = gettime() + timeout/10.;
 			elapsed = 0;
@@ -429,11 +440,11 @@ active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 
 				igt_spin_reset(spin[1]);
 
-				gem_execbuf(fd, &spin[1]->execbuf);
+				gem_execbuf(i915, &spin[1]->execbuf);
 
 				this = gettime();
 				igt_spin_end(spin[0]);
-				gem_sync(fd, spin[0]->handle);
+				gem_sync(i915, spin[0]->handle);
 				now = gettime();
 
 				elapsed += now - this;
@@ -450,7 +461,7 @@ active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 
 		igt_spin_reset(spin[0]);
 
-		gem_execbuf(fd, &spin[0]->execbuf);
+		gem_execbuf(i915, &spin[0]->execbuf);
 
 		end = gettime() + timeout;
 		elapsed = 0;
@@ -459,15 +470,15 @@ active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 			igt_spin_busywait_until_started(spin[0]);
 
 			for (int n = 0; n < wlen; n++)
-				gem_execbuf(fd, &execbuf);
+				gem_execbuf(i915, &execbuf);
 
 			igt_spin_reset(spin[1]);
 
-			gem_execbuf(fd, &spin[1]->execbuf);
+			gem_execbuf(i915, &spin[1]->execbuf);
 
 			this = gettime();
 			igt_spin_end(spin[0]);
-			gem_sync(fd, object.handle);
+			gem_sync(i915, object.handle);
 			now = gettime();
 
 			elapsed += now - this;
@@ -482,43 +493,44 @@ active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 			 names[child % num_engines] ? " c" : "C",
 			 cycles, 1e6*baseline, elapsed*1e6/cycles);
 
-		igt_spin_free(fd, spin[1]);
-		igt_spin_free(fd, spin[0]);
-		gem_close(fd, object.handle);
+		igt_spin_free(i915, spin[1]);
+		igt_spin_free(i915, spin[0]);
+		gem_close(i915, object.handle);
 	}
 	igt_waitchildren_timeout(2*timeout, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
 static void
-store_ring(int fd, unsigned ring, int num_children, int timeout)
+store_ring(int fd, const struct intel_execution_engine2 *e, int num_children, int timeout)
 {
+	const struct intel_execution_engine2 *e2;
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	unsigned engines[16];
 	const char *names[16];
 	int num_engines = 0;
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			if (!gem_can_store_dword(fd, eb_ring(e)))
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			if (!gem_class_can_store_dword(fd, e2->class))
 				continue;
 
-			names[num_engines] = e->name;
-			engines[num_engines++] = eb_ring(e);
+			names[num_engines] = e2->name;
+			engines[num_engines++] = e2->flags;
 			if (num_engines == ARRAY_SIZE(engines))
 				break;
 		}
 
 		num_children *= num_engines;
 	} else {
-		gem_require_ring(fd, ring);
-		igt_require(gem_can_store_dword(fd, ring));
+		igt_require(gem_class_can_store_dword(fd, e->class));
 		names[num_engines] = NULL;
-		engines[num_engines++] = ring;
+		engines[num_engines++] = e->flags;
 	}
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_children) {
+		int i915;
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 object[2];
 		struct drm_i915_gem_relocation_entry reloc[1024];
@@ -527,6 +539,8 @@ store_ring(int fd, unsigned ring, int num_children, int timeout)
 		unsigned long cycles;
 		uint32_t *batch, *b;
 
+		i915 = gem_reopen_driver(fd);
+		gem_context_copy_engines(fd, 0, i915, 0);
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(object);
 		execbuf.flags = engines[child % num_engines];
@@ -536,20 +550,20 @@ store_ring(int fd, unsigned ring, int num_children, int timeout)
 			execbuf.flags |= I915_EXEC_SECURE;
 
 		memset(object, 0, sizeof(object));
-		object[0].handle = gem_create(fd, 4096);
-		gem_write(fd, object[0].handle, 0, &bbe, sizeof(bbe));
+		object[0].handle = gem_create(i915, 4096);
+		gem_write(i915, object[0].handle, 0, &bbe, sizeof(bbe));
 		execbuf.buffer_count = 1;
-		gem_execbuf(fd, &execbuf);
+		gem_execbuf(i915, &execbuf);
 
 		object[0].flags |= EXEC_OBJECT_WRITE;
-		object[1].handle = gem_create(fd, 20*1024);
+		object[1].handle = gem_create(i915, 20*1024);
 
 		object[1].relocs_ptr = to_user_pointer(reloc);
 		object[1].relocation_count = 1024;
 
-		batch = gem_mmap__cpu(fd, object[1].handle, 0, 20*1024,
+		batch = gem_mmap__cpu(i915, object[1].handle, 0, 20*1024,
 				PROT_WRITE | PROT_READ);
-		gem_set_domain(fd, object[1].handle,
+		gem_set_domain(i915, object[1].handle,
 				I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
 
 		memset(reloc, 0, sizeof(reloc));
@@ -582,15 +596,15 @@ store_ring(int fd, unsigned ring, int num_children, int timeout)
 		igt_assert((b - batch)*sizeof(uint32_t) < 20*1024);
 		munmap(batch, 20*1024);
 		execbuf.buffer_count = 2;
-		gem_execbuf(fd, &execbuf);
-		gem_sync(fd, object[1].handle);
+		gem_execbuf(i915, &execbuf);
+		gem_sync(i915, object[1].handle);
 
 		start = gettime();
 		cycles = 0;
 		do {
 			do {
-				gem_execbuf(fd, &execbuf);
-				gem_sync(fd, object[1].handle);
+				gem_execbuf(i915, &execbuf);
+				gem_sync(i915, object[1].handle);
 			} while (++cycles & 1023);
 		} while ((elapsed = gettime() - start) < timeout);
 		igt_info("%s%sompleted %ld cycles: %.3f us\n",
@@ -598,16 +612,17 @@ store_ring(int fd, unsigned ring, int num_children, int timeout)
 			 names[child % num_engines] ? " c" : "C",
 			 cycles, elapsed*1e6/cycles);
 
-		gem_close(fd, object[1].handle);
-		gem_close(fd, object[0].handle);
+		gem_close(i915, object[1].handle);
+		gem_close(i915, object[0].handle);
 	}
 	igt_waitchildren_timeout(timeout+10, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
 static void
-switch_ring(int fd, unsigned ring, int num_children, int timeout)
+switch_ring(int fd, const struct intel_execution_engine2 *e, int num_children, int timeout)
 {
+	const struct intel_execution_engine2 *e2;
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	unsigned engines[16];
 	const char *names[16];
@@ -615,27 +630,28 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 
 	gem_require_contexts(fd);
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			if (!gem_can_store_dword(fd, eb_ring(e)))
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			if (!gem_class_can_store_dword(fd, e2->class))
 				continue;
 
-			names[num_engines] = e->name;
-			engines[num_engines++] = eb_ring(e);
+			names[num_engines] = e2->name;
+			engines[num_engines++] = e2->flags;
 			if (num_engines == ARRAY_SIZE(engines))
 				break;
 		}
 
 		num_children *= num_engines;
 	} else {
-		gem_require_ring(fd, ring);
-		igt_require(gem_can_store_dword(fd, ring));
+		igt_require(gem_class_can_store_dword(fd, e->class));
 		names[num_engines] = NULL;
-		engines[num_engines++] = ring;
+		engines[num_engines++] = e->flags;
 	}
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_children) {
+		int i915;
+		uint32_t ctx;
 		struct context {
 			struct drm_i915_gem_exec_object2 object[2];
 			struct drm_i915_gem_relocation_entry reloc[1024];
@@ -643,7 +659,13 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 		} contexts[2];
 		double elapsed, baseline;
 		unsigned long cycles;
-
+		/*
+		 * Ensure the gpu is idle by launching
+		 * nop execbuf and stalling for it.
+		 */
+		i915 = gem_reopen_driver(fd);
+		ctx = gem_context_create(fd);
+		gem_context_copy_engines(fd, 0, i915, ctx);
 		for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
 			const uint32_t bbe = MI_BATCH_BUFFER_END;
 			const uint32_t sz = 32 << 10;
@@ -657,23 +679,23 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 			c->execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
 			if (gen < 6)
 				c->execbuf.flags |= I915_EXEC_SECURE;
-			c->execbuf.rsvd1 = gem_context_create(fd);
+			c->execbuf.rsvd1 = ctx;
 
 			memset(c->object, 0, sizeof(c->object));
-			c->object[0].handle = gem_create(fd, 4096);
-			gem_write(fd, c->object[0].handle, 0, &bbe, sizeof(bbe));
+			c->object[0].handle = gem_create(i915, 4096);
+			gem_write(i915, c->object[0].handle, 0, &bbe, sizeof(bbe));
 			c->execbuf.buffer_count = 1;
-			gem_execbuf(fd, &c->execbuf);
+			gem_execbuf(i915, &c->execbuf);
 
 			c->object[0].flags |= EXEC_OBJECT_WRITE;
-			c->object[1].handle = gem_create(fd, sz);
+			c->object[1].handle = gem_create(i915, sz);
 
 			c->object[1].relocs_ptr = to_user_pointer(c->reloc);
 			c->object[1].relocation_count = 1024 * i;
 
-			batch = gem_mmap__cpu(fd, c->object[1].handle, 0, sz,
+			batch = gem_mmap__cpu(i915, c->object[1].handle, 0, sz,
 					PROT_WRITE | PROT_READ);
-			gem_set_domain(fd, c->object[1].handle,
+			gem_set_domain(i915, c->object[1].handle,
 					I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
 
 			memset(c->reloc, 0, sizeof(c->reloc));
@@ -707,8 +729,8 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 			igt_assert((b - batch)*sizeof(uint32_t) < sz);
 			munmap(batch, sz);
 			c->execbuf.buffer_count = 2;
-			gem_execbuf(fd, &c->execbuf);
-			gem_sync(fd, c->object[1].handle);
+			gem_execbuf(i915, &c->execbuf);
+			gem_sync(i915, c->object[1].handle);
 		}
 
 		cycles = 0;
@@ -717,12 +739,12 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 			do {
 				double this;
 
-				gem_execbuf(fd, &contexts[1].execbuf);
-				gem_execbuf(fd, &contexts[0].execbuf);
+				gem_execbuf(i915, &contexts[1].execbuf);
+				gem_execbuf(i915, &contexts[0].execbuf);
 
 				this = gettime();
-				gem_sync(fd, contexts[1].object[1].handle);
-				gem_sync(fd, contexts[0].object[1].handle);
+				gem_sync(i915, contexts[1].object[1].handle);
+				gem_sync(i915, contexts[0].object[1].handle);
 				baseline += gettime() - this;
 			} while (++cycles & 1023);
 		}
@@ -734,14 +756,14 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 			do {
 				double this;
 
-				gem_execbuf(fd, &contexts[1].execbuf);
-				gem_execbuf(fd, &contexts[0].execbuf);
+				gem_execbuf(i915, &contexts[1].execbuf);
+				gem_execbuf(i915, &contexts[0].execbuf);
 
 				this = gettime();
-				gem_sync(fd, contexts[0].object[1].handle);
+				gem_sync(i915, contexts[0].object[1].handle);
 				elapsed += gettime() - this;
 
-				gem_sync(fd, contexts[1].object[1].handle);
+				gem_sync(i915, contexts[1].object[1].handle);
 			} while (++cycles & 1023);
 		}
 		elapsed /= cycles;
@@ -752,9 +774,9 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 			 cycles, elapsed*1e6, baseline*1e6);
 
 		for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
-			gem_close(fd, contexts[i].object[1].handle);
-			gem_close(fd, contexts[i].object[0].handle);
-			gem_context_destroy(fd, contexts[i].execbuf.rsvd1);
+			gem_close(i915, contexts[i].object[1].handle);
+			gem_close(i915, contexts[i].object[0].handle);
+			gem_context_destroy(i915, contexts[i].execbuf.rsvd1);
 		}
 	}
 	igt_waitchildren_timeout(timeout+10, NULL);
@@ -803,7 +825,7 @@ static void *waiter(void *arg)
 }
 
 static void
-__store_many(int fd, unsigned ring, int timeout, unsigned long *cycles)
+__store_many(int fd, const struct intel_execution_engine2 *e, int timeout, unsigned long *cycles)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -817,7 +839,7 @@ __store_many(int fd, unsigned ring, int timeout, unsigned long *cycles)
 
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(object);
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
 	execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
 	if (gen < 6)
@@ -931,8 +953,9 @@ __store_many(int fd, unsigned ring, int timeout, unsigned long *cycles)
 }
 
 static void
-store_many(int fd, unsigned ring, int timeout)
+store_many(int fd, const struct intel_execution_engine2 *e, int timeout)
 {
+	const struct intel_execution_engine2 *e2;
 	unsigned long *shared;
 	const char *names[16];
 	int n = 0;
@@ -942,24 +965,23 @@ store_many(int fd, unsigned ring, int timeout)
 
 	intel_detect_and_clear_missed_interrupts(fd);
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			if (!gem_can_store_dword(fd, eb_ring(e)))
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			if (!gem_class_can_store_dword(fd, e2->class))
 				continue;
 
 			igt_fork(child, 1)
 				__store_many(fd,
-					     eb_ring(e),
+					     e2->flags,
 					     timeout,
 					     &shared[n]);
 
-			names[n++] = e->name;
+			names[n++] = e2->name;
 		}
 		igt_waitchildren();
 	} else {
-		gem_require_ring(fd, ring);
-		igt_require(gem_can_store_dword(fd, ring));
-		__store_many(fd, ring, timeout, &shared[n]);
+		igt_require(gem_class_can_store_dword(fd, e->class));
+		__store_many(fd, e, timeout, &shared[n]);
 		names[n++] = NULL;
 	}
 
@@ -974,11 +996,12 @@ store_many(int fd, unsigned ring, int timeout)
 static void
 sync_all(int fd, int num_children, int timeout)
 {
+	const struct intel_execution_engine2 *e;
 	unsigned engines[16];
 	int num_engines = 0;
 
-	for_each_physical_engine(e, fd) {
-		engines[num_engines++] = eb_ring(e);
+	__for_each_physical_engine(fd, e) {
+		engines[num_engines++] = e->flags;
 		if (num_engines == ARRAY_SIZE(engines))
 			break;
 	}
@@ -986,21 +1009,24 @@ sync_all(int fd, int num_children, int timeout)
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_children) {
+		int i915;
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 object;
 		struct drm_i915_gem_execbuffer2 execbuf;
 		double start, elapsed;
 		unsigned long cycles;
 
+		i915 = gem_reopen_driver(fd);
+		gem_context_copy_engines(fd, 0, i915, 0);
 		memset(&object, 0, sizeof(object));
-		object.handle = gem_create(fd, 4096);
-		gem_write(fd, object.handle, 0, &bbe, sizeof(bbe));
+		object.handle = gem_create(i915, 4096);
+		gem_write(i915, object.handle, 0, &bbe, sizeof(bbe));
 
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
-		gem_execbuf(fd, &execbuf);
-		gem_sync(fd, object.handle);
+		gem_execbuf(i915, &execbuf);
+		gem_sync(i915, object.handle);
 
 		start = gettime();
 		cycles = 0;
@@ -1008,15 +1034,15 @@ sync_all(int fd, int num_children, int timeout)
 			do {
 				for (int n = 0; n < num_engines; n++) {
 					execbuf.flags = engines[n];
-					gem_execbuf(fd, &execbuf);
+					gem_execbuf(i915, &execbuf);
 				}
-				gem_sync(fd, object.handle);
+				gem_sync(i915, object.handle);
 			} while (++cycles & 1023);
 		} while ((elapsed = gettime() - start) < timeout);
 		igt_info("Completed %ld cycles: %.3f us\n",
 			 cycles, elapsed*1e6/cycles);
 
-		gem_close(fd, object.handle);
+		gem_close(i915, object.handle);
 	}
 	igt_waitchildren_timeout(timeout+10, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
@@ -1025,15 +1051,16 @@ sync_all(int fd, int num_children, int timeout)
 static void
 store_all(int fd, int num_children, int timeout)
 {
+	const struct intel_execution_engine2 *e;
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	unsigned engines[16];
 	int num_engines = 0;
 
-	for_each_physical_engine(e, fd) {
-		if (!gem_can_store_dword(fd, eb_ring(e)))
+	__for_each_physical_engine(fd, e) {
+		if (!gem_class_can_store_dword(fd, e->class))
 			continue;
 
-		engines[num_engines++] = eb_ring(e);
+		engines[num_engines++] = e->flags;
 		if (num_engines == ARRAY_SIZE(engines))
 			break;
 	}
@@ -1041,6 +1068,7 @@ store_all(int fd, int num_children, int timeout)
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_children) {
+		int i915;
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 object[2];
 		struct drm_i915_gem_relocation_entry reloc[1024];
@@ -1049,6 +1077,8 @@ store_all(int fd, int num_children, int timeout)
 		unsigned long cycles;
 		uint32_t *batch, *b;
 
+		i915 = gem_reopen_driver(fd);
+		gem_context_copy_engines(fd, 0, i915, 0);
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(object);
 		execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
@@ -1057,20 +1087,20 @@ store_all(int fd, int num_children, int timeout)
 			execbuf.flags |= I915_EXEC_SECURE;
 
 		memset(object, 0, sizeof(object));
-		object[0].handle = gem_create(fd, 4096);
-		gem_write(fd, object[0].handle, 0, &bbe, sizeof(bbe));
+		object[0].handle = gem_create(i915, 4096);
+		gem_write(i915, object[0].handle, 0, &bbe, sizeof(bbe));
 		execbuf.buffer_count = 1;
-		gem_execbuf(fd, &execbuf);
+		gem_execbuf(i915, &execbuf);
 
 		object[0].flags |= EXEC_OBJECT_WRITE;
-		object[1].handle = gem_create(fd, 1024*16 + 4096);
+		object[1].handle = gem_create(i915, 1024*16 + 4096);
 
 		object[1].relocs_ptr = to_user_pointer(reloc);
 		object[1].relocation_count = 1024;
 
-		batch = gem_mmap__cpu(fd, object[1].handle, 0, 16*1024 + 4096,
+		batch = gem_mmap__cpu(i915, object[1].handle, 0, 16*1024 + 4096,
 				PROT_WRITE | PROT_READ);
-		gem_set_domain(fd, object[1].handle,
+		gem_set_domain(i915, object[1].handle,
 				I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
 
 		memset(reloc, 0, sizeof(reloc));
@@ -1103,8 +1133,8 @@ store_all(int fd, int num_children, int timeout)
 		igt_assert((b - batch)*sizeof(uint32_t) < 20*1024);
 		munmap(batch, 16*1024+4096);
 		execbuf.buffer_count = 2;
-		gem_execbuf(fd, &execbuf);
-		gem_sync(fd, object[1].handle);
+		gem_execbuf(i915, &execbuf);
+		gem_sync(i915, object[1].handle);
 
 		start = gettime();
 		cycles = 0;
@@ -1114,102 +1144,103 @@ store_all(int fd, int num_children, int timeout)
 				for (int n = 0; n < num_engines; n++) {
 					execbuf.flags &= ~ENGINE_MASK;
 					execbuf.flags |= engines[n];
-					gem_execbuf(fd, &execbuf);
+					gem_execbuf(i915, &execbuf);
 				}
-				gem_sync(fd, object[1].handle);
+				gem_sync(i915, object[1].handle);
 			} while (++cycles & 1023);
 		} while ((elapsed = gettime() - start) < timeout);
 		igt_info("Completed %ld cycles: %.3f us\n",
 			 cycles, elapsed*1e6/cycles);
 
-		gem_close(fd, object[1].handle);
-		gem_close(fd, object[0].handle);
+		gem_close(i915, object[1].handle);
+		gem_close(i915, object[0].handle);
 	}
 	igt_waitchildren_timeout(timeout+10, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
 static void
-preempt(int fd, unsigned ring, int num_children, int timeout)
+preempt(int fd, const struct intel_execution_engine2 *e, int num_children, int timeout)
 {
+	const struct intel_execution_engine2 *e2;
 	unsigned engines[16];
 	const char *names[16];
 	int num_engines = 0;
-	uint32_t ctx[2];
 
-	if (ring == ALL_ENGINES) {
-		for_each_physical_engine(e, fd) {
-			names[num_engines] = e->name;
-			engines[num_engines++] = eb_ring(e);
+	if (!e) {
+		__for_each_physical_engine(fd, e2) {
+			names[num_engines] = e2->name;
+			engines[num_engines++] = e2->flags;
 			if (num_engines == ARRAY_SIZE(engines))
 				break;
 		}
 
 		num_children *= num_engines;
 	} else {
-		gem_require_ring(fd, ring);
 		names[num_engines] = NULL;
-		engines[num_engines++] = ring;
+		engines[num_engines++] = e->flags;
 	}
 
-	ctx[0] = gem_context_create(fd);
-	gem_context_set_priority(fd, ctx[0], MIN_PRIO);
-
-	ctx[1] = gem_context_create(fd);
-	gem_context_set_priority(fd, ctx[1], MAX_PRIO);
-
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_children) {
+		int i915;
+		uint32_t ctx[2];
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 object;
 		struct drm_i915_gem_execbuffer2 execbuf;
 		double start, elapsed;
 		unsigned long cycles;
 
+		i915 = gem_reopen_driver(fd);
+		ctx[1] = gem_context_clone_with_engines(fd, 0);
+		gem_context_set_priority(fd, ctx[1], MAX_PRIO);
+		gem_context_copy_engines(fd, 0, i915, ctx[1]);
 		memset(&object, 0, sizeof(object));
-		object.handle = gem_create(fd, 4096);
-		gem_write(fd, object.handle, 0, &bbe, sizeof(bbe));
+		object.handle = gem_create(i915, 4096);
+		gem_write(i915, object.handle, 0, &bbe, sizeof(bbe));
 
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		execbuf.flags = engines[child % num_engines];
 		execbuf.rsvd1 = ctx[1];
-		gem_execbuf(fd, &execbuf);
-		gem_sync(fd, object.handle);
-
+		gem_execbuf(i915, &execbuf);
+		gem_sync(i915, object.handle);
+		ctx[0] = gem_context_clone_with_engines(fd, 0);
+		gem_context_set_priority(fd, ctx[0], MIN_PRIO);
+		gem_context_copy_engines(fd, 0, i915, ctx[0]);
 		start = gettime();
 		cycles = 0;
 		do {
 			igt_spin_t *spin =
-				__igt_spin_new(fd,
+				__igt_spin_new(i915,
 					       .ctx = ctx[0],
 					       .engine = execbuf.flags);
 
 			do {
-				gem_execbuf(fd, &execbuf);
-				gem_sync(fd, object.handle);
+				gem_execbuf(i915, &execbuf);
+				gem_sync(i915, object.handle);
 			} while (++cycles & 1023);
 
-			igt_spin_free(fd, spin);
+			igt_spin_free(i915, spin);
 		} while ((elapsed = gettime() - start) < timeout);
 		igt_info("%s%sompleted %ld cycles: %.3f us\n",
 			 names[child % num_engines] ?: "",
 			 names[child % num_engines] ? " c" : "C",
 			 cycles, elapsed*1e6/cycles);
 
-		gem_close(fd, object.handle);
+		gem_context_destroy(i915, ctx[1]);
+		gem_context_destroy(i915, ctx[0]);
+		gem_close(i915, object.handle);
 	}
 	igt_waitchildren_timeout(timeout+10, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 
-	gem_context_destroy(fd, ctx[1]);
-	gem_context_destroy(fd, ctx[0]);
 }
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	int fd = -1;
 
@@ -1221,56 +1252,113 @@ igt_main
 
 		igt_fork_hang_detector(fd);
 	}
-
-	for (e = intel_execution_engines; e->name; e++) {
-		igt_subtest_f("%s", e->name)
-			sync_ring(fd, eb_ring(e), 1, 20);
-		igt_subtest_f("idle-%s", e->name)
-			idle_ring(fd, eb_ring(e), 20);
-		igt_subtest_f("active-%s", e->name)
-			active_ring(fd, eb_ring(e), 20);
-		igt_subtest_f("wakeup-%s", e->name)
-			wakeup_ring(fd, eb_ring(e), 20, 1);
-		igt_subtest_f("active-wakeup-%s", e->name)
-			active_wakeup_ring(fd, eb_ring(e), 20, 1);
-		igt_subtest_f("double-wakeup-%s", e->name)
-			wakeup_ring(fd, eb_ring(e), 20, 2);
-		igt_subtest_f("store-%s", e->name)
-			store_ring(fd, eb_ring(e), 1, 20);
-		igt_subtest_f("switch-%s", e->name)
-			switch_ring(fd, eb_ring(e), 1, 20);
-		igt_subtest_f("forked-switch-%s", e->name)
-			switch_ring(fd, eb_ring(e), ncpus, 20);
-		igt_subtest_f("many-%s", e->name)
-			store_many(fd, eb_ring(e), 20);
-		igt_subtest_f("forked-%s", e->name)
-			sync_ring(fd, eb_ring(e), ncpus, 20);
-		igt_subtest_f("forked-store-%s", e->name)
-			store_ring(fd, eb_ring(e), ncpus, 20);
+	igt_subtest_with_dynamic("basic_sync_ring") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				sync_ring(fd, e, 1, 20);
+		}
+	}
+	igt_subtest_with_dynamic("idle") {
+		__for_each_physical_engine(fd, e) {
+			 /* Requires master for STORE_DWORD on gen4/5 */
+			 igt_dynamic_f("%s", e->name)
+				idle_ring(fd, e, 20);
+		 }
+	}
+	igt_subtest_with_dynamic("active") {
+		__for_each_physical_engine(fd, e) {
+			 /* Requires master for STORE_DWORD on gen4/5 */
+			 igt_dynamic_f("%s", e->name)
+				active_ring(fd, e, 20);
+		 }
+	}
+	igt_subtest_with_dynamic("wakeup") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				wakeup_ring(fd, e, 150, 1);
+		}
+	}
+	igt_subtest_with_dynamic("active-wakeup") {
+		__for_each_physical_engine(fd, e) {
+			 /* Requires master for STORE_DWORD on gen4/5 */
+			 igt_dynamic_f("%s", e->name)
+				active_wakeup_ring(fd, e, 1, 20);
+		 }
+	}
+	igt_subtest_with_dynamic("double-wakeup") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				wakeup_ring(fd, e, 20, 2);
+		}
+	}
+	igt_subtest_with_dynamic("store") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				store_ring(fd, e, 1, 20);
+		}
+	}
+	igt_subtest_with_dynamic("switch") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				switch_ring(fd, e, 1, 20);
+		}
+	}
+	igt_subtest_with_dynamic("forked-switch") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				switch_ring(fd, e, ncpus, 20);
+		}
+	}
+	igt_subtest_with_dynamic("many") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				store_many(fd, e, 20);
+		}
+	}
+	igt_subtest_with_dynamic("forked") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				sync_ring(fd, e, ncpus, 20);
+		}
+	}
+	igt_subtest_with_dynamic("forked-store") {
+		__for_each_physical_engine(fd, e) {
+			/* Requires master for STORE_DWORD on gen4/5 */
+			igt_dynamic_f("%s", e->name)
+				store_ring(fd, e, ncpus, 20);
+		}
 	}
 
 	igt_subtest("basic-each")
-		sync_ring(fd, ALL_ENGINES, 1, 2);
+		sync_ring(fd, NULL, 1, 2);
 	igt_subtest("basic-store-each")
-		store_ring(fd, ALL_ENGINES, 1, 2);
+		store_ring(fd, NULL, 1, 2);
 	igt_subtest("basic-many-each")
-		store_many(fd, ALL_ENGINES, 2);
+		store_many(fd, NULL, 2);
 	igt_subtest("switch-each")
-		switch_ring(fd, ALL_ENGINES, 1, 20);
+		switch_ring(fd, NULL, 1, 20);
 	igt_subtest("forked-switch-each")
-		switch_ring(fd, ALL_ENGINES, ncpus, 20);
+		switch_ring(fd, NULL, ncpus, 20);
 	igt_subtest("forked-each")
-		sync_ring(fd, ALL_ENGINES, ncpus, 20);
+		sync_ring(fd, NULL, ncpus, 20);
 	igt_subtest("forked-store-each")
-		store_ring(fd, ALL_ENGINES, ncpus, 20);
+		store_ring(fd, NULL, ncpus, 20);
 	igt_subtest("active-each")
-		active_ring(fd, ALL_ENGINES, 20);
+		active_ring(fd, NULL, 20);
 	igt_subtest("wakeup-each")
-		wakeup_ring(fd, ALL_ENGINES, 20, 1);
+		wakeup_ring(fd, NULL, 20, 1);
 	igt_subtest("active-wakeup-each")
-		active_wakeup_ring(fd, ALL_ENGINES, 20, 1);
+		active_wakeup_ring(fd, NULL, 20, 1);
 	igt_subtest("double-wakeup-each")
-		wakeup_ring(fd, ALL_ENGINES, 20, 2);
+		wakeup_ring(fd, NULL, 20, 2);
 
 	igt_subtest("basic-all")
 		sync_all(fd, 1, 2);
@@ -1294,14 +1382,15 @@ igt_main
 		}
 
 		igt_subtest("preempt-all")
-			preempt(fd, ALL_ENGINES, 1, 20);
-
-		for (e = intel_execution_engines; e->name; e++) {
-			igt_subtest_f("preempt-%s", e->name)
-				preempt(fd, eb_ring(e), ncpus, 20);
+			preempt(fd, NULL, 1, 20);
+		igt_subtest_with_dynamic("preempt") {
+			__for_each_physical_engine(fd, e) {
+				/* Requires master for STORE_DWORD on gen4/5 */
+				igt_dynamic_f("%s", e->name)
+					preempt(fd, e, ncpus, 20);
+			}
 		}
 	}
-
 	igt_fixture {
 		igt_stop_hang_detector();
 		close(fd);
-- 
2.25.0

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
  2020-02-26 13:02 [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines sai gowtham
@ 2020-02-26 13:13 ` Chris Wilson
  2020-04-06  9:57   ` Ch, Sai Gowtham
  2020-02-26 14:52 ` [igt-dev] ✗ GitLab.Pipeline: failure for " Patchwork
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2020-02-26 13:13 UTC (permalink / raw)
  To: igt-dev, sai.gowtham.ch

Quoting sai gowtham (2020-02-26 13:02:41)
> @@ -1221,56 +1252,113 @@ igt_main
>  
>                 igt_fork_hang_detector(fd);
>         }

To be safe, I need one to cover the legacy API. To check the bare
essential that we can wait on a newly submitted request. A sync_ring,
and a sync_all.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [igt-dev] ✗ GitLab.Pipeline: failure for tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
  2020-02-26 13:02 [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines sai gowtham
  2020-02-26 13:13 ` Chris Wilson
@ 2020-02-26 14:52 ` Patchwork
  2020-02-26 16:13 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
  2020-02-27  3:52 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-26 14:52 UTC (permalink / raw)
  To: sai gowtham; +Cc: igt-dev

== Series Details ==

Series: tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
URL   : https://patchwork.freedesktop.org/series/73955/
State : failure

== Summary ==

ERROR! This series introduces new undocumented tests:

gem_sync@active
gem_sync@active-wakeup
gem_sync@basic_sync_ring
gem_sync@double-wakeup
gem_sync@forked
gem_sync@forked-store
gem_sync@forked-switch
gem_sync@idle
gem_sync@many
gem_sync@preempt
gem_sync@store
gem_sync@switch
gem_sync@wakeup

Can you document them as per the requirement in the [CONTRIBUTING.md]?

[Documentation] has more details on how to do this.

Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d

Thanks in advance!

[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Other than that, pipeline status: SUCCESS.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/112893 for the overview.

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/112893
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [igt-dev] ✓ Fi.CI.BAT: success for tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
  2020-02-26 13:02 [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines sai gowtham
  2020-02-26 13:13 ` Chris Wilson
  2020-02-26 14:52 ` [igt-dev] ✗ GitLab.Pipeline: failure for " Patchwork
@ 2020-02-26 16:13 ` Patchwork
  2020-02-27  3:52 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-26 16:13 UTC (permalink / raw)
  To: sai gowtham; +Cc: igt-dev

== Series Details ==

Series: tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
URL   : https://patchwork.freedesktop.org/series/73955/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8007 -> IGTPW_4228
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/index.html

Known issues
------------

  Here are the changes found in IGTPW_4228 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-ilk-650:         [PASS][1] -> [DMESG-WARN][2] ([i915#116])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/fi-ilk-650/igt@gem_exec_suspend@basic-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/fi-ilk-650/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-tgl-y:           [PASS][3] -> [FAIL][4] ([CI#94])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cml-s:           [PASS][5] -> [DMESG-FAIL][6] ([i915#877])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/fi-cml-s/igt@i915_selftest@live_gem_contexts.html

  * igt@prime_self_import@basic-llseek-bad:
    - fi-tgl-y:           [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html

  
#### Possible fixes ####

  * igt@gem_flink_basic@bad-flink:
    - fi-tgl-y:           [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/fi-tgl-y/igt@gem_flink_basic@bad-flink.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/fi-tgl-y/igt@gem_flink_basic@bad-flink.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][11] ([fdo#111407]) -> [FAIL][12] ([fdo#111096] / [i915#323])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [i915#116]: https://gitlab.freedesktop.org/drm/intel/issues/116
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877


Participating hosts (48 -> 43)
------------------------------

  Additional (2): fi-skl-6770hq fi-tgl-u 
  Missing    (7): fi-kbl-soraka fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5469 -> IGTPW_4228

  CI-20190529: 20190529
  CI_DRM_8007: 8dbfb8dcfb623026de73fdb617785f507064af89 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4228: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/index.html
  IGT_5469: 4f875016eb1ebc211b8aadb280ae16c7e6cdc8ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+++ 13 lines
--- 91 lines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [igt-dev] ✗ Fi.CI.IGT: failure for tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
  2020-02-26 13:02 [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines sai gowtham
                   ` (2 preceding siblings ...)
  2020-02-26 16:13 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-02-27  3:52 ` Patchwork
  3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-27  3:52 UTC (permalink / raw)
  To: sai gowtham; +Cc: igt-dev

== Series Details ==

Series: tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
URL   : https://patchwork.freedesktop.org/series/73955/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8007_full -> IGTPW_4228_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4228_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4228_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4228_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_pwrite@huge-cpu-fbr:
    - shard-hsw:          [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw1/igt@gem_pwrite@huge-cpu-fbr.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw5/igt@gem_pwrite@huge-cpu-fbr.html

  * igt@gem_sync@basic-many-each:
    - shard-snb:          [PASS][3] -> [CRASH][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb4/igt@gem_sync@basic-many-each.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb5/igt@gem_sync@basic-many-each.html
    - shard-hsw:          [PASS][5] -> [CRASH][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw7/igt@gem_sync@basic-many-each.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw4/igt@gem_sync@basic-many-each.html
    - shard-kbl:          [PASS][7] -> [CRASH][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-kbl6/igt@gem_sync@basic-many-each.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-kbl4/igt@gem_sync@basic-many-each.html
    - shard-iclb:         [PASS][9] -> [CRASH][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb2/igt@gem_sync@basic-many-each.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb5/igt@gem_sync@basic-many-each.html
    - shard-apl:          [PASS][11] -> [CRASH][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-apl3/igt@gem_sync@basic-many-each.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-apl6/igt@gem_sync@basic-many-each.html
    - shard-glk:          [PASS][13] -> [CRASH][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-glk7/igt@gem_sync@basic-many-each.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-glk7/igt@gem_sync@basic-many-each.html
    - shard-tglb:         [PASS][15] -> [CRASH][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-tglb7/igt@gem_sync@basic-many-each.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-tglb6/igt@gem_sync@basic-many-each.html

  * igt@sw_sync@sync_multi_producer_single_consumer:
    - shard-apl:          [PASS][17] -> [TIMEOUT][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-apl6/igt@sw_sync@sync_multi_producer_single_consumer.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-apl4/igt@sw_sync@sync_multi_producer_single_consumer.html

  
New tests
---------

  New tests have been introduced between CI_DRM_8007_full and IGTPW_4228_full:

### New IGT tests (6) ###

  * igt@gem_sync@basic_sync_ring:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_sync@basic_sync_ring@bcs0:
    - Statuses : 7 pass(s)
    - Exec time: [20.04, 20.45] s

  * igt@gem_sync@basic_sync_ring@rcs0:
    - Statuses : 7 pass(s)
    - Exec time: [20.02, 20.28] s

  * igt@gem_sync@basic_sync_ring@vcs0:
    - Statuses : 7 pass(s)
    - Exec time: [20.03, 20.22] s

  * igt@gem_sync@basic_sync_ring@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [20.05, 20.06] s

  * igt@gem_sync@basic_sync_ring@vecs0:
    - Statuses : 6 pass(s)
    - Exec time: [20.02, 20.17] s

  

Known issues
------------

  Here are the changes found in IGTPW_4228_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-apl3/igt@gem_eio@in-flight-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-apl6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#110854])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb2/igt@gem_exec_balancer@smoke.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb8/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@pi-distinct-iova-bsd:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([i915#677])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb3/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#112146]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][27] -> [FAIL][28] ([i915#644])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
    - shard-tglb:         [PASS][29] -> [FAIL][30] ([i915#644])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-tglb5/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-tglb6/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [PASS][31] -> [DMESG-WARN][32] ([fdo#110789] / [fdo#111870]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw1/igt@gem_userptr_blits@sync-unmap-after-close.html
    - shard-snb:          [PASS][33] -> [DMESG-WARN][34] ([fdo#110789] / [fdo#111870] / [i915#478]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb2/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@i915_pm_rps@waitboost:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([i915#413])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb6/igt@i915_pm_rps@waitboost.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb6/igt@i915_pm_rps@waitboost.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-tglb:         [PASS][37] -> [FAIL][38] ([i915#488])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-tglb2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-tglb8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-glk:          [PASS][39] -> [FAIL][40] ([i915#899])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-glk6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][41] -> [FAIL][42] ([i915#173])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb3/igt@kms_psr@no_drrs.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][43] -> [SKIP][44] ([fdo#109441]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb2/igt@kms_psr@psr2_basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb5/igt@kms_psr@psr2_basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][45] -> [DMESG-WARN][46] ([i915#180]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [PASS][47] -> [SKIP][48] ([fdo#112080]) +9 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb4/igt@perf_pmu@busy-vcs1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb7/igt@perf_pmu@busy-vcs1.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][49] -> [SKIP][50] ([fdo#109276]) +22 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [SKIP][53] ([fdo#112080]) -> [PASS][54] +12 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb7/igt@gem_exec_parallel@vcs1-fds.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html

  * {igt@gem_exec_schedule@implicit-read-write-bsd1}:
    - shard-iclb:         [SKIP][55] ([fdo#109276] / [i915#677]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb3/igt@gem_exec_schedule@implicit-read-write-bsd1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb4/igt@gem_exec_schedule@implicit-read-write-bsd1.html

  * igt@gem_exec_schedule@pi-common-bsd:
    - shard-iclb:         [SKIP][57] ([i915#677]) -> [PASS][58] +3 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb5/igt@gem_exec_schedule@pi-common-bsd.html

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [SKIP][59] ([fdo#112146]) -> [PASS][60] +5 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb1/igt@gem_exec_schedule@preempt-bsd.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb3/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][61] ([fdo#109276]) -> [PASS][62] +18 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb8/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-kbl:          [FAIL][63] ([i915#644]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-kbl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-kbl4/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          [INCOMPLETE][65] ([fdo#103665]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-kbl2/igt@gem_softpin@noreloc-s3.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-kbl4/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-hsw:          [SKIP][67] ([fdo#109271]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw1/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
    - shard-glk:          [SKIP][69] ([fdo#109271]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-glk7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-glk1/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * {igt@i915_pm_rpm@gem-mmap-type@wb}:
    - shard-hsw:          [DMESG-WARN][71] -> [PASS][72] +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw7/igt@i915_pm_rpm@gem-mmap-type@wb.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw4/igt@i915_pm_rpm@gem-mmap-type@wb.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-kbl:          [FAIL][73] ([fdo#103375]) -> [PASS][74] +1 similar issue
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-kbl4/igt@i915_pm_rpm@system-suspend-modeset.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-kbl7/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@i915_pm_rps@reset:
    - shard-iclb:         [FAIL][75] ([i915#413]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb2/igt@i915_pm_rps@reset.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb6/igt@i915_pm_rps@reset.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding:
    - shard-apl:          [FAIL][77] ([i915#54]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][79] ([i915#79]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-snb:          [DMESG-WARN][81] ([i915#478]) -> [PASS][82] +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
    - shard-glk:          [FAIL][83] ([i915#49]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@primary_mmap_gtt:
    - shard-tglb:         [SKIP][87] ([i915#668]) -> [PASS][88] +8 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-tglb3/igt@kms_psr@primary_mmap_gtt.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-tglb6/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [SKIP][89] ([fdo#109441]) -> [PASS][90] +2 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb5/igt@kms_psr@psr2_sprite_render.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb2/igt@kms_psr@psr2_sprite_render.html

  * igt@sw_sync@sync_multi_producer_single_consumer:
    - shard-tglb:         [TIMEOUT][91] -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-tglb7/igt@sw_sync@sync_multi_producer_single_consumer.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-tglb1/igt@sw_sync@sync_multi_producer_single_consumer.html
    - shard-iclb:         [TIMEOUT][93] -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb3/igt@sw_sync@sync_multi_producer_single_consumer.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb3/igt@sw_sync@sync_multi_producer_single_consumer.html

  
#### Warnings ####

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-tglb:         [SKIP][95] -> [SKIP][96] ([fdo#111644])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-tglb6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-tglb2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
    - shard-iclb:         [SKIP][97] -> [SKIP][98] ([fdo#110892])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb1/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][99] ([fdo#109349]) -> [DMESG-WARN][100] ([i915#1226])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@runner@aborted:
    - shard-hsw:          ([FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108]) ([fdo#111870] / [i915#226]) -> ([FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116]) ([fdo#111870])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw5/igt@runner@aborted.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw7/igt@runner@aborted.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw7/igt@runner@aborted.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw5/igt@runner@aborted.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw6/igt@runner@aborted.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw7/igt@runner@aborted.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw1/igt@runner@aborted.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-hsw5/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw1/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw4/igt@runner@aborted.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw7/igt@runner@aborted.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw1/igt@runner@aborted.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw1/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw7/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw7/igt@runner@aborted.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-hsw1/igt@runner@aborted.html
    - shard-snb:          ([FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([fdo#111870] / [i915#1077] / [i915#698]) -> ([FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([fdo#111870] / [i915#1077])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb4/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb6/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb2/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb4/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb6/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb2/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb6/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8007/shard-snb2/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb5/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb6/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb5/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb6/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb6/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb4/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb2/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/shard-snb2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#1077]: https://gitlab.freedesktop.org/drm/intel/issues/1077
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
  [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#226]: https://gitlab.freedesktop.org/drm/intel/issues/226
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
  [i915#488]: https://gitlab.freedesktop.org/drm/intel/issues/488
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#698]: https://gitlab.freedesktop.org/drm/intel/issues/698
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899


Participating hosts (10 -> 8)
------------------------------

  Missing    (2): pig-skl-6260u pig-glk-j5005 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5469 -> IGTPW_4228
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_8007: 8dbfb8dcfb623026de73fdb617785f507064af89 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4228: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/index.html
  IGT_5469: 4f875016eb1ebc211b8aadb280ae16c7e6cdc8ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4228/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.
  2020-02-26 13:13 ` Chris Wilson
@ 2020-04-06  9:57   ` Ch, Sai Gowtham
  0 siblings, 0 replies; 6+ messages in thread
From: Ch, Sai Gowtham @ 2020-04-06  9:57 UTC (permalink / raw)
  To: Chris Wilson, igt-dev

Patch has been sent  https://patchwork.freedesktop.org/patch/360240/

Thanks,
Gowtham

-----Original Message-----
From: Chris Wilson <chris@chris-wilson.co.uk> 
Sent: Wednesday, February 26, 2020 6:43 PM
To: igt-dev@lists.freedesktop.org; Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
Subject: Re: [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines.

Quoting sai gowtham (2020-02-26 13:02:41)
> @@ -1221,56 +1252,113 @@ igt_main
>  
>                 igt_fork_hang_detector(fd);
>         }

To be safe, I need one to cover the legacy API. To check the bare essential that we can wait on a newly submitted request. A sync_ring, and a sync_all.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-04-06  9:57 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-26 13:02 [igt-dev] [PATCH] [PATCH i-g-t] tests/i915/gem_sync.c :Added __for_each_physical_engine to utilize all available engines sai gowtham
2020-02-26 13:13 ` Chris Wilson
2020-04-06  9:57   ` Ch, Sai Gowtham
2020-02-26 14:52 ` [igt-dev] ✗ GitLab.Pipeline: failure for " Patchwork
2020-02-26 16:13 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2020-02-27  3:52 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork

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