* [PATCH 1/2] phy: cadence: salvo: add salvo phy driver
@ 2020-02-27 6:27 Peter Chen
2020-02-27 6:27 ` [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc Peter Chen
2020-03-12 10:16 ` [PATCH 1/2] phy: cadence: salvo: add salvo phy driver Peter Chen
0 siblings, 2 replies; 10+ messages in thread
From: Peter Chen @ 2020-02-27 6:27 UTC (permalink / raw)
To: kishon, robh+dt
Cc: linux-usb, linux-imx, aniljoy, jun.li, devicetree, Peter Chen
Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2.
According to the Cadence, this PHY is a legacy Module, and Sierra and
Torrent are later evolutions from it, and their sequence overlap is
minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY
drivers.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
---
drivers/phy/cadence/Kconfig | 9 +
drivers/phy/cadence/Makefile | 1 +
drivers/phy/cadence/phy-cadence-salvo.c | 316 ++++++++++++++++++++++++
3 files changed, 326 insertions(+)
create mode 100644 drivers/phy/cadence/phy-cadence-salvo.c
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index b2db916db64b..eca272b227b7 100644
--- a/drivers/phy/cadence/Kconfig
+++ b/drivers/phy/cadence/Kconfig
@@ -27,3 +27,12 @@ config PHY_CADENCE_SIERRA
select GENERIC_PHY
help
Enable this to support the Cadence Sierra PHY driver
+
+config PHY_CADENCE_SALVO
+ tristate "Cadence Salvo PHY Driver"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to support the Cadence SALVO PHY driver,
+ this PHY is a legacy PHY, and only are used for USB3
+ and USB2.
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
index 8f89560f1711..7c7d13c0c647 100644
--- a/drivers/phy/cadence/Makefile
+++ b/drivers/phy/cadence/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
+obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o
diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
new file mode 100644
index 000000000000..fa666527356d
--- /dev/null
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Salvo PHY is a 28nm PHY, it is a legacy PHY, and only
+ * for USB3 and USB2.
+ *
+ * Copyright (c) 2019-2020 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+/* PHY register definition */
+#define PHY_PMA_CMN_CTRL1 0xC800
+#define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
+#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
+#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
+#define TB_ADDR_CMN_PLL0_INTDIV 0x0094
+#define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
+#define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
+#define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
+#define TB_ADDR_CMN_PLL0_SS_CTRL2 0x0099
+#define TB_ADDR_CMN_PLL0_DSM_DIAG 0x0097
+#define TB_ADDR_CMN_DIAG_PLL0_OVRD 0x01c2
+#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD 0x01c0
+#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD 0x01c1
+#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE 0x01C5
+#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE 0x01C6
+#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG 0x01C7
+#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE 0x01c4
+#define TB_ADDR_CMN_PSM_CLK_CTRL 0x0061
+#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR 0x40ea
+#define TB_ADDR_XCVR_PSM_RCTRL 0x4001
+#define TB_ADDR_TX_PSC_A0 0x4100
+#define TB_ADDR_TX_PSC_A1 0x4101
+#define TB_ADDR_TX_PSC_A2 0x4102
+#define TB_ADDR_TX_PSC_A3 0x4103
+#define TB_ADDR_TX_DIAG_ECTRL_OVRD 0x41f5
+#define TB_ADDR_TX_PSC_CAL 0x4106
+#define TB_ADDR_TX_PSC_RDY 0x4107
+#define TB_ADDR_RX_PSC_A0 0x8000
+#define TB_ADDR_RX_PSC_A1 0x8001
+#define TB_ADDR_RX_PSC_A2 0x8002
+#define TB_ADDR_RX_PSC_A3 0x8003
+#define TB_ADDR_RX_PSC_CAL 0x8006
+#define TB_ADDR_RX_PSC_RDY 0x8007
+#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 0x4058
+#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
+#define TB_ADDR_RX_SLC_CU_ITER_TMR 0x80e3
+#define TB_ADDR_RX_SIGDET_HL_FILT_TMR 0x8090
+#define TB_ADDR_RX_SAMP_DAC_CTRL 0x8058
+#define TB_ADDR_RX_DIAG_SIGDET_TUNE 0x81dc
+#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 0x81df
+#define TB_ADDR_RX_DIAG_BS_TM 0x81f5
+#define TB_ADDR_RX_DIAG_DFE_CTRL1 0x81d3
+#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 0x81c7
+#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 0x81c2
+#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 0x81c1
+#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 0x81c9
+#define TB_ADDR_RX_DIAG_RXFE_TM3 0x81f8
+#define TB_ADDR_RX_DIAG_RXFE_TM4 0x81f9
+#define TB_ADDR_RX_DIAG_LFPSDET_TUNE 0x81dd
+#define TB_ADDR_RX_DIAG_DFE_CTRL3 0x81d5
+#define TB_ADDR_RX_DIAG_SC2C_DELAY 0x81e1
+#define TB_ADDR_RX_REE_VGA_GAIN_NODFE 0x81bf
+#define TB_ADDR_XCVR_PSM_CAL_TMR 0x4002
+#define TB_ADDR_XCVR_PSM_A0BYP_TMR 0x4004
+#define TB_ADDR_XCVR_PSM_A0IN_TMR 0x4003
+#define TB_ADDR_XCVR_PSM_A1IN_TMR 0x4005
+#define TB_ADDR_XCVR_PSM_A2IN_TMR 0x4006
+#define TB_ADDR_XCVR_PSM_A3IN_TMR 0x4007
+#define TB_ADDR_XCVR_PSM_A4IN_TMR 0x4008
+#define TB_ADDR_XCVR_PSM_A5IN_TMR 0x4009
+#define TB_ADDR_XCVR_PSM_A0OUT_TMR 0x400a
+#define TB_ADDR_XCVR_PSM_A1OUT_TMR 0x400b
+#define TB_ADDR_XCVR_PSM_A2OUT_TMR 0x400c
+#define TB_ADDR_XCVR_PSM_A3OUT_TMR 0x400d
+#define TB_ADDR_XCVR_PSM_A4OUT_TMR 0x400e
+#define TB_ADDR_XCVR_PSM_A5OUT_TMR 0x400f
+#define TB_ADDR_TX_RCVDET_EN_TMR 0x4122
+#define TB_ADDR_TX_RCVDET_ST_TMR 0x4123
+#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
+#define TB_ADDR_TX_RCVDETSC_CTRL 0x4124
+
+/* TB_ADDR_TX_RCVDETSC_CTRL */
+#define RXDET_IN_P3_32KHZ BIT(1)
+
+struct cdns_reg_pairs {
+ u16 val;
+ u32 off;
+};
+
+struct cdns_salvo_data {
+ u8 reg_offset_shift;
+ struct cdns_reg_pairs *init_sequence_val;
+ u8 init_sequence_length;
+};
+
+struct cdns_salvo_phy {
+ struct phy *phy;
+ struct clk *clk;
+ void __iomem *base;
+ struct cdns_salvo_data *data;
+};
+
+static const struct of_device_id cdns_salvo_phy_of_match[];
+static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg)
+{
+ return (u16)readl(salvo_phy->base +
+ reg * (1 << salvo_phy->data->reg_offset_shift));
+}
+
+static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy,
+ u32 reg, u16 val)
+{
+ writel(val, salvo_phy->base +
+ reg * (1 << salvo_phy->data->reg_offset_shift));
+}
+
+/*
+ * Below bringup sequence pair are from Cadence PHY's User Guide
+ * and NXP platform tuning results.
+ */
+static struct cdns_reg_pairs cdns_nxp_sequence_pair[] = {
+ {0x0830, PHY_PMA_CMN_CTRL1},
+ {0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL},
+ {0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR},
+ {0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR},
+ {0x00d0, TB_ADDR_CMN_PLL0_INTDIV},
+ {0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV},
+ {0x0034, TB_ADDR_CMN_PLL0_HIGH_THR},
+ {0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1},
+ {0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2},
+ {0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG},
+ {0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD},
+ {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD},
+ {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD},
+ {0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE},
+ {0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE},
+ {0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG},
+ {0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE},
+ {0x000a, TB_ADDR_CMN_PSM_CLK_CTRL},
+ {0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR},
+ {0xbefc, TB_ADDR_XCVR_PSM_RCTRL},
+
+ {0x7799, TB_ADDR_TX_PSC_A0},
+ {0x7798, TB_ADDR_TX_PSC_A1},
+ {0x509b, TB_ADDR_TX_PSC_A2},
+ {0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD},
+ {0x509b, TB_ADDR_TX_PSC_A3},
+ {0x2090, TB_ADDR_TX_PSC_CAL},
+ {0x2090, TB_ADDR_TX_PSC_RDY},
+
+ {0xA6FD, TB_ADDR_RX_PSC_A0},
+ {0xA6FD, TB_ADDR_RX_PSC_A1},
+ {0xA410, TB_ADDR_RX_PSC_A2},
+ {0x2410, TB_ADDR_RX_PSC_A3},
+
+ {0x23FF, TB_ADDR_RX_PSC_CAL},
+ {0x2010, TB_ADDR_RX_PSC_RDY},
+
+ {0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000},
+ {0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY},
+ {0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR},
+ {0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR},
+ {0x0000, TB_ADDR_RX_SAMP_DAC_CTRL},
+ {0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE},
+ {0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2},
+ {0x0480, TB_ADDR_RX_DIAG_BS_TM},
+ {0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1},
+ {0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4},
+ {0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0},
+ {0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0},
+ {0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6},
+ {0x8000, TB_ADDR_RX_DIAG_RXFE_TM3},
+ {0x0003, TB_ADDR_RX_DIAG_RXFE_TM4},
+ {0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE},
+ {0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3},
+ {0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY},
+ {0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE},
+
+ {0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR},
+ {0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR},
+ {0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR},
+ {0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR},
+ {0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR},
+ {0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR},
+ {0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR},
+ {0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR},
+
+ {0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR},
+ {0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR},
+ {0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR},
+ {0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR},
+ {0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR},
+ {0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR},
+ /* Change rx detect parameter */
+ {0x0960, TB_ADDR_TX_RCVDET_EN_TMR},
+ {0x01e0, TB_ADDR_TX_RCVDET_ST_TMR},
+ {0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR},
+};
+
+
+static int cdns_salvo_phy_power_on(struct phy *phy)
+{
+ struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
+ struct cdns_salvo_data *data = salvo_phy->data;
+ int ret, i;
+ u16 value;
+
+ ret = clk_prepare_enable(salvo_phy->clk);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < data->init_sequence_length; i++) {
+ struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i;
+
+ cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val);
+ }
+
+ /* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
+ value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL);
+ value |= RXDET_IN_P3_32KHZ;
+ cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL,
+ RXDET_IN_P3_32KHZ);
+
+ udelay(10);
+
+ return ret;
+}
+
+static int cdns_salvo_phy_power_off(struct phy *phy)
+{
+ struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
+
+ clk_disable_unprepare(salvo_phy->clk);
+
+ return 0;
+}
+
+static struct phy_ops cdns_salvo_phy_ops = {
+ .power_on = cdns_salvo_phy_power_on,
+ .power_off = cdns_salvo_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int cdns_salvo_phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct cdns_salvo_phy *salvo_phy;
+ struct resource *res;
+ const struct of_device_id *match;
+ struct cdns_salvo_data *data;
+
+ match = of_match_device(cdns_salvo_phy_of_match, dev);
+ if (!match)
+ return -EINVAL;
+
+ data = (struct cdns_salvo_data *)match->data;
+ salvo_phy = devm_kzalloc(dev, sizeof(*salvo_phy), GFP_KERNEL);
+ if (!salvo_phy)
+ return -ENOMEM;
+
+ salvo_phy->data = data;
+ salvo_phy->clk = devm_clk_get_optional(dev, "salvo_phy_clk");
+ if (IS_ERR(salvo_phy->clk))
+ return PTR_ERR(salvo_phy->clk);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ salvo_phy->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(salvo_phy->base))
+ return PTR_ERR(salvo_phy->base);
+
+ salvo_phy->phy = devm_phy_create(dev, NULL, &cdns_salvo_phy_ops);
+ if (IS_ERR(salvo_phy->phy))
+ return PTR_ERR(salvo_phy->phy);
+
+ phy_set_drvdata(salvo_phy->phy, salvo_phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct cdns_salvo_data cdns_nxp_salvo_data = {
+ 2,
+ cdns_nxp_sequence_pair,
+ ARRAY_SIZE(cdns_nxp_sequence_pair),
+};
+
+static const struct of_device_id cdns_salvo_phy_of_match[] = {
+ {
+ .compatible = "nxp,salvo-phy",
+ .data = &cdns_nxp_salvo_data,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, cdns_salvo_phy_of_match);
+
+static struct platform_driver cdns_salvo_phy_driver = {
+ .probe = cdns_salvo_phy_probe,
+ .driver = {
+ .name = "cdns-salvo-phy",
+ .of_match_table = cdns_salvo_phy_of_match,
+ }
+};
+module_platform_driver(cdns_salvo_phy_driver);
+
+MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Cadence SALVO PHY Driver");
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc
2020-02-27 6:27 [PATCH 1/2] phy: cadence: salvo: add salvo phy driver Peter Chen
@ 2020-02-27 6:27 ` Peter Chen
2020-02-27 17:08 ` Rob Herring
2020-03-12 10:16 ` [PATCH 1/2] phy: cadence: salvo: add salvo phy driver Peter Chen
1 sibling, 1 reply; 10+ messages in thread
From: Peter Chen @ 2020-02-27 6:27 UTC (permalink / raw)
To: kishon, robh+dt
Cc: linux-usb, linux-imx, aniljoy, jun.li, devicetree, Peter Chen
Add Cadence SALVO PHY binding doc, this PHY is a lagacy module,
and is only used for USB3 and USB2.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
---
.../bindings/phy/cdns,salvo-phy.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml b/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
new file mode 100644
index 000000000000..f829f44c5e33
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2020 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence SALVO PHY
+
+maintainers:
+ - Peter Chen <peter.chen@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - nxp,salvo-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: salvo_phy_clk
+
+ "#phy-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ usb3phy: usb3-phy {
+ compatible = "nxp,salvo-phy";
+ reg = <0x5B160000 0x40000>;
+ clocks = <&usb3_lpcg 4>;
+ clock-names = "salvo_phy_clk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ #phy-cells = <0>;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc
2020-02-27 6:27 ` [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc Peter Chen
@ 2020-02-27 17:08 ` Rob Herring
2020-02-28 9:29 ` Peter Chen
0 siblings, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-02-27 17:08 UTC (permalink / raw)
To: Peter Chen
Cc: kishon, robh+dt, linux-usb, linux-imx, aniljoy, jun.li,
devicetree, Peter Chen
On Thu, 27 Feb 2020 14:27:54 +0800, Peter Chen wrote:
> Add Cadence SALVO PHY binding doc, this PHY is a lagacy module,
> and is only used for USB3 and USB2.
>
> Signed-off-by: Peter Chen <peter.chen@nxp.com>
> ---
> .../bindings/phy/cdns,salvo-phy.yaml | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
warning: no schema found in file: Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: ignoring, error parsing file
Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: while scanning a block scalar
in "<unicode string>", line 39, column 5
found a tab character where an indentation space is expected
in "<unicode string>", line 41, column 1
Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts] Error 1
Makefile:1263: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1245562
Please check and re-submit.
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc
2020-02-27 17:08 ` Rob Herring
@ 2020-02-28 9:29 ` Peter Chen
2020-02-28 13:37 ` Rob Herring
0 siblings, 1 reply; 10+ messages in thread
From: Peter Chen @ 2020-02-28 9:29 UTC (permalink / raw)
To: Rob Herring
Cc: kishon, robh+dt, linux-usb, dl-linux-imx, aniljoy, Jun Li, devicetree
> > .../bindings/phy/cdns,salvo-phy.yaml | 47 +++++++++++++++++++
> > 1 file changed, 47 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> >
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> warning: no schema found in file:
> Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: ignoring, error
> parsing file
> Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-
> 37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be
> at root node
> Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: while scanning a
> block scalar
> in "<unicode string>", line 39, column 5 found a tab character where an indentation
> space is expected
> in "<unicode string>", line 41, column 1
> Documentation/devicetree/bindings/Makefile:12: recipe for target
> 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
> make[1]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts]
> Error 1
> Makefile:1263: recipe for target 'dt_binding_check' failed
> make: *** [dt_binding_check] Error 2
>
Hi Rob,
After changing some format, I still got below errors, would you please point to
what's wrong with line 40, column 12? Thanks.
31 required:
32 - compatible
33 - reg
34 - "#phy-cells"
35
36 additionalProperties: false
37
38 examples:
39 -|
40 usb3phy: usb3-phy {
41 compatible = "nxp,salvo-phy";
42 reg = <0x5B160000 0x40000>;
43 clocks = <&usb3_lpcg 4>;
44 clock-names = "salvo_phy_clk";
45 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
46 #phy-cells = <0>;
47 };
make[1]: Entering directory '/home/b29397/work/projects/upstream/usb/outout/imx_v8'
CHKDT Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
/home/b29397/work/projects/upstream/usb/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: mapping values are not allowed in this context
in "<unicode string>", line 40, column 12
/home/b29397/work/projects/upstream/usb/Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
make[2]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts] Error 1
/home/b29397/work/projects/upstream/usb/Makefile:1262: recipe for target 'dt_binding_check' failed
make[1]: *** [dt_binding_check] Error 2
make[1]: Leaving directory '/home/b29397/work/projects/upstream/usb/outout/imx_v8'
Makefile:179: recipe for target 'sub-make' failed
make: *** [sub-make] Error 2
Peter
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc
2020-02-28 9:29 ` Peter Chen
@ 2020-02-28 13:37 ` Rob Herring
2020-03-02 2:58 ` Peter Chen
0 siblings, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-02-28 13:37 UTC (permalink / raw)
To: Peter Chen; +Cc: kishon, linux-usb, dl-linux-imx, aniljoy, Jun Li, devicetree
On Fri, Feb 28, 2020 at 3:29 AM Peter Chen <peter.chen@nxp.com> wrote:
>
>
> > > .../bindings/phy/cdns,salvo-phy.yaml | 47 +++++++++++++++++++
> > > 1 file changed, 47 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> > >
> >
> > My bot found errors running 'make dt_binding_check' on your patch:
> >
> > warning: no schema found in file:
> > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> > /builds/robherring/linux-dt-
> > review/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: ignoring, error
> > parsing file
> > Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-
> > 37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be
> > at root node
> > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: while scanning a
> > block scalar
> > in "<unicode string>", line 39, column 5 found a tab character where an indentation
> > space is expected
> > in "<unicode string>", line 41, column 1
> > Documentation/devicetree/bindings/Makefile:12: recipe for target
> > 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
> > make[1]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts]
> > Error 1
> > Makefile:1263: recipe for target 'dt_binding_check' failed
> > make: *** [dt_binding_check] Error 2
> >
> Hi Rob,
>
> After changing some format, I still got below errors, would you please point to
> what's wrong with line 40, column 12? Thanks.
It is line numbers of the generated .example.dts you need to look at.
>
> 31 required:
> 32 - compatible
> 33 - reg
> 34 - "#phy-cells"
> 35
> 36 additionalProperties: false
> 37
> 38 examples:
> 39 -|
> 40 usb3phy: usb3-phy {
Needs a unit address.
> 41 compatible = "nxp,salvo-phy";
> 42 reg = <0x5B160000 0x40000>;
> 43 clocks = <&usb3_lpcg 4>;
> 44 clock-names = "salvo_phy_clk";
> 45 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
Need to include the header for this define.
> 46 #phy-cells = <0>;
> 47 };
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc
2020-02-28 13:37 ` Rob Herring
@ 2020-03-02 2:58 ` Peter Chen
2020-03-02 16:14 ` Rob Herring
0 siblings, 1 reply; 10+ messages in thread
From: Peter Chen @ 2020-03-02 2:58 UTC (permalink / raw)
To: Rob Herring; +Cc: kishon, linux-usb, dl-linux-imx, aniljoy, Jun Li, devicetree
On 20-02-28 07:37:14, Rob Herring wrote:
> On Fri, Feb 28, 2020 at 3:29 AM Peter Chen <peter.chen@nxp.com> wrote:
> >
> >
> > > > .../bindings/phy/cdns,salvo-phy.yaml | 47 +++++++++++++++++++
> > > > 1 file changed, 47 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> > > >
> > >
> > > My bot found errors running 'make dt_binding_check' on your patch:
> > >
> > > warning: no schema found in file:
> > > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> > > /builds/robherring/linux-dt-
> > > review/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: ignoring, error
> > > parsing file
> > > Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-
> > > 37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be
> > > at root node
> > > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: while scanning a
> > > block scalar
> > > in "<unicode string>", line 39, column 5 found a tab character where an indentation
> > > space is expected
> > > in "<unicode string>", line 41, column 1
> > > Documentation/devicetree/bindings/Makefile:12: recipe for target
> > > 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
> > > make[1]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts]
> > > Error 1
> > > Makefile:1263: recipe for target 'dt_binding_check' failed
> > > make: *** [dt_binding_check] Error 2
> > >
> > Hi Rob,
> >
> > After changing some format, I still got below errors, would you please point to
> > what's wrong with line 40, column 12? Thanks.
>
> It is line numbers of the generated .example.dts you need to look at.
There is no cdns,salvo-phy.example.dts file at both source folder or
obj (-O) folder. I use https://github.com/robherring/dt-schema to
create dt-doc-validate. The command I use to verify yaml file:
make O=$OUTKNL dt_binding_check, OUTKNL is my kernel obj folder.
I am sorry I get below error:
make[1]: Entering directory '/home/b29397/work/projects/upstream/usb/outout/imx_v8'
CHKDT Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
/home/b29397/work/projects/upstream/usb/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: while parsing a block mapping
in "<unicode string>", line 5, column 1
did not find expected key
in "<unicode string>", line 42, column 5
/home/b29397/work/projects/upstream/usb/Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
make[2]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts] Error 1
/home/b29397/work/projects/upstream/usb/Makefile:1262: recipe for target 'dt_binding_check' failed
make[1]: *** [dt_binding_check] Error 2
make[1]: Leaving directory '/home/b29397/work/projects/upstream/usb/outout/imx_v8'
Makefile:179: recipe for target 'sub-make' failed
make: *** [sub-make] Error 2
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (c) 2020 NXP
3 %YAML 1.2
4 ---
5 $id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8 title: Cadence SALVO PHY
9
10 maintainers:
11 - Peter Chen <peter.chen@nxp.com>
12
13 properties:
14 compatible:
15 enum:
16 - nxp,salvo-phy
17
18 reg:
19 maxItems: 1
20
21 clocks:
22 maxItems: 1
23
24 clock-names:
25 items:
26 - const: salvo_phy_clk
27
28 "#phy-cells":
29 const: 1
30
31 required:
32 - compatible
33 - reg
34 - "#phy-cells"
35
36 additionalProperties: false
37
38 examples:
39 -|
40 #include <dt-bindings/firmware/imx/rsrc.h>
41
42 usb3phy: usb3-phy@5B160000 {
43 compatible = "nxp,salvo-phy";
44 reg = <0x5B160000 0x40000>;
45 clocks = <&usb3_lpcg 4>;
46 clock-names = "salvo_phy_clk";
47 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
48 #phy-cells = <0>;
49 };
--
Thanks,
Peter Chen
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc
2020-03-02 2:58 ` Peter Chen
@ 2020-03-02 16:14 ` Rob Herring
2020-03-03 9:23 ` Peter Chen
0 siblings, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-03-02 16:14 UTC (permalink / raw)
To: Peter Chen; +Cc: kishon, linux-usb, dl-linux-imx, aniljoy, Jun Li, devicetree
On Sun, Mar 1, 2020 at 8:58 PM Peter Chen <peter.chen@nxp.com> wrote:
>
> On 20-02-28 07:37:14, Rob Herring wrote:
> > On Fri, Feb 28, 2020 at 3:29 AM Peter Chen <peter.chen@nxp.com> wrote:
> > >
> > >
> > > > > .../bindings/phy/cdns,salvo-phy.yaml | 47 +++++++++++++++++++
> > > > > 1 file changed, 47 insertions(+)
> > > > > create mode 100644
> > > > > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> > > > >
> > > >
> > > > My bot found errors running 'make dt_binding_check' on your patch:
> > > >
> > > > warning: no schema found in file:
> > > > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> > > > /builds/robherring/linux-dt-
> > > > review/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: ignoring, error
> > > > parsing file
> > > > Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-
> > > > 37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be
> > > > at root node
> > > > Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: while scanning a
> > > > block scalar
> > > > in "<unicode string>", line 39, column 5 found a tab character where an indentation
> > > > space is expected
> > > > in "<unicode string>", line 41, column 1
> > > > Documentation/devicetree/bindings/Makefile:12: recipe for target
> > > > 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
> > > > make[1]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts]
> > > > Error 1
> > > > Makefile:1263: recipe for target 'dt_binding_check' failed
> > > > make: *** [dt_binding_check] Error 2
> > > >
> > > Hi Rob,
> > >
> > > After changing some format, I still got below errors, would you please point to
> > > what's wrong with line 40, column 12? Thanks.
> >
> > It is line numbers of the generated .example.dts you need to look at.
Sorry, it is the schema file line numbers.
> There is no cdns,salvo-phy.example.dts file at both source folder or
Because there's an error in the schema file.
> obj (-O) folder. I use https://github.com/robherring/dt-schema to
> create dt-doc-validate. The command I use to verify yaml file:
> make O=$OUTKNL dt_binding_check, OUTKNL is my kernel obj folder.
>
> I am sorry I get below error:
>
> make[1]: Entering directory '/home/b29397/work/projects/upstream/usb/outout/imx_v8'
> CHKDT Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
> /home/b29397/work/projects/upstream/usb/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml: while parsing a block mapping
> in "<unicode string>", line 5, column 1
> did not find expected key
> in "<unicode string>", line 42, column 5
> /home/b29397/work/projects/upstream/usb/Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts' failed
> make[2]: *** [Documentation/devicetree/bindings/phy/cdns,salvo-phy.example.dts] Error 1
> /home/b29397/work/projects/upstream/usb/Makefile:1262: recipe for target 'dt_binding_check' failed
> make[1]: *** [dt_binding_check] Error 2
> make[1]: Leaving directory '/home/b29397/work/projects/upstream/usb/outout/imx_v8'
> Makefile:179: recipe for target 'sub-make' failed
> make: *** [sub-make] Error 2
>
> 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> 2 # Copyright (c) 2020 NXP
> 3 %YAML 1.2
> 4 ---
> 5 $id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
> 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
> 7
> 8 title: Cadence SALVO PHY
> 9
> 10 maintainers:
> 11 - Peter Chen <peter.chen@nxp.com>
> 12
> 13 properties:
> 14 compatible:
> 15 enum:
> 16 - nxp,salvo-phy
> 17
> 18 reg:
> 19 maxItems: 1
> 20
> 21 clocks:
> 22 maxItems: 1
> 23
> 24 clock-names:
> 25 items:
> 26 - const: salvo_phy_clk
> 27
> 28 "#phy-cells":
> 29 const: 1
> 30
> 31 required:
> 32 - compatible
> 33 - reg
> 34 - "#phy-cells"
> 35
> 36 additionalProperties: false
> 37
> 38 examples:
> 39 -|
The indentation is wrong here. It should be 2 spaces, not 4. What
follows has to be indented more than the above line. Indentation is
how the end of the block is found.
> 40 #include <dt-bindings/firmware/imx/rsrc.h>
> 41
> 42 usb3phy: usb3-phy@5B160000 {
> 43 compatible = "nxp,salvo-phy";
> 44 reg = <0x5B160000 0x40000>;
> 45 clocks = <&usb3_lpcg 4>;
> 46 clock-names = "salvo_phy_clk";
> 47 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
> 48 #phy-cells = <0>;
> 49 };
>
>
> --
>
> Thanks,
> Peter Chen
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc
2020-03-02 16:14 ` Rob Herring
@ 2020-03-03 9:23 ` Peter Chen
0 siblings, 0 replies; 10+ messages in thread
From: Peter Chen @ 2020-03-03 9:23 UTC (permalink / raw)
To: Rob Herring; +Cc: kishon, linux-usb, dl-linux-imx, aniljoy, Jun Li, devicetree
> > 38 examples:
> > 39 -|
>
> The indentation is wrong here. It should be 2 spaces, not 4. What follows has to be
> indented more than the above line. Indentation is how the end of the block is found.
>
> > 40 #include <dt-bindings/firmware/imx/rsrc.h>
> > 41
> > 42 usb3phy: usb3-phy@5B160000 {
> > 43 compatible = "nxp,salvo-phy";
> > 44 reg = <0x5B160000 0x40000>;
> > 45 clocks = <&usb3_lpcg 4>;
> > 46 clock-names = "salvo_phy_clk";
> > 47 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
> > 48 #phy-cells = <0>;
> > 49 };
Thanks, Rob, I fixed it. I will send v2 after driver review finishes.
Peter
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 1/2] phy: cadence: salvo: add salvo phy driver
2020-02-27 6:27 [PATCH 1/2] phy: cadence: salvo: add salvo phy driver Peter Chen
2020-02-27 6:27 ` [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc Peter Chen
@ 2020-03-12 10:16 ` Peter Chen
2020-03-13 11:15 ` Kishon Vijay Abraham I
1 sibling, 1 reply; 10+ messages in thread
From: Peter Chen @ 2020-03-12 10:16 UTC (permalink / raw)
To: kishon, robh+dt; +Cc: linux-usb, dl-linux-imx, aniljoy, Jun Li, devicetree
>
> Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2.
> According to the Cadence, this PHY is a legacy Module, and Sierra and Torrent are
> later evolutions from it, and their sequence overlap is minimal, meaning we cannot
> reuse either (Sierra & Torrent) of the PHY drivers.
>
> Signed-off-by: Peter Chen <peter.chen@nxp.com>
A gentle ping...
Peter
> ---
> drivers/phy/cadence/Kconfig | 9 +
> drivers/phy/cadence/Makefile | 1 +
> drivers/phy/cadence/phy-cadence-salvo.c | 316 ++++++++++++++++++++++++
> 3 files changed, 326 insertions(+)
> create mode 100644 drivers/phy/cadence/phy-cadence-salvo.c
>
> diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index
> b2db916db64b..eca272b227b7 100644
> --- a/drivers/phy/cadence/Kconfig
> +++ b/drivers/phy/cadence/Kconfig
> @@ -27,3 +27,12 @@ config PHY_CADENCE_SIERRA
> select GENERIC_PHY
> help
> Enable this to support the Cadence Sierra PHY driver
> +
> +config PHY_CADENCE_SALVO
> + tristate "Cadence Salvo PHY Driver"
> + depends on OF && HAS_IOMEM
> + select GENERIC_PHY
> + help
> + Enable this to support the Cadence SALVO PHY driver,
> + this PHY is a legacy PHY, and only are used for USB3
> + and USB2.
> diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index
> 8f89560f1711..7c7d13c0c647 100644
> --- a/drivers/phy/cadence/Makefile
> +++ b/drivers/phy/cadence/Makefile
> @@ -2,3 +2,4 @@
> obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
> obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
> obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
> +obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o
> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-
> cadence-salvo.c
> new file mode 100644
> index 000000000000..fa666527356d
> --- /dev/null
> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
> @@ -0,0 +1,316 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Salvo PHY is a 28nm PHY, it is a legacy PHY, and only
> + * for USB3 and USB2.
> + *
> + * Copyright (c) 2019-2020 NXP
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +/* PHY register definition */
> +#define PHY_PMA_CMN_CTRL1 0xC800
> +#define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
> +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
> +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
> +#define TB_ADDR_CMN_PLL0_INTDIV 0x0094
> +#define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
> +#define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
> +#define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
> +#define TB_ADDR_CMN_PLL0_SS_CTRL2 0x0099
> +#define TB_ADDR_CMN_PLL0_DSM_DIAG 0x0097
> +#define TB_ADDR_CMN_DIAG_PLL0_OVRD 0x01c2
> +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD 0x01c0
> +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD 0x01c1
> +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE 0x01C5
> +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE 0x01C6
> +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG 0x01C7
> +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE 0x01c4
> +#define TB_ADDR_CMN_PSM_CLK_CTRL 0x0061
> +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR 0x40ea
> +#define TB_ADDR_XCVR_PSM_RCTRL 0x4001
> +#define TB_ADDR_TX_PSC_A0 0x4100
> +#define TB_ADDR_TX_PSC_A1 0x4101
> +#define TB_ADDR_TX_PSC_A2 0x4102
> +#define TB_ADDR_TX_PSC_A3 0x4103
> +#define TB_ADDR_TX_DIAG_ECTRL_OVRD 0x41f5
> +#define TB_ADDR_TX_PSC_CAL 0x4106
> +#define TB_ADDR_TX_PSC_RDY 0x4107
> +#define TB_ADDR_RX_PSC_A0 0x8000
> +#define TB_ADDR_RX_PSC_A1 0x8001
> +#define TB_ADDR_RX_PSC_A2 0x8002
> +#define TB_ADDR_RX_PSC_A3 0x8003
> +#define TB_ADDR_RX_PSC_CAL 0x8006
> +#define TB_ADDR_RX_PSC_RDY 0x8007
> +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 0x4058
> +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
> +#define TB_ADDR_RX_SLC_CU_ITER_TMR 0x80e3
> +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR 0x8090
> +#define TB_ADDR_RX_SAMP_DAC_CTRL 0x8058
> +#define TB_ADDR_RX_DIAG_SIGDET_TUNE 0x81dc
> +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 0x81df
> +#define TB_ADDR_RX_DIAG_BS_TM 0x81f5
> +#define TB_ADDR_RX_DIAG_DFE_CTRL1 0x81d3
> +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 0x81c7
> +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 0x81c2
> +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 0x81c1
> +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 0x81c9
> +#define TB_ADDR_RX_DIAG_RXFE_TM3 0x81f8
> +#define TB_ADDR_RX_DIAG_RXFE_TM4 0x81f9
> +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE 0x81dd
> +#define TB_ADDR_RX_DIAG_DFE_CTRL3 0x81d5
> +#define TB_ADDR_RX_DIAG_SC2C_DELAY 0x81e1
> +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE 0x81bf
> +#define TB_ADDR_XCVR_PSM_CAL_TMR 0x4002
> +#define TB_ADDR_XCVR_PSM_A0BYP_TMR 0x4004
> +#define TB_ADDR_XCVR_PSM_A0IN_TMR 0x4003
> +#define TB_ADDR_XCVR_PSM_A1IN_TMR 0x4005
> +#define TB_ADDR_XCVR_PSM_A2IN_TMR 0x4006
> +#define TB_ADDR_XCVR_PSM_A3IN_TMR 0x4007
> +#define TB_ADDR_XCVR_PSM_A4IN_TMR 0x4008
> +#define TB_ADDR_XCVR_PSM_A5IN_TMR 0x4009
> +#define TB_ADDR_XCVR_PSM_A0OUT_TMR 0x400a
> +#define TB_ADDR_XCVR_PSM_A1OUT_TMR 0x400b
> +#define TB_ADDR_XCVR_PSM_A2OUT_TMR 0x400c
> +#define TB_ADDR_XCVR_PSM_A3OUT_TMR 0x400d
> +#define TB_ADDR_XCVR_PSM_A4OUT_TMR 0x400e
> +#define TB_ADDR_XCVR_PSM_A5OUT_TMR 0x400f
> +#define TB_ADDR_TX_RCVDET_EN_TMR 0x4122
> +#define TB_ADDR_TX_RCVDET_ST_TMR 0x4123
> +#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
> +#define TB_ADDR_TX_RCVDETSC_CTRL 0x4124
> +
> +/* TB_ADDR_TX_RCVDETSC_CTRL */
> +#define RXDET_IN_P3_32KHZ BIT(1)
> +
> +struct cdns_reg_pairs {
> + u16 val;
> + u32 off;
> +};
> +
> +struct cdns_salvo_data {
> + u8 reg_offset_shift;
> + struct cdns_reg_pairs *init_sequence_val;
> + u8 init_sequence_length;
> +};
> +
> +struct cdns_salvo_phy {
> + struct phy *phy;
> + struct clk *clk;
> + void __iomem *base;
> + struct cdns_salvo_data *data;
> +};
> +
> +static const struct of_device_id cdns_salvo_phy_of_match[]; static u16
> +cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg) {
> + return (u16)readl(salvo_phy->base +
> + reg * (1 << salvo_phy->data->reg_offset_shift));
> +}
> +
> +static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy,
> + u32 reg, u16 val)
> +{
> + writel(val, salvo_phy->base +
> + reg * (1 << salvo_phy->data->reg_offset_shift));
> +}
> +
> +/*
> + * Below bringup sequence pair are from Cadence PHY's User Guide
> + * and NXP platform tuning results.
> + */
> +static struct cdns_reg_pairs cdns_nxp_sequence_pair[] = {
> + {0x0830, PHY_PMA_CMN_CTRL1},
> + {0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL},
> + {0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR},
> + {0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR},
> + {0x00d0, TB_ADDR_CMN_PLL0_INTDIV},
> + {0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV},
> + {0x0034, TB_ADDR_CMN_PLL0_HIGH_THR},
> + {0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1},
> + {0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2},
> + {0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG},
> + {0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD},
> + {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD},
> + {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD},
> + {0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE},
> + {0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE},
> + {0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG},
> + {0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE},
> + {0x000a, TB_ADDR_CMN_PSM_CLK_CTRL},
> + {0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR},
> + {0xbefc, TB_ADDR_XCVR_PSM_RCTRL},
> +
> + {0x7799, TB_ADDR_TX_PSC_A0},
> + {0x7798, TB_ADDR_TX_PSC_A1},
> + {0x509b, TB_ADDR_TX_PSC_A2},
> + {0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD},
> + {0x509b, TB_ADDR_TX_PSC_A3},
> + {0x2090, TB_ADDR_TX_PSC_CAL},
> + {0x2090, TB_ADDR_TX_PSC_RDY},
> +
> + {0xA6FD, TB_ADDR_RX_PSC_A0},
> + {0xA6FD, TB_ADDR_RX_PSC_A1},
> + {0xA410, TB_ADDR_RX_PSC_A2},
> + {0x2410, TB_ADDR_RX_PSC_A3},
> +
> + {0x23FF, TB_ADDR_RX_PSC_CAL},
> + {0x2010, TB_ADDR_RX_PSC_RDY},
> +
> + {0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000},
> + {0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY},
> + {0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR},
> + {0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR},
> + {0x0000, TB_ADDR_RX_SAMP_DAC_CTRL},
> + {0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE},
> + {0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2},
> + {0x0480, TB_ADDR_RX_DIAG_BS_TM},
> + {0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1},
> + {0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4},
> + {0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0},
> + {0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0},
> + {0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6},
> + {0x8000, TB_ADDR_RX_DIAG_RXFE_TM3},
> + {0x0003, TB_ADDR_RX_DIAG_RXFE_TM4},
> + {0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE},
> + {0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3},
> + {0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY},
> + {0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE},
> +
> + {0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR},
> + {0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR},
> + {0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR},
> + {0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR},
> + {0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR},
> + {0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR},
> + {0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR},
> + {0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR},
> +
> + {0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR},
> + {0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR},
> + {0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR},
> + {0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR},
> + {0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR},
> + {0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR},
> + /* Change rx detect parameter */
> + {0x0960, TB_ADDR_TX_RCVDET_EN_TMR},
> + {0x01e0, TB_ADDR_TX_RCVDET_ST_TMR},
> + {0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR},
> +};
> +
> +
> +static int cdns_salvo_phy_power_on(struct phy *phy) {
> + struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
> + struct cdns_salvo_data *data = salvo_phy->data;
> + int ret, i;
> + u16 value;
> +
> + ret = clk_prepare_enable(salvo_phy->clk);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < data->init_sequence_length; i++) {
> + struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i;
> +
> + cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val);
> + }
> +
> + /* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
> + value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL);
> + value |= RXDET_IN_P3_32KHZ;
> + cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL,
> + RXDET_IN_P3_32KHZ);
> +
> + udelay(10);
> +
> + return ret;
> +}
> +
> +static int cdns_salvo_phy_power_off(struct phy *phy) {
> + struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
> +
> + clk_disable_unprepare(salvo_phy->clk);
> +
> + return 0;
> +}
> +
> +static struct phy_ops cdns_salvo_phy_ops = {
> + .power_on = cdns_salvo_phy_power_on,
> + .power_off = cdns_salvo_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int cdns_salvo_phy_probe(struct platform_device *pdev) {
> + struct phy_provider *phy_provider;
> + struct device *dev = &pdev->dev;
> + struct cdns_salvo_phy *salvo_phy;
> + struct resource *res;
> + const struct of_device_id *match;
> + struct cdns_salvo_data *data;
> +
> + match = of_match_device(cdns_salvo_phy_of_match, dev);
> + if (!match)
> + return -EINVAL;
> +
> + data = (struct cdns_salvo_data *)match->data;
> + salvo_phy = devm_kzalloc(dev, sizeof(*salvo_phy), GFP_KERNEL);
> + if (!salvo_phy)
> + return -ENOMEM;
> +
> + salvo_phy->data = data;
> + salvo_phy->clk = devm_clk_get_optional(dev, "salvo_phy_clk");
> + if (IS_ERR(salvo_phy->clk))
> + return PTR_ERR(salvo_phy->clk);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + salvo_phy->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(salvo_phy->base))
> + return PTR_ERR(salvo_phy->base);
> +
> + salvo_phy->phy = devm_phy_create(dev, NULL, &cdns_salvo_phy_ops);
> + if (IS_ERR(salvo_phy->phy))
> + return PTR_ERR(salvo_phy->phy);
> +
> + phy_set_drvdata(salvo_phy->phy, salvo_phy);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct cdns_salvo_data cdns_nxp_salvo_data = {
> + 2,
> + cdns_nxp_sequence_pair,
> + ARRAY_SIZE(cdns_nxp_sequence_pair),
> +};
> +
> +static const struct of_device_id cdns_salvo_phy_of_match[] = {
> + {
> + .compatible = "nxp,salvo-phy",
> + .data = &cdns_nxp_salvo_data,
> + },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, cdns_salvo_phy_of_match);
> +
> +static struct platform_driver cdns_salvo_phy_driver = {
> + .probe = cdns_salvo_phy_probe,
> + .driver = {
> + .name = "cdns-salvo-phy",
> + .of_match_table = cdns_salvo_phy_of_match,
> + }
> +};
> +module_platform_driver(cdns_salvo_phy_driver);
> +
> +MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>");
> MODULE_LICENSE("GPL
> +v2"); MODULE_DESCRIPTION("Cadence SALVO PHY Driver");
> --
> 2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] phy: cadence: salvo: add salvo phy driver
2020-03-12 10:16 ` [PATCH 1/2] phy: cadence: salvo: add salvo phy driver Peter Chen
@ 2020-03-13 11:15 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-03-13 11:15 UTC (permalink / raw)
To: Peter Chen, robh+dt; +Cc: linux-usb, dl-linux-imx, aniljoy, Jun Li, devicetree
Hi Peter,
On 12/03/20 3:46 pm, Peter Chen wrote:
>
>>
>> Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2.
>> According to the Cadence, this PHY is a legacy Module, and Sierra and Torrent are
>> later evolutions from it, and their sequence overlap is minimal, meaning we cannot
>> reuse either (Sierra & Torrent) of the PHY drivers.
>>
>> Signed-off-by: Peter Chen <peter.chen@nxp.com>
>
> A gentle ping...
I need Ack from Rob on the dt-binding to merge this.
Thanks
Kishon
>
> Peter
>
>> ---
>> drivers/phy/cadence/Kconfig | 9 +
>> drivers/phy/cadence/Makefile | 1 +
>> drivers/phy/cadence/phy-cadence-salvo.c | 316 ++++++++++++++++++++++++
>> 3 files changed, 326 insertions(+)
>> create mode 100644 drivers/phy/cadence/phy-cadence-salvo.c
>>
>> diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index
>> b2db916db64b..eca272b227b7 100644
>> --- a/drivers/phy/cadence/Kconfig
>> +++ b/drivers/phy/cadence/Kconfig
>> @@ -27,3 +27,12 @@ config PHY_CADENCE_SIERRA
>> select GENERIC_PHY
>> help
>> Enable this to support the Cadence Sierra PHY driver
>> +
>> +config PHY_CADENCE_SALVO
>> + tristate "Cadence Salvo PHY Driver"
>> + depends on OF && HAS_IOMEM
>> + select GENERIC_PHY
>> + help
>> + Enable this to support the Cadence SALVO PHY driver,
>> + this PHY is a legacy PHY, and only are used for USB3
>> + and USB2.
>> diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index
>> 8f89560f1711..7c7d13c0c647 100644
>> --- a/drivers/phy/cadence/Makefile
>> +++ b/drivers/phy/cadence/Makefile
>> @@ -2,3 +2,4 @@
>> obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
>> obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
>> obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
>> +obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o
>> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-
>> cadence-salvo.c
>> new file mode 100644
>> index 000000000000..fa666527356d
>> --- /dev/null
>> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
>> @@ -0,0 +1,316 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Salvo PHY is a 28nm PHY, it is a legacy PHY, and only
>> + * for USB3 and USB2.
>> + *
>> + * Copyright (c) 2019-2020 NXP
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/delay.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +
>> +/* PHY register definition */
>> +#define PHY_PMA_CMN_CTRL1 0xC800
>> +#define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
>> +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
>> +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
>> +#define TB_ADDR_CMN_PLL0_INTDIV 0x0094
>> +#define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
>> +#define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
>> +#define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
>> +#define TB_ADDR_CMN_PLL0_SS_CTRL2 0x0099
>> +#define TB_ADDR_CMN_PLL0_DSM_DIAG 0x0097
>> +#define TB_ADDR_CMN_DIAG_PLL0_OVRD 0x01c2
>> +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD 0x01c0
>> +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD 0x01c1
>> +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE 0x01C5
>> +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE 0x01C6
>> +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG 0x01C7
>> +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE 0x01c4
>> +#define TB_ADDR_CMN_PSM_CLK_CTRL 0x0061
>> +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR 0x40ea
>> +#define TB_ADDR_XCVR_PSM_RCTRL 0x4001
>> +#define TB_ADDR_TX_PSC_A0 0x4100
>> +#define TB_ADDR_TX_PSC_A1 0x4101
>> +#define TB_ADDR_TX_PSC_A2 0x4102
>> +#define TB_ADDR_TX_PSC_A3 0x4103
>> +#define TB_ADDR_TX_DIAG_ECTRL_OVRD 0x41f5
>> +#define TB_ADDR_TX_PSC_CAL 0x4106
>> +#define TB_ADDR_TX_PSC_RDY 0x4107
>> +#define TB_ADDR_RX_PSC_A0 0x8000
>> +#define TB_ADDR_RX_PSC_A1 0x8001
>> +#define TB_ADDR_RX_PSC_A2 0x8002
>> +#define TB_ADDR_RX_PSC_A3 0x8003
>> +#define TB_ADDR_RX_PSC_CAL 0x8006
>> +#define TB_ADDR_RX_PSC_RDY 0x8007
>> +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 0x4058
>> +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
>> +#define TB_ADDR_RX_SLC_CU_ITER_TMR 0x80e3
>> +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR 0x8090
>> +#define TB_ADDR_RX_SAMP_DAC_CTRL 0x8058
>> +#define TB_ADDR_RX_DIAG_SIGDET_TUNE 0x81dc
>> +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 0x81df
>> +#define TB_ADDR_RX_DIAG_BS_TM 0x81f5
>> +#define TB_ADDR_RX_DIAG_DFE_CTRL1 0x81d3
>> +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 0x81c7
>> +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 0x81c2
>> +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 0x81c1
>> +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 0x81c9
>> +#define TB_ADDR_RX_DIAG_RXFE_TM3 0x81f8
>> +#define TB_ADDR_RX_DIAG_RXFE_TM4 0x81f9
>> +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE 0x81dd
>> +#define TB_ADDR_RX_DIAG_DFE_CTRL3 0x81d5
>> +#define TB_ADDR_RX_DIAG_SC2C_DELAY 0x81e1
>> +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE 0x81bf
>> +#define TB_ADDR_XCVR_PSM_CAL_TMR 0x4002
>> +#define TB_ADDR_XCVR_PSM_A0BYP_TMR 0x4004
>> +#define TB_ADDR_XCVR_PSM_A0IN_TMR 0x4003
>> +#define TB_ADDR_XCVR_PSM_A1IN_TMR 0x4005
>> +#define TB_ADDR_XCVR_PSM_A2IN_TMR 0x4006
>> +#define TB_ADDR_XCVR_PSM_A3IN_TMR 0x4007
>> +#define TB_ADDR_XCVR_PSM_A4IN_TMR 0x4008
>> +#define TB_ADDR_XCVR_PSM_A5IN_TMR 0x4009
>> +#define TB_ADDR_XCVR_PSM_A0OUT_TMR 0x400a
>> +#define TB_ADDR_XCVR_PSM_A1OUT_TMR 0x400b
>> +#define TB_ADDR_XCVR_PSM_A2OUT_TMR 0x400c
>> +#define TB_ADDR_XCVR_PSM_A3OUT_TMR 0x400d
>> +#define TB_ADDR_XCVR_PSM_A4OUT_TMR 0x400e
>> +#define TB_ADDR_XCVR_PSM_A5OUT_TMR 0x400f
>> +#define TB_ADDR_TX_RCVDET_EN_TMR 0x4122
>> +#define TB_ADDR_TX_RCVDET_ST_TMR 0x4123
>> +#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
>> +#define TB_ADDR_TX_RCVDETSC_CTRL 0x4124
>> +
>> +/* TB_ADDR_TX_RCVDETSC_CTRL */
>> +#define RXDET_IN_P3_32KHZ BIT(1)
>> +
>> +struct cdns_reg_pairs {
>> + u16 val;
>> + u32 off;
>> +};
>> +
>> +struct cdns_salvo_data {
>> + u8 reg_offset_shift;
>> + struct cdns_reg_pairs *init_sequence_val;
>> + u8 init_sequence_length;
>> +};
>> +
>> +struct cdns_salvo_phy {
>> + struct phy *phy;
>> + struct clk *clk;
>> + void __iomem *base;
>> + struct cdns_salvo_data *data;
>> +};
>> +
>> +static const struct of_device_id cdns_salvo_phy_of_match[]; static u16
>> +cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg) {
>> + return (u16)readl(salvo_phy->base +
>> + reg * (1 << salvo_phy->data->reg_offset_shift));
>> +}
>> +
>> +static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy,
>> + u32 reg, u16 val)
>> +{
>> + writel(val, salvo_phy->base +
>> + reg * (1 << salvo_phy->data->reg_offset_shift));
>> +}
>> +
>> +/*
>> + * Below bringup sequence pair are from Cadence PHY's User Guide
>> + * and NXP platform tuning results.
>> + */
>> +static struct cdns_reg_pairs cdns_nxp_sequence_pair[] = {
>> + {0x0830, PHY_PMA_CMN_CTRL1},
>> + {0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL},
>> + {0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR},
>> + {0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR},
>> + {0x00d0, TB_ADDR_CMN_PLL0_INTDIV},
>> + {0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV},
>> + {0x0034, TB_ADDR_CMN_PLL0_HIGH_THR},
>> + {0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1},
>> + {0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2},
>> + {0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG},
>> + {0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD},
>> + {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD},
>> + {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD},
>> + {0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE},
>> + {0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE},
>> + {0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG},
>> + {0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE},
>> + {0x000a, TB_ADDR_CMN_PSM_CLK_CTRL},
>> + {0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR},
>> + {0xbefc, TB_ADDR_XCVR_PSM_RCTRL},
>> +
>> + {0x7799, TB_ADDR_TX_PSC_A0},
>> + {0x7798, TB_ADDR_TX_PSC_A1},
>> + {0x509b, TB_ADDR_TX_PSC_A2},
>> + {0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD},
>> + {0x509b, TB_ADDR_TX_PSC_A3},
>> + {0x2090, TB_ADDR_TX_PSC_CAL},
>> + {0x2090, TB_ADDR_TX_PSC_RDY},
>> +
>> + {0xA6FD, TB_ADDR_RX_PSC_A0},
>> + {0xA6FD, TB_ADDR_RX_PSC_A1},
>> + {0xA410, TB_ADDR_RX_PSC_A2},
>> + {0x2410, TB_ADDR_RX_PSC_A3},
>> +
>> + {0x23FF, TB_ADDR_RX_PSC_CAL},
>> + {0x2010, TB_ADDR_RX_PSC_RDY},
>> +
>> + {0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000},
>> + {0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY},
>> + {0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR},
>> + {0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR},
>> + {0x0000, TB_ADDR_RX_SAMP_DAC_CTRL},
>> + {0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE},
>> + {0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2},
>> + {0x0480, TB_ADDR_RX_DIAG_BS_TM},
>> + {0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1},
>> + {0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4},
>> + {0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0},
>> + {0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0},
>> + {0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6},
>> + {0x8000, TB_ADDR_RX_DIAG_RXFE_TM3},
>> + {0x0003, TB_ADDR_RX_DIAG_RXFE_TM4},
>> + {0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE},
>> + {0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3},
>> + {0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY},
>> + {0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE},
>> +
>> + {0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR},
>> + {0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR},
>> + {0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR},
>> + {0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR},
>> + {0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR},
>> + {0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR},
>> + {0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR},
>> + {0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR},
>> +
>> + {0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR},
>> + {0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR},
>> + {0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR},
>> + {0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR},
>> + {0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR},
>> + {0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR},
>> + /* Change rx detect parameter */
>> + {0x0960, TB_ADDR_TX_RCVDET_EN_TMR},
>> + {0x01e0, TB_ADDR_TX_RCVDET_ST_TMR},
>> + {0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR},
>> +};
>> +
>> +
>> +static int cdns_salvo_phy_power_on(struct phy *phy) {
>> + struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
>> + struct cdns_salvo_data *data = salvo_phy->data;
>> + int ret, i;
>> + u16 value;
>> +
>> + ret = clk_prepare_enable(salvo_phy->clk);
>> + if (ret)
>> + return ret;
>> +
>> + for (i = 0; i < data->init_sequence_length; i++) {
>> + struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i;
>> +
>> + cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val);
>> + }
>> +
>> + /* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
>> + value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL);
>> + value |= RXDET_IN_P3_32KHZ;
>> + cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL,
>> + RXDET_IN_P3_32KHZ);
>> +
>> + udelay(10);
>> +
>> + return ret;
>> +}
>> +
>> +static int cdns_salvo_phy_power_off(struct phy *phy) {
>> + struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
>> +
>> + clk_disable_unprepare(salvo_phy->clk);
>> +
>> + return 0;
>> +}
>> +
>> +static struct phy_ops cdns_salvo_phy_ops = {
>> + .power_on = cdns_salvo_phy_power_on,
>> + .power_off = cdns_salvo_phy_power_off,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int cdns_salvo_phy_probe(struct platform_device *pdev) {
>> + struct phy_provider *phy_provider;
>> + struct device *dev = &pdev->dev;
>> + struct cdns_salvo_phy *salvo_phy;
>> + struct resource *res;
>> + const struct of_device_id *match;
>> + struct cdns_salvo_data *data;
>> +
>> + match = of_match_device(cdns_salvo_phy_of_match, dev);
>> + if (!match)
>> + return -EINVAL;
>> +
>> + data = (struct cdns_salvo_data *)match->data;
>> + salvo_phy = devm_kzalloc(dev, sizeof(*salvo_phy), GFP_KERNEL);
>> + if (!salvo_phy)
>> + return -ENOMEM;
>> +
>> + salvo_phy->data = data;
>> + salvo_phy->clk = devm_clk_get_optional(dev, "salvo_phy_clk");
>> + if (IS_ERR(salvo_phy->clk))
>> + return PTR_ERR(salvo_phy->clk);
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + salvo_phy->base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(salvo_phy->base))
>> + return PTR_ERR(salvo_phy->base);
>> +
>> + salvo_phy->phy = devm_phy_create(dev, NULL, &cdns_salvo_phy_ops);
>> + if (IS_ERR(salvo_phy->phy))
>> + return PTR_ERR(salvo_phy->phy);
>> +
>> + phy_set_drvdata(salvo_phy->phy, salvo_phy);
>> +
>> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> + return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct cdns_salvo_data cdns_nxp_salvo_data = {
>> + 2,
>> + cdns_nxp_sequence_pair,
>> + ARRAY_SIZE(cdns_nxp_sequence_pair),
>> +};
>> +
>> +static const struct of_device_id cdns_salvo_phy_of_match[] = {
>> + {
>> + .compatible = "nxp,salvo-phy",
>> + .data = &cdns_nxp_salvo_data,
>> + },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, cdns_salvo_phy_of_match);
>> +
>> +static struct platform_driver cdns_salvo_phy_driver = {
>> + .probe = cdns_salvo_phy_probe,
>> + .driver = {
>> + .name = "cdns-salvo-phy",
>> + .of_match_table = cdns_salvo_phy_of_match,
>> + }
>> +};
>> +module_platform_driver(cdns_salvo_phy_driver);
>> +
>> +MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>");
>> MODULE_LICENSE("GPL
>> +v2"); MODULE_DESCRIPTION("Cadence SALVO PHY Driver");
>> --
>> 2.17.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-03-13 11:11 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-27 6:27 [PATCH 1/2] phy: cadence: salvo: add salvo phy driver Peter Chen
2020-02-27 6:27 ` [PATCH 2/2] doc: dt-binding: cdns-salvo-phy: add binding doc Peter Chen
2020-02-27 17:08 ` Rob Herring
2020-02-28 9:29 ` Peter Chen
2020-02-28 13:37 ` Rob Herring
2020-03-02 2:58 ` Peter Chen
2020-03-02 16:14 ` Rob Herring
2020-03-03 9:23 ` Peter Chen
2020-03-12 10:16 ` [PATCH 1/2] phy: cadence: salvo: add salvo phy driver Peter Chen
2020-03-13 11:15 ` Kishon Vijay Abraham I
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