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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Implement Wa_1407901919
Date: Thu, 27 Feb 2020 14:01:01 -0800	[thread overview]
Message-ID: <20200227220101.321671-11-jose.souza@intel.com> (raw)
In-Reply-To: <20200227220101.321671-1-jose.souza@intel.com>

This will fix a memory coherence issue.

v3: using whitespace to make easy to read WA (Chris)

BSpec: 52890
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h             | 20 +++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3e375a3b7714..c59e1a604ab8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -601,6 +601,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	 */
 	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 	       FF_MODE2_TDS_TIMER_128, 0);
+
+	/* Wa_1407901919:tgl */
+	wa_add(wal, ICL_HDC_MODE,
+	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
+	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W,
+	       0,
+	       HDC_COHERENT_ACCESS_L1_CACHE_DIS |
+	       HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80cf02a6eec1..28822585537b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7883,15 +7883,17 @@ enum {
 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
 
 /* GEN8 chicken */
-#define HDC_CHICKEN0				_MMIO(0x7300)
-#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
-#define ICL_HDC_MODE				_MMIO(0xE5F4)
-#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
-#define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
-#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
-#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
-#define  HDC_FORCE_NON_COHERENT			(1 << 4)
-#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
+#define HDC_CHICKEN0					_MMIO(0x7300)
+#define CNL_HDC_CHICKEN0				_MMIO(0xE5F0)
+#define ICL_HDC_MODE					_MMIO(0xE5F4)
+#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE		REG_BIT(15)
+#define  HDC_FENCE_DEST_SLM_DISABLE			REG_BIT(14)
+#define  HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W	REG_BIT(13)
+#define  HDC_COHERENT_ACCESS_L1_CACHE_DIS		REG_BIT(12)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED		REG_BIT(11)
+#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	REG_BIT(5)
+#define  HDC_FORCE_NON_COHERENT				REG_BIT(4)
+#define  HDC_BARRIER_PERFORMANCE_DISABLE		REG_BIT(10)
 
 #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
 
-- 
2.25.1

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  parent reply	other threads:[~2020-02-27 22:00 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-27 22:00 [Intel-gfx] [PATCH v3 01/11] drm/i915/tgl: Implement Wa_1409804808 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 02/11] drm/i915/tgl: Implement Wa_1806527549 José Roberto de Souza
2020-02-28 21:07   ` Matt Roper
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 03/11] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 04/11] drm/i915/tgl: Extend Wa_1606931601 for all steppings José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 05/11] drm/i915/tgl: Add note to Wa_1607297627 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 06/11] drm/i915/tgl: Add note about Wa_1607063988 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 07/11] drm/i915/tgl: Fix the Wa number of a fix José Roberto de Souza
2020-02-28 21:10   ` Matt Roper
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 08/11] drm/i915/tgl: Add note about Wa_1409142259 José Roberto de Souza
2020-02-28 21:16   ` Matt Roper
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping José Roberto de Souza
2020-02-28 21:25   ` Matt Roper
2020-02-29  0:04     ` Souza, Jose
2020-02-29  0:29       ` Matt Roper
2020-02-29  0:45         ` Souza, Jose
2020-02-29  1:15           ` Matt Roper
2020-02-27 22:01 ` [Intel-gfx] [PATCH v3 10/11] drm/i915/tgl: Add Wa number to WaAllowPMDepthAndInvocationCountAccessFromUMD José Roberto de Souza
2020-02-27 22:35   ` Lionel Landwerlin
2020-02-27 22:01 ` José Roberto de Souza [this message]
2020-02-28 22:07   ` [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Implement Wa_1407901919 Matt Roper
2020-02-28 22:10     ` Souza, Jose
2020-03-02 20:31       ` Rafael Antognolli
2020-02-28  2:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,01/11] drm/i915/tgl: Implement Wa_1409804808 Patchwork
2020-02-29 12:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-02 20:05   ` Souza, Jose

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