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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 08/11] drm/i915/tgl: Add note about Wa_1409142259
Date: Thu, 27 Feb 2020 14:00:58 -0800	[thread overview]
Message-ID: <20200227220101.321671-8-jose.souza@intel.com> (raw)
In-Reply-To: <20200227220101.321671-1-jose.souza@intel.com>

Different issues with the same fix, so justing adding
Wa_1409142259, Wa_1409252684, Wa_1409217633, Wa_1409207793,
Wa_1409178076 and 1408979724 to the comment so other devs can check if
this Was were implemetend with a simple grep.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0cdd3c50e0ae..ba0265763484 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,7 +580,15 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
-	/* Wa_1409142259:tgl */
+	/*
+	 * Wa_1409142259:tgl
+	 * Wa_1409347922:tgl
+	 * Wa_1409252684:tgl
+	 * Wa_1409217633:tgl
+	 * Wa_1409207793:tgl
+	 * Wa_1409178076:tgl
+	 * Wa_1408979724:tgl
+	 */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 
-- 
2.25.1

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  parent reply	other threads:[~2020-02-27 22:00 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-27 22:00 [Intel-gfx] [PATCH v3 01/11] drm/i915/tgl: Implement Wa_1409804808 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 02/11] drm/i915/tgl: Implement Wa_1806527549 José Roberto de Souza
2020-02-28 21:07   ` Matt Roper
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 03/11] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 04/11] drm/i915/tgl: Extend Wa_1606931601 for all steppings José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 05/11] drm/i915/tgl: Add note to Wa_1607297627 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 06/11] drm/i915/tgl: Add note about Wa_1607063988 José Roberto de Souza
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 07/11] drm/i915/tgl: Fix the Wa number of a fix José Roberto de Souza
2020-02-28 21:10   ` Matt Roper
2020-02-27 22:00 ` José Roberto de Souza [this message]
2020-02-28 21:16   ` [Intel-gfx] [PATCH v3 08/11] drm/i915/tgl: Add note about Wa_1409142259 Matt Roper
2020-02-27 22:00 ` [Intel-gfx] [PATCH v3 09/11] drm/i915/tgl: Restrict Wa_1408615072 to A0 stepping José Roberto de Souza
2020-02-28 21:25   ` Matt Roper
2020-02-29  0:04     ` Souza, Jose
2020-02-29  0:29       ` Matt Roper
2020-02-29  0:45         ` Souza, Jose
2020-02-29  1:15           ` Matt Roper
2020-02-27 22:01 ` [Intel-gfx] [PATCH v3 10/11] drm/i915/tgl: Add Wa number to WaAllowPMDepthAndInvocationCountAccessFromUMD José Roberto de Souza
2020-02-27 22:35   ` Lionel Landwerlin
2020-02-27 22:01 ` [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Implement Wa_1407901919 José Roberto de Souza
2020-02-28 22:07   ` Matt Roper
2020-02-28 22:10     ` Souza, Jose
2020-03-02 20:31       ` Rafael Antognolli
2020-02-28  2:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,01/11] drm/i915/tgl: Implement Wa_1409804808 Patchwork
2020-02-29 12:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-02 20:05   ` Souza, Jose

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