* [Intel-gfx] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use
@ 2020-02-28 10:43 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Several tests depend upon the implicit engine->mmio_base but have no
means of determining the physical layout. Since the kernel has started
providing this information, start putting it to use.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/i915/gem_engine_topology.c | 84 ++++++++++++++++++++++++++++++++++
lib/i915/gem_engine_topology.h | 5 ++
tests/i915/gem_ctx_shared.c | 38 +++++----------
tests/i915/gem_exec_latency.c | 17 ++++---
4 files changed, 111 insertions(+), 33 deletions(-)
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 58dff3208..640777ae4 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -21,7 +21,12 @@
* IN THE SOFTWARE.
*/
+#include <fcntl.h>
+#include <unistd.h>
+
#include "drmtest.h"
+#include "igt_sysfs.h"
+#include "intel_chipset.h"
#include "ioctl_wrappers.h"
#include "i915/gem_engine_topology.h"
@@ -327,3 +332,82 @@ bool gem_engine_is_equal(const struct intel_execution_engine2 *e1,
{
return e1->class == e2->class && e1->instance == e2->instance;
}
+
+static int descend(int dir, const char *path)
+{
+ int fd;
+
+ fd = openat(dir, path, O_RDONLY);
+ close(dir);
+
+ return fd;
+}
+
+int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
+ const char *fmt, ...)
+{
+ FILE *file;
+ va_list ap;
+ int ret;
+ int fd;
+
+ fd = igt_sysfs_open(i915);
+ if (fd < 0)
+ return fd;
+
+ fd = descend(fd, "engine");
+ if (fd < 0)
+ return fd;
+
+ fd = descend(fd, engine);
+ if (fd < 0)
+ return fd;
+
+ fd = descend(fd, attr);
+ if (fd < 0)
+ return fd;
+
+ file = fdopen(fd, "r");
+ if (!file) {
+ close(fd);
+ return -1;
+ }
+
+ va_start(ap, fmt);
+ ret = vfscanf(file, fmt, ap);
+ va_end(ap);
+
+ fclose(file);
+ return ret;
+}
+
+uint32_t gem_engine_mmio_base(int i915, const char *engine)
+{
+ unsigned int mmio = 0;
+
+ if (gem_engine_property_scanf(i915, engine, "mmio_base",
+ "%x", &mmio) < 0) {
+ int gen = intel_gen(intel_get_drm_devid(i915));
+
+ /* The layout of xcs1+ is unreliable -- hence the property! */
+ if (!strcmp(engine, "rcs0")) {
+ mmio = 0x2000;
+ } else if (!strcmp(engine, "bcs0")) {
+ mmio = 0x22000;
+ } else if (!strcmp(engine, "vcs0")) {
+ if (gen < 6)
+ mmio = 0x4000;
+ else if (gen < 11)
+ mmio = 0x12000;
+ else
+ mmio = 0x1c0000;
+ } else if (!strcmp(engine, "vecs0")) {
+ if (gen < 11)
+ mmio = 0x1a000;
+ else
+ mmio = 0x1c8000;
+ }
+ }
+
+ return mmio;
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 027d86be2..219c84b72 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -75,4 +75,9 @@ struct intel_execution_engine2 gem_eb_flags_to_engine(unsigned int flags);
#define __for_each_physical_engine(fd__, e__) \
____for_each_physical_engine(fd__, 0, e__)
+__attribute__((format(scanf, 4, 5)))
+int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
+ const char *fmt, ...);
+uint32_t gem_engine_mmio_base(int i915, const char *engine);
+
#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
index 820b96c1a..9ea020d7b 100644
--- a/tests/i915/gem_ctx_shared.c
+++ b/tests/i915/gem_ctx_shared.c
@@ -38,6 +38,7 @@
#include <drm.h>
+#include "i915/gem_engine_topology.h"
#include "igt_rand.h"
#include "igt_vgem.h"
#include "sync_file.h"
@@ -548,6 +549,14 @@ static uint32_t store_timestamp(int i915,
return obj.handle;
}
+static uint32_t ring_base(int i915, unsigned ring)
+{
+ if (ring == I915_EXEC_DEFAULT)
+ ring = I915_EXEC_RENDER; /* XXX */
+
+ return gem_engine_mmio_base(i915, gem_eb_flags_to_engine(ring).name);
+}
+
static void independent(int i915, unsigned ring, unsigned flags)
{
const int TIMESTAMP = 1023;
@@ -555,33 +564,8 @@ static void independent(int i915, unsigned ring, unsigned flags)
igt_spin_t *spin[MAX_ELSP_QLEN];
unsigned int mmio_base;
- /* XXX i915_query()! */
- switch (ring) {
- case I915_EXEC_DEFAULT:
- case I915_EXEC_RENDER:
- mmio_base = 0x2000;
- break;
-#if 0
- case I915_EXEC_BSD:
- mmio_base = 0x12000;
- break;
-#endif
- case I915_EXEC_BLT:
- mmio_base = 0x22000;
- break;
-
-#define GEN11_VECS0_BASE 0x1c8000
-#define GEN11_VECS1_BASE 0x1d8000
- case I915_EXEC_VEBOX:
- if (intel_gen(intel_get_drm_devid(i915)) >= 11)
- mmio_base = GEN11_VECS0_BASE;
- else
- mmio_base = 0x1a000;
- break;
-
- default:
- igt_skip("mmio base not known\n");
- }
+ mmio_base = ring_base(i915, ring);
+ igt_require_f(mmio_base, "mmio base not known\n");
for (int n = 0; n < ARRAY_SIZE(spin); n++) {
const struct igt_spin_factory opts = {
diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
index 3d99182a0..d2159f317 100644
--- a/tests/i915/gem_exec_latency.c
+++ b/tests/i915/gem_exec_latency.c
@@ -109,7 +109,7 @@ poll_ring(int fd, unsigned ring, const char *name)
igt_spin_free(fd, spin[0]);
}
-#define RCS_TIMESTAMP (0x2000 + 0x358)
+#define TIMESTAMP (0x358)
static void latency_on_ring(int fd,
unsigned ring, const char *name,
unsigned flags)
@@ -119,6 +119,7 @@ static void latency_on_ring(int fd,
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_relocation_entry reloc;
struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
igt_spin_t *spin = NULL;
IGT_CORK_HANDLE(c);
volatile uint32_t *reg;
@@ -128,7 +129,8 @@ static void latency_on_ring(int fd,
double gpu_latency;
int i, j;
- reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + RCS_TIMESTAMP);
+ igt_require(mmio_base);
+ reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + mmio_base + TIMESTAMP);
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(&obj[1]);
@@ -176,7 +178,7 @@ static void latency_on_ring(int fd,
map[i++] = 0x24 << 23 | 1;
if (has_64bit_reloc)
map[i-1]++;
- map[i++] = RCS_TIMESTAMP; /* ring local! */
+ map[i++] = mmio_base + TIMESTAMP;
map[i++] = offset;
if (has_64bit_reloc)
map[i++] = offset >> 32;
@@ -266,11 +268,14 @@ static void latency_from_ring(int fd,
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_relocation_entry reloc;
struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
const unsigned int repeats = ring_size / 2;
uint32_t *map, *results;
uint32_t ctx[2] = {};
int i, j;
+ igt_require(mmio_base);
+
if (flags & PREEMPT) {
ctx[0] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[0], -1023);
@@ -351,7 +356,7 @@ static void latency_from_ring(int fd,
map[i++] = 0x24 << 23 | 1;
if (has_64bit_reloc)
map[i-1]++;
- map[i++] = RCS_TIMESTAMP; /* ring local! */
+ map[i++] = mmio_base + TIMESTAMP;
map[i++] = offset;
if (has_64bit_reloc)
map[i++] = offset >> 32;
@@ -376,7 +381,7 @@ static void latency_from_ring(int fd,
map[i++] = 0x24 << 23 | 1;
if (has_64bit_reloc)
map[i-1]++;
- map[i++] = RCS_TIMESTAMP; /* ring local! */
+ map[i++] = mmio_base + TIMESTAMP;
map[i++] = offset;
if (has_64bit_reloc)
map[i++] = offset >> 32;
@@ -669,7 +674,7 @@ igt_main
ring_size = 1024;
intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device);
- rcs_clock = clockrate(device, RCS_TIMESTAMP);
+ rcs_clock = clockrate(device, 0x2000 + TIMESTAMP);
igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n",
rcs_clock / 1e3, 1e9 / rcs_clock);
rcs_clock = 1e9 / rcs_clock;
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [igt-dev] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use
@ 2020-02-28 10:43 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Several tests depend upon the implicit engine->mmio_base but have no
means of determining the physical layout. Since the kernel has started
providing this information, start putting it to use.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/i915/gem_engine_topology.c | 84 ++++++++++++++++++++++++++++++++++
lib/i915/gem_engine_topology.h | 5 ++
tests/i915/gem_ctx_shared.c | 38 +++++----------
tests/i915/gem_exec_latency.c | 17 ++++---
4 files changed, 111 insertions(+), 33 deletions(-)
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 58dff3208..640777ae4 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -21,7 +21,12 @@
* IN THE SOFTWARE.
*/
+#include <fcntl.h>
+#include <unistd.h>
+
#include "drmtest.h"
+#include "igt_sysfs.h"
+#include "intel_chipset.h"
#include "ioctl_wrappers.h"
#include "i915/gem_engine_topology.h"
@@ -327,3 +332,82 @@ bool gem_engine_is_equal(const struct intel_execution_engine2 *e1,
{
return e1->class == e2->class && e1->instance == e2->instance;
}
+
+static int descend(int dir, const char *path)
+{
+ int fd;
+
+ fd = openat(dir, path, O_RDONLY);
+ close(dir);
+
+ return fd;
+}
+
+int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
+ const char *fmt, ...)
+{
+ FILE *file;
+ va_list ap;
+ int ret;
+ int fd;
+
+ fd = igt_sysfs_open(i915);
+ if (fd < 0)
+ return fd;
+
+ fd = descend(fd, "engine");
+ if (fd < 0)
+ return fd;
+
+ fd = descend(fd, engine);
+ if (fd < 0)
+ return fd;
+
+ fd = descend(fd, attr);
+ if (fd < 0)
+ return fd;
+
+ file = fdopen(fd, "r");
+ if (!file) {
+ close(fd);
+ return -1;
+ }
+
+ va_start(ap, fmt);
+ ret = vfscanf(file, fmt, ap);
+ va_end(ap);
+
+ fclose(file);
+ return ret;
+}
+
+uint32_t gem_engine_mmio_base(int i915, const char *engine)
+{
+ unsigned int mmio = 0;
+
+ if (gem_engine_property_scanf(i915, engine, "mmio_base",
+ "%x", &mmio) < 0) {
+ int gen = intel_gen(intel_get_drm_devid(i915));
+
+ /* The layout of xcs1+ is unreliable -- hence the property! */
+ if (!strcmp(engine, "rcs0")) {
+ mmio = 0x2000;
+ } else if (!strcmp(engine, "bcs0")) {
+ mmio = 0x22000;
+ } else if (!strcmp(engine, "vcs0")) {
+ if (gen < 6)
+ mmio = 0x4000;
+ else if (gen < 11)
+ mmio = 0x12000;
+ else
+ mmio = 0x1c0000;
+ } else if (!strcmp(engine, "vecs0")) {
+ if (gen < 11)
+ mmio = 0x1a000;
+ else
+ mmio = 0x1c8000;
+ }
+ }
+
+ return mmio;
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 027d86be2..219c84b72 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -75,4 +75,9 @@ struct intel_execution_engine2 gem_eb_flags_to_engine(unsigned int flags);
#define __for_each_physical_engine(fd__, e__) \
____for_each_physical_engine(fd__, 0, e__)
+__attribute__((format(scanf, 4, 5)))
+int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
+ const char *fmt, ...);
+uint32_t gem_engine_mmio_base(int i915, const char *engine);
+
#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
index 820b96c1a..9ea020d7b 100644
--- a/tests/i915/gem_ctx_shared.c
+++ b/tests/i915/gem_ctx_shared.c
@@ -38,6 +38,7 @@
#include <drm.h>
+#include "i915/gem_engine_topology.h"
#include "igt_rand.h"
#include "igt_vgem.h"
#include "sync_file.h"
@@ -548,6 +549,14 @@ static uint32_t store_timestamp(int i915,
return obj.handle;
}
+static uint32_t ring_base(int i915, unsigned ring)
+{
+ if (ring == I915_EXEC_DEFAULT)
+ ring = I915_EXEC_RENDER; /* XXX */
+
+ return gem_engine_mmio_base(i915, gem_eb_flags_to_engine(ring).name);
+}
+
static void independent(int i915, unsigned ring, unsigned flags)
{
const int TIMESTAMP = 1023;
@@ -555,33 +564,8 @@ static void independent(int i915, unsigned ring, unsigned flags)
igt_spin_t *spin[MAX_ELSP_QLEN];
unsigned int mmio_base;
- /* XXX i915_query()! */
- switch (ring) {
- case I915_EXEC_DEFAULT:
- case I915_EXEC_RENDER:
- mmio_base = 0x2000;
- break;
-#if 0
- case I915_EXEC_BSD:
- mmio_base = 0x12000;
- break;
-#endif
- case I915_EXEC_BLT:
- mmio_base = 0x22000;
- break;
-
-#define GEN11_VECS0_BASE 0x1c8000
-#define GEN11_VECS1_BASE 0x1d8000
- case I915_EXEC_VEBOX:
- if (intel_gen(intel_get_drm_devid(i915)) >= 11)
- mmio_base = GEN11_VECS0_BASE;
- else
- mmio_base = 0x1a000;
- break;
-
- default:
- igt_skip("mmio base not known\n");
- }
+ mmio_base = ring_base(i915, ring);
+ igt_require_f(mmio_base, "mmio base not known\n");
for (int n = 0; n < ARRAY_SIZE(spin); n++) {
const struct igt_spin_factory opts = {
diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
index 3d99182a0..d2159f317 100644
--- a/tests/i915/gem_exec_latency.c
+++ b/tests/i915/gem_exec_latency.c
@@ -109,7 +109,7 @@ poll_ring(int fd, unsigned ring, const char *name)
igt_spin_free(fd, spin[0]);
}
-#define RCS_TIMESTAMP (0x2000 + 0x358)
+#define TIMESTAMP (0x358)
static void latency_on_ring(int fd,
unsigned ring, const char *name,
unsigned flags)
@@ -119,6 +119,7 @@ static void latency_on_ring(int fd,
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_relocation_entry reloc;
struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
igt_spin_t *spin = NULL;
IGT_CORK_HANDLE(c);
volatile uint32_t *reg;
@@ -128,7 +129,8 @@ static void latency_on_ring(int fd,
double gpu_latency;
int i, j;
- reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + RCS_TIMESTAMP);
+ igt_require(mmio_base);
+ reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + mmio_base + TIMESTAMP);
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(&obj[1]);
@@ -176,7 +178,7 @@ static void latency_on_ring(int fd,
map[i++] = 0x24 << 23 | 1;
if (has_64bit_reloc)
map[i-1]++;
- map[i++] = RCS_TIMESTAMP; /* ring local! */
+ map[i++] = mmio_base + TIMESTAMP;
map[i++] = offset;
if (has_64bit_reloc)
map[i++] = offset >> 32;
@@ -266,11 +268,14 @@ static void latency_from_ring(int fd,
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_relocation_entry reloc;
struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
const unsigned int repeats = ring_size / 2;
uint32_t *map, *results;
uint32_t ctx[2] = {};
int i, j;
+ igt_require(mmio_base);
+
if (flags & PREEMPT) {
ctx[0] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[0], -1023);
@@ -351,7 +356,7 @@ static void latency_from_ring(int fd,
map[i++] = 0x24 << 23 | 1;
if (has_64bit_reloc)
map[i-1]++;
- map[i++] = RCS_TIMESTAMP; /* ring local! */
+ map[i++] = mmio_base + TIMESTAMP;
map[i++] = offset;
if (has_64bit_reloc)
map[i++] = offset >> 32;
@@ -376,7 +381,7 @@ static void latency_from_ring(int fd,
map[i++] = 0x24 << 23 | 1;
if (has_64bit_reloc)
map[i-1]++;
- map[i++] = RCS_TIMESTAMP; /* ring local! */
+ map[i++] = mmio_base + TIMESTAMP;
map[i++] = offset;
if (has_64bit_reloc)
map[i++] = offset >> 32;
@@ -669,7 +674,7 @@ igt_main
ring_size = 1024;
intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device);
- rcs_clock = clockrate(device, RCS_TIMESTAMP);
+ rcs_clock = clockrate(device, 0x2000 + TIMESTAMP);
igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n",
rcs_clock / 1e3, 1e9 / rcs_clock);
rcs_clock = 1e9 / rcs_clock;
--
2.25.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH i-g-t 2/5] i915/gem_ctx_isolation: Check engine relative registers
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
(?)
@ 2020-02-28 10:43 ` Chris Wilson
2020-02-28 19:46 ` [igt-dev] " Stimson, Dale B
-1 siblings, 1 reply; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_ctx_isolation.c | 164 ++++++++++++++++++++-------------
1 file changed, 100 insertions(+), 64 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 1b66fec11..eff4b1df2 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -70,6 +70,7 @@ static const struct named_register {
uint32_t ignore_bits;
uint32_t write_mask; /* some registers bits do not exist */
bool masked;
+ bool relative;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
@@ -109,7 +110,6 @@ static const struct named_register {
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
- { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
{ "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
@@ -138,79 +138,56 @@ static const struct named_register {
{ "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
{ "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
- { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
{ "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
{ "COMMON_SLICE_CHICKEN2", GEN_RANGE(9, 9), RCS0, 0x7014, .masked = true },
- { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
{ "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(11, 11) /* + glk */, RCS0, 0x731c, .masked = true },
{ "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true },
{ "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
- { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
{ "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
{ "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
- { "VCS0_GPR", GEN_RANGE(9, 10), VCS0, 0x12600, 32 },
- { "VCS1_GPR", GEN_RANGE(9, 10), VCS1, 0x1c600, 32 },
- { "VECS_GPR", GEN_RANGE(9, 10), VECS0, 0x1a600, 32 },
-
- { "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 },
- { "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 },
- { "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 },
- { "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 },
- { "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 },
+ { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
{}
}, ignore_registers[] = {
{ "RCS timestamp", GEN6, ~0u, 0x2358 },
{ "BCS timestamp", GEN7, ~0u, 0x22358 },
- { "VCS0 timestamp", GEN_RANGE(7, 10), ~0u, 0x12358 },
- { "VCS1 timestamp", GEN_RANGE(7, 10), ~0u, 0x1c358 },
- { "VECS timestamp", GEN_RANGE(8, 10), ~0u, 0x1a358 },
-
- { "VCS0 timestamp", GEN11, ~0u, 0x1c0358 },
- { "VCS1 timestamp", GEN11, ~0u, 0x1c4358 },
- { "VCS2 timestamp", GEN11, ~0u, 0x1d0358 },
- { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
- { "VECS timestamp", GEN11, ~0u, 0x1c8358 },
+ { "xCS timestamp", GEN8, ALL, 0x358, .relative = true },
/* huc read only */
- { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2000 },
- { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2014 },
- { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x23b0 },
-
- { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
- { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
- { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
-
- { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2000 },
- { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2014 },
- { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x23b0 },
-
- { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
- { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
- { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
+ { "BSD 0x2000", GEN11, ALL, 0x2000, .relative = true },
+ { "BSD 0x2014", GEN11, ALL, 0x2014, .relative = true },
+ { "BSD 0x23b0", GEN11, ALL, 0x23b0, .relative = true },
{}
};
-static const char *register_name(uint32_t offset, char *buf, size_t len)
+static const char *
+register_name(uint32_t offset, uint32_t mmio_base, char *buf, size_t len)
{
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
unsigned int width = r->count ? 4*r->count : 4;
- if (offset >= r->offset && offset < r->offset + width) {
+ uint32_t base;
+
+ base = r->offset;
+ if (r->relative)
+ base += mmio_base;
+
+ if (offset >= base && offset < base + width) {
if (r->count <= 1)
return r->name;
snprintf(buf, len, "%s[%d]",
- r->name, (offset - r->offset)/4);
+ r->name, (offset - base) / 4);
return buf;
}
}
@@ -218,22 +195,35 @@ static const char *register_name(uint32_t offset, char *buf, size_t len)
return "unknown";
}
-static const struct named_register *lookup_register(uint32_t offset)
+static const struct named_register *
+lookup_register(uint32_t offset, uint32_t mmio_base)
{
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
unsigned int width = r->count ? 4*r->count : 4;
- if (offset >= r->offset && offset < r->offset + width)
+ uint32_t base;
+
+ base = r->offset;
+ if (r->relative)
+ base += mmio_base;
+
+ if (offset >= base && offset < base + width)
return r;
}
return NULL;
}
-static bool ignore_register(uint32_t offset)
+static bool ignore_register(uint32_t offset, uint32_t mmio_base)
{
for (const struct named_register *r = ignore_registers; r->name; r++) {
unsigned int width = r->count ? 4*r->count : 4;
- if (offset >= r->offset && offset < r->offset + width)
+ uint32_t base;
+
+ base = r->offset;
+ if (r->relative)
+ base += mmio_base;
+
+ if (offset >= base && offset < base + width)
return true;
}
@@ -248,6 +238,7 @@ static void tmpl_regs(int fd,
{
const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
unsigned int regs_size;
uint32_t *regs;
@@ -259,12 +250,20 @@ static void tmpl_regs(int fd,
I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ uint32_t offset;
+
if (!(r->engine_mask & engine_bit))
continue;
if (!(r->gen_mask & gen_bit))
continue;
- for (unsigned count = r->count ?: 1, offset = r->offset;
- count--; offset += 4) {
+ if (r->relative && !mmio_base)
+ continue;
+
+ offset = r->offset;
+ if (r->relative)
+ offset += mmio_base;
+
+ for (unsigned count = r->count ?: 1; count--; offset += 4) {
uint32_t x = value;
if (r->write_mask)
x &= r->write_mask;
@@ -284,6 +283,7 @@ static uint32_t read_regs(int fd,
const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
const unsigned int gen_bit = 1 << gen;
const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
const bool r64b = gen >= 8;
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_relocation_entry *reloc;
@@ -311,13 +311,20 @@ static uint32_t read_regs(int fd,
n = 0;
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ uint32_t offset;
+
if (!(r->engine_mask & engine_bit))
continue;
if (!(r->gen_mask & gen_bit))
continue;
+ if (r->relative && !mmio_base)
+ continue;
+
+ offset = r->offset;
+ if (r->relative)
+ offset += mmio_base;
- for (unsigned count = r->count ?: 1, offset = r->offset;
- count--; offset += 4) {
+ for (unsigned count = r->count ?: 1; count--; offset += 4) {
*b++ = 0x24 << 23 | (1 + r64b); /* SRM */
*b++ = offset;
reloc[n].target_handle = obj[0].handle;
@@ -357,6 +364,7 @@ static void write_regs(int fd,
{
const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
struct drm_i915_gem_exec_object2 obj;
struct drm_i915_gem_execbuffer2 execbuf;
unsigned int batch_size;
@@ -372,12 +380,20 @@ static void write_regs(int fd,
gem_set_domain(fd, obj.handle,
I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ uint32_t offset;
+
if (!(r->engine_mask & engine_bit))
continue;
if (!(r->gen_mask & gen_bit))
continue;
- for (unsigned count = r->count ?: 1, offset = r->offset;
- count--; offset += 4) {
+ if (r->relative && !mmio_base)
+ continue;
+
+ offset = r->offset;
+ if (r->relative)
+ offset += mmio_base;
+
+ for (unsigned count = r->count ?: 1; count--; offset += 4) {
uint32_t x = value;
if (r->write_mask)
x &= r->write_mask;
@@ -410,6 +426,7 @@ static void restore_regs(int fd,
const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
const unsigned int gen_bit = 1 << gen;
const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
const bool r64b = gen >= 8;
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_execbuffer2 execbuf;
@@ -437,13 +454,20 @@ static void restore_regs(int fd,
n = 0;
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ uint32_t offset;
+
if (!(r->engine_mask & engine_bit))
continue;
if (!(r->gen_mask & gen_bit))
continue;
+ if (r->relative && !mmio_base)
+ continue;
+
+ offset = r->offset;
+ if (r->relative)
+ offset += mmio_base;
- for (unsigned count = r->count ?: 1, offset = r->offset;
- count--; offset += 4) {
+ for (unsigned count = r->count ?: 1; count--; offset += 4) {
*b++ = 0x29 << 23 | (1 + r64b); /* LRM */
*b++ = offset;
reloc[n].target_handle = obj[0].handle;
@@ -479,6 +503,7 @@ static void dump_regs(int fd,
const int gen = intel_gen(intel_get_drm_devid(fd));
const unsigned int gen_bit = 1 << gen;
const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
unsigned int regs_size;
uint32_t *out;
@@ -489,26 +514,36 @@ static void dump_regs(int fd,
gem_set_domain(fd, regs, I915_GEM_DOMAIN_CPU, 0);
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ uint32_t offset;
+
if (!(r->engine_mask & engine_bit))
continue;
if (!(r->gen_mask & gen_bit))
continue;
+ if (r->relative && !mmio_base)
+ continue;
+
+ offset = r->offset;
+ if (r->relative)
+ offset += mmio_base;
if (r->count <= 1) {
igt_debug("0x%04x (%s): 0x%08x\n",
- r->offset, r->name, out[r->offset/4]);
+ offset, r->name, out[offset / 4]);
} else {
for (unsigned x = 0; x < r->count; x++)
igt_debug("0x%04x (%s[%d]): 0x%08x\n",
- r->offset+4*x, r->name, x,
- out[r->offset/4 + x]);
+ offset + 4 * x, r->name, x,
+ out[offset / 4 + x]);
}
}
munmap(out, regs_size);
}
-static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
+static void compare_regs(int fd, const struct intel_execution_engine2 *e,
+ uint32_t A, uint32_t B, const char *who)
{
+ const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
unsigned int num_errors;
unsigned int regs_size;
uint32_t *a, *b;
@@ -532,11 +567,11 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
if (a[n] == b[n])
continue;
- if (ignore_register(offset))
+ if (ignore_register(offset, mmio_base))
continue;
mask = ~0u;
- r = lookup_register(offset);
+ r = lookup_register(offset, mmio_base);
if (r && r->masked)
mask >>= 16;
if (r && r->ignore_bits)
@@ -547,7 +582,7 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
igt_warn("Register 0x%04x (%s): A=%08x B=%08x\n",
offset,
- register_name(offset, buf, sizeof(buf)),
+ register_name(offset, mmio_base, buf, sizeof(buf)),
a[n] & mask, b[n] & mask);
num_errors++;
}
@@ -638,7 +673,7 @@ static void nonpriv(int fd,
igt_spin_free(fd, spin);
- compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+ compare_regs(fd, e, tmpl, regs[1], "nonpriv read/writes");
for (int n = 0; n < ARRAY_SIZE(regs); n++)
gem_close(fd, regs[n]);
@@ -707,8 +742,9 @@ static void isolation(int fd,
igt_spin_free(fd, spin);
if (!(flags & DIRTY1))
- compare_regs(fd, regs[0], tmp, "two reads of the same ctx");
- compare_regs(fd, regs[0], regs[1], "two virgin contexts");
+ compare_regs(fd, e, regs[0], tmp,
+ "two reads of the same ctx");
+ compare_regs(fd, e, regs[0], regs[1], "two virgin contexts");
for (int n = 0; n < ARRAY_SIZE(ctx); n++) {
gem_close(fd, regs[n]);
@@ -827,13 +863,13 @@ static void preservation(int fd,
char buf[80];
snprintf(buf, sizeof(buf), "dirty %x context\n", values[v]);
- compare_regs(fd, regs[v][0], regs[v][1], buf);
+ compare_regs(fd, e, regs[v][0], regs[v][1], buf);
gem_close(fd, regs[v][0]);
gem_close(fd, regs[v][1]);
gem_context_destroy(fd, ctx[v]);
}
- compare_regs(fd, regs[num_values][0], regs[num_values][1], "clean");
+ compare_regs(fd, e, regs[num_values][0], regs[num_values][1], "clean");
gem_context_destroy(fd, ctx[num_values]);
}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
@ 2020-02-28 10:43 ` Chris Wilson
-1 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
We [will] expose various per-engine scheduling controls. One of which,
'preempt_timeout_ms', defines how we wait for a preemption request to be
honoured by the currently executing context. If it fails to relieve the
GPU within the required timeout, the engine is reset and the miscreant
forcibly evicted.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/i915/gem_context.c | 64 ++++--
lib/i915/gem_context.h | 2 +
lib/i915/gem_engine_topology.c | 48 +++++
lib/i915/gem_engine_topology.h | 3 +
tests/Makefile.sources | 3 +
tests/i915/sysfs_preempt_timeout.c | 309 +++++++++++++++++++++++++++++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build | 1 +
8 files changed, 414 insertions(+), 17 deletions(-)
create mode 100644 tests/i915/sysfs_preempt_timeout.c
diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 50dfee3d1..169e43d2e 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -43,6 +43,21 @@
* software features improving submission model (context priority).
*/
+static int create_ext_ioctl(int i915,
+ struct drm_i915_gem_context_create_ext *arg)
+{
+ int err;
+
+ err = 0;
+ if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
+ err = -errno;
+ igt_assume(err);
+ }
+
+ errno = 0;
+ return err;
+}
+
/**
* gem_has_contexts:
* @fd: open i915 drm file descriptor
@@ -324,17 +339,14 @@ __gem_context_clone(int i915,
.flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
.extensions = to_user_pointer(&clone),
};
- int err = 0;
+ int err;
- if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &arg)) {
- err = -errno;
- igt_assume(err);
- }
+ err = create_ext_ioctl(i915, &arg);
+ if (err)
+ return err;
*out = arg.ctx_id;
-
- errno = 0;
- return err;
+ return 0;
}
static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
@@ -382,16 +394,8 @@ bool gem_has_context_clone(int i915)
.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
.extensions = to_user_pointer(&ext),
};
- int err;
-
- err = 0;
- if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create)) {
- err = -errno;
- igt_assume(err);
- }
- errno = 0;
- return err == -ENOENT;
+ return create_ext_ioctl(i915, &create) == -ENOENT;
}
/**
@@ -492,3 +496,29 @@ gem_context_copy_engines(int src_fd, uint32_t src, int dst_fd, uint32_t dst)
param.ctx_id = dst;
gem_context_set_param(dst_fd, ¶m);
}
+
+uint32_t gem_context_create_for_engine(int i915, unsigned int class, unsigned int inst)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ .engines = { { .engine_class = class, .engine_instance = inst } }
+ };
+ struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ .base = {
+ .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ .next_extension = 0, /* end of chain */
+ },
+ .param = {
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ .size = sizeof(engines),
+ },
+ };
+ struct drm_i915_gem_context_create_ext create = {
+ .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ .extensions = to_user_pointer(&p_engines),
+ };
+
+ igt_assert_eq(create_ext_ioctl(i915, &create), 0);
+ igt_assert_neq(create.ctx_id, 0);
+ return create.ctx_id;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index 15e5db281..b478c47a1 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -34,6 +34,8 @@ int __gem_context_create(int fd, uint32_t *ctx_id);
void gem_context_destroy(int fd, uint32_t ctx_id);
int __gem_context_destroy(int fd, uint32_t ctx_id);
+uint32_t gem_context_create_for_engine(int fd, unsigned int class, unsigned int inst);
+
int __gem_context_clone(int i915,
uint32_t src, unsigned int share,
unsigned int flags,
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 640777ae4..64a6b0472 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -22,6 +22,8 @@
*/
#include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/syscall.h>
#include <unistd.h>
#include "drmtest.h"
@@ -411,3 +413,49 @@ uint32_t gem_engine_mmio_base(int i915, const char *engine)
return mmio;
}
+
+void dyn_sysfs_engines(int i915, int engines, const char *file,
+ void (*test)(int, int))
+{
+ char buf[512];
+ int len;
+
+ lseek(engines, 0, SEEK_SET);
+ while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
+ void *ptr = buf;
+
+ while (len) {
+ struct linux_dirent64 {
+ ino64_t d_ino;
+ off64_t d_off;
+ unsigned short d_reclen;
+ unsigned char d_type;
+ char d_name[];
+ } *de = ptr;
+ char *name;
+ int engine;
+
+ ptr += de->d_reclen;
+ len -= de->d_reclen;
+
+ engine = openat(engines, de->d_name, O_RDONLY);
+ name = igt_sysfs_get(engine, "name");
+ if (!name) {
+ close(engine);
+ continue;
+ }
+
+ igt_dynamic(name) {
+ if (file) {
+ struct stat st;
+
+ igt_require(fstatat(engine, file, &st, 0) == 0);
+ }
+
+ test(i915, engine);
+ }
+
+ close(engine);
+ }
+ }
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 219c84b72..b624d607e 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -80,4 +80,7 @@ int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
const char *fmt, ...);
uint32_t gem_engine_mmio_base(int i915, const char *engine);
+void dyn_sysfs_engines(int i915, int engines, const char *file,
+ void (*test)(int i915, int engine));
+
#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 10913e86b..cc1d1fdd1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -103,6 +103,9 @@ TESTS_progs = \
vgem_slow \
$(NULL)
+TESTS_progs += sysfs_preempt_timeout
+sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
+
TESTS_progs += gem_bad_reloc
gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c
diff --git a/tests/i915/sysfs_preempt_timeout.c b/tests/i915/sysfs_preempt_timeout.c
new file mode 100644
index 000000000..71fe46387
--- /dev/null
+++ b/tests/i915/sysfs_preempt_timeout.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "sw_sync.h"
+
+#include "igt_debugfs.h"
+
+#define ATTR "preempt_timeout_ms"
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static bool enable_hangcheck(int i915, bool state)
+{
+ bool success;
+ int dir;
+
+ dir = igt_sysfs_open_parameters(i915);
+ if (dir < 0) /* no parameters, must be default! */
+ return false;
+
+ success = __enable_hangcheck(dir, state);
+ close(dir);
+
+ return success;
+}
+
+static void set_preempt_timeout(int engine, unsigned int value)
+{
+ unsigned int delay;
+
+ igt_sysfs_printf(engine, ATTR, "%u", value);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+ unsigned int delays[] = { 0, 1, 1000, 1234, 654321 };
+ unsigned int saved;
+
+ /* Quick test that store/show reports the same values */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++)
+ set_preempt_timeout(engine, delays[i]);
+
+ set_preempt_timeout(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+ unsigned int saved, delay;
+
+ /* Quick test that values that are not representable are rejected */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, "%d", -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, 40ull << 32);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param p = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_BANNABLE,
+ };
+
+ igt_assert_eq(__gem_context_set_param(i915, &p), 0);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+ uint32_t ctx;
+
+ ctx = gem_context_create_for_engine(i915, class, inst);
+ set_unbannable(i915, ctx);
+ gem_context_set_priority(i915, ctx, prio);
+
+ return ctx;
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+ unsigned int class, inst;
+ struct timespec ts = {};
+ igt_spin_t *spin[2];
+ uint64_t elapsed;
+ uint32_t ctx[2];
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_preempt_timeout(engine, timeout);
+
+ ctx[0] = create_context(i915, class, inst, -1023);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 1023);
+ igt_nsec_elapsed(&ts);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+ igt_spin_busywait_until_started(spin[1]);
+ elapsed = igt_nsec_elapsed(&ts);
+
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+ gem_quiescent_gpu(i915);
+
+ return elapsed;
+}
+
+static void test_timeout(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * Send down some non-preemptable workloads and then request a
+ * switch to a higher priority context. The HW will not be able to
+ * respond, so the kernel will be forced to reset the hog. This
+ * timeout should match our specification, and so we can measure
+ * the delay from requesting the preemption to its completion.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_timeout(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms\n",
+ ATTR, delays[i], elapsed * 1e-6);
+
+ /*
+ * We need to give a couple of jiffies slack for the scheduler timeouts
+ * and then a little more slack fr the overhead in submitting and
+ * measuring. 50ms should cover all of our sins and be useful
+ * tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+ "Forced preemption timeout exceeded request!\n");
+ }
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+ set_preempt_timeout(engine, saved);
+}
+
+static void test_off(int i915, int engine)
+{
+ unsigned int class, inst;
+ igt_spin_t *spin[2];
+ unsigned int saved;
+ uint32_t ctx[2];
+
+ /*
+ * We support setting the timeout to 0 to disable the reset on
+ * preemption failure. Having established that we can do forced
+ * preemption on demand, we use the same setup (non-preeemptable hog
+ * followed by a high priority context) and verify that the hog is
+ * never reset. Never is a long time, so we settle for 150s.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_preempt_timeout(engine, 0);
+
+ ctx[0] = create_context(i915, class, inst, -1023);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 1023);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+
+ for (int i = 0; i < 150; i++) {
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), 0);
+ sleep(1);
+ }
+
+ set_preempt_timeout(engine, 1);
+
+ igt_spin_busywait_until_started(spin[1]);
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+
+ set_preempt_timeout(engine, saved);
+}
+
+igt_main
+{
+ static const struct {
+ const char *name;
+ void (*fn)(int, int);
+ } tests[] = {
+ { "idempotent", test_idempotent },
+ { "invalid", test_invalid },
+ { "timeout", test_timeout },
+ { "off", test_off },
+ { }
+ };
+ int i915 = -1, engines = -1;
+
+ igt_fixture {
+ int sys;
+
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ igt_allow_hang(i915, 0, 0);
+
+ sys = igt_sysfs_open(i915);
+ igt_require(sys != -1);
+
+ engines = openat(sys, "engine", O_RDONLY);
+ igt_require(engines != -1);
+
+ close(sys);
+ }
+
+ for (typeof(*tests) *t = tests; t->name; t++)
+ igt_subtest_with_dynamic(t->name)
+ dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+ igt_fixture {
+ close(engines);
+ close(i915);
+ }
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index 390e4fa0c..01cd176ee 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -59,6 +59,7 @@ igt@gem_sync@(?!.*basic).*
igt@gem_tiled_swapping@(?!non-threaded).*
igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
igt@gem_wait@.*hang.*
+igt@sysfs_preemption_timeout@off.*
###############################################
# GEM: Not worth fixing
###############################################
diff --git a/tests/meson.build b/tests/meson.build
index dcc5e7b6a..0af1ed1e1 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -226,6 +226,7 @@ i915_progs = [
'i915_query',
'i915_selftest',
'i915_suspend',
+ 'sysfs_preempt_timeout',
]
test_deps = [ igt_deps ]
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [igt-dev] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
@ 2020-02-28 10:43 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
We [will] expose various per-engine scheduling controls. One of which,
'preempt_timeout_ms', defines how we wait for a preemption request to be
honoured by the currently executing context. If it fails to relieve the
GPU within the required timeout, the engine is reset and the miscreant
forcibly evicted.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/i915/gem_context.c | 64 ++++--
lib/i915/gem_context.h | 2 +
lib/i915/gem_engine_topology.c | 48 +++++
lib/i915/gem_engine_topology.h | 3 +
tests/Makefile.sources | 3 +
tests/i915/sysfs_preempt_timeout.c | 309 +++++++++++++++++++++++++++++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build | 1 +
8 files changed, 414 insertions(+), 17 deletions(-)
create mode 100644 tests/i915/sysfs_preempt_timeout.c
diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 50dfee3d1..169e43d2e 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -43,6 +43,21 @@
* software features improving submission model (context priority).
*/
+static int create_ext_ioctl(int i915,
+ struct drm_i915_gem_context_create_ext *arg)
+{
+ int err;
+
+ err = 0;
+ if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
+ err = -errno;
+ igt_assume(err);
+ }
+
+ errno = 0;
+ return err;
+}
+
/**
* gem_has_contexts:
* @fd: open i915 drm file descriptor
@@ -324,17 +339,14 @@ __gem_context_clone(int i915,
.flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
.extensions = to_user_pointer(&clone),
};
- int err = 0;
+ int err;
- if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &arg)) {
- err = -errno;
- igt_assume(err);
- }
+ err = create_ext_ioctl(i915, &arg);
+ if (err)
+ return err;
*out = arg.ctx_id;
-
- errno = 0;
- return err;
+ return 0;
}
static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
@@ -382,16 +394,8 @@ bool gem_has_context_clone(int i915)
.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
.extensions = to_user_pointer(&ext),
};
- int err;
-
- err = 0;
- if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create)) {
- err = -errno;
- igt_assume(err);
- }
- errno = 0;
- return err == -ENOENT;
+ return create_ext_ioctl(i915, &create) == -ENOENT;
}
/**
@@ -492,3 +496,29 @@ gem_context_copy_engines(int src_fd, uint32_t src, int dst_fd, uint32_t dst)
param.ctx_id = dst;
gem_context_set_param(dst_fd, ¶m);
}
+
+uint32_t gem_context_create_for_engine(int i915, unsigned int class, unsigned int inst)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ .engines = { { .engine_class = class, .engine_instance = inst } }
+ };
+ struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ .base = {
+ .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ .next_extension = 0, /* end of chain */
+ },
+ .param = {
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ .size = sizeof(engines),
+ },
+ };
+ struct drm_i915_gem_context_create_ext create = {
+ .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ .extensions = to_user_pointer(&p_engines),
+ };
+
+ igt_assert_eq(create_ext_ioctl(i915, &create), 0);
+ igt_assert_neq(create.ctx_id, 0);
+ return create.ctx_id;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index 15e5db281..b478c47a1 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -34,6 +34,8 @@ int __gem_context_create(int fd, uint32_t *ctx_id);
void gem_context_destroy(int fd, uint32_t ctx_id);
int __gem_context_destroy(int fd, uint32_t ctx_id);
+uint32_t gem_context_create_for_engine(int fd, unsigned int class, unsigned int inst);
+
int __gem_context_clone(int i915,
uint32_t src, unsigned int share,
unsigned int flags,
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 640777ae4..64a6b0472 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -22,6 +22,8 @@
*/
#include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/syscall.h>
#include <unistd.h>
#include "drmtest.h"
@@ -411,3 +413,49 @@ uint32_t gem_engine_mmio_base(int i915, const char *engine)
return mmio;
}
+
+void dyn_sysfs_engines(int i915, int engines, const char *file,
+ void (*test)(int, int))
+{
+ char buf[512];
+ int len;
+
+ lseek(engines, 0, SEEK_SET);
+ while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
+ void *ptr = buf;
+
+ while (len) {
+ struct linux_dirent64 {
+ ino64_t d_ino;
+ off64_t d_off;
+ unsigned short d_reclen;
+ unsigned char d_type;
+ char d_name[];
+ } *de = ptr;
+ char *name;
+ int engine;
+
+ ptr += de->d_reclen;
+ len -= de->d_reclen;
+
+ engine = openat(engines, de->d_name, O_RDONLY);
+ name = igt_sysfs_get(engine, "name");
+ if (!name) {
+ close(engine);
+ continue;
+ }
+
+ igt_dynamic(name) {
+ if (file) {
+ struct stat st;
+
+ igt_require(fstatat(engine, file, &st, 0) == 0);
+ }
+
+ test(i915, engine);
+ }
+
+ close(engine);
+ }
+ }
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 219c84b72..b624d607e 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -80,4 +80,7 @@ int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
const char *fmt, ...);
uint32_t gem_engine_mmio_base(int i915, const char *engine);
+void dyn_sysfs_engines(int i915, int engines, const char *file,
+ void (*test)(int i915, int engine));
+
#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 10913e86b..cc1d1fdd1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -103,6 +103,9 @@ TESTS_progs = \
vgem_slow \
$(NULL)
+TESTS_progs += sysfs_preempt_timeout
+sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
+
TESTS_progs += gem_bad_reloc
gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c
diff --git a/tests/i915/sysfs_preempt_timeout.c b/tests/i915/sysfs_preempt_timeout.c
new file mode 100644
index 000000000..71fe46387
--- /dev/null
+++ b/tests/i915/sysfs_preempt_timeout.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "sw_sync.h"
+
+#include "igt_debugfs.h"
+
+#define ATTR "preempt_timeout_ms"
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static bool enable_hangcheck(int i915, bool state)
+{
+ bool success;
+ int dir;
+
+ dir = igt_sysfs_open_parameters(i915);
+ if (dir < 0) /* no parameters, must be default! */
+ return false;
+
+ success = __enable_hangcheck(dir, state);
+ close(dir);
+
+ return success;
+}
+
+static void set_preempt_timeout(int engine, unsigned int value)
+{
+ unsigned int delay;
+
+ igt_sysfs_printf(engine, ATTR, "%u", value);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+ unsigned int delays[] = { 0, 1, 1000, 1234, 654321 };
+ unsigned int saved;
+
+ /* Quick test that store/show reports the same values */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++)
+ set_preempt_timeout(engine, delays[i]);
+
+ set_preempt_timeout(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+ unsigned int saved, delay;
+
+ /* Quick test that values that are not representable are rejected */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, "%d", -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, 40ull << 32);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param p = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_BANNABLE,
+ };
+
+ igt_assert_eq(__gem_context_set_param(i915, &p), 0);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+ uint32_t ctx;
+
+ ctx = gem_context_create_for_engine(i915, class, inst);
+ set_unbannable(i915, ctx);
+ gem_context_set_priority(i915, ctx, prio);
+
+ return ctx;
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+ unsigned int class, inst;
+ struct timespec ts = {};
+ igt_spin_t *spin[2];
+ uint64_t elapsed;
+ uint32_t ctx[2];
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_preempt_timeout(engine, timeout);
+
+ ctx[0] = create_context(i915, class, inst, -1023);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 1023);
+ igt_nsec_elapsed(&ts);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+ igt_spin_busywait_until_started(spin[1]);
+ elapsed = igt_nsec_elapsed(&ts);
+
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+ gem_quiescent_gpu(i915);
+
+ return elapsed;
+}
+
+static void test_timeout(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * Send down some non-preemptable workloads and then request a
+ * switch to a higher priority context. The HW will not be able to
+ * respond, so the kernel will be forced to reset the hog. This
+ * timeout should match our specification, and so we can measure
+ * the delay from requesting the preemption to its completion.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_timeout(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms\n",
+ ATTR, delays[i], elapsed * 1e-6);
+
+ /*
+ * We need to give a couple of jiffies slack for the scheduler timeouts
+ * and then a little more slack fr the overhead in submitting and
+ * measuring. 50ms should cover all of our sins and be useful
+ * tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+ "Forced preemption timeout exceeded request!\n");
+ }
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+ set_preempt_timeout(engine, saved);
+}
+
+static void test_off(int i915, int engine)
+{
+ unsigned int class, inst;
+ igt_spin_t *spin[2];
+ unsigned int saved;
+ uint32_t ctx[2];
+
+ /*
+ * We support setting the timeout to 0 to disable the reset on
+ * preemption failure. Having established that we can do forced
+ * preemption on demand, we use the same setup (non-preeemptable hog
+ * followed by a high priority context) and verify that the hog is
+ * never reset. Never is a long time, so we settle for 150s.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_preempt_timeout(engine, 0);
+
+ ctx[0] = create_context(i915, class, inst, -1023);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 1023);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+
+ for (int i = 0; i < 150; i++) {
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), 0);
+ sleep(1);
+ }
+
+ set_preempt_timeout(engine, 1);
+
+ igt_spin_busywait_until_started(spin[1]);
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+
+ set_preempt_timeout(engine, saved);
+}
+
+igt_main
+{
+ static const struct {
+ const char *name;
+ void (*fn)(int, int);
+ } tests[] = {
+ { "idempotent", test_idempotent },
+ { "invalid", test_invalid },
+ { "timeout", test_timeout },
+ { "off", test_off },
+ { }
+ };
+ int i915 = -1, engines = -1;
+
+ igt_fixture {
+ int sys;
+
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ igt_allow_hang(i915, 0, 0);
+
+ sys = igt_sysfs_open(i915);
+ igt_require(sys != -1);
+
+ engines = openat(sys, "engine", O_RDONLY);
+ igt_require(engines != -1);
+
+ close(sys);
+ }
+
+ for (typeof(*tests) *t = tests; t->name; t++)
+ igt_subtest_with_dynamic(t->name)
+ dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+ igt_fixture {
+ close(engines);
+ close(i915);
+ }
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index 390e4fa0c..01cd176ee 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -59,6 +59,7 @@ igt@gem_sync@(?!.*basic).*
igt@gem_tiled_swapping@(?!non-threaded).*
igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
igt@gem_wait@.*hang.*
+igt@sysfs_preemption_timeout@off.*
###############################################
# GEM: Not worth fixing
###############################################
diff --git a/tests/meson.build b/tests/meson.build
index dcc5e7b6a..0af1ed1e1 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -226,6 +226,7 @@ i915_progs = [
'i915_query',
'i915_selftest',
'i915_suspend',
+ 'sysfs_preempt_timeout',
]
test_deps = [ igt_deps ]
--
2.25.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
` (2 preceding siblings ...)
(?)
@ 2020-02-28 10:43 ` Chris Wilson
2020-02-28 23:34 ` Andi Shyti
-1 siblings, 1 reply; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
We [will] expose various per-engine scheduling controls. One of which,
'heartbeat_duration_ms', defines how often we send a heartbeat down the
engine to check upon the health of the engine. If a heartbeat does not
complete within the interval (or two), the engine is declared hung.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/Makefile.sources | 3 +
tests/i915/sysfs_heartbeat_interval.c | 456 ++++++++++++++++++++++++++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build | 1 +
4 files changed, 461 insertions(+)
create mode 100644 tests/i915/sysfs_heartbeat_interval.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index cc1d1fdd1..cc3ef5355 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -103,6 +103,9 @@ TESTS_progs = \
vgem_slow \
$(NULL)
+TESTS_progs += sysfs_heartbeat_interval
+sysfs_heartbeat_interval_SOURCES = i915/sysfs_heartbeat_interval.c
+
TESTS_progs += sysfs_preempt_timeout
sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
diff --git a/tests/i915/sysfs_heartbeat_interval.c b/tests/i915/sysfs_heartbeat_interval.c
new file mode 100644
index 000000000..131105437
--- /dev/null
+++ b/tests/i915/sysfs_heartbeat_interval.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <signal.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "sw_sync.h"
+
+#include "igt_debugfs.h"
+
+#define ATTR "heartbeat_interval_ms"
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static void enable_hangcheck(int i915, bool state)
+{
+ int dir;
+
+ dir = igt_sysfs_open_parameters(i915);
+ if (dir < 0) /* no parameters, must be default! */
+ return;
+
+ __enable_hangcheck(dir, state);
+ close(dir);
+}
+
+static void set_heartbeat(int engine, unsigned int value)
+{
+ unsigned int delay = ~value;
+
+ igt_debug("set %s:%d\n", ATTR, value);
+ igt_require(igt_sysfs_printf(engine, ATTR, "%u", value) > 0);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+ unsigned int delays[] = { 1, 1000, 5000, 50000, 123456789 };
+ unsigned int saved;
+
+ /* Quick test that the property reports the values we set */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++)
+ set_heartbeat(engine, delays[i]);
+
+ set_heartbeat(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+ unsigned int saved, delay;
+
+ /* Quick test that we reject any unrepresentable intervals */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, 10ull << 32);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param p = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_BANNABLE,
+ };
+
+ igt_assert_eq(__gem_context_set_param(i915, &p), 0);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+ uint32_t ctx;
+
+ ctx = gem_context_create_for_engine(i915, class, inst);
+ set_unbannable(i915, ctx);
+ gem_context_set_priority(i915, ctx, prio);
+
+ return ctx;
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+ unsigned int class, inst;
+ struct timespec ts = {};
+ igt_spin_t *spin[2];
+ uint64_t elapsed;
+ uint32_t ctx[2];
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_heartbeat(engine, timeout);
+
+ ctx[0] = create_context(i915, class, inst, 1023);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, -1023);
+ igt_nsec_elapsed(&ts);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+ igt_spin_busywait_until_started(spin[1]);
+ elapsed = igt_nsec_elapsed(&ts);
+
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+ gem_quiescent_gpu(i915);
+
+ return elapsed;
+}
+
+static void test_precise(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * The heartbeat interval defines how long the kernel waits between
+ * checking on the status of the engines. It first sends down a
+ * heartbeat pulse, waits the interval and sees if the system managed
+ * to complete the pulse. If not, it gives a priority bump to the pulse
+ * and waits again. This is repeated until the priority cannot be bumped
+ * any more, and the system is declared hung.
+ *
+ * If we combine the preemptive pulse with forced preemption, we instead
+ * get a much faster hang detection. Thus in combination we can measure
+ * the system response time to reseting a hog as a measure of the
+ * heartbeat interval, and so confirm it matches our specification.
+ */
+
+ igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+ gem_quiescent_gpu(i915);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_timeout(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms[%d]\n", ATTR,
+ delays[i], elapsed * 1e-6,
+ (int)(elapsed / 1000 / 1000));
+
+ /*
+ * It takes a couple of missed heartbeats before we start
+ * terminating hogs, and a little bit of jiffie slack for
+ * scheduling at each step. 150ms should cover all of our
+ * sins and be useful tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < 3 * delays[i] + 150,
+ "Heartbeat interval (and CPR) exceeded request!\n");
+ }
+
+ gem_quiescent_gpu(i915);
+ set_heartbeat(engine, saved);
+}
+
+static void test_nopreempt(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * The same principle as test_precise(), except that forced preemption
+ * is disabled (or simply not supported by the platform). This time,
+ * it waits until the system misses a few heartbeat before doing a
+ * per-engine/full-gpu reset. As such it is less precise, but we
+ * can still estimate an upper bound for our specified heartbeat
+ * interval and verify the system conforms.
+ */
+
+ /* Test heartbeats with forced preemption disabled */
+ igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 0);
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+ gem_quiescent_gpu(i915);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_timeout(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms[%d]\n", ATTR,
+ delays[i], elapsed * 1e-6,
+ (int)(elapsed / 1000 / 1000));
+
+ /*
+ * It takes a few missed heartbeats before we start
+ * terminating hogs, and a little bit of jiffie slack for
+ * scheduling at each step. 250ms should cover all of our
+ * sins and be useful tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < 5 * delays[i] + 250,
+ "Heartbeat interval (and CPR) exceeded request!\n");
+ }
+
+ gem_quiescent_gpu(i915);
+ set_heartbeat(engine, saved);
+}
+
+static void client(int i915, int engine, int *ctl, int duration, int expect)
+{
+ unsigned int class, inst;
+ unsigned long count = 0;
+ uint32_t ctx;
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ ctx = create_context(i915, class, inst, 0);
+
+ while (!READ_ONCE(*ctl)) {
+ igt_spin_t *spin;
+
+ spin = igt_spin_new(i915, ctx,
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin);
+
+ igt_spin_set_timeout(spin, (uint64_t)duration * 1000 * 1000);
+ sync_fence_wait(spin->out_fence, -1);
+
+ igt_assert_eq(sync_fence_status(spin->out_fence), expect);
+ count++;
+ }
+
+ gem_context_destroy(i915, ctx);
+ igt_info("%s client completed %lu spins\n",
+ expect < 0 ? "Bad" : "Good", count);
+}
+
+static void sigign(int sig)
+{
+}
+
+static void wait_until(int duration)
+{
+ signal(SIGCHLD, sigign);
+ sleep(duration);
+ signal(SIGCHLD, SIG_IGN);
+}
+
+static void __test_mixed(int i915, int engine,
+ int heartbeat,
+ int good,
+ int bad,
+ int duration)
+{
+ unsigned int saved;
+ int *shared;
+
+ /*
+ * Given two clients of which one is a hog, be sure we cleanly
+ * terminate the hog leaving the good client to run.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+ gem_quiescent_gpu(i915);
+
+ shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_assert(shared != MAP_FAILED);
+
+ set_heartbeat(engine, heartbeat);
+
+ igt_fork(child, 1) /* good client */
+ client(i915, engine, shared, good, 1);
+ igt_fork(child, 1) /* bad client */
+ client(i915, engine, shared, bad, -EIO);
+
+ wait_until(duration);
+
+ *shared = true;
+ igt_waitchildren();
+ munmap(shared, 4096);
+
+ gem_quiescent_gpu(i915);
+ set_heartbeat(engine, saved);
+}
+
+static void test_mixed(int i915, int engine)
+{
+ /*
+ * Hogs rarely run alone. Our hang detection must carefully wean
+ * out the hogs from the innocent clients. Thus we run a mixed workload
+ * with non-preemptable hogs that exceed the heartbeat, and quicker
+ * innocents. We inspect the fence status of each to verify that
+ * only the hogs are reset.
+ */
+ igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+ __test_mixed(i915, engine, 10, 10, 100, 5);
+}
+
+static void test_long(int i915, int engine)
+{
+ /*
+ * Some clients relish being hogs, and demand that the system
+ * never do hangchecking. Never is hard to test, so instead we
+ * run over a day and verify that only the super hogs are reset.
+ */
+ igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 0);
+ __test_mixed(i915, engine,
+ 60 * 1000, /* 60s */
+ 60 * 1000, /* 60s */
+ 300 * 1000, /* 5min */
+ 24 * 3600 /* 24hours */);
+}
+
+static void test_off(int i915, int engine)
+{
+ unsigned int class, inst;
+ unsigned int saved;
+ igt_spin_t *spin;
+ uint32_t ctx;
+
+ /*
+ * Some other clients request that there is never any interruption
+ * or jitter in their workload and so demand that the kernel never
+ * sends a heartbeat to steal precious cycles from their workload.
+ * Turn off the heartbeat and check that the workload is uninterrupted
+ * for 150s.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+ gem_quiescent_gpu(i915);
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_heartbeat(engine, 0);
+
+ ctx = create_context(i915, class, inst, 0);
+
+ spin = igt_spin_new(i915, ctx,
+ .flags = (IGT_SPIN_POLL_RUN |
+ IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin);
+
+ for (int i = 0; i < 150; i++) {
+ igt_assert_eq(sync_fence_status(spin->out_fence), 0);
+ sleep(1);
+ }
+
+ set_heartbeat(engine, 1);
+
+ igt_assert_eq(sync_fence_wait(spin->out_fence, 250), 0);
+ igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
+
+ igt_spin_free(i915, spin);
+
+ gem_quiescent_gpu(i915);
+ set_heartbeat(engine, saved);
+}
+
+igt_main
+{
+ static const struct {
+ const char *name;
+ void (*fn)(int, int);
+ } tests[] = {
+ { "idempotent", test_idempotent },
+ { "invalid", test_invalid },
+ { "precise", test_precise },
+ { "nopreempt", test_nopreempt },
+ { "mixed", test_mixed },
+ { "off", test_off },
+ { "long", test_long },
+ { }
+ };
+ int i915 = -1, engines = -1;
+
+ igt_fixture {
+ int sys;
+
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ igt_allow_hang(i915, 0, 0);
+
+ sys = igt_sysfs_open(i915);
+ igt_require(sys != -1);
+
+ engines = openat(sys, "engine", O_RDONLY);
+ igt_require(engines != -1);
+ close(sys);
+
+ enable_hangcheck(i915, true);
+ }
+
+ for (typeof(*tests) *t = tests; t->name; t++)
+ igt_subtest_with_dynamic(t->name)
+ dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+ igt_fixture {
+ close(engines);
+ close(i915);
+ }
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index 01cd176ee..eb5c9226a 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -59,6 +59,7 @@ igt@gem_sync@(?!.*basic).*
igt@gem_tiled_swapping@(?!non-threaded).*
igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
igt@gem_wait@.*hang.*
+igt@sysfs_heartbeat_timeout@long.*
igt@sysfs_preemption_timeout@off.*
###############################################
# GEM: Not worth fixing
diff --git a/tests/meson.build b/tests/meson.build
index 0af1ed1e1..bc1af9b1e 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -226,6 +226,7 @@ i915_progs = [
'i915_query',
'i915_selftest',
'i915_suspend',
+ 'sysfs_heartbeat_interval',
'sysfs_preempt_timeout',
]
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH i-g-t 5/5] i915: Exercise timeslice sysfs property
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
@ 2020-02-28 10:43 ` Chris Wilson
-1 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
We [will] expose various per-engine scheduling controls. One of which,
'timeslice_duration_ms', defines the scheduling quantum. If a context
exhausts its timeslice, it will be preempted in favour of running one of
its compatriots.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/Makefile.sources | 3 +
tests/i915/sysfs_timeslice_duration.c | 500 ++++++++++++++++++++++++++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build | 1 +
4 files changed, 505 insertions(+)
create mode 100644 tests/i915/sysfs_timeslice_duration.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index cc3ef5355..ab0f82d3c 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -109,6 +109,9 @@ sysfs_heartbeat_interval_SOURCES = i915/sysfs_heartbeat_interval.c
TESTS_progs += sysfs_preempt_timeout
sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
+TESTS_progs += sysfs_timeslice_duration
+sysfs_timeslice_duration_SOURCES = i915/sysfs_timeslice_duration.c
+
TESTS_progs += gem_bad_reloc
gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c
diff --git a/tests/i915/sysfs_timeslice_duration.c b/tests/i915/sysfs_timeslice_duration.c
new file mode 100644
index 000000000..3166c72d4
--- /dev/null
+++ b/tests/i915/sysfs_timeslice_duration.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "i915/gem_mman.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "intel_chipset.h"
+#include "intel_reg.h"
+#include "sw_sync.h"
+
+#define ATTR "timeslice_duration_ms"
+
+#define MI_SEMAPHORE_WAIT (0x1c << 23)
+#define MI_SEMAPHORE_POLL (1 << 15)
+#define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
+#define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)
+#define MI_SEMAPHORE_SAD_LT_SDD (2 << 12)
+#define MI_SEMAPHORE_SAD_LTE_SDD (3 << 12)
+#define MI_SEMAPHORE_SAD_EQ_SDD (4 << 12)
+#define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static bool enable_hangcheck(int i915, bool state)
+{
+ bool success;
+ int dir;
+
+ dir = igt_sysfs_open_parameters(i915);
+ if (dir < 0) /* no parameters, must be default! */
+ return false;
+
+ success = __enable_hangcheck(dir, state);
+ close(dir);
+
+ return success;
+}
+
+static void set_timeslice(int engine, unsigned int value)
+{
+ unsigned int delay;
+
+ igt_sysfs_printf(engine, ATTR, "%u", value);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+ const unsigned int delays[] = { 0, 1, 1234, 654321 };
+ unsigned int saved;
+
+ /* Quick test to verify the kernel reports the same values as we write */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++)
+ set_timeslice(engine, delays[i]);
+
+ set_timeslice(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+ unsigned int saved, delay;
+
+ /* Quick test that non-representable delays are rejected */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, "%d", -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, 123ull << 32);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param p = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_BANNABLE,
+ };
+
+ igt_assert_eq(__gem_context_set_param(i915, &p), 0);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+ uint32_t ctx;
+
+ ctx = gem_context_create_for_engine(i915, class, inst);
+ set_unbannable(i915, ctx);
+ gem_context_set_priority(i915, ctx, prio);
+
+ return ctx;
+}
+
+static int cmp_u32(const void *_a, const void *_b)
+{
+ const uint32_t *a = _a, *b = _b;
+
+ return *a - *b;
+}
+
+static double clockrate(int i915)
+{
+ int freq;
+ drm_i915_getparam_t gp = {
+ .value = &freq,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+
+ igt_require(igt_ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp) == 0);
+ return 1e9 / freq;
+}
+
+static uint64_t __test_duration(int i915, int engine, unsigned int timeout)
+{
+ struct drm_i915_gem_exec_object2 obj[3] = {
+ {
+ .handle = gem_create(i915, 4096),
+ .offset = 0,
+ .flags = EXEC_OBJECT_PINNED,
+ },
+ {
+ .handle = gem_create(i915, 4096),
+ .offset = 4096,
+ .flags = EXEC_OBJECT_PINNED,
+ },
+ { gem_create(i915, 4096) }
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = ARRAY_SIZE(obj),
+ .buffers_ptr = to_user_pointer(obj),
+ };
+ const int gen = intel_gen(intel_get_drm_devid(i915));
+ double duration = clockrate(i915);
+ unsigned int class, inst, mmio;
+ uint32_t *cs, *map;
+ uint32_t ctx[2];
+ int start;
+ int i;
+
+ igt_require(gem_scheduler_has_preemption(i915));
+ igt_require(gen >= 8); /* MI_SEMAPHORE_WAIT */
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+ igt_require(igt_sysfs_scanf(engine, "mmio_base", "%x", &mmio) == 1);
+
+ set_timeslice(engine, timeout);
+
+ ctx[0] = create_context(i915, class, inst, 0);
+ ctx[1] = create_context(i915, class, inst, 0);
+
+ map = gem_mmap__cpu(i915, obj[2].handle, 0, 4096, PROT_WRITE);
+
+ cs = map;
+ for (i = 0; i < 10; i++) {
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD |
+ (4 - 2 + (gen >= 12));
+ *cs++ = 0;
+ *cs++ = obj[0].offset + sizeof(uint32_t) * i;
+ *cs++ = 0;
+ if (gen >= 12)
+ *cs++ = 0;
+
+ *cs++ = 0x24 << 23 | 2; /* SRM */
+ *cs++ = mmio + 0x358;
+ *cs++ = obj[1].offset + sizeof(uint32_t) * i;
+ *cs++ = 0;
+
+ *cs++ = MI_STORE_DWORD_IMM;
+ *cs++ = obj[0].offset +
+ 4096 - sizeof(uint32_t) * i - sizeof(uint32_t);
+ *cs++ = 0;
+ *cs++ = 1;
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ cs += 16 - ((cs - map) & 15);
+ start = (cs - map) * sizeof(*cs);
+ for (i = 0; i < 10; i++) {
+ *cs++ = MI_STORE_DWORD_IMM;
+ *cs++ = obj[0].offset + sizeof(uint32_t) * i;
+ *cs++ = 0;
+ *cs++ = 1;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD |
+ (4 - 2 + (gen >= 12));
+ *cs++ = 0;
+ *cs++ = obj[0].offset +
+ 4096 - sizeof(uint32_t) * i - sizeof(uint32_t);
+ *cs++ = 0;
+ if (gen >= 12)
+ *cs++ = 0;
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+ igt_assert(cs - map < 4096 / sizeof(*cs));
+ munmap(map, 4096);
+
+ eb.rsvd1 = ctx[0];
+ gem_execbuf(i915, &eb);
+
+ eb.rsvd1 = ctx[1];
+ eb.batch_start_offset = start;
+ gem_execbuf(i915, &eb);
+
+ gem_sync(i915, obj[2].handle);
+
+ gem_set_domain(i915, obj[1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+ map = gem_mmap__cpu(i915, obj[1].handle, 0, 4096, PROT_WRITE);
+ for (i = 0; i < 9; i++)
+ map[i] = map[i + 1] - map[i];
+ qsort(map, 9, sizeof(*map), cmp_u32);
+ duration *= map[4] / 2; /* 2 sema-waits between timestamp updates */
+ munmap(map, 4096);
+
+ for (i = 0; i < ARRAY_SIZE(ctx); i++)
+ gem_context_destroy(i915, ctx[i]);
+
+ for (i = 0; i < ARRAY_SIZE(obj); i++)
+ gem_close(i915, obj[i].handle);
+
+ return duration;
+}
+
+static void test_duration(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * Timeslicing at its very basic level is sharing the GPU by
+ * running one context for interval before running another. After
+ * each interval the running context is swapped for another runnable
+ * context.
+ *
+ * We can measure this directly by watching the xCS_TIMESTAMP and
+ * recording its value every time we switch into the context, using
+ * a couple of semaphores to busyspin for the timeslice.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_duration(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms\n",
+ ATTR, delays[i], elapsed * 1e-6);
+
+ /*
+ * We need to give a couple of jiffies slack for the scheduler timeouts
+ * and then a little more slack fr the overhead in submitting and
+ * measuring. 50ms should cover all of our sins and be useful
+ * tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+ "Timeslice exceeded request!\n");
+ }
+
+ gem_quiescent_gpu(i915);
+ set_timeslice(engine, saved);
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+ unsigned int class, inst;
+ struct timespec ts = {};
+ igt_spin_t *spin[2];
+ uint64_t elapsed;
+ uint32_t ctx[2];
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_timeslice(engine, timeout);
+
+ ctx[0] = create_context(i915, class, inst, 0);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 0);
+ igt_nsec_elapsed(&ts);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+ igt_spin_busywait_until_started(spin[1]);
+ elapsed = igt_nsec_elapsed(&ts);
+
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+ gem_quiescent_gpu(i915);
+
+ return elapsed;
+}
+
+static void test_timeout(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * Timeslicing requires us to preempt the running context in order to
+ * switch into its contemporary. If we couple a unpreemptable hog
+ * with a fast forced reset, we can measure the timeslice by how long
+ * it takes for the hog to be reset and the high priority context
+ * to complete.
+ */
+
+ igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_timeout(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms\n",
+ ATTR, delays[i], elapsed * 1e-6);
+
+ /*
+ * We need to give a couple of jiffies slack for the scheduler timeouts
+ * and then a little more slack fr the overhead in submitting and
+ * measuring. 50ms should cover all of our sins and be useful
+ * tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+ "Timeslice exceeded request!\n");
+ }
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+ set_timeslice(engine, saved);
+}
+
+static void test_off(int i915, int engine)
+{
+ unsigned int class, inst;
+ unsigned int saved;
+ igt_spin_t *spin[2];
+ uint32_t ctx[2];
+
+ /*
+ * As always, there are some who must run uninterrupted and simply do
+ * not want to share the GPU even for a microsecond. Those greedy
+ * clients can disable timeslicing entirely, and so set the timeslice
+ * to 0. We test that a hog is not preempted within the 150s of
+ * our boredom threshold.
+ */
+
+ igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_timeslice(engine, 0);
+
+ ctx[0] = create_context(i915, class, inst, 0);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 0);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+
+ for (int i = 0; i < 150; i++) {
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), 0);
+ sleep(1);
+ }
+
+ set_timeslice(engine, 1);
+
+ igt_spin_busywait_until_started(spin[1]);
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+
+ set_timeslice(engine, saved);
+}
+
+igt_main
+{
+ static const struct {
+ const char *name;
+ void (*fn)(int, int);
+ } tests[] = {
+ { "idempotent", test_idempotent },
+ { "invalid", test_invalid },
+ { "duration", test_duration },
+ { "timeout", test_timeout },
+ { "off", test_off },
+ { }
+ };
+ int i915 = -1, engines = -1;
+
+ igt_fixture {
+ int sys;
+
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ igt_allow_hang(i915, 0, 0);
+
+ sys = igt_sysfs_open(i915);
+ igt_require(sys != -1);
+
+ engines = openat(sys, "engine", O_RDONLY);
+ igt_require(engines != -1);
+
+ close(sys);
+ }
+
+ for (typeof(*tests) *t = tests; t->name; t++)
+ igt_subtest_with_dynamic(t->name)
+ dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+ igt_fixture {
+ close(engines);
+ close(i915);
+ }
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index eb5c9226a..a3c4239aa 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -61,6 +61,7 @@ igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
igt@gem_wait@.*hang.*
igt@sysfs_heartbeat_timeout@long.*
igt@sysfs_preemption_timeout@off.*
+igt@sysfs_timeslice_duration@off.*
###############################################
# GEM: Not worth fixing
###############################################
diff --git a/tests/meson.build b/tests/meson.build
index bc1af9b1e..0cba10e27 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -228,6 +228,7 @@ i915_progs = [
'i915_suspend',
'sysfs_heartbeat_interval',
'sysfs_preempt_timeout',
+ 'sysfs_timeslice_duration',
]
test_deps = [ igt_deps ]
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [igt-dev] [PATCH i-g-t 5/5] i915: Exercise timeslice sysfs property
@ 2020-02-28 10:43 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
We [will] expose various per-engine scheduling controls. One of which,
'timeslice_duration_ms', defines the scheduling quantum. If a context
exhausts its timeslice, it will be preempted in favour of running one of
its compatriots.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/Makefile.sources | 3 +
tests/i915/sysfs_timeslice_duration.c | 500 ++++++++++++++++++++++++++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build | 1 +
4 files changed, 505 insertions(+)
create mode 100644 tests/i915/sysfs_timeslice_duration.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index cc3ef5355..ab0f82d3c 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -109,6 +109,9 @@ sysfs_heartbeat_interval_SOURCES = i915/sysfs_heartbeat_interval.c
TESTS_progs += sysfs_preempt_timeout
sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c
+TESTS_progs += sysfs_timeslice_duration
+sysfs_timeslice_duration_SOURCES = i915/sysfs_timeslice_duration.c
+
TESTS_progs += gem_bad_reloc
gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c
diff --git a/tests/i915/sysfs_timeslice_duration.c b/tests/i915/sysfs_timeslice_duration.c
new file mode 100644
index 000000000..3166c72d4
--- /dev/null
+++ b/tests/i915/sysfs_timeslice_duration.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <dirent.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "i915/gem_engine_topology.h"
+#include "i915/gem_mman.h"
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "intel_chipset.h"
+#include "intel_reg.h"
+#include "sw_sync.h"
+
+#define ATTR "timeslice_duration_ms"
+
+#define MI_SEMAPHORE_WAIT (0x1c << 23)
+#define MI_SEMAPHORE_POLL (1 << 15)
+#define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
+#define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)
+#define MI_SEMAPHORE_SAD_LT_SDD (2 << 12)
+#define MI_SEMAPHORE_SAD_LTE_SDD (3 << 12)
+#define MI_SEMAPHORE_SAD_EQ_SDD (4 << 12)
+#define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static bool enable_hangcheck(int i915, bool state)
+{
+ bool success;
+ int dir;
+
+ dir = igt_sysfs_open_parameters(i915);
+ if (dir < 0) /* no parameters, must be default! */
+ return false;
+
+ success = __enable_hangcheck(dir, state);
+ close(dir);
+
+ return success;
+}
+
+static void set_timeslice(int engine, unsigned int value)
+{
+ unsigned int delay;
+
+ igt_sysfs_printf(engine, ATTR, "%u", value);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, value);
+}
+
+static void test_idempotent(int i915, int engine)
+{
+ const unsigned int delays[] = { 0, 1, 1234, 654321 };
+ unsigned int saved;
+
+ /* Quick test to verify the kernel reports the same values as we write */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++)
+ set_timeslice(engine, delays[i]);
+
+ set_timeslice(engine, saved);
+}
+
+static void test_invalid(int i915, int engine)
+{
+ unsigned int saved, delay;
+
+ /* Quick test that non-representable delays are rejected */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, "%d", -1);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+
+ igt_sysfs_printf(engine, ATTR, PRIu64, 123ull << 32);
+ igt_sysfs_scanf(engine, ATTR, "%u", &delay);
+ igt_assert_eq(delay, saved);
+}
+
+static void set_unbannable(int i915, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param p = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_BANNABLE,
+ };
+
+ igt_assert_eq(__gem_context_set_param(i915, &p), 0);
+}
+
+static uint32_t create_context(int i915, unsigned int class, unsigned int inst, int prio)
+{
+ uint32_t ctx;
+
+ ctx = gem_context_create_for_engine(i915, class, inst);
+ set_unbannable(i915, ctx);
+ gem_context_set_priority(i915, ctx, prio);
+
+ return ctx;
+}
+
+static int cmp_u32(const void *_a, const void *_b)
+{
+ const uint32_t *a = _a, *b = _b;
+
+ return *a - *b;
+}
+
+static double clockrate(int i915)
+{
+ int freq;
+ drm_i915_getparam_t gp = {
+ .value = &freq,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+
+ igt_require(igt_ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp) == 0);
+ return 1e9 / freq;
+}
+
+static uint64_t __test_duration(int i915, int engine, unsigned int timeout)
+{
+ struct drm_i915_gem_exec_object2 obj[3] = {
+ {
+ .handle = gem_create(i915, 4096),
+ .offset = 0,
+ .flags = EXEC_OBJECT_PINNED,
+ },
+ {
+ .handle = gem_create(i915, 4096),
+ .offset = 4096,
+ .flags = EXEC_OBJECT_PINNED,
+ },
+ { gem_create(i915, 4096) }
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = ARRAY_SIZE(obj),
+ .buffers_ptr = to_user_pointer(obj),
+ };
+ const int gen = intel_gen(intel_get_drm_devid(i915));
+ double duration = clockrate(i915);
+ unsigned int class, inst, mmio;
+ uint32_t *cs, *map;
+ uint32_t ctx[2];
+ int start;
+ int i;
+
+ igt_require(gem_scheduler_has_preemption(i915));
+ igt_require(gen >= 8); /* MI_SEMAPHORE_WAIT */
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+ igt_require(igt_sysfs_scanf(engine, "mmio_base", "%x", &mmio) == 1);
+
+ set_timeslice(engine, timeout);
+
+ ctx[0] = create_context(i915, class, inst, 0);
+ ctx[1] = create_context(i915, class, inst, 0);
+
+ map = gem_mmap__cpu(i915, obj[2].handle, 0, 4096, PROT_WRITE);
+
+ cs = map;
+ for (i = 0; i < 10; i++) {
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD |
+ (4 - 2 + (gen >= 12));
+ *cs++ = 0;
+ *cs++ = obj[0].offset + sizeof(uint32_t) * i;
+ *cs++ = 0;
+ if (gen >= 12)
+ *cs++ = 0;
+
+ *cs++ = 0x24 << 23 | 2; /* SRM */
+ *cs++ = mmio + 0x358;
+ *cs++ = obj[1].offset + sizeof(uint32_t) * i;
+ *cs++ = 0;
+
+ *cs++ = MI_STORE_DWORD_IMM;
+ *cs++ = obj[0].offset +
+ 4096 - sizeof(uint32_t) * i - sizeof(uint32_t);
+ *cs++ = 0;
+ *cs++ = 1;
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ cs += 16 - ((cs - map) & 15);
+ start = (cs - map) * sizeof(*cs);
+ for (i = 0; i < 10; i++) {
+ *cs++ = MI_STORE_DWORD_IMM;
+ *cs++ = obj[0].offset + sizeof(uint32_t) * i;
+ *cs++ = 0;
+ *cs++ = 1;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD |
+ (4 - 2 + (gen >= 12));
+ *cs++ = 0;
+ *cs++ = obj[0].offset +
+ 4096 - sizeof(uint32_t) * i - sizeof(uint32_t);
+ *cs++ = 0;
+ if (gen >= 12)
+ *cs++ = 0;
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+ igt_assert(cs - map < 4096 / sizeof(*cs));
+ munmap(map, 4096);
+
+ eb.rsvd1 = ctx[0];
+ gem_execbuf(i915, &eb);
+
+ eb.rsvd1 = ctx[1];
+ eb.batch_start_offset = start;
+ gem_execbuf(i915, &eb);
+
+ gem_sync(i915, obj[2].handle);
+
+ gem_set_domain(i915, obj[1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+ map = gem_mmap__cpu(i915, obj[1].handle, 0, 4096, PROT_WRITE);
+ for (i = 0; i < 9; i++)
+ map[i] = map[i + 1] - map[i];
+ qsort(map, 9, sizeof(*map), cmp_u32);
+ duration *= map[4] / 2; /* 2 sema-waits between timestamp updates */
+ munmap(map, 4096);
+
+ for (i = 0; i < ARRAY_SIZE(ctx); i++)
+ gem_context_destroy(i915, ctx[i]);
+
+ for (i = 0; i < ARRAY_SIZE(obj); i++)
+ gem_close(i915, obj[i].handle);
+
+ return duration;
+}
+
+static void test_duration(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * Timeslicing at its very basic level is sharing the GPU by
+ * running one context for interval before running another. After
+ * each interval the running context is swapped for another runnable
+ * context.
+ *
+ * We can measure this directly by watching the xCS_TIMESTAMP and
+ * recording its value every time we switch into the context, using
+ * a couple of semaphores to busyspin for the timeslice.
+ */
+
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_duration(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms\n",
+ ATTR, delays[i], elapsed * 1e-6);
+
+ /*
+ * We need to give a couple of jiffies slack for the scheduler timeouts
+ * and then a little more slack fr the overhead in submitting and
+ * measuring. 50ms should cover all of our sins and be useful
+ * tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+ "Timeslice exceeded request!\n");
+ }
+
+ gem_quiescent_gpu(i915);
+ set_timeslice(engine, saved);
+}
+
+static uint64_t __test_timeout(int i915, int engine, unsigned int timeout)
+{
+ unsigned int class, inst;
+ struct timespec ts = {};
+ igt_spin_t *spin[2];
+ uint64_t elapsed;
+ uint32_t ctx[2];
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_timeslice(engine, timeout);
+
+ ctx[0] = create_context(i915, class, inst, 0);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 0);
+ igt_nsec_elapsed(&ts);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+ igt_spin_busywait_until_started(spin[1]);
+ elapsed = igt_nsec_elapsed(&ts);
+
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+ gem_quiescent_gpu(i915);
+
+ return elapsed;
+}
+
+static void test_timeout(int i915, int engine)
+{
+ int delays[] = { 1, 50, 100, 500 };
+ unsigned int saved;
+
+ /*
+ * Timeslicing requires us to preempt the running context in order to
+ * switch into its contemporary. If we couple a unpreemptable hog
+ * with a fast forced reset, we can measure the timeslice by how long
+ * it takes for the hog to be reset and the high priority context
+ * to complete.
+ */
+
+ igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ for (int i = 0; i < ARRAY_SIZE(delays); i++) {
+ uint64_t elapsed;
+
+ elapsed = __test_timeout(i915, engine, delays[i]);
+ igt_info("%s:%d, elapsed=%.3fms\n",
+ ATTR, delays[i], elapsed * 1e-6);
+
+ /*
+ * We need to give a couple of jiffies slack for the scheduler timeouts
+ * and then a little more slack fr the overhead in submitting and
+ * measuring. 50ms should cover all of our sins and be useful
+ * tolerance.
+ */
+ igt_assert_f(elapsed / 1000 / 1000 < delays[i] + 50,
+ "Timeslice exceeded request!\n");
+ }
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+ set_timeslice(engine, saved);
+}
+
+static void test_off(int i915, int engine)
+{
+ unsigned int class, inst;
+ unsigned int saved;
+ igt_spin_t *spin[2];
+ uint32_t ctx[2];
+
+ /*
+ * As always, there are some who must run uninterrupted and simply do
+ * not want to share the GPU even for a microsecond. Those greedy
+ * clients can disable timeslicing entirely, and so set the timeslice
+ * to 0. We test that a hog is not preempted within the 150s of
+ * our boredom threshold.
+ */
+
+ igt_require(igt_sysfs_printf(engine, "preempt_timeout_ms", "%u", 1) == 1);
+ igt_assert(igt_sysfs_scanf(engine, ATTR, "%u", &saved) == 1);
+ igt_debug("Initial %s:%u\n", ATTR, saved);
+
+ gem_quiescent_gpu(i915);
+ igt_require(enable_hangcheck(i915, false));
+
+ igt_assert(igt_sysfs_scanf(engine, "class", "%u", &class) == 1);
+ igt_assert(igt_sysfs_scanf(engine, "instance", "%u", &inst) == 1);
+
+ set_timeslice(engine, 0);
+
+ ctx[0] = create_context(i915, class, inst, 0);
+ spin[0] = igt_spin_new(i915, ctx[0],
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT));
+ igt_spin_busywait_until_started(spin[0]);
+
+ ctx[1] = create_context(i915, class, inst, 0);
+ spin[1] = igt_spin_new(i915, ctx[1], .flags = IGT_SPIN_POLL_RUN);
+
+ for (int i = 0; i < 150; i++) {
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), 0);
+ sleep(1);
+ }
+
+ set_timeslice(engine, 1);
+
+ igt_spin_busywait_until_started(spin[1]);
+ igt_spin_free(i915, spin[1]);
+
+ igt_assert_eq(sync_fence_wait(spin[0]->out_fence, 1), 0);
+ igt_assert_eq(sync_fence_status(spin[0]->out_fence), -EIO);
+
+ igt_spin_free(i915, spin[0]);
+
+ gem_context_destroy(i915, ctx[1]);
+ gem_context_destroy(i915, ctx[0]);
+
+ igt_assert(enable_hangcheck(i915, true));
+ gem_quiescent_gpu(i915);
+
+ set_timeslice(engine, saved);
+}
+
+igt_main
+{
+ static const struct {
+ const char *name;
+ void (*fn)(int, int);
+ } tests[] = {
+ { "idempotent", test_idempotent },
+ { "invalid", test_invalid },
+ { "duration", test_duration },
+ { "timeout", test_timeout },
+ { "off", test_off },
+ { }
+ };
+ int i915 = -1, engines = -1;
+
+ igt_fixture {
+ int sys;
+
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ igt_allow_hang(i915, 0, 0);
+
+ sys = igt_sysfs_open(i915);
+ igt_require(sys != -1);
+
+ engines = openat(sys, "engine", O_RDONLY);
+ igt_require(engines != -1);
+
+ close(sys);
+ }
+
+ for (typeof(*tests) *t = tests; t->name; t++)
+ igt_subtest_with_dynamic(t->name)
+ dyn_sysfs_engines(i915, engines, ATTR, t->fn);
+
+ igt_fixture {
+ close(engines);
+ close(i915);
+ }
+}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index eb5c9226a..a3c4239aa 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -61,6 +61,7 @@ igt@gem_userptr_blits@(major|minor|forked|mlocked|swapping).*
igt@gem_wait@.*hang.*
igt@sysfs_heartbeat_timeout@long.*
igt@sysfs_preemption_timeout@off.*
+igt@sysfs_timeslice_duration@off.*
###############################################
# GEM: Not worth fixing
###############################################
diff --git a/tests/meson.build b/tests/meson.build
index bc1af9b1e..0cba10e27 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -228,6 +228,7 @@ i915_progs = [
'i915_suspend',
'sysfs_heartbeat_interval',
'sysfs_preempt_timeout',
+ 'sysfs_timeslice_duration',
]
test_deps = [ igt_deps ]
--
2.25.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: failure for series starting with [i-g-t,1/5] i915: Start putting the mmio_base to wider use
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
` (4 preceding siblings ...)
(?)
@ 2020-02-28 11:15 ` Patchwork
-1 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2020-02-28 11:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/5] i915: Start putting the mmio_base to wider use
URL : https://patchwork.freedesktop.org/series/74073/
State : failure
== Summary ==
ERROR! This series introduces new undocumented tests:
sysfs_heartbeat_interval
sysfs_heartbeat_interval@idempotent
sysfs_heartbeat_interval@invalid
sysfs_heartbeat_interval@long
sysfs_heartbeat_interval@mixed
sysfs_heartbeat_interval@nopreempt
sysfs_heartbeat_interval@off
sysfs_heartbeat_interval@precise
sysfs_preempt_timeout
sysfs_preempt_timeout@idempotent
sysfs_preempt_timeout@invalid
sysfs_preempt_timeout@off
sysfs_preempt_timeout@timeout
sysfs_timeslice_duration
sysfs_timeslice_duration@duration
sysfs_timeslice_duration@idempotent
sysfs_timeslice_duration@invalid
sysfs_timeslice_duration@off
sysfs_timeslice_duration@timeout
Can you document them as per the requirement in the [CONTRIBUTING.md]?
[Documentation] has more details on how to do this.
Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d
Thanks in advance!
[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe
Other than that, pipeline status: SUCCESS.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/113849 for the overview.
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/113849
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/5] i915: Start putting the mmio_base to wider use
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
` (5 preceding siblings ...)
(?)
@ 2020-02-28 11:52 ` Patchwork
-1 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2020-02-28 11:52 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/5] i915: Start putting the mmio_base to wider use
URL : https://patchwork.freedesktop.org/series/74073/
State : success
== Summary ==
CI Bug Log - changes from IGT_5475 -> IGTPW_4238
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_4238:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-u}: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/fi-tgl-u/igt@runner@aborted.html
Known issues
------------
Here are the changes found in IGTPW_4238 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][2] -> [DMESG-WARN][3] ([i915#44])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][4] ([i915#92]) -> [PASS][5] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
- fi-kbl-guc: [SKIP][6] ([fdo#109271]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem_contexts:
- fi-cml-s: [DMESG-FAIL][8] ([i915#877]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-skl-6770hq: [SKIP][10] ([fdo#109271]) -> [PASS][11] +5 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-skl-6770hq: [DMESG-WARN][12] ([i915#106]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Participating hosts (52 -> 44)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5475 -> IGTPW_4238
CI-20190529: 20190529
CI_DRM_8026: 6ce18c241dde9ee20b19ff42f8198552a57ab259 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4238: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/index.html
IGT_5475: ca52e3cb94072f8a6c59f6379f569f79e71a088b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@sysfs_heartbeat_interval@idempotent
+igt@sysfs_heartbeat_interval@invalid
+igt@sysfs_heartbeat_interval@long
+igt@sysfs_heartbeat_interval@mixed
+igt@sysfs_heartbeat_interval@nopreempt
+igt@sysfs_heartbeat_interval@off
+igt@sysfs_heartbeat_interval@precise
+igt@sysfs_preempt_timeout@idempotent
+igt@sysfs_preempt_timeout@invalid
+igt@sysfs_preempt_timeout@off
+igt@sysfs_preempt_timeout@timeout
+igt@sysfs_timeslice_duration@duration
+igt@sysfs_timeslice_duration@idempotent
+igt@sysfs_timeslice_duration@invalid
+igt@sysfs_timeslice_duration@off
+igt@sysfs_timeslice_duration@timeout
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
@ 2020-02-28 19:45 ` Stimson, Dale B
-1 siblings, 0 replies; 30+ messages in thread
From: Stimson, Dale B @ 2020-02-28 19:45 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
On 2020-02-28 10:43:36, Chris Wilson wrote:
> Several tests depend upon the implicit engine->mmio_base but have no
> means of determining the physical layout. Since the kernel has started
> providing this information, start putting it to use.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
> ---
> lib/i915/gem_engine_topology.c | 84 ++++++++++++++++++++++++++++++++++
> lib/i915/gem_engine_topology.h | 5 ++
> tests/i915/gem_ctx_shared.c | 38 +++++----------
> tests/i915/gem_exec_latency.c | 17 ++++---
> 4 files changed, 111 insertions(+), 33 deletions(-)
>
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> index 58dff3208..640777ae4 100644
> --- a/lib/i915/gem_engine_topology.c
> +++ b/lib/i915/gem_engine_topology.c
> @@ -21,7 +21,12 @@
> * IN THE SOFTWARE.
> */
>
> +#include <fcntl.h>
> +#include <unistd.h>
> +
> #include "drmtest.h"
> +#include "igt_sysfs.h"
> +#include "intel_chipset.h"
> #include "ioctl_wrappers.h"
>
> #include "i915/gem_engine_topology.h"
> @@ -327,3 +332,82 @@ bool gem_engine_is_equal(const struct intel_execution_engine2 *e1,
> {
> return e1->class == e2->class && e1->instance == e2->instance;
> }
> +
> +static int descend(int dir, const char *path)
> +{
> + int fd;
> +
> + fd = openat(dir, path, O_RDONLY);
> + close(dir);
> +
> + return fd;
> +}
> +
> +int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
> + const char *fmt, ...)
> +{
> + FILE *file;
> + va_list ap;
> + int ret;
> + int fd;
> +
> + fd = igt_sysfs_open(i915);
> + if (fd < 0)
> + return fd;
> +
> + fd = descend(fd, "engine");
> + if (fd < 0)
> + return fd;
> +
> + fd = descend(fd, engine);
> + if (fd < 0)
> + return fd;
> +
> + fd = descend(fd, attr);
> + if (fd < 0)
> + return fd;
> +
> + file = fdopen(fd, "r");
> + if (!file) {
> + close(fd);
> + return -1;
> + }
> +
> + va_start(ap, fmt);
> + ret = vfscanf(file, fmt, ap);
> + va_end(ap);
> +
> + fclose(file);
> + return ret;
> +}
> +
> +uint32_t gem_engine_mmio_base(int i915, const char *engine)
> +{
> + unsigned int mmio = 0;
> +
> + if (gem_engine_property_scanf(i915, engine, "mmio_base",
> + "%x", &mmio) < 0) {
> + int gen = intel_gen(intel_get_drm_devid(i915));
> +
> + /* The layout of xcs1+ is unreliable -- hence the property! */
> + if (!strcmp(engine, "rcs0")) {
> + mmio = 0x2000;
> + } else if (!strcmp(engine, "bcs0")) {
> + mmio = 0x22000;
> + } else if (!strcmp(engine, "vcs0")) {
> + if (gen < 6)
> + mmio = 0x4000;
> + else if (gen < 11)
> + mmio = 0x12000;
> + else
> + mmio = 0x1c0000;
> + } else if (!strcmp(engine, "vecs0")) {
> + if (gen < 11)
> + mmio = 0x1a000;
> + else
> + mmio = 0x1c8000;
> + }
> + }
> +
> + return mmio;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> index 027d86be2..219c84b72 100644
> --- a/lib/i915/gem_engine_topology.h
> +++ b/lib/i915/gem_engine_topology.h
> @@ -75,4 +75,9 @@ struct intel_execution_engine2 gem_eb_flags_to_engine(unsigned int flags);
> #define __for_each_physical_engine(fd__, e__) \
> ____for_each_physical_engine(fd__, 0, e__)
>
> +__attribute__((format(scanf, 4, 5)))
> +int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
> + const char *fmt, ...);
> +uint32_t gem_engine_mmio_base(int i915, const char *engine);
> +
> #endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
> index 820b96c1a..9ea020d7b 100644
> --- a/tests/i915/gem_ctx_shared.c
> +++ b/tests/i915/gem_ctx_shared.c
> @@ -38,6 +38,7 @@
>
> #include <drm.h>
>
> +#include "i915/gem_engine_topology.h"
> #include "igt_rand.h"
> #include "igt_vgem.h"
> #include "sync_file.h"
> @@ -548,6 +549,14 @@ static uint32_t store_timestamp(int i915,
> return obj.handle;
> }
>
> +static uint32_t ring_base(int i915, unsigned ring)
> +{
> + if (ring == I915_EXEC_DEFAULT)
> + ring = I915_EXEC_RENDER; /* XXX */
> +
> + return gem_engine_mmio_base(i915, gem_eb_flags_to_engine(ring).name);
> +}
> +
> static void independent(int i915, unsigned ring, unsigned flags)
> {
> const int TIMESTAMP = 1023;
> @@ -555,33 +564,8 @@ static void independent(int i915, unsigned ring, unsigned flags)
> igt_spin_t *spin[MAX_ELSP_QLEN];
> unsigned int mmio_base;
>
> - /* XXX i915_query()! */
> - switch (ring) {
> - case I915_EXEC_DEFAULT:
> - case I915_EXEC_RENDER:
> - mmio_base = 0x2000;
> - break;
> -#if 0
> - case I915_EXEC_BSD:
> - mmio_base = 0x12000;
> - break;
> -#endif
> - case I915_EXEC_BLT:
> - mmio_base = 0x22000;
> - break;
> -
> -#define GEN11_VECS0_BASE 0x1c8000
> -#define GEN11_VECS1_BASE 0x1d8000
> - case I915_EXEC_VEBOX:
> - if (intel_gen(intel_get_drm_devid(i915)) >= 11)
> - mmio_base = GEN11_VECS0_BASE;
> - else
> - mmio_base = 0x1a000;
> - break;
> -
> - default:
> - igt_skip("mmio base not known\n");
> - }
> + mmio_base = ring_base(i915, ring);
> + igt_require_f(mmio_base, "mmio base not known\n");
>
> for (int n = 0; n < ARRAY_SIZE(spin); n++) {
> const struct igt_spin_factory opts = {
> diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
> index 3d99182a0..d2159f317 100644
> --- a/tests/i915/gem_exec_latency.c
> +++ b/tests/i915/gem_exec_latency.c
> @@ -109,7 +109,7 @@ poll_ring(int fd, unsigned ring, const char *name)
> igt_spin_free(fd, spin[0]);
> }
>
> -#define RCS_TIMESTAMP (0x2000 + 0x358)
> +#define TIMESTAMP (0x358)
> static void latency_on_ring(int fd,
> unsigned ring, const char *name,
> unsigned flags)
> @@ -119,6 +119,7 @@ static void latency_on_ring(int fd,
> struct drm_i915_gem_exec_object2 obj[3];
> struct drm_i915_gem_relocation_entry reloc;
> struct drm_i915_gem_execbuffer2 execbuf;
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
> igt_spin_t *spin = NULL;
> IGT_CORK_HANDLE(c);
> volatile uint32_t *reg;
> @@ -128,7 +129,8 @@ static void latency_on_ring(int fd,
> double gpu_latency;
> int i, j;
>
> - reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + RCS_TIMESTAMP);
> + igt_require(mmio_base);
> + reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + mmio_base + TIMESTAMP);
>
> memset(&execbuf, 0, sizeof(execbuf));
> execbuf.buffers_ptr = to_user_pointer(&obj[1]);
> @@ -176,7 +178,7 @@ static void latency_on_ring(int fd,
> map[i++] = 0x24 << 23 | 1;
> if (has_64bit_reloc)
> map[i-1]++;
> - map[i++] = RCS_TIMESTAMP; /* ring local! */
> + map[i++] = mmio_base + TIMESTAMP;
> map[i++] = offset;
> if (has_64bit_reloc)
> map[i++] = offset >> 32;
> @@ -266,11 +268,14 @@ static void latency_from_ring(int fd,
> struct drm_i915_gem_exec_object2 obj[3];
> struct drm_i915_gem_relocation_entry reloc;
> struct drm_i915_gem_execbuffer2 execbuf;
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
> const unsigned int repeats = ring_size / 2;
> uint32_t *map, *results;
> uint32_t ctx[2] = {};
> int i, j;
>
> + igt_require(mmio_base);
> +
> if (flags & PREEMPT) {
> ctx[0] = gem_context_create(fd);
> gem_context_set_priority(fd, ctx[0], -1023);
> @@ -351,7 +356,7 @@ static void latency_from_ring(int fd,
> map[i++] = 0x24 << 23 | 1;
> if (has_64bit_reloc)
> map[i-1]++;
> - map[i++] = RCS_TIMESTAMP; /* ring local! */
> + map[i++] = mmio_base + TIMESTAMP;
> map[i++] = offset;
> if (has_64bit_reloc)
> map[i++] = offset >> 32;
> @@ -376,7 +381,7 @@ static void latency_from_ring(int fd,
> map[i++] = 0x24 << 23 | 1;
> if (has_64bit_reloc)
> map[i-1]++;
> - map[i++] = RCS_TIMESTAMP; /* ring local! */
> + map[i++] = mmio_base + TIMESTAMP;
> map[i++] = offset;
> if (has_64bit_reloc)
> map[i++] = offset >> 32;
> @@ -669,7 +674,7 @@ igt_main
> ring_size = 1024;
>
> intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device);
> - rcs_clock = clockrate(device, RCS_TIMESTAMP);
> + rcs_clock = clockrate(device, 0x2000 + TIMESTAMP);
> igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n",
> rcs_clock / 1e3, 1e9 / rcs_clock);
> rcs_clock = 1e9 / rcs_clock;
> --
> 2.25.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use
@ 2020-02-28 19:45 ` Stimson, Dale B
0 siblings, 0 replies; 30+ messages in thread
From: Stimson, Dale B @ 2020-02-28 19:45 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
On 2020-02-28 10:43:36, Chris Wilson wrote:
> Several tests depend upon the implicit engine->mmio_base but have no
> means of determining the physical layout. Since the kernel has started
> providing this information, start putting it to use.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
> ---
> lib/i915/gem_engine_topology.c | 84 ++++++++++++++++++++++++++++++++++
> lib/i915/gem_engine_topology.h | 5 ++
> tests/i915/gem_ctx_shared.c | 38 +++++----------
> tests/i915/gem_exec_latency.c | 17 ++++---
> 4 files changed, 111 insertions(+), 33 deletions(-)
>
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> index 58dff3208..640777ae4 100644
> --- a/lib/i915/gem_engine_topology.c
> +++ b/lib/i915/gem_engine_topology.c
> @@ -21,7 +21,12 @@
> * IN THE SOFTWARE.
> */
>
> +#include <fcntl.h>
> +#include <unistd.h>
> +
> #include "drmtest.h"
> +#include "igt_sysfs.h"
> +#include "intel_chipset.h"
> #include "ioctl_wrappers.h"
>
> #include "i915/gem_engine_topology.h"
> @@ -327,3 +332,82 @@ bool gem_engine_is_equal(const struct intel_execution_engine2 *e1,
> {
> return e1->class == e2->class && e1->instance == e2->instance;
> }
> +
> +static int descend(int dir, const char *path)
> +{
> + int fd;
> +
> + fd = openat(dir, path, O_RDONLY);
> + close(dir);
> +
> + return fd;
> +}
> +
> +int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
> + const char *fmt, ...)
> +{
> + FILE *file;
> + va_list ap;
> + int ret;
> + int fd;
> +
> + fd = igt_sysfs_open(i915);
> + if (fd < 0)
> + return fd;
> +
> + fd = descend(fd, "engine");
> + if (fd < 0)
> + return fd;
> +
> + fd = descend(fd, engine);
> + if (fd < 0)
> + return fd;
> +
> + fd = descend(fd, attr);
> + if (fd < 0)
> + return fd;
> +
> + file = fdopen(fd, "r");
> + if (!file) {
> + close(fd);
> + return -1;
> + }
> +
> + va_start(ap, fmt);
> + ret = vfscanf(file, fmt, ap);
> + va_end(ap);
> +
> + fclose(file);
> + return ret;
> +}
> +
> +uint32_t gem_engine_mmio_base(int i915, const char *engine)
> +{
> + unsigned int mmio = 0;
> +
> + if (gem_engine_property_scanf(i915, engine, "mmio_base",
> + "%x", &mmio) < 0) {
> + int gen = intel_gen(intel_get_drm_devid(i915));
> +
> + /* The layout of xcs1+ is unreliable -- hence the property! */
> + if (!strcmp(engine, "rcs0")) {
> + mmio = 0x2000;
> + } else if (!strcmp(engine, "bcs0")) {
> + mmio = 0x22000;
> + } else if (!strcmp(engine, "vcs0")) {
> + if (gen < 6)
> + mmio = 0x4000;
> + else if (gen < 11)
> + mmio = 0x12000;
> + else
> + mmio = 0x1c0000;
> + } else if (!strcmp(engine, "vecs0")) {
> + if (gen < 11)
> + mmio = 0x1a000;
> + else
> + mmio = 0x1c8000;
> + }
> + }
> +
> + return mmio;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> index 027d86be2..219c84b72 100644
> --- a/lib/i915/gem_engine_topology.h
> +++ b/lib/i915/gem_engine_topology.h
> @@ -75,4 +75,9 @@ struct intel_execution_engine2 gem_eb_flags_to_engine(unsigned int flags);
> #define __for_each_physical_engine(fd__, e__) \
> ____for_each_physical_engine(fd__, 0, e__)
>
> +__attribute__((format(scanf, 4, 5)))
> +int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
> + const char *fmt, ...);
> +uint32_t gem_engine_mmio_base(int i915, const char *engine);
> +
> #endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
> index 820b96c1a..9ea020d7b 100644
> --- a/tests/i915/gem_ctx_shared.c
> +++ b/tests/i915/gem_ctx_shared.c
> @@ -38,6 +38,7 @@
>
> #include <drm.h>
>
> +#include "i915/gem_engine_topology.h"
> #include "igt_rand.h"
> #include "igt_vgem.h"
> #include "sync_file.h"
> @@ -548,6 +549,14 @@ static uint32_t store_timestamp(int i915,
> return obj.handle;
> }
>
> +static uint32_t ring_base(int i915, unsigned ring)
> +{
> + if (ring == I915_EXEC_DEFAULT)
> + ring = I915_EXEC_RENDER; /* XXX */
> +
> + return gem_engine_mmio_base(i915, gem_eb_flags_to_engine(ring).name);
> +}
> +
> static void independent(int i915, unsigned ring, unsigned flags)
> {
> const int TIMESTAMP = 1023;
> @@ -555,33 +564,8 @@ static void independent(int i915, unsigned ring, unsigned flags)
> igt_spin_t *spin[MAX_ELSP_QLEN];
> unsigned int mmio_base;
>
> - /* XXX i915_query()! */
> - switch (ring) {
> - case I915_EXEC_DEFAULT:
> - case I915_EXEC_RENDER:
> - mmio_base = 0x2000;
> - break;
> -#if 0
> - case I915_EXEC_BSD:
> - mmio_base = 0x12000;
> - break;
> -#endif
> - case I915_EXEC_BLT:
> - mmio_base = 0x22000;
> - break;
> -
> -#define GEN11_VECS0_BASE 0x1c8000
> -#define GEN11_VECS1_BASE 0x1d8000
> - case I915_EXEC_VEBOX:
> - if (intel_gen(intel_get_drm_devid(i915)) >= 11)
> - mmio_base = GEN11_VECS0_BASE;
> - else
> - mmio_base = 0x1a000;
> - break;
> -
> - default:
> - igt_skip("mmio base not known\n");
> - }
> + mmio_base = ring_base(i915, ring);
> + igt_require_f(mmio_base, "mmio base not known\n");
>
> for (int n = 0; n < ARRAY_SIZE(spin); n++) {
> const struct igt_spin_factory opts = {
> diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
> index 3d99182a0..d2159f317 100644
> --- a/tests/i915/gem_exec_latency.c
> +++ b/tests/i915/gem_exec_latency.c
> @@ -109,7 +109,7 @@ poll_ring(int fd, unsigned ring, const char *name)
> igt_spin_free(fd, spin[0]);
> }
>
> -#define RCS_TIMESTAMP (0x2000 + 0x358)
> +#define TIMESTAMP (0x358)
> static void latency_on_ring(int fd,
> unsigned ring, const char *name,
> unsigned flags)
> @@ -119,6 +119,7 @@ static void latency_on_ring(int fd,
> struct drm_i915_gem_exec_object2 obj[3];
> struct drm_i915_gem_relocation_entry reloc;
> struct drm_i915_gem_execbuffer2 execbuf;
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
> igt_spin_t *spin = NULL;
> IGT_CORK_HANDLE(c);
> volatile uint32_t *reg;
> @@ -128,7 +129,8 @@ static void latency_on_ring(int fd,
> double gpu_latency;
> int i, j;
>
> - reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + RCS_TIMESTAMP);
> + igt_require(mmio_base);
> + reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + mmio_base + TIMESTAMP);
>
> memset(&execbuf, 0, sizeof(execbuf));
> execbuf.buffers_ptr = to_user_pointer(&obj[1]);
> @@ -176,7 +178,7 @@ static void latency_on_ring(int fd,
> map[i++] = 0x24 << 23 | 1;
> if (has_64bit_reloc)
> map[i-1]++;
> - map[i++] = RCS_TIMESTAMP; /* ring local! */
> + map[i++] = mmio_base + TIMESTAMP;
> map[i++] = offset;
> if (has_64bit_reloc)
> map[i++] = offset >> 32;
> @@ -266,11 +268,14 @@ static void latency_from_ring(int fd,
> struct drm_i915_gem_exec_object2 obj[3];
> struct drm_i915_gem_relocation_entry reloc;
> struct drm_i915_gem_execbuffer2 execbuf;
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, name);
> const unsigned int repeats = ring_size / 2;
> uint32_t *map, *results;
> uint32_t ctx[2] = {};
> int i, j;
>
> + igt_require(mmio_base);
> +
> if (flags & PREEMPT) {
> ctx[0] = gem_context_create(fd);
> gem_context_set_priority(fd, ctx[0], -1023);
> @@ -351,7 +356,7 @@ static void latency_from_ring(int fd,
> map[i++] = 0x24 << 23 | 1;
> if (has_64bit_reloc)
> map[i-1]++;
> - map[i++] = RCS_TIMESTAMP; /* ring local! */
> + map[i++] = mmio_base + TIMESTAMP;
> map[i++] = offset;
> if (has_64bit_reloc)
> map[i++] = offset >> 32;
> @@ -376,7 +381,7 @@ static void latency_from_ring(int fd,
> map[i++] = 0x24 << 23 | 1;
> if (has_64bit_reloc)
> map[i-1]++;
> - map[i++] = RCS_TIMESTAMP; /* ring local! */
> + map[i++] = mmio_base + TIMESTAMP;
> map[i++] = offset;
> if (has_64bit_reloc)
> map[i++] = offset >> 32;
> @@ -669,7 +674,7 @@ igt_main
> ring_size = 1024;
>
> intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device);
> - rcs_clock = clockrate(device, RCS_TIMESTAMP);
> + rcs_clock = clockrate(device, 0x2000 + TIMESTAMP);
> igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n",
> rcs_clock / 1e3, 1e9 / rcs_clock);
> rcs_clock = 1e9 / rcs_clock;
> --
> 2.25.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 2/5] i915/gem_ctx_isolation: Check engine relative registers
2020-02-28 10:43 ` [Intel-gfx] [PATCH i-g-t 2/5] i915/gem_ctx_isolation: Check engine relative registers Chris Wilson
@ 2020-02-28 19:46 ` Stimson, Dale B
0 siblings, 0 replies; 30+ messages in thread
From: Stimson, Dale B @ 2020-02-28 19:46 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
On 2020-02-28 10:43:37, Chris Wilson wrote:
> Some of the non-privileged registers are at the same offset on each
> engine. We can improve our coverage for unknown HW layout by using the
> reported engine->mmio_base for relative offsets.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
> ---
> tests/i915/gem_ctx_isolation.c | 164 ++++++++++++++++++++-------------
> 1 file changed, 100 insertions(+), 64 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 1b66fec11..eff4b1df2 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -70,6 +70,7 @@ static const struct named_register {
> uint32_t ignore_bits;
> uint32_t write_mask; /* some registers bits do not exist */
> bool masked;
> + bool relative;
> } nonpriv_registers[] = {
> { "NOPID", NOCTX, RCS0, 0x2094 },
> { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> @@ -109,7 +110,6 @@ static const struct named_register {
> { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
> { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> - { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> { "OACTXID", GEN8, RCS0, 0x2364 },
> { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
> @@ -138,79 +138,56 @@ static const struct named_register {
>
> { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
> { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
> - { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
>
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
> { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> { "COMMON_SLICE_CHICKEN2", GEN_RANGE(9, 9), RCS0, 0x7014, .masked = true },
> - { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
> { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(11, 11) /* + glk */, RCS0, 0x731c, .masked = true },
> { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
> { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true },
> { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
>
> - { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
> { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
>
> { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
> { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
>
> - { "VCS0_GPR", GEN_RANGE(9, 10), VCS0, 0x12600, 32 },
> - { "VCS1_GPR", GEN_RANGE(9, 10), VCS1, 0x1c600, 32 },
> - { "VECS_GPR", GEN_RANGE(9, 10), VECS0, 0x1a600, 32 },
> -
> - { "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 },
> - { "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 },
> - { "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 },
> - { "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 },
> - { "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 },
> + { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
>
> {}
> }, ignore_registers[] = {
> { "RCS timestamp", GEN6, ~0u, 0x2358 },
> { "BCS timestamp", GEN7, ~0u, 0x22358 },
>
> - { "VCS0 timestamp", GEN_RANGE(7, 10), ~0u, 0x12358 },
> - { "VCS1 timestamp", GEN_RANGE(7, 10), ~0u, 0x1c358 },
> - { "VECS timestamp", GEN_RANGE(8, 10), ~0u, 0x1a358 },
> -
> - { "VCS0 timestamp", GEN11, ~0u, 0x1c0358 },
> - { "VCS1 timestamp", GEN11, ~0u, 0x1c4358 },
> - { "VCS2 timestamp", GEN11, ~0u, 0x1d0358 },
> - { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
> - { "VECS timestamp", GEN11, ~0u, 0x1c8358 },
> + { "xCS timestamp", GEN8, ALL, 0x358, .relative = true },
>
> /* huc read only */
> - { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2000 },
> - { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2014 },
> - { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x23b0 },
> -
> - { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
> - { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
> - { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
> -
> - { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2000 },
> - { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2014 },
> - { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x23b0 },
> -
> - { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
> - { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
> - { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
> + { "BSD 0x2000", GEN11, ALL, 0x2000, .relative = true },
> + { "BSD 0x2014", GEN11, ALL, 0x2014, .relative = true },
> + { "BSD 0x23b0", GEN11, ALL, 0x23b0, .relative = true },
>
> {}
> };
>
> -static const char *register_name(uint32_t offset, char *buf, size_t len)
> +static const char *
> +register_name(uint32_t offset, uint32_t mmio_base, char *buf, size_t len)
> {
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> unsigned int width = r->count ? 4*r->count : 4;
> - if (offset >= r->offset && offset < r->offset + width) {
> + uint32_t base;
> +
> + base = r->offset;
> + if (r->relative)
> + base += mmio_base;
> +
> + if (offset >= base && offset < base + width) {
> if (r->count <= 1)
> return r->name;
>
> snprintf(buf, len, "%s[%d]",
> - r->name, (offset - r->offset)/4);
> + r->name, (offset - base) / 4);
> return buf;
> }
> }
> @@ -218,22 +195,35 @@ static const char *register_name(uint32_t offset, char *buf, size_t len)
> return "unknown";
> }
>
> -static const struct named_register *lookup_register(uint32_t offset)
> +static const struct named_register *
> +lookup_register(uint32_t offset, uint32_t mmio_base)
> {
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> unsigned int width = r->count ? 4*r->count : 4;
> - if (offset >= r->offset && offset < r->offset + width)
> + uint32_t base;
> +
> + base = r->offset;
> + if (r->relative)
> + base += mmio_base;
> +
> + if (offset >= base && offset < base + width)
> return r;
> }
>
> return NULL;
> }
>
> -static bool ignore_register(uint32_t offset)
> +static bool ignore_register(uint32_t offset, uint32_t mmio_base)
> {
> for (const struct named_register *r = ignore_registers; r->name; r++) {
> unsigned int width = r->count ? 4*r->count : 4;
> - if (offset >= r->offset && offset < r->offset + width)
> + uint32_t base;
> +
> + base = r->offset;
> + if (r->relative)
> + base += mmio_base;
> +
> + if (offset >= base && offset < base + width)
> return true;
> }
>
> @@ -248,6 +238,7 @@ static void tmpl_regs(int fd,
> {
> const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> unsigned int regs_size;
> uint32_t *regs;
>
> @@ -259,12 +250,20 @@ static void tmpl_regs(int fd,
> I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
>
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
> +
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> uint32_t x = value;
> if (r->write_mask)
> x &= r->write_mask;
> @@ -284,6 +283,7 @@ static uint32_t read_regs(int fd,
> const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> const unsigned int gen_bit = 1 << gen;
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> const bool r64b = gen >= 8;
> struct drm_i915_gem_exec_object2 obj[2];
> struct drm_i915_gem_relocation_entry *reloc;
> @@ -311,13 +311,20 @@ static uint32_t read_regs(int fd,
>
> n = 0;
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
>
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> *b++ = 0x24 << 23 | (1 + r64b); /* SRM */
> *b++ = offset;
> reloc[n].target_handle = obj[0].handle;
> @@ -357,6 +364,7 @@ static void write_regs(int fd,
> {
> const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> struct drm_i915_gem_exec_object2 obj;
> struct drm_i915_gem_execbuffer2 execbuf;
> unsigned int batch_size;
> @@ -372,12 +380,20 @@ static void write_regs(int fd,
> gem_set_domain(fd, obj.handle,
> I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
> +
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> uint32_t x = value;
> if (r->write_mask)
> x &= r->write_mask;
> @@ -410,6 +426,7 @@ static void restore_regs(int fd,
> const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> const unsigned int gen_bit = 1 << gen;
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> const bool r64b = gen >= 8;
> struct drm_i915_gem_exec_object2 obj[2];
> struct drm_i915_gem_execbuffer2 execbuf;
> @@ -437,13 +454,20 @@ static void restore_regs(int fd,
>
> n = 0;
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
>
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> *b++ = 0x29 << 23 | (1 + r64b); /* LRM */
> *b++ = offset;
> reloc[n].target_handle = obj[0].handle;
> @@ -479,6 +503,7 @@ static void dump_regs(int fd,
> const int gen = intel_gen(intel_get_drm_devid(fd));
> const unsigned int gen_bit = 1 << gen;
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> unsigned int regs_size;
> uint32_t *out;
>
> @@ -489,26 +514,36 @@ static void dump_regs(int fd,
> gem_set_domain(fd, regs, I915_GEM_DOMAIN_CPU, 0);
>
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
>
> if (r->count <= 1) {
> igt_debug("0x%04x (%s): 0x%08x\n",
> - r->offset, r->name, out[r->offset/4]);
> + offset, r->name, out[offset / 4]);
> } else {
> for (unsigned x = 0; x < r->count; x++)
> igt_debug("0x%04x (%s[%d]): 0x%08x\n",
> - r->offset+4*x, r->name, x,
> - out[r->offset/4 + x]);
> + offset + 4 * x, r->name, x,
> + out[offset / 4 + x]);
> }
> }
> munmap(out, regs_size);
> }
>
> -static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> +static void compare_regs(int fd, const struct intel_execution_engine2 *e,
> + uint32_t A, uint32_t B, const char *who)
> {
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> unsigned int num_errors;
> unsigned int regs_size;
> uint32_t *a, *b;
> @@ -532,11 +567,11 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> if (a[n] == b[n])
> continue;
>
> - if (ignore_register(offset))
> + if (ignore_register(offset, mmio_base))
> continue;
>
> mask = ~0u;
> - r = lookup_register(offset);
> + r = lookup_register(offset, mmio_base);
> if (r && r->masked)
> mask >>= 16;
> if (r && r->ignore_bits)
> @@ -547,7 +582,7 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
>
> igt_warn("Register 0x%04x (%s): A=%08x B=%08x\n",
> offset,
> - register_name(offset, buf, sizeof(buf)),
> + register_name(offset, mmio_base, buf, sizeof(buf)),
> a[n] & mask, b[n] & mask);
> num_errors++;
> }
> @@ -638,7 +673,7 @@ static void nonpriv(int fd,
>
> igt_spin_free(fd, spin);
>
> - compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
> + compare_regs(fd, e, tmpl, regs[1], "nonpriv read/writes");
>
> for (int n = 0; n < ARRAY_SIZE(regs); n++)
> gem_close(fd, regs[n]);
> @@ -707,8 +742,9 @@ static void isolation(int fd,
> igt_spin_free(fd, spin);
>
> if (!(flags & DIRTY1))
> - compare_regs(fd, regs[0], tmp, "two reads of the same ctx");
> - compare_regs(fd, regs[0], regs[1], "two virgin contexts");
> + compare_regs(fd, e, regs[0], tmp,
> + "two reads of the same ctx");
> + compare_regs(fd, e, regs[0], regs[1], "two virgin contexts");
>
> for (int n = 0; n < ARRAY_SIZE(ctx); n++) {
> gem_close(fd, regs[n]);
> @@ -827,13 +863,13 @@ static void preservation(int fd,
> char buf[80];
>
> snprintf(buf, sizeof(buf), "dirty %x context\n", values[v]);
> - compare_regs(fd, regs[v][0], regs[v][1], buf);
> + compare_regs(fd, e, regs[v][0], regs[v][1], buf);
>
> gem_close(fd, regs[v][0]);
> gem_close(fd, regs[v][1]);
> gem_context_destroy(fd, ctx[v]);
> }
> - compare_regs(fd, regs[num_values][0], regs[num_values][1], "clean");
> + compare_regs(fd, e, regs[num_values][0], regs[num_values][1], "clean");
> gem_context_destroy(fd, ctx[num_values]);
> }
>
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/5] i915/gem_ctx_isolation: Check engine relative registers
@ 2020-02-28 19:46 ` Stimson, Dale B
0 siblings, 0 replies; 30+ messages in thread
From: Stimson, Dale B @ 2020-02-28 19:46 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
On 2020-02-28 10:43:37, Chris Wilson wrote:
> Some of the non-privileged registers are at the same offset on each
> engine. We can improve our coverage for unknown HW layout by using the
> reported engine->mmio_base for relative offsets.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
> ---
> tests/i915/gem_ctx_isolation.c | 164 ++++++++++++++++++++-------------
> 1 file changed, 100 insertions(+), 64 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 1b66fec11..eff4b1df2 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -70,6 +70,7 @@ static const struct named_register {
> uint32_t ignore_bits;
> uint32_t write_mask; /* some registers bits do not exist */
> bool masked;
> + bool relative;
> } nonpriv_registers[] = {
> { "NOPID", NOCTX, RCS0, 0x2094 },
> { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> @@ -109,7 +110,6 @@ static const struct named_register {
> { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
> { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> - { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> { "OACTXID", GEN8, RCS0, 0x2364 },
> { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
> @@ -138,79 +138,56 @@ static const struct named_register {
>
> { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
> { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
> - { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
>
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
> { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> { "COMMON_SLICE_CHICKEN2", GEN_RANGE(9, 9), RCS0, 0x7014, .masked = true },
> - { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
> { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(11, 11) /* + glk */, RCS0, 0x731c, .masked = true },
> { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
> { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true },
> { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
>
> - { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
> { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
>
> { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
> { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
>
> - { "VCS0_GPR", GEN_RANGE(9, 10), VCS0, 0x12600, 32 },
> - { "VCS1_GPR", GEN_RANGE(9, 10), VCS1, 0x1c600, 32 },
> - { "VECS_GPR", GEN_RANGE(9, 10), VECS0, 0x1a600, 32 },
> -
> - { "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 },
> - { "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 },
> - { "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 },
> - { "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 },
> - { "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 },
> + { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
>
> {}
> }, ignore_registers[] = {
> { "RCS timestamp", GEN6, ~0u, 0x2358 },
> { "BCS timestamp", GEN7, ~0u, 0x22358 },
>
> - { "VCS0 timestamp", GEN_RANGE(7, 10), ~0u, 0x12358 },
> - { "VCS1 timestamp", GEN_RANGE(7, 10), ~0u, 0x1c358 },
> - { "VECS timestamp", GEN_RANGE(8, 10), ~0u, 0x1a358 },
> -
> - { "VCS0 timestamp", GEN11, ~0u, 0x1c0358 },
> - { "VCS1 timestamp", GEN11, ~0u, 0x1c4358 },
> - { "VCS2 timestamp", GEN11, ~0u, 0x1d0358 },
> - { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
> - { "VECS timestamp", GEN11, ~0u, 0x1c8358 },
> + { "xCS timestamp", GEN8, ALL, 0x358, .relative = true },
>
> /* huc read only */
> - { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2000 },
> - { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2014 },
> - { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x23b0 },
> -
> - { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
> - { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
> - { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
> -
> - { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2000 },
> - { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2014 },
> - { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x23b0 },
> -
> - { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
> - { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
> - { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
> + { "BSD 0x2000", GEN11, ALL, 0x2000, .relative = true },
> + { "BSD 0x2014", GEN11, ALL, 0x2014, .relative = true },
> + { "BSD 0x23b0", GEN11, ALL, 0x23b0, .relative = true },
>
> {}
> };
>
> -static const char *register_name(uint32_t offset, char *buf, size_t len)
> +static const char *
> +register_name(uint32_t offset, uint32_t mmio_base, char *buf, size_t len)
> {
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> unsigned int width = r->count ? 4*r->count : 4;
> - if (offset >= r->offset && offset < r->offset + width) {
> + uint32_t base;
> +
> + base = r->offset;
> + if (r->relative)
> + base += mmio_base;
> +
> + if (offset >= base && offset < base + width) {
> if (r->count <= 1)
> return r->name;
>
> snprintf(buf, len, "%s[%d]",
> - r->name, (offset - r->offset)/4);
> + r->name, (offset - base) / 4);
> return buf;
> }
> }
> @@ -218,22 +195,35 @@ static const char *register_name(uint32_t offset, char *buf, size_t len)
> return "unknown";
> }
>
> -static const struct named_register *lookup_register(uint32_t offset)
> +static const struct named_register *
> +lookup_register(uint32_t offset, uint32_t mmio_base)
> {
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> unsigned int width = r->count ? 4*r->count : 4;
> - if (offset >= r->offset && offset < r->offset + width)
> + uint32_t base;
> +
> + base = r->offset;
> + if (r->relative)
> + base += mmio_base;
> +
> + if (offset >= base && offset < base + width)
> return r;
> }
>
> return NULL;
> }
>
> -static bool ignore_register(uint32_t offset)
> +static bool ignore_register(uint32_t offset, uint32_t mmio_base)
> {
> for (const struct named_register *r = ignore_registers; r->name; r++) {
> unsigned int width = r->count ? 4*r->count : 4;
> - if (offset >= r->offset && offset < r->offset + width)
> + uint32_t base;
> +
> + base = r->offset;
> + if (r->relative)
> + base += mmio_base;
> +
> + if (offset >= base && offset < base + width)
> return true;
> }
>
> @@ -248,6 +238,7 @@ static void tmpl_regs(int fd,
> {
> const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> unsigned int regs_size;
> uint32_t *regs;
>
> @@ -259,12 +250,20 @@ static void tmpl_regs(int fd,
> I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
>
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
> +
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> uint32_t x = value;
> if (r->write_mask)
> x &= r->write_mask;
> @@ -284,6 +283,7 @@ static uint32_t read_regs(int fd,
> const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> const unsigned int gen_bit = 1 << gen;
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> const bool r64b = gen >= 8;
> struct drm_i915_gem_exec_object2 obj[2];
> struct drm_i915_gem_relocation_entry *reloc;
> @@ -311,13 +311,20 @@ static uint32_t read_regs(int fd,
>
> n = 0;
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
>
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> *b++ = 0x24 << 23 | (1 + r64b); /* SRM */
> *b++ = offset;
> reloc[n].target_handle = obj[0].handle;
> @@ -357,6 +364,7 @@ static void write_regs(int fd,
> {
> const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> struct drm_i915_gem_exec_object2 obj;
> struct drm_i915_gem_execbuffer2 execbuf;
> unsigned int batch_size;
> @@ -372,12 +380,20 @@ static void write_regs(int fd,
> gem_set_domain(fd, obj.handle,
> I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
> +
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> uint32_t x = value;
> if (r->write_mask)
> x &= r->write_mask;
> @@ -410,6 +426,7 @@ static void restore_regs(int fd,
> const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> const unsigned int gen_bit = 1 << gen;
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> const bool r64b = gen >= 8;
> struct drm_i915_gem_exec_object2 obj[2];
> struct drm_i915_gem_execbuffer2 execbuf;
> @@ -437,13 +454,20 @@ static void restore_regs(int fd,
>
> n = 0;
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
>
> - for (unsigned count = r->count ?: 1, offset = r->offset;
> - count--; offset += 4) {
> + for (unsigned count = r->count ?: 1; count--; offset += 4) {
> *b++ = 0x29 << 23 | (1 + r64b); /* LRM */
> *b++ = offset;
> reloc[n].target_handle = obj[0].handle;
> @@ -479,6 +503,7 @@ static void dump_regs(int fd,
> const int gen = intel_gen(intel_get_drm_devid(fd));
> const unsigned int gen_bit = 1 << gen;
> const unsigned int engine_bit = ENGINE(e->class, e->instance);
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> unsigned int regs_size;
> uint32_t *out;
>
> @@ -489,26 +514,36 @@ static void dump_regs(int fd,
> gem_set_domain(fd, regs, I915_GEM_DOMAIN_CPU, 0);
>
> for (const struct named_register *r = nonpriv_registers; r->name; r++) {
> + uint32_t offset;
> +
> if (!(r->engine_mask & engine_bit))
> continue;
> if (!(r->gen_mask & gen_bit))
> continue;
> + if (r->relative && !mmio_base)
> + continue;
> +
> + offset = r->offset;
> + if (r->relative)
> + offset += mmio_base;
>
> if (r->count <= 1) {
> igt_debug("0x%04x (%s): 0x%08x\n",
> - r->offset, r->name, out[r->offset/4]);
> + offset, r->name, out[offset / 4]);
> } else {
> for (unsigned x = 0; x < r->count; x++)
> igt_debug("0x%04x (%s[%d]): 0x%08x\n",
> - r->offset+4*x, r->name, x,
> - out[r->offset/4 + x]);
> + offset + 4 * x, r->name, x,
> + out[offset / 4 + x]);
> }
> }
> munmap(out, regs_size);
> }
>
> -static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> +static void compare_regs(int fd, const struct intel_execution_engine2 *e,
> + uint32_t A, uint32_t B, const char *who)
> {
> + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> unsigned int num_errors;
> unsigned int regs_size;
> uint32_t *a, *b;
> @@ -532,11 +567,11 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
> if (a[n] == b[n])
> continue;
>
> - if (ignore_register(offset))
> + if (ignore_register(offset, mmio_base))
> continue;
>
> mask = ~0u;
> - r = lookup_register(offset);
> + r = lookup_register(offset, mmio_base);
> if (r && r->masked)
> mask >>= 16;
> if (r && r->ignore_bits)
> @@ -547,7 +582,7 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
>
> igt_warn("Register 0x%04x (%s): A=%08x B=%08x\n",
> offset,
> - register_name(offset, buf, sizeof(buf)),
> + register_name(offset, mmio_base, buf, sizeof(buf)),
> a[n] & mask, b[n] & mask);
> num_errors++;
> }
> @@ -638,7 +673,7 @@ static void nonpriv(int fd,
>
> igt_spin_free(fd, spin);
>
> - compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
> + compare_regs(fd, e, tmpl, regs[1], "nonpriv read/writes");
>
> for (int n = 0; n < ARRAY_SIZE(regs); n++)
> gem_close(fd, regs[n]);
> @@ -707,8 +742,9 @@ static void isolation(int fd,
> igt_spin_free(fd, spin);
>
> if (!(flags & DIRTY1))
> - compare_regs(fd, regs[0], tmp, "two reads of the same ctx");
> - compare_regs(fd, regs[0], regs[1], "two virgin contexts");
> + compare_regs(fd, e, regs[0], tmp,
> + "two reads of the same ctx");
> + compare_regs(fd, e, regs[0], regs[1], "two virgin contexts");
>
> for (int n = 0; n < ARRAY_SIZE(ctx); n++) {
> gem_close(fd, regs[n]);
> @@ -827,13 +863,13 @@ static void preservation(int fd,
> char buf[80];
>
> snprintf(buf, sizeof(buf), "dirty %x context\n", values[v]);
> - compare_regs(fd, regs[v][0], regs[v][1], buf);
> + compare_regs(fd, e, regs[v][0], regs[v][1], buf);
>
> gem_close(fd, regs[v][0]);
> gem_close(fd, regs[v][1]);
> gem_context_destroy(fd, ctx[v]);
> }
> - compare_regs(fd, regs[num_values][0], regs[num_values][1], "clean");
> + compare_regs(fd, e, regs[num_values][0], regs[num_values][1], "clean");
> gem_context_destroy(fd, ctx[num_values]);
> }
>
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
@ 2020-02-28 21:27 ` Andi Shyti
-1 siblings, 0 replies; 30+ messages in thread
From: Andi Shyti @ 2020-02-28 21:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
Hi Chris,
On Fri, Feb 28, 2020 at 10:43:36AM +0000, Chris Wilson wrote:
> Several tests depend upon the implicit engine->mmio_base but have no
> means of determining the physical layout. Since the kernel has started
> providing this information, start putting it to use.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Looks good!
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Andi
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use
@ 2020-02-28 21:27 ` Andi Shyti
0 siblings, 0 replies; 30+ messages in thread
From: Andi Shyti @ 2020-02-28 21:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
Hi Chris,
On Fri, Feb 28, 2020 at 10:43:36AM +0000, Chris Wilson wrote:
> Several tests depend upon the implicit engine->mmio_base but have no
> means of determining the physical layout. Since the kernel has started
> providing this information, start putting it to use.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Looks good!
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Andi
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
(?)
@ 2020-02-28 23:27 ` Andi Shyti
2020-02-28 23:32 ` [igt-dev] " Chris Wilson
-1 siblings, 1 reply; 30+ messages in thread
From: Andi Shyti @ 2020-02-28 23:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
Hi Chris,
> +static int create_ext_ioctl(int i915,
> + struct drm_i915_gem_context_create_ext *arg)
> +{
> + int err;
> +
> + err = 0;
> + if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
> + err = -errno;
> + igt_assume(err);
> + }
> +
> + errno = 0;
> + return err;
> +}
> +
> /**
> * gem_has_contexts:
> * @fd: open i915 drm file descriptor
> @@ -324,17 +339,14 @@ __gem_context_clone(int i915,
> .flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> .extensions = to_user_pointer(&clone),
> };
> - int err = 0;
> + int err;
>
> - if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &arg)) {
> - err = -errno;
> - igt_assume(err);
> - }
> + err = create_ext_ioctl(i915, &arg);
> + if (err)
> + return err;
>
> *out = arg.ctx_id;
> -
> - errno = 0;
> - return err;
> + return 0;
> }
>
> static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
> @@ -382,16 +394,8 @@ bool gem_has_context_clone(int i915)
> .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> .extensions = to_user_pointer(&ext),
> };
> - int err;
> -
> - err = 0;
> - if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create)) {
> - err = -errno;
> - igt_assume(err);
> - }
> - errno = 0;
>
> - return err == -ENOENT;
> + return create_ext_ioctl(i915, &create) == -ENOENT;
> }
I'd like to see the above in a separate patch.
> +void dyn_sysfs_engines(int i915, int engines, const char *file,
> + void (*test)(int, int))
> +{
> + char buf[512];
> + int len;
> +
> + lseek(engines, 0, SEEK_SET);
> + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> + void *ptr = buf;
> +
> + while (len) {
> + struct linux_dirent64 {
> + ino64_t d_ino;
> + off64_t d_off;
> + unsigned short d_reclen;
> + unsigned char d_type;
> + char d_name[];
> + } *de = ptr;
what is the need for having your own linux_dirent64?
All the rest look good.
Andi
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-28 23:27 ` [Intel-gfx] " Andi Shyti
@ 2020-02-28 23:32 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 23:32 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx
Quoting Andi Shyti (2020-02-28 23:27:04)
> Hi Chris,
>
> > +static int create_ext_ioctl(int i915,
> > + struct drm_i915_gem_context_create_ext *arg)
> > +{
> > + int err;
> > +
> > + err = 0;
> > + if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
> > + err = -errno;
> > + igt_assume(err);
> > + }
> > +
> > + errno = 0;
> > + return err;
> > +}
> > +
> > /**
> > * gem_has_contexts:
> > * @fd: open i915 drm file descriptor
> > @@ -324,17 +339,14 @@ __gem_context_clone(int i915,
> > .flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> > .extensions = to_user_pointer(&clone),
> > };
> > - int err = 0;
> > + int err;
> >
> > - if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &arg)) {
> > - err = -errno;
> > - igt_assume(err);
> > - }
> > + err = create_ext_ioctl(i915, &arg);
> > + if (err)
> > + return err;
> >
> > *out = arg.ctx_id;
> > -
> > - errno = 0;
> > - return err;
> > + return 0;
> > }
> >
> > static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
> > @@ -382,16 +394,8 @@ bool gem_has_context_clone(int i915)
> > .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> > .extensions = to_user_pointer(&ext),
> > };
> > - int err;
> > -
> > - err = 0;
> > - if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create)) {
> > - err = -errno;
> > - igt_assume(err);
> > - }
> > - errno = 0;
> >
> > - return err == -ENOENT;
> > + return create_ext_ioctl(i915, &create) == -ENOENT;
> > }
>
> I'd like to see the above in a separate patch.
It's part of the test, I can put it back inside each .c if you prefer.
> > +void dyn_sysfs_engines(int i915, int engines, const char *file,
> > + void (*test)(int, int))
> > +{
> > + char buf[512];
> > + int len;
> > +
> > + lseek(engines, 0, SEEK_SET);
> > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > + void *ptr = buf;
> > +
> > + while (len) {
> > + struct linux_dirent64 {
> > + ino64_t d_ino;
> > + off64_t d_off;
> > + unsigned short d_reclen;
> > + unsigned char d_type;
> > + char d_name[];
> > + } *de = ptr;
>
> what is the need for having your own linux_dirent64?
fdopendir() takes ownership of the fd, preventing reuse. And
fdopendir(dup()) is getting ridiculous.
-Chris
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
@ 2020-02-28 23:32 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 23:32 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx
Quoting Andi Shyti (2020-02-28 23:27:04)
> Hi Chris,
>
> > +static int create_ext_ioctl(int i915,
> > + struct drm_i915_gem_context_create_ext *arg)
> > +{
> > + int err;
> > +
> > + err = 0;
> > + if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
> > + err = -errno;
> > + igt_assume(err);
> > + }
> > +
> > + errno = 0;
> > + return err;
> > +}
> > +
> > /**
> > * gem_has_contexts:
> > * @fd: open i915 drm file descriptor
> > @@ -324,17 +339,14 @@ __gem_context_clone(int i915,
> > .flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> > .extensions = to_user_pointer(&clone),
> > };
> > - int err = 0;
> > + int err;
> >
> > - if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &arg)) {
> > - err = -errno;
> > - igt_assume(err);
> > - }
> > + err = create_ext_ioctl(i915, &arg);
> > + if (err)
> > + return err;
> >
> > *out = arg.ctx_id;
> > -
> > - errno = 0;
> > - return err;
> > + return 0;
> > }
> >
> > static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
> > @@ -382,16 +394,8 @@ bool gem_has_context_clone(int i915)
> > .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> > .extensions = to_user_pointer(&ext),
> > };
> > - int err;
> > -
> > - err = 0;
> > - if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create)) {
> > - err = -errno;
> > - igt_assume(err);
> > - }
> > - errno = 0;
> >
> > - return err == -ENOENT;
> > + return create_ext_ioctl(i915, &create) == -ENOENT;
> > }
>
> I'd like to see the above in a separate patch.
It's part of the test, I can put it back inside each .c if you prefer.
> > +void dyn_sysfs_engines(int i915, int engines, const char *file,
> > + void (*test)(int, int))
> > +{
> > + char buf[512];
> > + int len;
> > +
> > + lseek(engines, 0, SEEK_SET);
> > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > + void *ptr = buf;
> > +
> > + while (len) {
> > + struct linux_dirent64 {
> > + ino64_t d_ino;
> > + off64_t d_off;
> > + unsigned short d_reclen;
> > + unsigned char d_type;
> > + char d_name[];
> > + } *de = ptr;
>
> what is the need for having your own linux_dirent64?
fdopendir() takes ownership of the fd, preventing reuse. And
fdopendir(dup()) is getting ridiculous.
-Chris
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls
2020-02-28 10:43 ` [Intel-gfx] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls Chris Wilson
@ 2020-02-28 23:34 ` Andi Shyti
2020-02-28 23:37 ` [igt-dev] " Chris Wilson
0 siblings, 1 reply; 30+ messages in thread
From: Andi Shyti @ 2020-02-28 23:34 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
On Fri, Feb 28, 2020 at 10:43:39AM +0000, Chris Wilson wrote:
> We [will] expose various per-engine scheduling controls. One of which,
> 'heartbeat_duration_ms', defines how often we send a heartbeat down the
> engine to check upon the health of the engine. If a heartbeat does not
> complete within the interval (or two), the engine is declared hung.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Someone with not a good eye might swear to have read this patch
once, and at patch 5/5 he will ask again the same question.
Why don't we put together in a library the things that patch
3/4/5 have in common?
Andi
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls
2020-02-28 23:34 ` Andi Shyti
@ 2020-02-28 23:37 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 23:37 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx
Quoting Andi Shyti (2020-02-28 23:34:48)
> On Fri, Feb 28, 2020 at 10:43:39AM +0000, Chris Wilson wrote:
> > We [will] expose various per-engine scheduling controls. One of which,
> > 'heartbeat_duration_ms', defines how often we send a heartbeat down the
> > engine to check upon the health of the engine. If a heartbeat does not
> > complete within the interval (or two), the engine is declared hung.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Someone with not a good eye might swear to have read this patch
> once, and at patch 5/5 he will ask again the same question.
>
> Why don't we put together in a library the things that patch
> 3/4/5 have in common?
They are. It's basically a repeating pattern of testing with local
assumptions. For the sole reason that I'm not very inventive.
-Chris
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls
@ 2020-02-28 23:37 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-28 23:37 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx
Quoting Andi Shyti (2020-02-28 23:34:48)
> On Fri, Feb 28, 2020 at 10:43:39AM +0000, Chris Wilson wrote:
> > We [will] expose various per-engine scheduling controls. One of which,
> > 'heartbeat_duration_ms', defines how often we send a heartbeat down the
> > engine to check upon the health of the engine. If a heartbeat does not
> > complete within the interval (or two), the engine is declared hung.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Someone with not a good eye might swear to have read this patch
> once, and at patch 5/5 he will ask again the same question.
>
> Why don't we put together in a library the things that patch
> 3/4/5 have in common?
They are. It's basically a repeating pattern of testing with local
assumptions. For the sole reason that I'm not very inventive.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-28 23:32 ` [igt-dev] " Chris Wilson
(?)
@ 2020-02-28 23:51 ` Andi Shyti
2020-02-29 10:21 ` [igt-dev] " Chris Wilson
-1 siblings, 1 reply; 30+ messages in thread
From: Andi Shyti @ 2020-02-28 23:51 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
> > > +void dyn_sysfs_engines(int i915, int engines, const char *file,
> > > + void (*test)(int, int))
> > > +{
> > > + char buf[512];
> > > + int len;
> > > +
> > > + lseek(engines, 0, SEEK_SET);
> > > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > > + void *ptr = buf;
> > > +
> > > + while (len) {
> > > + struct linux_dirent64 {
> > > + ino64_t d_ino;
> > > + off64_t d_off;
> > > + unsigned short d_reclen;
> > > + unsigned char d_type;
> > > + char d_name[];
> > > + } *de = ptr;
> >
> > what is the need for having your own linux_dirent64?
>
> fdopendir() takes ownership of the fd, preventing reuse. And
> fdopendir(dup()) is getting ridiculous.
why not using dirent64?
Andi
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-28 23:51 ` Andi Shyti
@ 2020-02-29 10:21 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-29 10:21 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx
Quoting Andi Shyti (2020-02-28 23:51:24)
> > > > +void dyn_sysfs_engines(int i915, int engines, const char *file,
> > > > + void (*test)(int, int))
> > > > +{
> > > > + char buf[512];
> > > > + int len;
> > > > +
> > > > + lseek(engines, 0, SEEK_SET);
> > > > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > > > + void *ptr = buf;
> > > > +
> > > > + while (len) {
> > > > + struct linux_dirent64 {
> > > > + ino64_t d_ino;
> > > > + off64_t d_off;
> > > > + unsigned short d_reclen;
> > > > + unsigned char d_type;
> > > > + char d_name[];
> > > > + } *de = ptr;
> > >
> > > what is the need for having your own linux_dirent64?
> >
> > fdopendir() takes ownership of the fd, preventing reuse. And
> > fdopendir(dup()) is getting ridiculous.
>
> why not using dirent64?
It's still the same problem that it takes a DIR, assuming ownership of
the fd. Why using linux_dirent64 because the manpage says so -- if you
are going to use the syscall, you need to match it's calling
conventions, not a middleman's.
-Chris
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
@ 2020-02-29 10:21 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-29 10:21 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx, Andi Shyti
Quoting Andi Shyti (2020-02-28 23:51:24)
> > > > +void dyn_sysfs_engines(int i915, int engines, const char *file,
> > > > + void (*test)(int, int))
> > > > +{
> > > > + char buf[512];
> > > > + int len;
> > > > +
> > > > + lseek(engines, 0, SEEK_SET);
> > > > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > > > + void *ptr = buf;
> > > > +
> > > > + while (len) {
> > > > + struct linux_dirent64 {
> > > > + ino64_t d_ino;
> > > > + off64_t d_off;
> > > > + unsigned short d_reclen;
> > > > + unsigned char d_type;
> > > > + char d_name[];
> > > > + } *de = ptr;
> > >
> > > what is the need for having your own linux_dirent64?
> >
> > fdopendir() takes ownership of the fd, preventing reuse. And
> > fdopendir(dup()) is getting ridiculous.
>
> why not using dirent64?
It's still the same problem that it takes a DIR, assuming ownership of
the fd. Why using linux_dirent64 because the manpage says so -- if you
are going to use the syscall, you need to match it's calling
conventions, not a middleman's.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-29 10:21 ` [igt-dev] " Chris Wilson
(?)
@ 2020-02-29 12:45 ` Andi Shyti
2020-02-29 18:34 ` [igt-dev] " Chris Wilson
-1 siblings, 1 reply; 30+ messages in thread
From: Andi Shyti @ 2020-02-29 12:45 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, intel-gfx
> > > > > + char buf[512];
> > > > > + int len;
> > > > > +
> > > > > + lseek(engines, 0, SEEK_SET);
> > > > > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > > > > + void *ptr = buf;
> > > > > +
> > > > > + while (len) {
> > > > > + struct linux_dirent64 {
> > > > > + ino64_t d_ino;
> > > > > + off64_t d_off;
> > > > > + unsigned short d_reclen;
> > > > > + unsigned char d_type;
> > > > > + char d_name[];
> > > > > + } *de = ptr;
> > > >
> > > > what is the need for having your own linux_dirent64?
> > >
> > > fdopendir() takes ownership of the fd, preventing reuse. And
> > > fdopendir(dup()) is getting ridiculous.
> >
> > why not using dirent64?
>
> It's still the same problem that it takes a DIR, assuming ownership of
> the fd. Why using linux_dirent64 because the manpage says so -- if you
> are going to use the syscall, you need to match it's calling
> conventions, not a middleman's.
I understand, but in bits/dirent.h there is, with some
assumptions, this part:
#ifdef __USE_LARGEFILE64
struct dirent64
{
__ino64_t d_ino;
__off64_t d_off;
unsigned short int d_reclen;
unsigned char d_type;
char d_name[256]; /* We must not include limits.h! */
};
#endif
why redefine a struct linux_dirent64?
Andi
PS We have time until Monday morning to discuss this, right? :)
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-29 12:45 ` Andi Shyti
@ 2020-02-29 18:34 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-29 18:34 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx
Quoting Andi Shyti (2020-02-29 12:45:27)
> > > > > > + char buf[512];
> > > > > > + int len;
> > > > > > +
> > > > > > + lseek(engines, 0, SEEK_SET);
> > > > > > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > > > > > + void *ptr = buf;
> > > > > > +
> > > > > > + while (len) {
> > > > > > + struct linux_dirent64 {
> > > > > > + ino64_t d_ino;
> > > > > > + off64_t d_off;
> > > > > > + unsigned short d_reclen;
> > > > > > + unsigned char d_type;
> > > > > > + char d_name[];
> > > > > > + } *de = ptr;
> > > > >
> > > > > what is the need for having your own linux_dirent64?
> > > >
> > > > fdopendir() takes ownership of the fd, preventing reuse. And
> > > > fdopendir(dup()) is getting ridiculous.
> > >
> > > why not using dirent64?
> >
> > It's still the same problem that it takes a DIR, assuming ownership of
> > the fd. Why using linux_dirent64 because the manpage says so -- if you
> > are going to use the syscall, you need to match it's calling
> > conventions, not a middleman's.
>
> I understand, but in bits/dirent.h there is, with some
> assumptions, this part:
>
> #ifdef __USE_LARGEFILE64
> struct dirent64
> {
> __ino64_t d_ino;
> __off64_t d_off;
> unsigned short int d_reclen;
> unsigned char d_type;
> char d_name[256]; /* We must not include limits.h! */
> };
> #endif
>
> why redefine a struct linux_dirent64?
Because the manpage didn't mention that!
-Chris
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
@ 2020-02-29 18:34 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-29 18:34 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx, Andi Shyti
Quoting Andi Shyti (2020-02-29 12:45:27)
> > > > > > + char buf[512];
> > > > > > + int len;
> > > > > > +
> > > > > > + lseek(engines, 0, SEEK_SET);
> > > > > > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > > > > > + void *ptr = buf;
> > > > > > +
> > > > > > + while (len) {
> > > > > > + struct linux_dirent64 {
> > > > > > + ino64_t d_ino;
> > > > > > + off64_t d_off;
> > > > > > + unsigned short d_reclen;
> > > > > > + unsigned char d_type;
> > > > > > + char d_name[];
> > > > > > + } *de = ptr;
> > > > >
> > > > > what is the need for having your own linux_dirent64?
> > > >
> > > > fdopendir() takes ownership of the fd, preventing reuse. And
> > > > fdopendir(dup()) is getting ridiculous.
> > >
> > > why not using dirent64?
> >
> > It's still the same problem that it takes a DIR, assuming ownership of
> > the fd. Why using linux_dirent64 because the manpage says so -- if you
> > are going to use the syscall, you need to match it's calling
> > conventions, not a middleman's.
>
> I understand, but in bits/dirent.h there is, with some
> assumptions, this part:
>
> #ifdef __USE_LARGEFILE64
> struct dirent64
> {
> __ino64_t d_ino;
> __off64_t d_off;
> unsigned short int d_reclen;
> unsigned char d_type;
> char d_name[256]; /* We must not include limits.h! */
> };
> #endif
>
> why redefine a struct linux_dirent64?
Because the manpage didn't mention that!
-Chris
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs
2020-02-29 18:34 ` [igt-dev] " Chris Wilson
(?)
@ 2020-02-29 18:39 ` Chris Wilson
-1 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2020-02-29 18:39 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev, intel-gfx
Quoting Chris Wilson (2020-02-29 18:34:49)
> Quoting Andi Shyti (2020-02-29 12:45:27)
> > > > > > > + char buf[512];
> > > > > > > + int len;
> > > > > > > +
> > > > > > > + lseek(engines, 0, SEEK_SET);
> > > > > > > + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> > > > > > > + void *ptr = buf;
> > > > > > > +
> > > > > > > + while (len) {
> > > > > > > + struct linux_dirent64 {
> > > > > > > + ino64_t d_ino;
> > > > > > > + off64_t d_off;
> > > > > > > + unsigned short d_reclen;
> > > > > > > + unsigned char d_type;
> > > > > > > + char d_name[];
> > > > > > > + } *de = ptr;
> > > > > >
> > > > > > what is the need for having your own linux_dirent64?
> > > > >
> > > > > fdopendir() takes ownership of the fd, preventing reuse. And
> > > > > fdopendir(dup()) is getting ridiculous.
> > > >
> > > > why not using dirent64?
> > >
> > > It's still the same problem that it takes a DIR, assuming ownership of
> > > the fd. Why using linux_dirent64 because the manpage says so -- if you
> > > are going to use the syscall, you need to match it's calling
> > > conventions, not a middleman's.
> >
> > I understand, but in bits/dirent.h there is, with some
> > assumptions, this part:
> >
> > #ifdef __USE_LARGEFILE64
> > struct dirent64
> > {
> > __ino64_t d_ino;
> > __off64_t d_off;
> > unsigned short int d_reclen;
> > unsigned char d_type;
> > char d_name[256]; /* We must not include limits.h! */
> > };
> > #endif
> >
> > why redefine a struct linux_dirent64?
>
> Because the manpage didn't mention that!
Though it is still a libc structure rather than the syscall definition
:(
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/5] i915: Start putting the mmio_base to wider use
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
` (8 preceding siblings ...)
(?)
@ 2020-03-01 1:09 ` Patchwork
-1 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2020-03-01 1:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/5] i915: Start putting the mmio_base to wider use
URL : https://patchwork.freedesktop.org/series/74073/
State : success
== Summary ==
CI Bug Log - changes from IGT_5475_full -> IGTPW_4238_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with IGTPW_4238_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_4238_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_4238_full:
### IGT changes ###
#### Possible regressions ####
* {igt@sysfs_heartbeat_interval@long} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1] +14 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb7/igt@sysfs_heartbeat_interval@long.html
* {igt@sysfs_timeslice_duration@duration} (NEW):
- shard-iclb: NOTRUN -> [SKIP][2] +14 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb1/igt@sysfs_timeslice_duration@duration.html
#### Warnings ####
* igt@gem_ctx_shared@exec-single-timeline-vebox:
- shard-hsw: [SKIP][3] ([fdo#109271]) -> [FAIL][4] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw4/igt@gem_ctx_shared@exec-single-timeline-vebox.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw1/igt@gem_ctx_shared@exec-single-timeline-vebox.html
* igt@gem_ctx_shared@single-timeline:
- shard-snb: [SKIP][5] ([fdo#109271]) -> [FAIL][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-snb4/igt@gem_ctx_shared@single-timeline.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-snb6/igt@gem_ctx_shared@single-timeline.html
New tests
---------
New tests have been introduced between IGT_5475_full and IGTPW_4238_full:
### New IGT tests (15) ###
* igt@sysfs_heartbeat_interval@idempotent:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_heartbeat_interval@invalid:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_heartbeat_interval@long:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_heartbeat_interval@mixed:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_heartbeat_interval@nopreempt:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_heartbeat_interval@off:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_heartbeat_interval@precise:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_preempt_timeout@idempotent:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_preempt_timeout@invalid:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_preempt_timeout@off:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_preempt_timeout@timeout:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@sysfs_timeslice_duration@duration:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_timeslice_duration@idempotent:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_timeslice_duration@invalid:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@sysfs_timeslice_duration@timeout:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_4238_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process@default:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#679])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb8/igt@gem_ctx_persistence@legacy-engines-mixed-process@default.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb4/igt@gem_ctx_persistence@legacy-engines-mixed-process@default.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@render:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([i915#1239])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb8/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb4/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
* igt@gem_exec_schedule@implicit-read-write-bsd2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276] / [i915#677])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb1/igt@gem_exec_schedule@implicit-read-write-bsd2.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb8/igt@gem_exec_schedule@implicit-read-write-bsd2.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([i915#677])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb5/igt@gem_exec_schedule@pi-common-bsd.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb4/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +6 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-apl3/igt@gem_softpin@noreloc-s3.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-apl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw7/igt@gem_userptr_blits@sync-unmap-after-close.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
- shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870] / [i915#478]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-snb5/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#54])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
- shard-kbl: [PASS][27] -> [FAIL][28] ([i915#54])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank:
- shard-hsw: [PASS][29] -> [INCOMPLETE][30] ([i915#61]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw1/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw7/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][31] -> [INCOMPLETE][32] ([fdo#103927])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#899])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb2/igt@kms_psr@psr2_suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb6/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][37] -> [FAIL][38] ([i915#31])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-apl7/igt@kms_setmode@basic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-apl7/igt@kms_setmode@basic.html
- shard-kbl: [PASS][39] -> [FAIL][40] ([i915#31])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-kbl7/igt@kms_setmode@basic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-kbl4/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-tglb: [PASS][41] -> [SKIP][42] ([fdo#112015])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb2/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb2/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
- shard-hsw: [PASS][43] -> [SKIP][44] ([fdo#109271])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw5/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw6/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109278])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb8/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb1/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
- shard-glk: [PASS][47] -> [SKIP][48] ([fdo#109271])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk4/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk4/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#112080]) +15 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb2/igt@perf_pmu@busy-no-semaphores-vcs1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb3/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109276]) +12 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][53] ([IGT#28]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-tglb: [FAIL][55] ([IGT#28]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb8/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb3/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@gem_ctx_shared@q-independent-bsd1:
- shard-apl: [SKIP][57] ([fdo#109271]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-apl3/igt@gem_ctx_shared@q-independent-bsd1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-apl8/igt@gem_ctx_shared@q-independent-bsd1.html
- shard-glk: [SKIP][59] ([fdo#109271]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk9/igt@gem_ctx_shared@q-independent-bsd1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk1/igt@gem_ctx_shared@q-independent-bsd1.html
- shard-kbl: [SKIP][61] ([fdo#109271]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-kbl2/igt@gem_ctx_shared@q-independent-bsd1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-kbl2/igt@gem_ctx_shared@q-independent-bsd1.html
- shard-tglb: [SKIP][63] ([IGT#32]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb8/igt@gem_ctx_shared@q-independent-bsd1.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb3/igt@gem_ctx_shared@q-independent-bsd1.html
* igt@gem_exec_balancer@hang:
- shard-tglb: [FAIL][65] ([i915#1277]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb6/igt@gem_exec_balancer@hang.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb5/igt@gem_exec_balancer@hang.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-snb: [DMESG-WARN][67] ([i915#478]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-snb2/igt@gem_exec_reloc@basic-gtt-cpu-active.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-snb5/igt@gem_exec_reloc@basic-gtt-cpu-active.html
- shard-hsw: [DMESG-WARN][69] ([i915#478]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw5/igt@gem_exec_reloc@basic-gtt-cpu-active.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw5/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [SKIP][71] ([fdo#109276] / [i915#677]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@implicit-write-read-bsd:
- shard-iclb: [SKIP][73] ([i915#677]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb1/igt@gem_exec_schedule@implicit-write-read-bsd.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb3/igt@gem_exec_schedule@implicit-write-read-bsd.html
* igt@gem_exec_schedule@pi-shared-iova-bsd2:
- shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +23 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb8/igt@gem_exec_schedule@pi-shared-iova-bsd2.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb1/igt@gem_exec_schedule@pi-shared-iova-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][77] ([fdo#112146]) -> [PASS][78] +5 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][79] ([i915#644]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk4/igt@gem_ppgtt@flink-and-close-vma-leak.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-tglb: [FAIL][81] ([i915#644]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb2/igt@gem_ppgtt@flink-and-close-vma-leak.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb3/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][83] ([i915#716]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk8/igt@gen9_exec_parse@allowed-all.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [FAIL][85] ([i915#447]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb7/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_pm_rps@waitboost:
- shard-tglb: [FAIL][87] ([i915#413]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb5/igt@i915_pm_rps@waitboost.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb7/igt@i915_pm_rps@waitboost.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][89] ([i915#72]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][91] ([i915#79]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-glk: [FAIL][93] ([i915#34]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk2/igt@kms_flip@2x-plain-flip-ts-check.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk2/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [DMESG-WARN][95] ([i915#180]) -> [PASS][96] +4 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-glk: [FAIL][97] ([i915#899]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-glk5/igt@kms_plane_lowres@pipe-a-tiling-y.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][99] ([fdo#109441]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][101] ([i915#180]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@idle-vcs1:
- shard-iclb: [SKIP][103] ([fdo#112080]) -> [PASS][104] +10 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb6/igt@perf_pmu@idle-vcs1.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb1/igt@perf_pmu@idle-vcs1.html
#### Warnings ####
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [DMESG-WARN][105] ([fdo#111870] / [i915#478]) -> [DMESG-WARN][106] ([fdo#110789] / [fdo#111870] / [i915#478])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-snb4/igt@gem_userptr_blits@dmabuf-sync.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-snb5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][107] ([i915#468]) -> [FAIL][108] ([i915#454])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: [INCOMPLETE][109] ([i915#1233]) -> [DMESG-FAIL][110] ([i915#1233])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-tglb5/igt@i915_selftest@live@gt_lrc.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-tglb8/igt@i915_selftest@live@gt_lrc.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][111] ([fdo#109349]) -> [DMESG-WARN][112] ([i915#1226])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [DMESG-WARN][113] ([i915#180]) -> [INCOMPLETE][114] ([fdo#103665] / [i915#600])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@runner@aborted:
- shard-hsw: ([FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121]) ([fdo#111870] / [i915#478]) -> ([FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128]) ([fdo#111870])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw5/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw7/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw6/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw1/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw6/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5475/shard-hsw4/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw5/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw4/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw7/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw6/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw6/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/shard-hsw4/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[IGT#32]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/32
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112015]: https://bugs.freedesktop.org/show_bug.cgi?id=112015
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
[i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#600]: https://gitlab.freedesktop.org/drm/intel/issues/600
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5475 -> IGTPW_4238
CI-20190529: 20190529
CI_DRM_8026: 6ce18c241dde9ee20b19ff42f8198552a57ab259 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4238: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/index.html
IGT_5475: ca52e3cb94072f8a6c59f6379f569f79e71a088b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4238/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2020-03-01 1:09 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-28 10:43 [Intel-gfx] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use Chris Wilson
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
2020-02-28 10:43 ` [Intel-gfx] [PATCH i-g-t 2/5] i915/gem_ctx_isolation: Check engine relative registers Chris Wilson
2020-02-28 19:46 ` Stimson, Dale B
2020-02-28 19:46 ` [igt-dev] " Stimson, Dale B
2020-02-28 10:43 ` [Intel-gfx] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs Chris Wilson
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
2020-02-28 23:27 ` [Intel-gfx] " Andi Shyti
2020-02-28 23:32 ` Chris Wilson
2020-02-28 23:32 ` [igt-dev] " Chris Wilson
2020-02-28 23:51 ` Andi Shyti
2020-02-29 10:21 ` Chris Wilson
2020-02-29 10:21 ` [igt-dev] " Chris Wilson
2020-02-29 12:45 ` Andi Shyti
2020-02-29 18:34 ` Chris Wilson
2020-02-29 18:34 ` [igt-dev] " Chris Wilson
2020-02-29 18:39 ` Chris Wilson
2020-02-28 10:43 ` [Intel-gfx] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls Chris Wilson
2020-02-28 23:34 ` Andi Shyti
2020-02-28 23:37 ` Chris Wilson
2020-02-28 23:37 ` [igt-dev] " Chris Wilson
2020-02-28 10:43 ` [Intel-gfx] [PATCH i-g-t 5/5] i915: Exercise timeslice sysfs property Chris Wilson
2020-02-28 10:43 ` [igt-dev] " Chris Wilson
2020-02-28 11:15 ` [igt-dev] ✗ GitLab.Pipeline: failure for series starting with [i-g-t,1/5] i915: Start putting the mmio_base to wider use Patchwork
2020-02-28 11:52 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2020-02-28 19:45 ` [Intel-gfx] [igt-dev] [PATCH i-g-t 1/5] " Stimson, Dale B
2020-02-28 19:45 ` Stimson, Dale B
2020-02-28 21:27 ` [Intel-gfx] " Andi Shyti
2020-02-28 21:27 ` [igt-dev] " Andi Shyti
2020-03-01 1:09 ` [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/5] " Patchwork
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