* [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine
@ 2020-03-01 21:50 Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 01/18] hw/arm: add Allwinner H3 System-on-Chip Niek Linnenbank
` (17 more replies)
0 siblings, 18 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
Dear QEMU developers,
Hereby I would like to contribute the following set of patches to QEMU
which add support for the Allwinner H3 System on Chip and the
Orange Pi PC machine. The following features and devices are supported:
* SMP (Quad Core Cortex A7)
* Generic Interrupt Controller configuration
* SRAM mappings
* SDRAM controller
* Real Time Clock
* Timer device (re-used from Allwinner A10)
* UART
* SD/MMC storage controller
* EMAC ethernet
* USB 2.0 interfaces
* Clock Control Unit
* System Control module
* Security Identifier device
Functionality related to graphical output such as HDMI, GPU,
Display Engine and audio are not included. Recently released
mainline Linux kernels (4.19 up to latest master), mainline U-Boot
and NetBSD 9.0 are known to work.
For full details on how to use the Orange Pi PC machine, see the file
docs/orangepi.rst which is included as a patch in this series.
The contents of this patch series is available on Github at:
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v6
The followings are currently known issues in this series:
- RTC date & time is not persistent
- boot0 custom Allwinner bootloader not yet working
- Watchdog not yet implemented, affects U-Boot 'reset' and shutdown/reboot
-> This is part of the existing A10 timer that needs to be generalized first
Looking forward to your review comments. I will do my best
to update the patches where needed.
===== CHANGELOG =====
v6:
* hw/arm/orangepi.c: remove usage of memory_region_allocate_system_memory and OrangePiState
* hw/misc/allwinner-cpucfg.c: add missing break statement in write function after REG_CLK_GATING
v5: https://lists.gnu.org/archive/html/qemu-devel/2020-02/msg04525.html
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v5
v4: https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg03960.html
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v4
v3: https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg01534.html
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v3
v2: https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg03265.html
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v2
v1: https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg00320.html
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v1
With kind regards,
Niek Linnenbank
Niek Linnenbank (13):
hw/arm: add Allwinner H3 System-on-Chip
hw/arm: add Xunlong Orange Pi PC machine
hw/arm/allwinner-h3: add Clock Control Unit
hw/arm/allwinner-h3: add USB host controller
hw/arm/allwinner-h3: add System Control module
hw/arm/allwinner: add CPU Configuration module
hw/arm/allwinner: add Security Identifier device
hw/arm/allwinner: add SD/MMC host controller
hw/arm/allwinner-h3: add EMAC ethernet device
hw/arm/allwinner-h3: add Boot ROM support
hw/arm/allwinner-h3: add SDRAM controller device
hw/arm/allwinner: add RTC device support
docs: add Orange Pi PC document
Philippe Mathieu-Daudé (5):
tests/boot_linux_console: Add a quick test for the OrangePi PC board
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi
PC
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi
PC
docs/orangepi.rst | 226 +++++++
default-configs/arm-softmmu.mak | 1 +
hw/usb/hcd-ehci.h | 1 +
include/hw/arm/allwinner-a10.h | 4 +
include/hw/arm/allwinner-h3.h | 161 +++++
include/hw/misc/allwinner-cpucfg.h | 52 ++
include/hw/misc/allwinner-h3-ccu.h | 66 ++
include/hw/misc/allwinner-h3-dramc.h | 106 +++
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++
include/hw/misc/allwinner-sid.h | 60 ++
include/hw/net/allwinner-sun8i-emac.h | 99 +++
include/hw/rtc/allwinner-rtc.h | 134 ++++
include/hw/sd/allwinner-sdhost.h | 135 ++++
hw/arm/allwinner-a10.c | 19 +
hw/arm/allwinner-h3.c | 466 +++++++++++++
hw/arm/cubieboard.c | 15 +
hw/arm/orangepi.c | 128 ++++
hw/misc/allwinner-cpucfg.c | 271 ++++++++
hw/misc/allwinner-h3-ccu.c | 242 +++++++
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++
hw/misc/allwinner-h3-sysctrl.c | 140 ++++
hw/misc/allwinner-sid.c | 168 +++++
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++
hw/rtc/allwinner-rtc.c | 411 ++++++++++++
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++
hw/usb/hcd-ehci-sysbus.c | 17 +
MAINTAINERS | 9 +
hw/arm/Kconfig | 12 +
hw/arm/Makefile.objs | 1 +
hw/misc/Makefile.objs | 5 +
hw/misc/trace-events | 19 +
hw/net/Kconfig | 3 +
hw/net/Makefile.objs | 1 +
hw/net/trace-events | 10 +
hw/rtc/Makefile.objs | 1 +
hw/rtc/trace-events | 4 +
hw/sd/Makefile.objs | 1 +
hw/sd/trace-events | 7 +
tests/acceptance/boot_linux_console.py | 224 +++++++
39 files changed, 5369 insertions(+)
create mode 100644 docs/orangepi.rst
create mode 100644 include/hw/arm/allwinner-h3.h
create mode 100644 include/hw/misc/allwinner-cpucfg.h
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
create mode 100644 include/hw/misc/allwinner-sid.h
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
create mode 100644 include/hw/rtc/allwinner-rtc.h
create mode 100644 include/hw/sd/allwinner-sdhost.h
create mode 100644 hw/arm/allwinner-h3.c
create mode 100644 hw/arm/orangepi.c
create mode 100644 hw/misc/allwinner-cpucfg.c
create mode 100644 hw/misc/allwinner-h3-ccu.c
create mode 100644 hw/misc/allwinner-h3-dramc.c
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
create mode 100644 hw/misc/allwinner-sid.c
create mode 100644 hw/net/allwinner-sun8i-emac.c
create mode 100644 hw/rtc/allwinner-rtc.c
create mode 100644 hw/sd/allwinner-sdhost.c
--
2.17.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v6 01/18] hw/arm: add Allwinner H3 System-on-Chip
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-03 10:53 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 02/18] hw/arm: add Xunlong Orange Pi PC machine Niek Linnenbank
` (16 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
various I/O modules. This commit adds support for the Allwinner H3
System on Chip.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/allwinner-h3.h | 106 +++++++++++
hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++
MAINTAINERS | 7 +
hw/arm/Kconfig | 8 +
hw/arm/Makefile.objs | 1 +
6 files changed, 450 insertions(+)
create mode 100644 include/hw/arm/allwinner-h3.h
create mode 100644 hw/arm/allwinner-h3.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 645e6201bb..36a0e89daa 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -41,3 +41,4 @@ CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_SEMIHOSTING=y
+CONFIG_ALLWINNER_H3=y
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
new file mode 100644
index 0000000000..2aac9b78ec
--- /dev/null
+++ b/include/hw/arm/allwinner-h3.h
@@ -0,0 +1,106 @@
+/*
+ * Allwinner H3 System on Chip emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
+ * processor cores. Features and specifications include DDR2/DDR3 memory,
+ * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
+ * various I/O modules.
+ *
+ * This implementation is based on the following datasheet:
+ *
+ * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
+ *
+ * The latest datasheet and more info can be found on the Linux Sunxi wiki:
+ *
+ * https://linux-sunxi.org/H3
+ */
+
+#ifndef HW_ARM_ALLWINNER_H3_H
+#define HW_ARM_ALLWINNER_H3_H
+
+#include "qom/object.h"
+#include "hw/arm/boot.h"
+#include "hw/timer/allwinner-a10-pit.h"
+#include "hw/intc/arm_gic.h"
+#include "target/arm/cpu.h"
+
+/**
+ * Allwinner H3 device list
+ *
+ * This enumeration is can be used refer to a particular device in the
+ * Allwinner H3 SoC. For example, the physical memory base address for
+ * each device can be found in the AwH3State object in the memmap member
+ * using the device enum value as index.
+ *
+ * @see AwH3State
+ */
+enum {
+ AW_H3_SRAM_A1,
+ AW_H3_SRAM_A2,
+ AW_H3_SRAM_C,
+ AW_H3_PIT,
+ AW_H3_UART0,
+ AW_H3_UART1,
+ AW_H3_UART2,
+ AW_H3_UART3,
+ AW_H3_GIC_DIST,
+ AW_H3_GIC_CPU,
+ AW_H3_GIC_HYP,
+ AW_H3_GIC_VCPU,
+ AW_H3_SDRAM
+};
+
+/** Total number of CPU cores in the H3 SoC */
+#define AW_H3_NUM_CPUS (4)
+
+/**
+ * Allwinner H3 object model
+ * @{
+ */
+
+/** Object type for the Allwinner H3 SoC */
+#define TYPE_AW_H3 "allwinner-h3"
+
+/** Convert input object to Allwinner H3 state object */
+#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
+
+/** @} */
+
+/**
+ * Allwinner H3 object
+ *
+ * This struct contains the state of all the devices
+ * which are currently emulated by the H3 SoC code.
+ */
+typedef struct AwH3State {
+ /*< private >*/
+ DeviceState parent_obj;
+ /*< public >*/
+
+ ARMCPU cpus[AW_H3_NUM_CPUS];
+ const hwaddr *memmap;
+ AwA10PITState timer;
+ GICState gic;
+ MemoryRegion sram_a1;
+ MemoryRegion sram_a2;
+ MemoryRegion sram_c;
+} AwH3State;
+
+#endif /* HW_ARM_ALLWINNER_H3_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
new file mode 100644
index 0000000000..7958f37685
--- /dev/null
+++ b/hw/arm/allwinner-h3.c
@@ -0,0 +1,327 @@
+/*
+ * Allwinner H3 System on Chip emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "exec/address-spaces.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "hw/qdev-core.h"
+#include "cpu.h"
+#include "hw/sysbus.h"
+#include "hw/char/serial.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+#include "hw/arm/allwinner-h3.h"
+
+/* Memory map */
+const hwaddr allwinner_h3_memmap[] = {
+ [AW_H3_SRAM_A1] = 0x00000000,
+ [AW_H3_SRAM_A2] = 0x00044000,
+ [AW_H3_SRAM_C] = 0x00010000,
+ [AW_H3_PIT] = 0x01c20c00,
+ [AW_H3_UART0] = 0x01c28000,
+ [AW_H3_UART1] = 0x01c28400,
+ [AW_H3_UART2] = 0x01c28800,
+ [AW_H3_UART3] = 0x01c28c00,
+ [AW_H3_GIC_DIST] = 0x01c81000,
+ [AW_H3_GIC_CPU] = 0x01c82000,
+ [AW_H3_GIC_HYP] = 0x01c84000,
+ [AW_H3_GIC_VCPU] = 0x01c86000,
+ [AW_H3_SDRAM] = 0x40000000
+};
+
+/* List of unimplemented devices */
+struct AwH3Unimplemented {
+ const char *device_name;
+ hwaddr base;
+ hwaddr size;
+} unimplemented[] = {
+ { "d-engine", 0x01000000, 4 * MiB },
+ { "d-inter", 0x01400000, 128 * KiB },
+ { "syscon", 0x01c00000, 4 * KiB },
+ { "dma", 0x01c02000, 4 * KiB },
+ { "nfdc", 0x01c03000, 4 * KiB },
+ { "ts", 0x01c06000, 4 * KiB },
+ { "keymem", 0x01c0b000, 4 * KiB },
+ { "lcd0", 0x01c0c000, 4 * KiB },
+ { "lcd1", 0x01c0d000, 4 * KiB },
+ { "ve", 0x01c0e000, 4 * KiB },
+ { "mmc0", 0x01c0f000, 4 * KiB },
+ { "mmc1", 0x01c10000, 4 * KiB },
+ { "mmc2", 0x01c11000, 4 * KiB },
+ { "sid", 0x01c14000, 1 * KiB },
+ { "crypto", 0x01c15000, 4 * KiB },
+ { "msgbox", 0x01c17000, 4 * KiB },
+ { "spinlock", 0x01c18000, 4 * KiB },
+ { "usb0-otg", 0x01c19000, 4 * KiB },
+ { "usb0-phy", 0x01c1a000, 4 * KiB },
+ { "usb1-phy", 0x01c1b000, 4 * KiB },
+ { "usb2-phy", 0x01c1c000, 4 * KiB },
+ { "usb3-phy", 0x01c1d000, 4 * KiB },
+ { "smc", 0x01c1e000, 4 * KiB },
+ { "ccu", 0x01c20000, 1 * KiB },
+ { "pio", 0x01c20800, 1 * KiB },
+ { "owa", 0x01c21000, 1 * KiB },
+ { "pwm", 0x01c21400, 1 * KiB },
+ { "keyadc", 0x01c21800, 1 * KiB },
+ { "pcm0", 0x01c22000, 1 * KiB },
+ { "pcm1", 0x01c22400, 1 * KiB },
+ { "pcm2", 0x01c22800, 1 * KiB },
+ { "audio", 0x01c22c00, 2 * KiB },
+ { "smta", 0x01c23400, 1 * KiB },
+ { "ths", 0x01c25000, 1 * KiB },
+ { "uart0", 0x01c28000, 1 * KiB },
+ { "uart1", 0x01c28400, 1 * KiB },
+ { "uart2", 0x01c28800, 1 * KiB },
+ { "uart3", 0x01c28c00, 1 * KiB },
+ { "twi0", 0x01c2ac00, 1 * KiB },
+ { "twi1", 0x01c2b000, 1 * KiB },
+ { "twi2", 0x01c2b400, 1 * KiB },
+ { "scr", 0x01c2c400, 1 * KiB },
+ { "emac", 0x01c30000, 64 * KiB },
+ { "gpu", 0x01c40000, 64 * KiB },
+ { "hstmr", 0x01c60000, 4 * KiB },
+ { "dramcom", 0x01c62000, 4 * KiB },
+ { "dramctl0", 0x01c63000, 4 * KiB },
+ { "dramphy0", 0x01c65000, 4 * KiB },
+ { "spi0", 0x01c68000, 4 * KiB },
+ { "spi1", 0x01c69000, 4 * KiB },
+ { "csi", 0x01cb0000, 320 * KiB },
+ { "tve", 0x01e00000, 64 * KiB },
+ { "hdmi", 0x01ee0000, 128 * KiB },
+ { "rtc", 0x01f00000, 1 * KiB },
+ { "r_timer", 0x01f00800, 1 * KiB },
+ { "r_intc", 0x01f00c00, 1 * KiB },
+ { "r_wdog", 0x01f01000, 1 * KiB },
+ { "r_prcm", 0x01f01400, 1 * KiB },
+ { "r_twd", 0x01f01800, 1 * KiB },
+ { "r_cpucfg", 0x01f01c00, 1 * KiB },
+ { "r_cir-rx", 0x01f02000, 1 * KiB },
+ { "r_twi", 0x01f02400, 1 * KiB },
+ { "r_uart", 0x01f02800, 1 * KiB },
+ { "r_pio", 0x01f02c00, 1 * KiB },
+ { "r_pwm", 0x01f03800, 1 * KiB },
+ { "core-dbg", 0x3f500000, 128 * KiB },
+ { "tsgen-ro", 0x3f506000, 4 * KiB },
+ { "tsgen-ctl", 0x3f507000, 4 * KiB },
+ { "ddr-mem", 0x40000000, 2 * GiB },
+ { "n-brom", 0xffff0000, 32 * KiB },
+ { "s-brom", 0xffff0000, 64 * KiB }
+};
+
+/* Per Processor Interrupts */
+enum {
+ AW_H3_GIC_PPI_MAINT = 9,
+ AW_H3_GIC_PPI_HYPTIMER = 10,
+ AW_H3_GIC_PPI_VIRTTIMER = 11,
+ AW_H3_GIC_PPI_SECTIMER = 13,
+ AW_H3_GIC_PPI_PHYSTIMER = 14
+};
+
+/* Shared Processor Interrupts */
+enum {
+ AW_H3_GIC_SPI_UART0 = 0,
+ AW_H3_GIC_SPI_UART1 = 1,
+ AW_H3_GIC_SPI_UART2 = 2,
+ AW_H3_GIC_SPI_UART3 = 3,
+ AW_H3_GIC_SPI_TIMER0 = 18,
+ AW_H3_GIC_SPI_TIMER1 = 19,
+};
+
+/* Allwinner H3 general constants */
+enum {
+ AW_H3_GIC_NUM_SPI = 128
+};
+
+static void allwinner_h3_init(Object *obj)
+{
+ AwH3State *s = AW_H3(obj);
+
+ s->memmap = allwinner_h3_memmap;
+
+ for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
+ ARM_CPU_TYPE_NAME("cortex-a7"),
+ &error_abort, NULL);
+ }
+
+ sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
+ TYPE_ARM_GIC);
+
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
+ TYPE_AW_A10_PIT);
+ object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
+ "clk0-freq", &error_abort);
+ object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
+ "clk1-freq", &error_abort);
+}
+
+static void allwinner_h3_realize(DeviceState *dev, Error **errp)
+{
+ AwH3State *s = AW_H3(dev);
+ unsigned i;
+
+ /* CPUs */
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
+
+ /* Provide Power State Coordination Interface */
+ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
+ QEMU_PSCI_CONDUIT_HVC);
+
+ /* Disable secondary CPUs */
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
+ i > 0);
+
+ /* All exception levels required */
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
+
+ /* Mark realized */
+ qdev_init_nofail(DEVICE(&s->cpus[i]));
+ }
+
+ /* Generic Interrupt Controller */
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
+ GIC_INTERNAL);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
+ qdev_init_nofail(DEVICE(&s->gic));
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
+
+ /*
+ * Wire the outputs from each CPU's generic timer and the GICv3
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
+ */
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
+ DeviceState *cpudev = DEVICE(&s->cpus[i]);
+ int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
+ int irq;
+ /*
+ * Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs used for this board.
+ */
+ const int timer_irq[] = {
+ [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
+ [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
+ [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
+ [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
+ };
+
+ /* Connect CPU timer outputs to GIC PPI inputs */
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
+ qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ ppibase + timer_irq[irq]));
+ }
+
+ /* Connect GIC outputs to CPU interrupt inputs */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
+
+ /* GIC maintenance signal */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ ppibase + AW_H3_GIC_PPI_MAINT));
+ }
+
+ /* Timer */
+ qdev_init_nofail(DEVICE(&s->timer));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
+
+ /* SRAM */
+ memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
+ 64 * KiB, &error_abort);
+ memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
+ 32 * KiB, &error_abort);
+ memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
+ 44 * KiB, &error_abort);
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
+ &s->sram_a1);
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
+ &s->sram_a2);
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
+ &s->sram_c);
+
+ /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ /* UART1 */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
+ 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
+ /* UART2 */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
+ 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
+ /* UART3 */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
+ 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
+
+ /* Unimplemented devices */
+ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
+ create_unimplemented_device(unimplemented[i].device_name,
+ unimplemented[i].base,
+ unimplemented[i].size);
+ }
+}
+
+static void allwinner_h3_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = allwinner_h3_realize;
+ /* Reason: uses serial_hd() in realize function */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo allwinner_h3_type_info = {
+ .name = TYPE_AW_H3,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AwH3State),
+ .instance_init = allwinner_h3_init,
+ .class_init = allwinner_h3_class_init,
+};
+
+static void allwinner_h3_register_types(void)
+{
+ type_register_static(&allwinner_h3_type_info);
+}
+
+type_init(allwinner_h3_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index c258391cad..d5c0c25cc4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -490,6 +490,13 @@ F: hw/*/allwinner*
F: include/hw/*/allwinner*
F: hw/arm/cubieboard.c
+Allwinner-h3
+M: Niek Linnenbank <nieklinnenbank@gmail.com>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/*/allwinner-h3*
+F: include/hw/*/allwinner-h3*
+
ARM PrimeCell and CMSDK devices
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 61635f52c4..a7034218f0 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -296,6 +296,14 @@ config ALLWINNER_A10
select SERIAL
select UNIMP
+config ALLWINNER_H3
+ bool
+ select ALLWINNER_A10_PIT
+ select SERIAL
+ select ARM_TIMER
+ select ARM_GIC
+ select UNIMP
+
config RASPI
bool
select FRAMEBUFFER
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 336f6dd374..ae577e875f 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -35,6 +35,7 @@ obj-$(CONFIG_DIGIC) += digic.o
obj-$(CONFIG_OMAP) += omap1.o omap2.o
obj-$(CONFIG_STRONGARM) += strongarm.o
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 02/18] hw/arm: add Xunlong Orange Pi PC machine
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 01/18] hw/arm: add Allwinner H3 System-on-Chip Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-03 11:02 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 03/18] hw/arm/allwinner-h3: add Clock Control Unit Niek Linnenbank
` (15 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other I/O. This commit add support for the Xunlong
Orange Pi PC machine.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
---
hw/arm/orangepi.c | 89 ++++++++++++++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
hw/arm/Makefile.objs | 2 +-
3 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/orangepi.c
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
new file mode 100644
index 0000000000..19adfca917
--- /dev/null
+++ b/hw/arm/orangepi.c
@@ -0,0 +1,89 @@
+/*
+ * Orange Pi emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "exec/address-spaces.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/sysbus.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/arm/allwinner-h3.h"
+#include "sysemu/sysemu.h"
+
+static struct arm_boot_info orangepi_binfo = {
+ .nb_cpus = AW_H3_NUM_CPUS,
+};
+
+static void orangepi_init(MachineState *machine)
+{
+ AwH3State *h3;
+
+ /* BIOS is not supported by this board */
+ if (bios_name) {
+ error_report("BIOS not supported for this machine");
+ exit(1);
+ }
+
+ /* This board has fixed size RAM */
+ if (machine->ram_size != 1 * GiB) {
+ error_report("This machine can only be used with 1GiB of RAM");
+ exit(1);
+ }
+
+ /* Only allow Cortex-A7 for this board */
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
+ error_report("This board can only be used with cortex-a7 CPU");
+ exit(1);
+ }
+
+ h3 = AW_H3(object_new(TYPE_AW_H3));
+
+ /* Setup timer properties */
+ object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
+ &error_abort);
+ object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
+ &error_abort);
+
+ /* Mark H3 object realized */
+ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
+
+ /* SDRAM */
+ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
+ machine->ram);
+
+ orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
+ orangepi_binfo.ram_size = machine->ram_size;
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
+}
+
+static void orangepi_machine_init(MachineClass *mc)
+{
+ mc->desc = "Orange Pi PC";
+ mc->init = orangepi_init;
+ mc->min_cpus = AW_H3_NUM_CPUS;
+ mc->max_cpus = AW_H3_NUM_CPUS;
+ mc->default_cpus = AW_H3_NUM_CPUS;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ mc->default_ram_size = 1 * GiB;
+ mc->default_ram_id = "orangepi.ram";
+}
+
+DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5c0c25cc4..02ecba8d9c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -496,6 +496,7 @@ L: qemu-arm@nongnu.org
S: Maintained
F: hw/*/allwinner-h3*
F: include/hw/*/allwinner-h3*
+F: hw/arm/orangepi.c
ARM PrimeCell and CMSDK devices
M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index ae577e875f..534a6a119e 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -35,7 +35,7 @@ obj-$(CONFIG_DIGIC) += digic.o
obj-$(CONFIG_OMAP) += omap1.o omap2.o
obj-$(CONFIG_STRONGARM) += strongarm.o
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 03/18] hw/arm/allwinner-h3: add Clock Control Unit
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 01/18] hw/arm: add Allwinner H3 System-on-Chip Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 02/18] hw/arm: add Xunlong Orange Pi PC machine Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-03 11:10 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 04/18] hw/arm/allwinner-h3: add USB host controller Niek Linnenbank
` (14 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++
hw/arm/allwinner-h3.c | 9 +-
hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
5 files changed, 320 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
create mode 100644 hw/misc/allwinner-h3-ccu.c
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 2aac9b78ec..abdc20871a 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -39,6 +39,7 @@
#include "hw/arm/boot.h"
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/arm_gic.h"
+#include "hw/misc/allwinner-h3-ccu.h"
#include "target/arm/cpu.h"
/**
@@ -55,6 +56,7 @@ enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
+ AW_H3_CCU,
AW_H3_PIT,
AW_H3_UART0,
AW_H3_UART1,
@@ -97,6 +99,7 @@ typedef struct AwH3State {
ARMCPU cpus[AW_H3_NUM_CPUS];
const hwaddr *memmap;
AwA10PITState timer;
+ AwH3ClockCtlState ccu;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h
new file mode 100644
index 0000000000..eec59649f3
--- /dev/null
+++ b/include/hw/misc/allwinner-h3-ccu.h
@@ -0,0 +1,66 @@
+/*
+ * Allwinner H3 Clock Control Unit emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_H3_CCU_H
+#define HW_MISC_ALLWINNER_H3_CCU_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Size of register I/O address space used by CCU device */
+#define AW_H3_CCU_IOSIZE (0x400)
+
+/** Total number of known registers */
+#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
+#define AW_H3_CCU(obj) \
+ OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU)
+
+/** @} */
+
+/**
+ * Allwinner H3 CCU object instance state.
+ */
+typedef struct AwH3ClockCtlState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_H3_CCU_REGS_NUM];
+
+} AwH3ClockCtlState;
+
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 7958f37685..1fff3c317b 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -36,6 +36,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_SRAM_A1] = 0x00000000,
[AW_H3_SRAM_A2] = 0x00044000,
[AW_H3_SRAM_C] = 0x00010000,
+ [AW_H3_CCU] = 0x01c20000,
[AW_H3_PIT] = 0x01c20c00,
[AW_H3_UART0] = 0x01c28000,
[AW_H3_UART1] = 0x01c28400,
@@ -77,7 +78,6 @@ struct AwH3Unimplemented {
{ "usb2-phy", 0x01c1c000, 4 * KiB },
{ "usb3-phy", 0x01c1d000, 4 * KiB },
{ "smc", 0x01c1e000, 4 * KiB },
- { "ccu", 0x01c20000, 1 * KiB },
{ "pio", 0x01c20800, 1 * KiB },
{ "owa", 0x01c21000, 1 * KiB },
{ "pwm", 0x01c21400, 1 * KiB },
@@ -172,6 +172,9 @@ static void allwinner_h3_init(Object *obj)
"clk0-freq", &error_abort);
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
"clk1-freq", &error_abort);
+
+ sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
+ TYPE_AW_H3_CCU);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -277,6 +280,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
&s->sram_c);
+ /* Clock Control Unit */
+ qdev_init_nofail(DEVICE(&s->ccu));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
+
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c
new file mode 100644
index 0000000000..18d1074545
--- /dev/null
+++ b/hw/misc/allwinner-h3-ccu.c
@@ -0,0 +1,242 @@
+/*
+ * Allwinner H3 Clock Control Unit emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-h3-ccu.h"
+
+/* CCU register offsets */
+enum {
+ REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
+ REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
+ REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
+ REG_PLL_VE = 0x0018, /* PLL VE Control */
+ REG_PLL_DDR = 0x0020, /* PLL DDR Control */
+ REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
+ REG_PLL_GPU = 0x0038, /* PLL GPU Control */
+ REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
+ REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
+ REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
+ REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */
+ REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */
+ REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */
+ REG_MBUS = 0x00FC, /* MBUS Reset */
+ REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
+ REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */
+ REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */
+ REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */
+ REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */
+ REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */
+ REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */
+ REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */
+ REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */
+ REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */
+ REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
+ REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */
+ REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */
+};
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+/* CCU register flags */
+enum {
+ REG_DRAM_CFG_UPDATE = (1 << 16),
+};
+
+enum {
+ REG_PLL_ENABLE = (1 << 31),
+ REG_PLL_LOCK = (1 << 28),
+};
+
+
+/* CCU register reset values */
+enum {
+ REG_PLL_CPUX_RST = 0x00001000,
+ REG_PLL_AUDIO_RST = 0x00035514,
+ REG_PLL_VIDEO_RST = 0x03006207,
+ REG_PLL_VE_RST = 0x03006207,
+ REG_PLL_DDR_RST = 0x00001000,
+ REG_PLL_PERIPH0_RST = 0x00041811,
+ REG_PLL_GPU_RST = 0x03006207,
+ REG_PLL_PERIPH1_RST = 0x00041811,
+ REG_PLL_DE_RST = 0x03006207,
+ REG_CPUX_AXI_RST = 0x00010000,
+ REG_APB1_RST = 0x00001010,
+ REG_APB2_RST = 0x01000000,
+ REG_DRAM_CFG_RST = 0x00000000,
+ REG_MBUS_RST = 0x80000000,
+ REG_PLL_TIME0_RST = 0x000000FF,
+ REG_PLL_TIME1_RST = 0x000000FF,
+ REG_PLL_CPUX_BIAS_RST = 0x08100200,
+ REG_PLL_AUDIO_BIAS_RST = 0x10100000,
+ REG_PLL_VIDEO_BIAS_RST = 0x10100000,
+ REG_PLL_VE_BIAS_RST = 0x10100000,
+ REG_PLL_DDR_BIAS_RST = 0x81104000,
+ REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
+ REG_PLL_GPU_BIAS_RST = 0x10100000,
+ REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
+ REG_PLL_DE_BIAS_RST = 0x10100000,
+ REG_PLL_CPUX_TUNING_RST = 0x0A101000,
+ REG_PLL_DDR_TUNING_RST = 0x14880000,
+};
+
+static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3ClockCtlState *s = AW_H3_CCU(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ switch (offset) {
+ case 0x308 ... AW_H3_CCU_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ return s->regs[idx];
+}
+
+static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3ClockCtlState *s = AW_H3_CCU(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ switch (offset) {
+ case REG_DRAM_CFG: /* DRAM Configuration */
+ val &= ~REG_DRAM_CFG_UPDATE;
+ break;
+ case REG_PLL_CPUX: /* PLL CPUX Control */
+ case REG_PLL_AUDIO: /* PLL Audio Control */
+ case REG_PLL_VIDEO: /* PLL Video Control */
+ case REG_PLL_VE: /* PLL VE Control */
+ case REG_PLL_DDR: /* PLL DDR Control */
+ case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
+ case REG_PLL_GPU: /* PLL GPU Control */
+ case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
+ case REG_PLL_DE: /* PLL Display Engine Control */
+ if (val & REG_PLL_ENABLE) {
+ val |= REG_PLL_LOCK;
+ }
+ break;
+ case 0x308 ... AW_H3_CCU_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+
+ s->regs[idx] = (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_h3_ccu_ops = {
+ .read = allwinner_h3_ccu_read,
+ .write = allwinner_h3_ccu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static void allwinner_h3_ccu_reset(DeviceState *dev)
+{
+ AwH3ClockCtlState *s = AW_H3_CCU(dev);
+
+ /* Set default values for registers */
+ s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST;
+ s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST;
+ s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST;
+ s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST;
+ s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST;
+ s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST;
+ s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST;
+ s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST;
+ s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST;
+ s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST;
+ s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST;
+ s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST;
+ s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST;
+ s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST;
+ s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST;
+ s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST;
+}
+
+static void allwinner_h3_ccu_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwH3ClockCtlState *s = AW_H3_CCU(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
+ TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_h3_ccu_vmstate = {
+ .name = "allwinner-h3-ccu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = allwinner_h3_ccu_reset;
+ dc->vmsd = &allwinner_h3_ccu_vmstate;
+}
+
+static const TypeInfo allwinner_h3_ccu_info = {
+ .name = TYPE_AW_H3_CCU,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_h3_ccu_init,
+ .instance_size = sizeof(AwH3ClockCtlState),
+ .class_init = allwinner_h3_ccu_class_init,
+};
+
+static void allwinner_h3_ccu_register(void)
+{
+ type_register_static(&allwinner_h3_ccu_info);
+}
+
+type_init(allwinner_h3_ccu_register)
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index da993f45b7..5e635b74d5 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
common-obj-$(CONFIG_NSERIES) += cbus.o
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 04/18] hw/arm/allwinner-h3: add USB host controller
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (2 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 03/18] hw/arm/allwinner-h3: add Clock Control Unit Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-03 11:11 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 05/18] hw/arm/allwinner-h3: add System Control module Niek Linnenbank
` (13 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/usb/hcd-ehci.h | 1 +
include/hw/arm/allwinner-h3.h | 8 +++++++
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
hw/arm/Kconfig | 2 ++
5 files changed, 72 insertions(+)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 0298238f0b..edb59311c4 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -342,6 +342,7 @@ typedef struct EHCIPCIState {
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index abdc20871a..4f4dcbcd17 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -56,6 +56,14 @@ enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
+ AW_H3_EHCI0,
+ AW_H3_OHCI0,
+ AW_H3_EHCI1,
+ AW_H3_OHCI1,
+ AW_H3_EHCI2,
+ AW_H3_OHCI2,
+ AW_H3_EHCI3,
+ AW_H3_OHCI3,
AW_H3_CCU,
AW_H3_PIT,
AW_H3_UART0,
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 1fff3c317b..c205f06738 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -28,6 +28,7 @@
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "hw/misc/unimp.h"
+#include "hw/usb/hcd-ehci.h"
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
@@ -36,6 +37,14 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_SRAM_A1] = 0x00000000,
[AW_H3_SRAM_A2] = 0x00044000,
[AW_H3_SRAM_C] = 0x00010000,
+ [AW_H3_EHCI0] = 0x01c1a000,
+ [AW_H3_OHCI0] = 0x01c1a400,
+ [AW_H3_EHCI1] = 0x01c1b000,
+ [AW_H3_OHCI1] = 0x01c1b400,
+ [AW_H3_EHCI2] = 0x01c1c000,
+ [AW_H3_OHCI2] = 0x01c1c400,
+ [AW_H3_EHCI3] = 0x01c1d000,
+ [AW_H3_OHCI3] = 0x01c1d400,
[AW_H3_CCU] = 0x01c20000,
[AW_H3_PIT] = 0x01c20c00,
[AW_H3_UART0] = 0x01c28000,
@@ -144,6 +153,14 @@ enum {
AW_H3_GIC_SPI_UART3 = 3,
AW_H3_GIC_SPI_TIMER0 = 18,
AW_H3_GIC_SPI_TIMER1 = 19,
+ AW_H3_GIC_SPI_EHCI0 = 72,
+ AW_H3_GIC_SPI_OHCI0 = 73,
+ AW_H3_GIC_SPI_EHCI1 = 74,
+ AW_H3_GIC_SPI_OHCI1 = 75,
+ AW_H3_GIC_SPI_EHCI2 = 76,
+ AW_H3_GIC_SPI_OHCI2 = 77,
+ AW_H3_GIC_SPI_EHCI3 = 78,
+ AW_H3_GIC_SPI_OHCI3 = 79,
};
/* Allwinner H3 general constants */
@@ -284,6 +301,33 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_init_nofail(DEVICE(&s->ccu));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
+ /* Universal Serial Bus */
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI0));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI1));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI2));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI3));
+
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI0));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI1));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI2));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI3));
+
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 5b7991cffe..3730736540 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -131,6 +131,22 @@ static const TypeInfo ehci_exynos4210_type_info = {
.class_init = ehci_exynos4210_class_init,
};
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
+{
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ sec->capsbase = 0x0;
+ sec->opregbase = 0x10;
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
+}
+
+static const TypeInfo ehci_aw_h3_type_info = {
+ .name = TYPE_AW_H3_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_aw_h3_class_init,
+};
+
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@@ -252,6 +268,7 @@ static void ehci_sysbus_register_types(void)
type_register_static(&ehci_type_info);
type_register_static(&ehci_platform_type_info);
type_register_static(&ehci_exynos4210_type_info);
+ type_register_static(&ehci_aw_h3_type_info);
type_register_static(&ehci_tegra2_type_info);
type_register_static(&ehci_ppc4xx_type_info);
type_register_static(&ehci_fusbh200_type_info);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a7034218f0..5d78deba11 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -303,6 +303,8 @@ config ALLWINNER_H3
select ARM_TIMER
select ARM_GIC
select UNIMP
+ select USB_OHCI
+ select USB_EHCI_SYSBUS
config RASPI
bool
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 05/18] hw/arm/allwinner-h3: add System Control module
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (3 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 04/18] hw/arm/allwinner-h3: add USB host controller Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-03 12:01 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module Niek Linnenbank
` (12 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
hw/arm/allwinner-h3.c | 9 +-
hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
5 files changed, 219 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 4f4dcbcd17..43500c4262 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -40,6 +40,7 @@
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/arm_gic.h"
#include "hw/misc/allwinner-h3-ccu.h"
+#include "hw/misc/allwinner-h3-sysctrl.h"
#include "target/arm/cpu.h"
/**
@@ -56,6 +57,7 @@ enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
+ AW_H3_SYSCTRL,
AW_H3_EHCI0,
AW_H3_OHCI0,
AW_H3_EHCI1,
@@ -108,6 +110,7 @@ typedef struct AwH3State {
const hwaddr *memmap;
AwA10PITState timer;
AwH3ClockCtlState ccu;
+ AwH3SysCtrlState sysctrl;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h
new file mode 100644
index 0000000000..af4119e026
--- /dev/null
+++ b/include/hw/misc/allwinner-h3-sysctrl.h
@@ -0,0 +1,67 @@
+/*
+ * Allwinner H3 System Control emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
+#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Highest register address used by System Control device */
+#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
+
+/** Total number of known registers */
+#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
+ sizeof(uint32_t)) + 1)
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
+#define AW_H3_SYSCTRL(obj) \
+ OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
+
+/** @} */
+
+/**
+ * Allwinner H3 System Control object instance state
+ */
+typedef struct AwH3SysCtrlState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
+
+} AwH3SysCtrlState;
+
+#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index c205f06738..0aa46712db 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -37,6 +37,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_SRAM_A1] = 0x00000000,
[AW_H3_SRAM_A2] = 0x00044000,
[AW_H3_SRAM_C] = 0x00010000,
+ [AW_H3_SYSCTRL] = 0x01c00000,
[AW_H3_EHCI0] = 0x01c1a000,
[AW_H3_OHCI0] = 0x01c1a400,
[AW_H3_EHCI1] = 0x01c1b000,
@@ -66,7 +67,6 @@ struct AwH3Unimplemented {
} unimplemented[] = {
{ "d-engine", 0x01000000, 4 * MiB },
{ "d-inter", 0x01400000, 128 * KiB },
- { "syscon", 0x01c00000, 4 * KiB },
{ "dma", 0x01c02000, 4 * KiB },
{ "nfdc", 0x01c03000, 4 * KiB },
{ "ts", 0x01c06000, 4 * KiB },
@@ -192,6 +192,9 @@ static void allwinner_h3_init(Object *obj)
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
TYPE_AW_H3_CCU);
+
+ sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
+ TYPE_AW_H3_SYSCTRL);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -301,6 +304,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_init_nofail(DEVICE(&s->ccu));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
+ /* System Control */
+ qdev_init_nofail(DEVICE(&s->sysctrl));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
new file mode 100644
index 0000000000..1d07efa880
--- /dev/null
+++ b/hw/misc/allwinner-h3-sysctrl.c
@@ -0,0 +1,140 @@
+/*
+ * Allwinner H3 System Control emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-h3-sysctrl.h"
+
+/* System Control register offsets */
+enum {
+ REG_VER = 0x24, /* Version */
+ REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
+};
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+/* System Control register reset values */
+enum {
+ REG_VER_RST = 0x0,
+ REG_EMAC_PHY_CLK_RST = 0x58000,
+};
+
+static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ return s->regs[idx];
+}
+
+static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ switch (offset) {
+ case REG_VER: /* Version */
+ break;
+ default:
+ s->regs[idx] = (uint32_t) val;
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
+ .read = allwinner_h3_sysctrl_read,
+ .write = allwinner_h3_sysctrl_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static void allwinner_h3_sysctrl_reset(DeviceState *dev)
+{
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
+
+ /* Set default values for registers */
+ s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
+ s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
+}
+
+static void allwinner_h3_sysctrl_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
+ TYPE_AW_H3_SYSCTRL, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
+ .name = "allwinner-h3-sysctrl",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = allwinner_h3_sysctrl_reset;
+ dc->vmsd = &allwinner_h3_sysctrl_vmstate;
+}
+
+static const TypeInfo allwinner_h3_sysctrl_info = {
+ .name = TYPE_AW_H3_SYSCTRL,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_h3_sysctrl_init,
+ .instance_size = sizeof(AwH3SysCtrlState),
+ .class_init = allwinner_h3_sysctrl_class_init,
+};
+
+static void allwinner_h3_sysctrl_register(void)
+{
+ type_register_static(&allwinner_h3_sysctrl_info);
+}
+
+type_init(allwinner_h3_sysctrl_register)
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 5e635b74d5..63b2e528f9 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
common-obj-$(CONFIG_NSERIES) += cbus.o
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (4 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 05/18] hw/arm/allwinner-h3: add System Control module Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-03 12:09 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 07/18] hw/arm/allwinner: add Security Identifier device Niek Linnenbank
` (11 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
Various Allwinner System on Chip designs contain multiple processors
that can be configured and reset using the generic CPU Configuration
module interface. This commit adds support for the Allwinner CPU
configuration interface which emulates the following features:
* CPU reset
* CPU status
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-cpucfg.h | 52 ++++++
hw/arm/allwinner-h3.c | 9 +-
hw/misc/allwinner-cpucfg.c | 271 +++++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/trace-events | 5 +
6 files changed, 340 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-cpucfg.h
create mode 100644 hw/misc/allwinner-cpucfg.c
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 43500c4262..dc729176ab 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -40,6 +40,7 @@
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/arm_gic.h"
#include "hw/misc/allwinner-h3-ccu.h"
+#include "hw/misc/allwinner-cpucfg.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "target/arm/cpu.h"
@@ -76,6 +77,7 @@ enum {
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
AW_H3_GIC_VCPU,
+ AW_H3_CPUCFG,
AW_H3_SDRAM
};
@@ -110,6 +112,7 @@ typedef struct AwH3State {
const hwaddr *memmap;
AwA10PITState timer;
AwH3ClockCtlState ccu;
+ AwCpuCfgState cpucfg;
AwH3SysCtrlState sysctrl;
GICState gic;
MemoryRegion sram_a1;
diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h
new file mode 100644
index 0000000000..2c3693a8be
--- /dev/null
+++ b/include/hw/misc/allwinner-cpucfg.h
@@ -0,0 +1,52 @@
+/*
+ * Allwinner CPU Configuration Module emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_CPUCFG_H
+#define HW_MISC_ALLWINNER_CPUCFG_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_CPUCFG "allwinner-cpucfg"
+#define AW_CPUCFG(obj) \
+ OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG)
+
+/** @} */
+
+/**
+ * Allwinner CPU Configuration Module instance state
+ */
+typedef struct AwCpuCfgState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ MemoryRegion iomem;
+ uint32_t gen_ctrl;
+ uint32_t super_standby;
+ uint32_t entry_addr;
+
+} AwCpuCfgState;
+
+#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 0aa46712db..b9a5597f2a 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -56,6 +56,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_GIC_CPU] = 0x01c82000,
[AW_H3_GIC_HYP] = 0x01c84000,
[AW_H3_GIC_VCPU] = 0x01c86000,
+ [AW_H3_CPUCFG] = 0x01f01c00,
[AW_H3_SDRAM] = 0x40000000
};
@@ -122,7 +123,6 @@ struct AwH3Unimplemented {
{ "r_wdog", 0x01f01000, 1 * KiB },
{ "r_prcm", 0x01f01400, 1 * KiB },
{ "r_twd", 0x01f01800, 1 * KiB },
- { "r_cpucfg", 0x01f01c00, 1 * KiB },
{ "r_cir-rx", 0x01f02000, 1 * KiB },
{ "r_twi", 0x01f02400, 1 * KiB },
{ "r_uart", 0x01f02800, 1 * KiB },
@@ -195,6 +195,9 @@ static void allwinner_h3_init(Object *obj)
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
TYPE_AW_H3_SYSCTRL);
+
+ sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
+ TYPE_AW_CPUCFG);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -308,6 +311,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_init_nofail(DEVICE(&s->sysctrl));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
+ /* CPU Configuration */
+ qdev_init_nofail(DEVICE(&s->cpucfg));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c
new file mode 100644
index 0000000000..2f84606edf
--- /dev/null
+++ b/hw/misc/allwinner-cpucfg.c
@@ -0,0 +1,271 @@
+/*
+ * Allwinner CPU Configuration Module emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "qemu/timer.h"
+#include "hw/core/cpu.h"
+#include "arm-powerctl.h"
+#include "hw/misc/allwinner-cpucfg.h"
+#include "trace.h"
+
+/* CPUCFG register offsets */
+enum {
+ REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */
+ REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
+ REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
+ REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
+ REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
+ REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
+ REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */
+ REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
+ REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
+ REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */
+ REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
+ REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
+ REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */
+ REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */
+ REG_CLK_GATING = 0x0144, /* CPU Clock Gating */
+ REG_GEN_CTRL = 0x0184, /* General Control */
+ REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */
+ REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */
+ REG_DBG_EXTERN = 0x01E4, /* Debug External */
+ REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
+ REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
+ REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
+};
+
+/* CPUCFG register flags */
+enum {
+ CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)),
+ CPUX_STATUS_SMP = (1 << 0),
+ CPU_SYS_RESET_RELEASED = (1 << 0),
+ CLK_GATING_ENABLE = ((1 << 8) | 0xF),
+};
+
+/* CPUCFG register reset values */
+enum {
+ REG_CLK_GATING_RST = 0x0000010F,
+ REG_GEN_CTRL_RST = 0x00000020,
+ REG_SUPER_STANDBY_RST = 0x0,
+ REG_CNT64_CTRL_RST = 0x0,
+};
+
+/* CPUCFG constants */
+enum {
+ CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
+};
+
+static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
+{
+ int ret;
+
+ trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
+
+ ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
+ CPU_EXCEPTION_LEVEL_ON_RESET, false);
+ if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) {
+ error_report("%s: failed to bring up CPU %d: err %d",
+ __func__, cpu_id, ret);
+ return;
+ }
+}
+
+static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwCpuCfgState *s = AW_CPUCFG(opaque);
+ uint64_t val = 0;
+
+ switch (offset) {
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
+ case REG_CPU_SYS_RST: /* CPU System Reset */
+ val = CPU_SYS_RESET_RELEASED;
+ break;
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
+ val = CPUX_RESET_RELEASED;
+ break;
+ case REG_CPU0_CTRL: /* CPU#0 Control */
+ case REG_CPU1_CTRL: /* CPU#1 Control */
+ case REG_CPU2_CTRL: /* CPU#2 Control */
+ case REG_CPU3_CTRL: /* CPU#3 Control */
+ val = 0;
+ break;
+ case REG_CPU0_STATUS: /* CPU#0 Status */
+ case REG_CPU1_STATUS: /* CPU#1 Status */
+ case REG_CPU2_STATUS: /* CPU#2 Status */
+ case REG_CPU3_STATUS: /* CPU#3 Status */
+ val = CPUX_STATUS_SMP;
+ break;
+ case REG_CLK_GATING: /* CPU Clock Gating */
+ val = CLK_GATING_ENABLE;
+ break;
+ case REG_GEN_CTRL: /* General Control */
+ val = s->gen_ctrl;
+ break;
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
+ val = s->super_standby;
+ break;
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
+ val = s->entry_addr;
+ break;
+ case REG_DBG_EXTERN: /* Debug External */
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+
+ trace_allwinner_cpucfg_read(offset, val, size);
+
+ return val;
+}
+
+static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwCpuCfgState *s = AW_CPUCFG(opaque);
+
+ trace_allwinner_cpucfg_write(offset, val, size);
+
+ switch (offset) {
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
+ case REG_CPU_SYS_RST: /* CPU System Reset */
+ break;
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
+ if (val) {
+ allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6);
+ }
+ break;
+ case REG_CPU0_CTRL: /* CPU#0 Control */
+ case REG_CPU1_CTRL: /* CPU#1 Control */
+ case REG_CPU2_CTRL: /* CPU#2 Control */
+ case REG_CPU3_CTRL: /* CPU#3 Control */
+ case REG_CPU0_STATUS: /* CPU#0 Status */
+ case REG_CPU1_STATUS: /* CPU#1 Status */
+ case REG_CPU2_STATUS: /* CPU#2 Status */
+ case REG_CPU3_STATUS: /* CPU#3 Status */
+ case REG_CLK_GATING: /* CPU Clock Gating */
+ break;
+ case REG_GEN_CTRL: /* General Control */
+ s->gen_ctrl = val;
+ break;
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
+ s->super_standby = val;
+ break;
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
+ s->entry_addr = val;
+ break;
+ case REG_DBG_EXTERN: /* Debug External */
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_cpucfg_ops = {
+ .read = allwinner_cpucfg_read,
+ .write = allwinner_cpucfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static void allwinner_cpucfg_reset(DeviceState *dev)
+{
+ AwCpuCfgState *s = AW_CPUCFG(dev);
+
+ /* Set default values for registers */
+ s->gen_ctrl = REG_GEN_CTRL_RST;
+ s->super_standby = REG_SUPER_STANDBY_RST;
+ s->entry_addr = 0;
+}
+
+static void allwinner_cpucfg_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwCpuCfgState *s = AW_CPUCFG(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s,
+ TYPE_AW_CPUCFG, 1 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_cpucfg_vmstate = {
+ .name = "allwinner-cpucfg",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(gen_ctrl, AwCpuCfgState),
+ VMSTATE_UINT32(super_standby, AwCpuCfgState),
+ VMSTATE_UINT32(entry_addr, AwCpuCfgState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = allwinner_cpucfg_reset;
+ dc->vmsd = &allwinner_cpucfg_vmstate;
+}
+
+static const TypeInfo allwinner_cpucfg_info = {
+ .name = TYPE_AW_CPUCFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_cpucfg_init,
+ .instance_size = sizeof(AwCpuCfgState),
+ .class_init = allwinner_cpucfg_class_init,
+};
+
+static void allwinner_cpucfg_register(void)
+{
+ type_register_static(&allwinner_cpucfg_info);
+}
+
+type_init(allwinner_cpucfg_register)
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 63b2e528f9..f3788a5903 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
common-obj-$(CONFIG_NSERIES) += cbus.o
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 7f0f5dff3a..ede1650672 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -1,5 +1,10 @@
# See docs/devel/tracing.txt for syntax documentation.
+# allwinner-cpucfg.c
+allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32
+allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+
# eccmemctl.c
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 07/18] hw/arm/allwinner: add Security Identifier device
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (5 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 08/18] hw/arm/allwinner: add SD/MMC host controller Niek Linnenbank
` (10 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-sid.h | 60 ++++++++++++
hw/arm/allwinner-h3.c | 11 ++-
hw/arm/orangepi.c | 9 ++
hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/trace-events | 4 +
7 files changed, 255 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-sid.h
create mode 100644 hw/misc/allwinner-sid.c
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index dc729176ab..85416d9d64 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -42,6 +42,7 @@
#include "hw/misc/allwinner-h3-ccu.h"
#include "hw/misc/allwinner-cpucfg.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
+#include "hw/misc/allwinner-sid.h"
#include "target/arm/cpu.h"
/**
@@ -59,6 +60,7 @@ enum {
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
AW_H3_SYSCTRL,
+ AW_H3_SID,
AW_H3_EHCI0,
AW_H3_OHCI0,
AW_H3_EHCI1,
@@ -114,6 +116,7 @@ typedef struct AwH3State {
AwH3ClockCtlState ccu;
AwCpuCfgState cpucfg;
AwH3SysCtrlState sysctrl;
+ AwSidState sid;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h
new file mode 100644
index 0000000000..4c1fa4762b
--- /dev/null
+++ b/include/hw/misc/allwinner-sid.h
@@ -0,0 +1,60 @@
+/*
+ * Allwinner Security ID emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_SID_H
+#define HW_MISC_ALLWINNER_SID_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "qemu/uuid.h"
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_SID "allwinner-sid"
+#define AW_SID(obj) \
+ OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID)
+
+/** @} */
+
+/**
+ * Allwinner Security ID object instance state
+ */
+typedef struct AwSidState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Control register defines how and what to read */
+ uint32_t control;
+
+ /** RdKey register contains the data retrieved by the device */
+ uint32_t rdkey;
+
+ /** Stores the emulated device identifier */
+ QemuUUID identifier;
+
+} AwSidState;
+
+#endif /* HW_MISC_ALLWINNER_SID_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index b9a5597f2a..deeea63f5f 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -38,6 +38,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_SRAM_A2] = 0x00044000,
[AW_H3_SRAM_C] = 0x00010000,
[AW_H3_SYSCTRL] = 0x01c00000,
+ [AW_H3_SID] = 0x01c14000,
[AW_H3_EHCI0] = 0x01c1a000,
[AW_H3_OHCI0] = 0x01c1a400,
[AW_H3_EHCI1] = 0x01c1b000,
@@ -78,7 +79,6 @@ struct AwH3Unimplemented {
{ "mmc0", 0x01c0f000, 4 * KiB },
{ "mmc1", 0x01c10000, 4 * KiB },
{ "mmc2", 0x01c11000, 4 * KiB },
- { "sid", 0x01c14000, 1 * KiB },
{ "crypto", 0x01c15000, 4 * KiB },
{ "msgbox", 0x01c17000, 4 * KiB },
{ "spinlock", 0x01c18000, 4 * KiB },
@@ -198,6 +198,11 @@ static void allwinner_h3_init(Object *obj)
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
TYPE_AW_CPUCFG);
+
+ sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
+ TYPE_AW_SID);
+ object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
+ "identifier", &error_abort);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -315,6 +320,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_init_nofail(DEVICE(&s->cpucfg));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
+ /* Security Identifier */
+ qdev_init_nofail(DEVICE(&s->sid));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 19adfca917..e27e5802ed 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -62,6 +62,15 @@ static void orangepi_init(MachineState *machine)
object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
&error_abort);
+ /* Setup SID properties. Currently using a default fixed SID identifier. */
+ if (qemu_uuid_is_null(&h3->sid.identifier)) {
+ qdev_prop_set_string(DEVICE(h3), "identifier",
+ "02c00081-1111-2222-3333-000044556677");
+ } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) {
+ fprintf(stderr, "WARNING: Security Identifier value does "
+ "not include H3 prefix\n");
+ }
+
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c
new file mode 100644
index 0000000000..196380c33a
--- /dev/null
+++ b/hw/misc/allwinner-sid.c
@@ -0,0 +1,168 @@
+/*
+ * Allwinner Security ID emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/allwinner-sid.h"
+#include "trace.h"
+
+/* SID register offsets */
+enum {
+ REG_PRCTL = 0x40, /* Control */
+ REG_RDKEY = 0x60, /* Read Key */
+};
+
+/* SID register flags */
+enum {
+ REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */
+ REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */
+};
+
+static uint64_t allwinner_sid_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwSidState *s = AW_SID(opaque);
+ uint64_t val = 0;
+
+ switch (offset) {
+ case REG_PRCTL: /* Control */
+ val = s->control;
+ break;
+ case REG_RDKEY: /* Read Key */
+ val = s->rdkey;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_sid_read(offset, val, size);
+
+ return val;
+}
+
+static void allwinner_sid_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwSidState *s = AW_SID(opaque);
+
+ trace_allwinner_sid_write(offset, val, size);
+
+ switch (offset) {
+ case REG_PRCTL: /* Control */
+ s->control = val;
+
+ if ((s->control & REG_PRCTL_OP_LOCK) &&
+ (s->control & REG_PRCTL_WRITE)) {
+ uint32_t id = s->control >> 16;
+
+ if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) {
+ s->rdkey = ldl_be_p(&s->identifier.data[id]);
+ }
+ }
+ s->control &= ~REG_PRCTL_WRITE;
+ break;
+ case REG_RDKEY: /* Read Key */
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_sid_ops = {
+ .read = allwinner_sid_read,
+ .write = allwinner_sid_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static void allwinner_sid_reset(DeviceState *dev)
+{
+ AwSidState *s = AW_SID(dev);
+
+ /* Set default values for registers */
+ s->control = 0;
+ s->rdkey = 0;
+}
+
+static void allwinner_sid_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwSidState *s = AW_SID(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s,
+ TYPE_AW_SID, 1 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static Property allwinner_sid_properties[] = {
+ DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static const VMStateDescription allwinner_sid_vmstate = {
+ .name = "allwinner-sid",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(control, AwSidState),
+ VMSTATE_UINT32(rdkey, AwSidState),
+ VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_sid_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = allwinner_sid_reset;
+ dc->vmsd = &allwinner_sid_vmstate;
+ device_class_set_props(dc, allwinner_sid_properties);
+}
+
+static const TypeInfo allwinner_sid_info = {
+ .name = TYPE_AW_SID,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_sid_init,
+ .instance_size = sizeof(AwSidState),
+ .class_init = allwinner_sid_class_init,
+};
+
+static void allwinner_sid_register(void)
+{
+ type_register_static(&allwinner_sid_info);
+}
+
+type_init(allwinner_sid_register)
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f3788a5903..daa734036e 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -31,6 +31,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
common-obj-$(CONFIG_NSERIES) += cbus.o
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index ede1650672..4f38328d9c 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -5,6 +5,10 @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+# allwinner-sid.c
+allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+
# eccmemctl.c
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 08/18] hw/arm/allwinner: add SD/MMC host controller
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (6 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 07/18] hw/arm/allwinner: add Security Identifier device Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-03 12:34 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 09/18] hw/arm/allwinner-h3: add EMAC ethernet device Niek Linnenbank
` (9 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated features:
* DMA transfers
* Direct FIFO I/O
* Short/Long format command responses
* Auto-Stop command (CMD12)
* Insert & remove card detection
The following boards are extended with the SD host controller:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/arm/allwinner-a10.h | 2 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/sd/allwinner-sdhost.h | 135 +++++
hw/arm/allwinner-a10.c | 11 +
hw/arm/allwinner-h3.c | 15 +-
hw/arm/cubieboard.c | 15 +
hw/arm/orangepi.c | 16 +
hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
hw/sd/Makefile.objs | 1 +
hw/sd/trace-events | 7 +
11 files changed, 1059 insertions(+), 1 deletion(-)
create mode 100644 include/hw/sd/allwinner-sdhost.h
create mode 100644 hw/sd/allwinner-sdhost.c
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index 8af724548f..ae33a84b18 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -7,6 +7,7 @@
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/allwinner-a10-pic.h"
#include "hw/net/allwinner_emac.h"
+#include "hw/sd/allwinner-sdhost.h"
#include "hw/ide/ahci.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
@@ -31,6 +32,7 @@ typedef struct AwA10State {
AwA10PICState intc;
AwEmacState emac;
AllwinnerAHCIState sata;
+ AwSdHostState mmc0;
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];
OHCISysBusState ohci[AW_A10_NUM_USB];
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 85416d9d64..d71a4917ab 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -43,6 +43,7 @@
#include "hw/misc/allwinner-cpucfg.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "hw/misc/allwinner-sid.h"
+#include "hw/sd/allwinner-sdhost.h"
#include "target/arm/cpu.h"
/**
@@ -60,6 +61,7 @@ enum {
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
AW_H3_SYSCTRL,
+ AW_H3_MMC0,
AW_H3_SID,
AW_H3_EHCI0,
AW_H3_OHCI0,
@@ -117,6 +119,7 @@ typedef struct AwH3State {
AwCpuCfgState cpucfg;
AwH3SysCtrlState sysctrl;
AwSidState sid;
+ AwSdHostState mmc0;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
new file mode 100644
index 0000000000..d94606a853
--- /dev/null
+++ b/include/hw/sd/allwinner-sdhost.h
@@ -0,0 +1,135 @@
+/*
+ * Allwinner (sun4i and above) SD Host Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SD_ALLWINNER_SDHOST_H
+#define HW_SD_ALLWINNER_SDHOST_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "hw/sd/sd.h"
+
+/**
+ * Object model types
+ * @{
+ */
+
+/** Generic Allwinner SD Host Controller (abstract) */
+#define TYPE_AW_SDHOST "allwinner-sdhost"
+
+/** Allwinner sun4i family (A10, A12) */
+#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
+
+/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
+#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
+
+/** @} */
+
+/**
+ * Object model macros
+ * @{
+ */
+
+#define AW_SDHOST(obj) \
+ OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST)
+#define AW_SDHOST_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST)
+#define AW_SDHOST_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST)
+
+/** @} */
+
+/**
+ * Allwinner SD Host Controller object instance state.
+ */
+typedef struct AwSdHostState {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+
+ /** Secure Digital (SD) bus, which connects to SD card (if present) */
+ SDBus sdbus;
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Interrupt output signal to notify CPU */
+ qemu_irq irq;
+
+ /** Number of bytes left in current DMA transfer */
+ uint32_t transfer_cnt;
+
+ /**
+ * @name Hardware Registers
+ * @{
+ */
+
+ uint32_t global_ctl; /**< Global Control */
+ uint32_t clock_ctl; /**< Clock Control */
+ uint32_t timeout; /**< Timeout */
+ uint32_t bus_width; /**< Bus Width */
+ uint32_t block_size; /**< Block Size */
+ uint32_t byte_count; /**< Byte Count */
+
+ uint32_t command; /**< Command */
+ uint32_t command_arg; /**< Command Argument */
+ uint32_t response[4]; /**< Command Response */
+
+ uint32_t irq_mask; /**< Interrupt Mask */
+ uint32_t irq_status; /**< Raw Interrupt Status */
+ uint32_t status; /**< Status */
+
+ uint32_t fifo_wlevel; /**< FIFO Water Level */
+ uint32_t fifo_func_sel; /**< FIFO Function Select */
+ uint32_t debug_enable; /**< Debug Enable */
+ uint32_t auto12_arg; /**< Auto Command 12 Argument */
+ uint32_t newtiming_set; /**< SD New Timing Set */
+ uint32_t newtiming_debug; /**< SD New Timing Debug */
+ uint32_t hardware_rst; /**< Hardware Reset */
+ uint32_t dmac; /**< Internal DMA Controller Control */
+ uint32_t desc_base; /**< Descriptor List Base Address */
+ uint32_t dmac_status; /**< Internal DMA Controller Status */
+ uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
+ uint32_t card_threshold; /**< Card Threshold Control */
+ uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
+ uint32_t response_crc; /**< Response CRC */
+ uint32_t data_crc[8]; /**< Data CRC */
+ uint32_t status_crc; /**< Status CRC */
+
+ /** @} */
+
+} AwSdHostState;
+
+/**
+ * Allwinner SD Host Controller class-level struct.
+ *
+ * This struct is filled by each sunxi device specific code
+ * such that the generic code can use this struct to support
+ * all devices.
+ */
+typedef struct AwSdHostClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ /** Maximum buffer size in bytes per DMA descriptor */
+ size_t max_desc_size;
+
+} AwSdHostClass;
+
+#endif /* HW_SD_ALLWINNER_SDHOST_H */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 2ae9c15311..dc62c76416 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -27,6 +27,7 @@
#include "hw/boards.h"
#include "hw/usb/hcd-ohci.h"
+#define AW_A10_MMC0_BASE 0x01c0f000
#define AW_A10_PIC_REG_BASE 0x01c20400
#define AW_A10_PIT_REG_BASE 0x01c20c00
#define AW_A10_UART0_REG_BASE 0x01c28000
@@ -64,6 +65,9 @@ static void aw_a10_init(Object *obj)
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
}
}
+
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
+ TYPE_AW_SDHOST_SUN4I);
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -164,6 +168,13 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(dev, 64 + i));
}
}
+
+ /* SD/MMC */
+ qdev_init_nofail(DEVICE(&s->mmc0));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
+ "sd-bus", &error_abort);
}
static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index deeea63f5f..8c7ac61517 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -38,6 +38,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_SRAM_A2] = 0x00044000,
[AW_H3_SRAM_C] = 0x00010000,
[AW_H3_SYSCTRL] = 0x01c00000,
+ [AW_H3_MMC0] = 0x01c0f000,
[AW_H3_SID] = 0x01c14000,
[AW_H3_EHCI0] = 0x01c1a000,
[AW_H3_OHCI0] = 0x01c1a400,
@@ -76,7 +77,6 @@ struct AwH3Unimplemented {
{ "lcd0", 0x01c0c000, 4 * KiB },
{ "lcd1", 0x01c0d000, 4 * KiB },
{ "ve", 0x01c0e000, 4 * KiB },
- { "mmc0", 0x01c0f000, 4 * KiB },
{ "mmc1", 0x01c10000, 4 * KiB },
{ "mmc2", 0x01c11000, 4 * KiB },
{ "crypto", 0x01c15000, 4 * KiB },
@@ -153,6 +153,7 @@ enum {
AW_H3_GIC_SPI_UART3 = 3,
AW_H3_GIC_SPI_TIMER0 = 18,
AW_H3_GIC_SPI_TIMER1 = 19,
+ AW_H3_GIC_SPI_MMC0 = 60,
AW_H3_GIC_SPI_EHCI0 = 72,
AW_H3_GIC_SPI_OHCI0 = 73,
AW_H3_GIC_SPI_EHCI1 = 74,
@@ -203,6 +204,9 @@ static void allwinner_h3_init(Object *obj)
TYPE_AW_SID);
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
"identifier", &error_abort);
+
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
+ TYPE_AW_SDHOST_SUN5I);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -324,6 +328,15 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_init_nofail(DEVICE(&s->sid));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
+ /* SD/MMC */
+ qdev_init_nofail(DEVICE(&s->mmc0));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
+
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
+ "sd-bus", &error_abort);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 089f9a30c1..91c09b054b 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/boards.h"
+#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
static struct arm_boot_info cubieboard_binfo = {
@@ -32,6 +33,10 @@ static void cubieboard_init(MachineState *machine)
{
AwA10State *a10 = AW_A10(object_new(TYPE_AW_A10));
Error *err = NULL;
+ DriveInfo *di;
+ BlockBackend *blk;
+ BusState *bus;
+ DeviceState *carddev;
object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
if (err != NULL) {
@@ -57,6 +62,16 @@ static void cubieboard_init(MachineState *machine)
exit(1);
}
+ /* Retrieve SD bus */
+ di = drive_get_next(IF_SD);
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
+ bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
+
+ /* Plug in SD card */
+ carddev = qdev_create(bus, TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
machine->ram);
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index e27e5802ed..d5291036a6 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -35,6 +35,10 @@ static struct arm_boot_info orangepi_binfo = {
static void orangepi_init(MachineState *machine)
{
AwH3State *h3;
+ DriveInfo *di;
+ BlockBackend *blk;
+ BusState *bus;
+ DeviceState *carddev;
/* BIOS is not supported by this board */
if (bios_name) {
@@ -74,6 +78,16 @@ static void orangepi_init(MachineState *machine)
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
+ /* Retrieve SD bus */
+ di = drive_get_next(IF_SD);
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
+ bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
+
+ /* Plug in SD card */
+ carddev = qdev_create(bus, TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+
/* SDRAM */
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
machine->ram);
@@ -87,6 +101,8 @@ static void orangepi_machine_init(MachineClass *mc)
{
mc->desc = "Orange Pi PC";
mc->init = orangepi_init;
+ mc->block_default_type = IF_SD;
+ mc->units_per_default_bus = 1;
mc->min_cpus = AW_H3_NUM_CPUS;
mc->max_cpus = AW_H3_NUM_CPUS;
mc->default_cpus = AW_H3_NUM_CPUS;
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
new file mode 100644
index 0000000000..f404e1fdb4
--- /dev/null
+++ b/hw/sd/allwinner-sdhost.c
@@ -0,0 +1,854 @@
+/*
+ * Allwinner (sun4i and above) SD Host Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "sysemu/blockdev.h"
+#include "hw/irq.h"
+#include "hw/sd/allwinner-sdhost.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
+#define AW_SDHOST_BUS(obj) \
+ OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
+
+/* SD Host register offsets */
+enum {
+ REG_SD_GCTL = 0x00, /* Global Control */
+ REG_SD_CKCR = 0x04, /* Clock Control */
+ REG_SD_TMOR = 0x08, /* Timeout */
+ REG_SD_BWDR = 0x0C, /* Bus Width */
+ REG_SD_BKSR = 0x10, /* Block Size */
+ REG_SD_BYCR = 0x14, /* Byte Count */
+ REG_SD_CMDR = 0x18, /* Command */
+ REG_SD_CAGR = 0x1C, /* Command Argument */
+ REG_SD_RESP0 = 0x20, /* Response Zero */
+ REG_SD_RESP1 = 0x24, /* Response One */
+ REG_SD_RESP2 = 0x28, /* Response Two */
+ REG_SD_RESP3 = 0x2C, /* Response Three */
+ REG_SD_IMKR = 0x30, /* Interrupt Mask */
+ REG_SD_MISR = 0x34, /* Masked Interrupt Status */
+ REG_SD_RISR = 0x38, /* Raw Interrupt Status */
+ REG_SD_STAR = 0x3C, /* Status */
+ REG_SD_FWLR = 0x40, /* FIFO Water Level */
+ REG_SD_FUNS = 0x44, /* FIFO Function Select */
+ REG_SD_DBGC = 0x50, /* Debug Enable */
+ REG_SD_A12A = 0x58, /* Auto command 12 argument */
+ REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
+ REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
+ REG_SD_HWRST = 0x78, /* Hardware Reset Register */
+ REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
+ REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
+ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
+ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
+ REG_SD_THLDC = 0x100, /* Card Threshold Control */
+ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
+ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
+ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
+ REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
+ REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
+ REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
+ REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
+ REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
+ REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
+ REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
+ REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
+ REG_SD_FIFO = 0x200, /* Read/Write FIFO */
+};
+
+/* SD Host register flags */
+enum {
+ SD_GCTL_FIFO_AC_MOD = (1 << 31),
+ SD_GCTL_DDR_MOD_SEL = (1 << 10),
+ SD_GCTL_CD_DBC_ENB = (1 << 8),
+ SD_GCTL_DMA_ENB = (1 << 5),
+ SD_GCTL_INT_ENB = (1 << 4),
+ SD_GCTL_DMA_RST = (1 << 2),
+ SD_GCTL_FIFO_RST = (1 << 1),
+ SD_GCTL_SOFT_RST = (1 << 0),
+};
+
+enum {
+ SD_CMDR_LOAD = (1 << 31),
+ SD_CMDR_CLKCHANGE = (1 << 21),
+ SD_CMDR_WRITE = (1 << 10),
+ SD_CMDR_AUTOSTOP = (1 << 12),
+ SD_CMDR_DATA = (1 << 9),
+ SD_CMDR_RESPONSE_LONG = (1 << 7),
+ SD_CMDR_RESPONSE = (1 << 6),
+ SD_CMDR_CMDID_MASK = (0x3f),
+};
+
+enum {
+ SD_RISR_CARD_REMOVE = (1 << 31),
+ SD_RISR_CARD_INSERT = (1 << 30),
+ SD_RISR_SDIO_INTR = (1 << 16),
+ SD_RISR_AUTOCMD_DONE = (1 << 14),
+ SD_RISR_DATA_COMPLETE = (1 << 3),
+ SD_RISR_CMD_COMPLETE = (1 << 2),
+ SD_RISR_NO_RESPONSE = (1 << 1),
+};
+
+enum {
+ SD_STAR_CARD_PRESENT = (1 << 8),
+};
+
+enum {
+ SD_IDST_INT_SUMMARY = (1 << 8),
+ SD_IDST_RECEIVE_IRQ = (1 << 1),
+ SD_IDST_TRANSMIT_IRQ = (1 << 0),
+ SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
+ SD_IDST_WR_MASK = (0x3ff),
+};
+
+/* SD Host register reset values */
+enum {
+ REG_SD_GCTL_RST = 0x00000300,
+ REG_SD_CKCR_RST = 0x0,
+ REG_SD_TMOR_RST = 0xFFFFFF40,
+ REG_SD_BWDR_RST = 0x0,
+ REG_SD_BKSR_RST = 0x00000200,
+ REG_SD_BYCR_RST = 0x00000200,
+ REG_SD_CMDR_RST = 0x0,
+ REG_SD_CAGR_RST = 0x0,
+ REG_SD_RESP_RST = 0x0,
+ REG_SD_IMKR_RST = 0x0,
+ REG_SD_MISR_RST = 0x0,
+ REG_SD_RISR_RST = 0x0,
+ REG_SD_STAR_RST = 0x00000100,
+ REG_SD_FWLR_RST = 0x000F0000,
+ REG_SD_FUNS_RST = 0x0,
+ REG_SD_DBGC_RST = 0x0,
+ REG_SD_A12A_RST = 0x0000FFFF,
+ REG_SD_NTSR_RST = 0x00000001,
+ REG_SD_SDBG_RST = 0x0,
+ REG_SD_HWRST_RST = 0x00000001,
+ REG_SD_DMAC_RST = 0x0,
+ REG_SD_DLBA_RST = 0x0,
+ REG_SD_IDST_RST = 0x0,
+ REG_SD_IDIE_RST = 0x0,
+ REG_SD_THLDC_RST = 0x0,
+ REG_SD_DSBD_RST = 0x0,
+ REG_SD_RES_CRC_RST = 0x0,
+ REG_SD_DATA_CRC_RST = 0x0,
+ REG_SD_CRC_STA_RST = 0x0,
+ REG_SD_FIFO_RST = 0x0,
+};
+
+/* Data transfer descriptor for DMA */
+typedef struct TransferDescriptor {
+ uint32_t status; /* Status flags */
+ uint32_t size; /* Data buffer size */
+ uint32_t addr; /* Data buffer address */
+ uint32_t next; /* Physical address of next descriptor */
+} TransferDescriptor;
+
+/* Data transfer descriptor flags */
+enum {
+ DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
+ DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
+ DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
+ DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
+ DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
+ DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
+ DESC_SIZE_MASK = (0xfffffffc)
+};
+
+static void allwinner_sdhost_update_irq(AwSdHostState *s)
+{
+ uint32_t irq;
+
+ if (s->global_ctl & SD_GCTL_INT_ENB) {
+ irq = s->irq_status & s->irq_mask;
+ } else {
+ irq = 0;
+ }
+
+ trace_allwinner_sdhost_update_irq(irq);
+ qemu_set_irq(s->irq, irq);
+}
+
+static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
+ uint32_t bytes)
+{
+ if (s->transfer_cnt > bytes) {
+ s->transfer_cnt -= bytes;
+ } else {
+ s->transfer_cnt = 0;
+ }
+
+ if (!s->transfer_cnt) {
+ s->irq_status |= SD_RISR_DATA_COMPLETE;
+ }
+}
+
+static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
+{
+ AwSdHostState *s = AW_SDHOST(dev);
+
+ trace_allwinner_sdhost_set_inserted(inserted);
+
+ if (inserted) {
+ s->irq_status |= SD_RISR_CARD_INSERT;
+ s->irq_status &= ~SD_RISR_CARD_REMOVE;
+ s->status |= SD_STAR_CARD_PRESENT;
+ } else {
+ s->irq_status &= ~SD_RISR_CARD_INSERT;
+ s->irq_status |= SD_RISR_CARD_REMOVE;
+ s->status &= ~SD_STAR_CARD_PRESENT;
+ }
+
+ allwinner_sdhost_update_irq(s);
+}
+
+static void allwinner_sdhost_send_command(AwSdHostState *s)
+{
+ SDRequest request;
+ uint8_t resp[16];
+ int rlen;
+
+ /* Auto clear load flag */
+ s->command &= ~SD_CMDR_LOAD;
+
+ /* Clock change does not actually interact with the SD bus */
+ if (!(s->command & SD_CMDR_CLKCHANGE)) {
+
+ /* Prepare request */
+ request.cmd = s->command & SD_CMDR_CMDID_MASK;
+ request.arg = s->command_arg;
+
+ /* Send request to SD bus */
+ rlen = sdbus_do_command(&s->sdbus, &request, resp);
+ if (rlen < 0) {
+ goto error;
+ }
+
+ /* If the command has a response, store it in the response registers */
+ if ((s->command & SD_CMDR_RESPONSE)) {
+ if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
+ s->response[0] = ldl_be_p(&resp[0]);
+ s->response[1] = s->response[2] = s->response[3] = 0;
+
+ } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
+ s->response[0] = ldl_be_p(&resp[12]);
+ s->response[1] = ldl_be_p(&resp[8]);
+ s->response[2] = ldl_be_p(&resp[4]);
+ s->response[3] = ldl_be_p(&resp[0]);
+ } else {
+ goto error;
+ }
+ }
+ }
+
+ /* Set interrupt status bits */
+ s->irq_status |= SD_RISR_CMD_COMPLETE;
+ return;
+
+error:
+ s->irq_status |= SD_RISR_NO_RESPONSE;
+}
+
+static void allwinner_sdhost_auto_stop(AwSdHostState *s)
+{
+ /*
+ * The stop command (CMD12) ensures the SD bus
+ * returns to the transfer state.
+ */
+ if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
+ /* First save current command registers */
+ uint32_t saved_cmd = s->command;
+ uint32_t saved_arg = s->command_arg;
+
+ /* Prepare stop command (CMD12) */
+ s->command &= ~SD_CMDR_CMDID_MASK;
+ s->command |= 12; /* CMD12 */
+ s->command_arg = 0;
+
+ /* Put the command on SD bus */
+ allwinner_sdhost_send_command(s);
+
+ /* Restore command values */
+ s->command = saved_cmd;
+ s->command_arg = saved_arg;
+
+ /* Set IRQ status bit for automatic stop done */
+ s->irq_status |= SD_RISR_AUTOCMD_DONE;
+ }
+}
+
+static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
+ hwaddr desc_addr,
+ TransferDescriptor *desc,
+ bool is_write, uint32_t max_bytes)
+{
+ AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
+ uint32_t num_done = 0;
+ uint32_t num_bytes = max_bytes;
+ uint8_t buf[1024];
+
+ /* Read descriptor */
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
+ if (desc->size == 0) {
+ desc->size = klass->max_desc_size;
+ } else if (desc->size > klass->max_desc_size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
+ " is out-of-bounds: %" PRIu32 " > %zu",
+ __func__, desc->size, klass->max_desc_size);
+ desc->size = klass->max_desc_size;
+ }
+ if (desc->size < num_bytes) {
+ num_bytes = desc->size;
+ }
+
+ trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
+ is_write, max_bytes);
+
+ while (num_done < num_bytes) {
+ /* Try to completely fill the local buffer */
+ uint32_t buf_bytes = num_bytes - num_done;
+ if (buf_bytes > sizeof(buf)) {
+ buf_bytes = sizeof(buf);
+ }
+
+ /* Write to SD bus */
+ if (is_write) {
+ cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
+ buf, buf_bytes);
+
+ for (uint32_t i = 0; i < buf_bytes; i++) {
+ sdbus_write_data(&s->sdbus, buf[i]);
+ }
+
+ /* Read from SD bus */
+ } else {
+ for (uint32_t i = 0; i < buf_bytes; i++) {
+ buf[i] = sdbus_read_data(&s->sdbus);
+ }
+ cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
+ buf, buf_bytes);
+ }
+ num_done += buf_bytes;
+ }
+
+ /* Clear hold flag and flush descriptor */
+ desc->status &= ~DESC_STATUS_HOLD;
+ cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
+
+ return num_done;
+}
+
+static void allwinner_sdhost_dma(AwSdHostState *s)
+{
+ TransferDescriptor desc;
+ hwaddr desc_addr = s->desc_base;
+ bool is_write = (s->command & SD_CMDR_WRITE);
+ uint32_t bytes_done = 0;
+
+ /* Check if DMA can be performed */
+ if (s->byte_count == 0 || s->block_size == 0 ||
+ !(s->global_ctl & SD_GCTL_DMA_ENB)) {
+ return;
+ }
+
+ /*
+ * For read operations, data must be available on the SD bus
+ * If not, it is an error and we should not act at all
+ */
+ if (!is_write && !sdbus_data_ready(&s->sdbus)) {
+ return;
+ }
+
+ /* Process the DMA descriptors until all data is copied */
+ while (s->byte_count > 0) {
+ bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
+ is_write, s->byte_count);
+ allwinner_sdhost_update_transfer_cnt(s, bytes_done);
+
+ if (bytes_done <= s->byte_count) {
+ s->byte_count -= bytes_done;
+ } else {
+ s->byte_count = 0;
+ }
+
+ if (desc.status & DESC_STATUS_LAST) {
+ break;
+ } else {
+ desc_addr = desc.next;
+ }
+ }
+
+ /* Raise IRQ to signal DMA is completed */
+ s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
+
+ /* Update DMAC bits */
+ s->dmac_status |= SD_IDST_INT_SUMMARY;
+
+ if (is_write) {
+ s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
+ } else {
+ s->dmac_status |= SD_IDST_RECEIVE_IRQ;
+ }
+}
+
+static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AwSdHostState *s = AW_SDHOST(opaque);
+ uint32_t res = 0;
+
+ switch (offset) {
+ case REG_SD_GCTL: /* Global Control */
+ res = s->global_ctl;
+ break;
+ case REG_SD_CKCR: /* Clock Control */
+ res = s->clock_ctl;
+ break;
+ case REG_SD_TMOR: /* Timeout */
+ res = s->timeout;
+ break;
+ case REG_SD_BWDR: /* Bus Width */
+ res = s->bus_width;
+ break;
+ case REG_SD_BKSR: /* Block Size */
+ res = s->block_size;
+ break;
+ case REG_SD_BYCR: /* Byte Count */
+ res = s->byte_count;
+ break;
+ case REG_SD_CMDR: /* Command */
+ res = s->command;
+ break;
+ case REG_SD_CAGR: /* Command Argument */
+ res = s->command_arg;
+ break;
+ case REG_SD_RESP0: /* Response Zero */
+ res = s->response[0];
+ break;
+ case REG_SD_RESP1: /* Response One */
+ res = s->response[1];
+ break;
+ case REG_SD_RESP2: /* Response Two */
+ res = s->response[2];
+ break;
+ case REG_SD_RESP3: /* Response Three */
+ res = s->response[3];
+ break;
+ case REG_SD_IMKR: /* Interrupt Mask */
+ res = s->irq_mask;
+ break;
+ case REG_SD_MISR: /* Masked Interrupt Status */
+ res = s->irq_status & s->irq_mask;
+ break;
+ case REG_SD_RISR: /* Raw Interrupt Status */
+ res = s->irq_status;
+ break;
+ case REG_SD_STAR: /* Status */
+ res = s->status;
+ break;
+ case REG_SD_FWLR: /* FIFO Water Level */
+ res = s->fifo_wlevel;
+ break;
+ case REG_SD_FUNS: /* FIFO Function Select */
+ res = s->fifo_func_sel;
+ break;
+ case REG_SD_DBGC: /* Debug Enable */
+ res = s->debug_enable;
+ break;
+ case REG_SD_A12A: /* Auto command 12 argument */
+ res = s->auto12_arg;
+ break;
+ case REG_SD_NTSR: /* SD NewTiming Set */
+ res = s->newtiming_set;
+ break;
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
+ res = s->newtiming_debug;
+ break;
+ case REG_SD_HWRST: /* Hardware Reset Register */
+ res = s->hardware_rst;
+ break;
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
+ res = s->dmac;
+ break;
+ case REG_SD_DLBA: /* Descriptor List Base Address */
+ res = s->desc_base;
+ break;
+ case REG_SD_IDST: /* Internal DMA Controller Status */
+ res = s->dmac_status;
+ break;
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
+ res = s->dmac_irq;
+ break;
+ case REG_SD_THLDC: /* Card Threshold Control */
+ res = s->card_threshold;
+ break;
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
+ res = s->startbit_detect;
+ break;
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
+ res = s->response_crc;
+ break;
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
+ res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
+ break;
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
+ res = s->status_crc;
+ break;
+ case REG_SD_FIFO: /* Read/Write FIFO */
+ if (sdbus_data_ready(&s->sdbus)) {
+ res = sdbus_read_data(&s->sdbus);
+ res |= sdbus_read_data(&s->sdbus) << 8;
+ res |= sdbus_read_data(&s->sdbus) << 16;
+ res |= sdbus_read_data(&s->sdbus) << 24;
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
+ allwinner_sdhost_auto_stop(s);
+ allwinner_sdhost_update_irq(s);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
+ __func__);
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
+ HWADDR_PRIx"\n", __func__, offset);
+ res = 0;
+ break;
+ }
+
+ trace_allwinner_sdhost_read(offset, res, size);
+ return res;
+}
+
+static void allwinner_sdhost_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ AwSdHostState *s = AW_SDHOST(opaque);
+
+ trace_allwinner_sdhost_write(offset, value, size);
+
+ switch (offset) {
+ case REG_SD_GCTL: /* Global Control */
+ s->global_ctl = value;
+ s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
+ SD_GCTL_SOFT_RST);
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_CKCR: /* Clock Control */
+ s->clock_ctl = value;
+ break;
+ case REG_SD_TMOR: /* Timeout */
+ s->timeout = value;
+ break;
+ case REG_SD_BWDR: /* Bus Width */
+ s->bus_width = value;
+ break;
+ case REG_SD_BKSR: /* Block Size */
+ s->block_size = value;
+ break;
+ case REG_SD_BYCR: /* Byte Count */
+ s->byte_count = value;
+ s->transfer_cnt = value;
+ break;
+ case REG_SD_CMDR: /* Command */
+ s->command = value;
+ if (value & SD_CMDR_LOAD) {
+ allwinner_sdhost_send_command(s);
+ allwinner_sdhost_dma(s);
+ allwinner_sdhost_auto_stop(s);
+ }
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_CAGR: /* Command Argument */
+ s->command_arg = value;
+ break;
+ case REG_SD_RESP0: /* Response Zero */
+ s->response[0] = value;
+ break;
+ case REG_SD_RESP1: /* Response One */
+ s->response[1] = value;
+ break;
+ case REG_SD_RESP2: /* Response Two */
+ s->response[2] = value;
+ break;
+ case REG_SD_RESP3: /* Response Three */
+ s->response[3] = value;
+ break;
+ case REG_SD_IMKR: /* Interrupt Mask */
+ s->irq_mask = value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_MISR: /* Masked Interrupt Status */
+ case REG_SD_RISR: /* Raw Interrupt Status */
+ s->irq_status &= ~value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_STAR: /* Status */
+ s->status &= ~value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_FWLR: /* FIFO Water Level */
+ s->fifo_wlevel = value;
+ break;
+ case REG_SD_FUNS: /* FIFO Function Select */
+ s->fifo_func_sel = value;
+ break;
+ case REG_SD_DBGC: /* Debug Enable */
+ s->debug_enable = value;
+ break;
+ case REG_SD_A12A: /* Auto command 12 argument */
+ s->auto12_arg = value;
+ break;
+ case REG_SD_NTSR: /* SD NewTiming Set */
+ s->newtiming_set = value;
+ break;
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
+ s->newtiming_debug = value;
+ break;
+ case REG_SD_HWRST: /* Hardware Reset Register */
+ s->hardware_rst = value;
+ break;
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
+ s->dmac = value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_DLBA: /* Descriptor List Base Address */
+ s->desc_base = value;
+ break;
+ case REG_SD_IDST: /* Internal DMA Controller Status */
+ s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
+ s->dmac_irq = value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_THLDC: /* Card Threshold Control */
+ s->card_threshold = value;
+ break;
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
+ s->startbit_detect = value;
+ break;
+ case REG_SD_FIFO: /* Read/Write FIFO */
+ sdbus_write_data(&s->sdbus, value & 0xff);
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
+ allwinner_sdhost_auto_stop(s);
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
+ HWADDR_PRIx"\n", __func__, offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_sdhost_ops = {
+ .read = allwinner_sdhost_read,
+ .write = allwinner_sdhost_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static const VMStateDescription vmstate_allwinner_sdhost = {
+ .name = "allwinner-sdhost",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(global_ctl, AwSdHostState),
+ VMSTATE_UINT32(clock_ctl, AwSdHostState),
+ VMSTATE_UINT32(timeout, AwSdHostState),
+ VMSTATE_UINT32(bus_width, AwSdHostState),
+ VMSTATE_UINT32(block_size, AwSdHostState),
+ VMSTATE_UINT32(byte_count, AwSdHostState),
+ VMSTATE_UINT32(transfer_cnt, AwSdHostState),
+ VMSTATE_UINT32(command, AwSdHostState),
+ VMSTATE_UINT32(command_arg, AwSdHostState),
+ VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
+ VMSTATE_UINT32(irq_mask, AwSdHostState),
+ VMSTATE_UINT32(irq_status, AwSdHostState),
+ VMSTATE_UINT32(status, AwSdHostState),
+ VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
+ VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
+ VMSTATE_UINT32(debug_enable, AwSdHostState),
+ VMSTATE_UINT32(auto12_arg, AwSdHostState),
+ VMSTATE_UINT32(newtiming_set, AwSdHostState),
+ VMSTATE_UINT32(newtiming_debug, AwSdHostState),
+ VMSTATE_UINT32(hardware_rst, AwSdHostState),
+ VMSTATE_UINT32(dmac, AwSdHostState),
+ VMSTATE_UINT32(desc_base, AwSdHostState),
+ VMSTATE_UINT32(dmac_status, AwSdHostState),
+ VMSTATE_UINT32(dmac_irq, AwSdHostState),
+ VMSTATE_UINT32(card_threshold, AwSdHostState),
+ VMSTATE_UINT32(startbit_detect, AwSdHostState),
+ VMSTATE_UINT32(response_crc, AwSdHostState),
+ VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
+ VMSTATE_UINT32(status_crc, AwSdHostState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_sdhost_init(Object *obj)
+{
+ AwSdHostState *s = AW_SDHOST(obj);
+
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
+
+ memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
+ TYPE_AW_SDHOST, 4 * KiB);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
+}
+
+static void allwinner_sdhost_reset(DeviceState *dev)
+{
+ AwSdHostState *s = AW_SDHOST(dev);
+
+ s->global_ctl = REG_SD_GCTL_RST;
+ s->clock_ctl = REG_SD_CKCR_RST;
+ s->timeout = REG_SD_TMOR_RST;
+ s->bus_width = REG_SD_BWDR_RST;
+ s->block_size = REG_SD_BKSR_RST;
+ s->byte_count = REG_SD_BYCR_RST;
+ s->transfer_cnt = 0;
+
+ s->command = REG_SD_CMDR_RST;
+ s->command_arg = REG_SD_CAGR_RST;
+
+ for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
+ s->response[i] = REG_SD_RESP_RST;
+ }
+
+ s->irq_mask = REG_SD_IMKR_RST;
+ s->irq_status = REG_SD_RISR_RST;
+ s->status = REG_SD_STAR_RST;
+
+ s->fifo_wlevel = REG_SD_FWLR_RST;
+ s->fifo_func_sel = REG_SD_FUNS_RST;
+ s->debug_enable = REG_SD_DBGC_RST;
+ s->auto12_arg = REG_SD_A12A_RST;
+ s->newtiming_set = REG_SD_NTSR_RST;
+ s->newtiming_debug = REG_SD_SDBG_RST;
+ s->hardware_rst = REG_SD_HWRST_RST;
+ s->dmac = REG_SD_DMAC_RST;
+ s->desc_base = REG_SD_DLBA_RST;
+ s->dmac_status = REG_SD_IDST_RST;
+ s->dmac_irq = REG_SD_IDIE_RST;
+ s->card_threshold = REG_SD_THLDC_RST;
+ s->startbit_detect = REG_SD_DSBD_RST;
+ s->response_crc = REG_SD_RES_CRC_RST;
+
+ for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
+ s->data_crc[i] = REG_SD_DATA_CRC_RST;
+ }
+
+ s->status_crc = REG_SD_CRC_STA_RST;
+}
+
+static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
+{
+ SDBusClass *sbc = SD_BUS_CLASS(klass);
+
+ sbc->set_inserted = allwinner_sdhost_set_inserted;
+}
+
+static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = allwinner_sdhost_reset;
+ dc->vmsd = &vmstate_allwinner_sdhost;
+}
+
+static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
+{
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
+ sc->max_desc_size = 8 * KiB;
+}
+
+static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
+{
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
+ sc->max_desc_size = 64 * KiB;
+}
+
+static TypeInfo allwinner_sdhost_info = {
+ .name = TYPE_AW_SDHOST,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_sdhost_init,
+ .instance_size = sizeof(AwSdHostState),
+ .class_init = allwinner_sdhost_class_init,
+ .class_size = sizeof(AwSdHostClass),
+ .abstract = true,
+};
+
+static const TypeInfo allwinner_sdhost_sun4i_info = {
+ .name = TYPE_AW_SDHOST_SUN4I,
+ .parent = TYPE_AW_SDHOST,
+ .class_init = allwinner_sdhost_sun4i_class_init,
+};
+
+static const TypeInfo allwinner_sdhost_sun5i_info = {
+ .name = TYPE_AW_SDHOST_SUN5I,
+ .parent = TYPE_AW_SDHOST,
+ .class_init = allwinner_sdhost_sun5i_class_init,
+};
+
+static const TypeInfo allwinner_sdhost_bus_info = {
+ .name = TYPE_AW_SDHOST_BUS,
+ .parent = TYPE_SD_BUS,
+ .instance_size = sizeof(SDBus),
+ .class_init = allwinner_sdhost_bus_class_init,
+};
+
+static void allwinner_sdhost_register_types(void)
+{
+ type_register_static(&allwinner_sdhost_info);
+ type_register_static(&allwinner_sdhost_sun4i_info);
+ type_register_static(&allwinner_sdhost_sun5i_info);
+ type_register_static(&allwinner_sdhost_bus_info);
+}
+
+type_init(allwinner_sdhost_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 5d78deba11..abb2c031bc 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -305,6 +305,7 @@ config ALLWINNER_H3
select UNIMP
select USB_OHCI
select USB_EHCI_SYSBUS
+ select SD
config RASPI
bool
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
index e371281ac4..0d1df1721c 100644
--- a/hw/sd/Makefile.objs
+++ b/hw/sd/Makefile.objs
@@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o
common-obj-$(CONFIG_SDHCI) += sdhci.o
common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
common-obj-$(CONFIG_OMAP) += omap_mmc.o
common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index efcff666a2..5f09d32eb2 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -1,5 +1,12 @@
# See docs/devel/tracing.txt for syntax documentation.
+# allwinner-sdhost.c
+allwinner_sdhost_set_inserted(bool inserted) "inserted %u"
+allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32
+allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32
+
# bcm2835_sdhost.c
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 09/18] hw/arm/allwinner-h3: add EMAC ethernet device
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (7 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 08/18] hw/arm/allwinner: add SD/MMC host controller Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 10/18] hw/arm/allwinner-h3: add Boot ROM support Niek Linnenbank
` (8 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
including emulation for the following functionality:
* DMA transfers
* MII interface
* Transmit CRC calculation
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/net/allwinner-sun8i-emac.h | 99 +++
hw/arm/allwinner-h3.c | 16 +-
hw/arm/orangepi.c | 3 +
hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
hw/net/Kconfig | 3 +
hw/net/Makefile.objs | 1 +
hw/net/trace-events | 10 +
9 files changed, 1006 insertions(+), 1 deletion(-)
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
create mode 100644 hw/net/allwinner-sun8i-emac.c
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index d71a4917ab..f9b9a02373 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -44,6 +44,7 @@
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "hw/misc/allwinner-sid.h"
#include "hw/sd/allwinner-sdhost.h"
+#include "hw/net/allwinner-sun8i-emac.h"
#include "target/arm/cpu.h"
/**
@@ -77,6 +78,7 @@ enum {
AW_H3_UART1,
AW_H3_UART2,
AW_H3_UART3,
+ AW_H3_EMAC,
AW_H3_GIC_DIST,
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
@@ -120,6 +122,7 @@ typedef struct AwH3State {
AwH3SysCtrlState sysctrl;
AwSidState sid;
AwSdHostState mmc0;
+ AwSun8iEmacState emac;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
new file mode 100644
index 0000000000..eda034e96b
--- /dev/null
+++ b/include/hw/net/allwinner-sun8i-emac.h
@@ -0,0 +1,99 @@
+/*
+ * Allwinner Sun8i Ethernet MAC emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
+#define HW_NET_ALLWINNER_SUN8I_EMAC_H
+
+#include "qom/object.h"
+#include "net/net.h"
+#include "hw/sysbus.h"
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
+#define AW_SUN8I_EMAC(obj) \
+ OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
+
+/** @} */
+
+/**
+ * Allwinner Sun8i EMAC object instance state
+ */
+typedef struct AwSun8iEmacState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Interrupt output signal to notify CPU */
+ qemu_irq irq;
+
+ /** Generic Network Interface Controller (NIC) for networking API */
+ NICState *nic;
+
+ /** Generic Network Interface Controller (NIC) configuration */
+ NICConf conf;
+
+ /**
+ * @name Media Independent Interface (MII)
+ * @{
+ */
+
+ uint8_t mii_phy_addr; /**< PHY address */
+ uint32_t mii_cr; /**< Control */
+ uint32_t mii_st; /**< Status */
+ uint32_t mii_adv; /**< Advertised Abilities */
+
+ /** @} */
+
+ /**
+ * @name Hardware Registers
+ * @{
+ */
+
+ uint32_t basic_ctl0; /**< Basic Control 0 */
+ uint32_t basic_ctl1; /**< Basic Control 1 */
+ uint32_t int_en; /**< Interrupt Enable */
+ uint32_t int_sta; /**< Interrupt Status */
+ uint32_t frm_flt; /**< Receive Frame Filter */
+
+ uint32_t rx_ctl0; /**< Receive Control 0 */
+ uint32_t rx_ctl1; /**< Receive Control 1 */
+ uint32_t rx_desc_head; /**< Receive Descriptor List Address */
+ uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
+
+ uint32_t tx_ctl0; /**< Transmit Control 0 */
+ uint32_t tx_ctl1; /**< Transmit Control 1 */
+ uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
+ uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
+ uint32_t tx_flowctl; /**< Transmit Flow Control */
+
+ uint32_t mii_cmd; /**< Management Interface Command */
+ uint32_t mii_data; /**< Management Interface Data */
+
+ /** @} */
+
+} AwSun8iEmacState;
+
+#endif /* HW_NET_ALLWINNER_SUN8I_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 8c7ac61517..d1245d2b01 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -54,6 +54,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_UART1] = 0x01c28400,
[AW_H3_UART2] = 0x01c28800,
[AW_H3_UART3] = 0x01c28c00,
+ [AW_H3_EMAC] = 0x01c30000,
[AW_H3_GIC_DIST] = 0x01c81000,
[AW_H3_GIC_CPU] = 0x01c82000,
[AW_H3_GIC_HYP] = 0x01c84000,
@@ -106,7 +107,6 @@ struct AwH3Unimplemented {
{ "twi1", 0x01c2b000, 1 * KiB },
{ "twi2", 0x01c2b400, 1 * KiB },
{ "scr", 0x01c2c400, 1 * KiB },
- { "emac", 0x01c30000, 64 * KiB },
{ "gpu", 0x01c40000, 64 * KiB },
{ "hstmr", 0x01c60000, 4 * KiB },
{ "dramcom", 0x01c62000, 4 * KiB },
@@ -162,6 +162,7 @@ enum {
AW_H3_GIC_SPI_OHCI2 = 77,
AW_H3_GIC_SPI_EHCI3 = 78,
AW_H3_GIC_SPI_OHCI3 = 79,
+ AW_H3_GIC_SPI_EMAC = 82
};
/* Allwinner H3 general constants */
@@ -207,6 +208,9 @@ static void allwinner_h3_init(Object *obj)
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
TYPE_AW_SDHOST_SUN5I);
+
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
+ TYPE_AW_SUN8I_EMAC);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -337,6 +341,16 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
"sd-bus", &error_abort);
+ /* EMAC */
+ if (nd_table[0].used) {
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
+ }
+ qdev_init_nofail(DEVICE(&s->emac));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index d5291036a6..d5cfc1f611 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -75,6 +75,9 @@ static void orangepi_init(MachineState *machine)
"not include H3 prefix\n");
}
+ /* Setup EMAC properties */
+ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
+
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
new file mode 100644
index 0000000000..3fc5e34640
--- /dev/null
+++ b/hw/net/allwinner-sun8i-emac.c
@@ -0,0 +1,871 @@
+/*
+ * Allwinner Sun8i Ethernet MAC emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "net/net.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "net/checksum.h"
+#include "qemu/module.h"
+#include "exec/cpu-common.h"
+#include "hw/net/allwinner-sun8i-emac.h"
+
+/* EMAC register offsets */
+enum {
+ REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */
+ REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */
+ REG_INT_STA = 0x0008, /* Interrupt Status */
+ REG_INT_EN = 0x000C, /* Interrupt Enable */
+ REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */
+ REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
+ REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
+ REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
+ REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
+ REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
+ REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
+ REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
+ REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
+ REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
+ REG_MII_CMD = 0x0048, /* Management Interface Command */
+ REG_MII_DATA = 0x004C, /* Management Interface Data */
+ REG_ADDR_HIGH = 0x0050, /* MAC Address High */
+ REG_ADDR_LOW = 0x0054, /* MAC Address Low */
+ REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
+ REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
+ REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
+ REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
+ REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
+ REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
+ REG_RGMII_STA = 0x00D0, /* RGMII Status */
+};
+
+/* EMAC register flags */
+enum {
+ BASIC_CTL0_100Mbps = (0b11 << 2),
+ BASIC_CTL0_FD = (1 << 0),
+ BASIC_CTL1_SOFTRST = (1 << 0),
+};
+
+enum {
+ INT_STA_RGMII_LINK = (1 << 16),
+ INT_STA_RX_EARLY = (1 << 13),
+ INT_STA_RX_OVERFLOW = (1 << 12),
+ INT_STA_RX_TIMEOUT = (1 << 11),
+ INT_STA_RX_DMA_STOP = (1 << 10),
+ INT_STA_RX_BUF_UA = (1 << 9),
+ INT_STA_RX = (1 << 8),
+ INT_STA_TX_EARLY = (1 << 5),
+ INT_STA_TX_UNDERFLOW = (1 << 4),
+ INT_STA_TX_TIMEOUT = (1 << 3),
+ INT_STA_TX_BUF_UA = (1 << 2),
+ INT_STA_TX_DMA_STOP = (1 << 1),
+ INT_STA_TX = (1 << 0),
+};
+
+enum {
+ INT_EN_RX_EARLY = (1 << 13),
+ INT_EN_RX_OVERFLOW = (1 << 12),
+ INT_EN_RX_TIMEOUT = (1 << 11),
+ INT_EN_RX_DMA_STOP = (1 << 10),
+ INT_EN_RX_BUF_UA = (1 << 9),
+ INT_EN_RX = (1 << 8),
+ INT_EN_TX_EARLY = (1 << 5),
+ INT_EN_TX_UNDERFLOW = (1 << 4),
+ INT_EN_TX_TIMEOUT = (1 << 3),
+ INT_EN_TX_BUF_UA = (1 << 2),
+ INT_EN_TX_DMA_STOP = (1 << 1),
+ INT_EN_TX = (1 << 0),
+};
+
+enum {
+ TX_CTL0_TX_EN = (1 << 31),
+ TX_CTL1_TX_DMA_START = (1 << 31),
+ TX_CTL1_TX_DMA_EN = (1 << 30),
+ TX_CTL1_TX_FLUSH = (1 << 0),
+};
+
+enum {
+ RX_CTL0_RX_EN = (1 << 31),
+ RX_CTL0_STRIP_FCS = (1 << 28),
+ RX_CTL0_CRC_IPV4 = (1 << 27),
+};
+
+enum {
+ RX_CTL1_RX_DMA_START = (1 << 31),
+ RX_CTL1_RX_DMA_EN = (1 << 30),
+ RX_CTL1_RX_MD = (1 << 1),
+};
+
+enum {
+ RX_FRM_FLT_DIS_ADDR = (1 << 31),
+};
+
+enum {
+ MII_CMD_PHY_ADDR_SHIFT = (12),
+ MII_CMD_PHY_ADDR_MASK = (0xf000),
+ MII_CMD_PHY_REG_SHIFT = (4),
+ MII_CMD_PHY_REG_MASK = (0xf0),
+ MII_CMD_PHY_RW = (1 << 1),
+ MII_CMD_PHY_BUSY = (1 << 0),
+};
+
+enum {
+ TX_DMA_STA_STOP = (0b000),
+ TX_DMA_STA_RUN_FETCH = (0b001),
+ TX_DMA_STA_WAIT_STA = (0b010),
+};
+
+enum {
+ RX_DMA_STA_STOP = (0b000),
+ RX_DMA_STA_RUN_FETCH = (0b001),
+ RX_DMA_STA_WAIT_FRM = (0b011),
+};
+
+/* EMAC register reset values */
+enum {
+ REG_BASIC_CTL_1_RST = 0x08000000,
+};
+
+/* EMAC constants */
+enum {
+ AW_SUN8I_EMAC_MIN_PKT_SZ = 64
+};
+
+/* Transmit/receive frame descriptor */
+typedef struct FrameDescriptor {
+ uint32_t status;
+ uint32_t status2;
+ uint32_t addr;
+ uint32_t next;
+} FrameDescriptor;
+
+/* Frame descriptor flags */
+enum {
+ DESC_STATUS_CTL = (1 << 31),
+ DESC_STATUS2_BUF_SIZE_MASK = (0x7ff),
+};
+
+/* Transmit frame descriptor flags */
+enum {
+ TX_DESC_STATUS_LENGTH_ERR = (1 << 14),
+ TX_DESC_STATUS2_FIRST_DESC = (1 << 29),
+ TX_DESC_STATUS2_LAST_DESC = (1 << 30),
+ TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27),
+};
+
+/* Receive frame descriptor flags */
+enum {
+ RX_DESC_STATUS_FIRST_DESC = (1 << 9),
+ RX_DESC_STATUS_LAST_DESC = (1 << 8),
+ RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000),
+ RX_DESC_STATUS_FRM_LEN_SHIFT = (16),
+ RX_DESC_STATUS_NO_BUF = (1 << 14),
+ RX_DESC_STATUS_HEADER_ERR = (1 << 7),
+ RX_DESC_STATUS_LENGTH_ERR = (1 << 4),
+ RX_DESC_STATUS_CRC_ERR = (1 << 1),
+ RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0),
+ RX_DESC_STATUS2_RX_INT_CTL = (1 << 31),
+};
+
+/* MII register offsets */
+enum {
+ MII_REG_CR = (0x0), /* Control */
+ MII_REG_ST = (0x1), /* Status */
+ MII_REG_ID_HIGH = (0x2), /* Identifier High */
+ MII_REG_ID_LOW = (0x3), /* Identifier Low */
+ MII_REG_ADV = (0x4), /* Advertised abilities */
+ MII_REG_LPA = (0x5), /* Link partner abilities */
+};
+
+/* MII register flags */
+enum {
+ MII_REG_CR_RESET = (1 << 15),
+ MII_REG_CR_POWERDOWN = (1 << 11),
+ MII_REG_CR_10Mbit = (0),
+ MII_REG_CR_100Mbit = (1 << 13),
+ MII_REG_CR_1000Mbit = (1 << 6),
+ MII_REG_CR_AUTO_NEG = (1 << 12),
+ MII_REG_CR_AUTO_NEG_RESTART = (1 << 9),
+ MII_REG_CR_FULLDUPLEX = (1 << 8),
+};
+
+enum {
+ MII_REG_ST_100BASE_T4 = (1 << 15),
+ MII_REG_ST_100BASE_X_FD = (1 << 14),
+ MII_REG_ST_100BASE_X_HD = (1 << 13),
+ MII_REG_ST_10_FD = (1 << 12),
+ MII_REG_ST_10_HD = (1 << 11),
+ MII_REG_ST_100BASE_T2_FD = (1 << 10),
+ MII_REG_ST_100BASE_T2_HD = (1 << 9),
+ MII_REG_ST_AUTONEG_COMPLETE = (1 << 5),
+ MII_REG_ST_AUTONEG_AVAIL = (1 << 3),
+ MII_REG_ST_LINK_UP = (1 << 2),
+};
+
+enum {
+ MII_REG_LPA_10_HD = (1 << 5),
+ MII_REG_LPA_10_FD = (1 << 6),
+ MII_REG_LPA_100_HD = (1 << 7),
+ MII_REG_LPA_100_FD = (1 << 8),
+ MII_REG_LPA_PAUSE = (1 << 10),
+ MII_REG_LPA_ASYMPAUSE = (1 << 11),
+};
+
+/* MII constants */
+enum {
+ MII_PHY_ID_HIGH = 0x0044,
+ MII_PHY_ID_LOW = 0x1400,
+};
+
+static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
+ bool link_active)
+{
+ if (link_active) {
+ s->mii_st |= MII_REG_ST_LINK_UP;
+ } else {
+ s->mii_st &= ~MII_REG_ST_LINK_UP;
+ }
+}
+
+static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
+ bool link_active)
+{
+ s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
+ MII_REG_CR_FULLDUPLEX;
+ s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
+ MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
+ MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
+ MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
+ s->mii_adv = 0;
+
+ allwinner_sun8i_emac_mii_set_link(s, link_active);
+}
+
+static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
+{
+ uint8_t addr, reg;
+
+ addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT;
+ reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
+
+ if (addr != s->mii_phy_addr) {
+ return;
+ }
+
+ /* Read or write a PHY register? */
+ if (s->mii_cmd & MII_CMD_PHY_RW) {
+ trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
+
+ switch (reg) {
+ case MII_REG_CR:
+ if (s->mii_data & MII_REG_CR_RESET) {
+ allwinner_sun8i_emac_mii_reset(s, s->mii_st &
+ MII_REG_ST_LINK_UP);
+ } else {
+ s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET |
+ MII_REG_CR_AUTO_NEG_RESTART);
+ }
+ break;
+ case MII_REG_ADV:
+ s->mii_adv = s->mii_data;
+ break;
+ case MII_REG_ID_HIGH:
+ case MII_REG_ID_LOW:
+ case MII_REG_LPA:
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
+ "unknown MII register 0x%x\n", reg);
+ break;
+ }
+ } else {
+ switch (reg) {
+ case MII_REG_CR:
+ s->mii_data = s->mii_cr;
+ break;
+ case MII_REG_ST:
+ s->mii_data = s->mii_st;
+ break;
+ case MII_REG_ID_HIGH:
+ s->mii_data = MII_PHY_ID_HIGH;
+ break;
+ case MII_REG_ID_LOW:
+ s->mii_data = MII_PHY_ID_LOW;
+ break;
+ case MII_REG_ADV:
+ s->mii_data = s->mii_adv;
+ break;
+ case MII_REG_LPA:
+ s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
+ MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
+ MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
+ "unknown MII register 0x%x\n", reg);
+ s->mii_data = 0;
+ break;
+ }
+
+ trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
+ }
+}
+
+static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
+{
+ qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
+}
+
+static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
+ size_t min_size)
+{
+ uint32_t paddr = desc->next;
+
+ cpu_physical_memory_read(paddr, desc, sizeof(*desc));
+
+ if ((desc->status & DESC_STATUS_CTL) &&
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
+ return paddr;
+ } else {
+ return 0;
+ }
+}
+
+static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
+ uint32_t start_addr,
+ size_t min_size)
+{
+ uint32_t desc_addr = start_addr;
+
+ /* Note that the list is a cycle. Last entry points back to the head. */
+ while (desc_addr != 0) {
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
+
+ if ((desc->status & DESC_STATUS_CTL) &&
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
+ return desc_addr;
+ } else if (desc->next == start_addr) {
+ break;
+ } else {
+ desc_addr = desc->next;
+ }
+ }
+
+ return 0;
+}
+
+static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
+ FrameDescriptor *desc,
+ size_t min_size)
+{
+ return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
+}
+
+static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
+ FrameDescriptor *desc,
+ size_t min_size)
+{
+ return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
+}
+
+static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
+ uint32_t phys_addr)
+{
+ cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
+}
+
+static int allwinner_sun8i_emac_can_receive(NetClientState *nc)
+{
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
+ FrameDescriptor desc;
+
+ return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
+ (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0);
+}
+
+static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
+ const uint8_t *buf,
+ size_t size)
+{
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
+ FrameDescriptor desc;
+ size_t bytes_left = size;
+ size_t desc_bytes = 0;
+ size_t pad_fcs_size = 4;
+ size_t padding = 0;
+
+ if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
+ return -1;
+ }
+
+ s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc,
+ AW_SUN8I_EMAC_MIN_PKT_SZ);
+ if (!s->rx_desc_curr) {
+ s->int_sta |= INT_STA_RX_BUF_UA;
+ }
+
+ /* Keep filling RX descriptors until the whole frame is written */
+ while (s->rx_desc_curr && bytes_left > 0) {
+ desc.status &= ~DESC_STATUS_CTL;
+ desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK;
+
+ if (bytes_left == size) {
+ desc.status |= RX_DESC_STATUS_FIRST_DESC;
+ }
+
+ if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
+ (bytes_left + pad_fcs_size)) {
+ desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
+ desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
+ } else {
+ padding = pad_fcs_size;
+ if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
+ padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
+ }
+
+ desc_bytes = (bytes_left);
+ desc.status |= RX_DESC_STATUS_LAST_DESC;
+ desc.status |= (bytes_left + padding)
+ << RX_DESC_STATUS_FRM_LEN_SHIFT;
+ }
+
+ cpu_physical_memory_write(desc.addr, buf, desc_bytes);
+ allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
+ trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
+ desc_bytes);
+
+ /* Check if frame needs to raise the receive interrupt */
+ if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
+ s->int_sta |= INT_STA_RX;
+ }
+
+ /* Increment variables */
+ buf += desc_bytes;
+ bytes_left -= desc_bytes;
+
+ /* Move to the next descriptor */
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
+ if (!s->rx_desc_curr) {
+ /* Not enough buffer space available */
+ s->int_sta |= INT_STA_RX_BUF_UA;
+ s->rx_desc_curr = s->rx_desc_head;
+ break;
+ }
+ }
+
+ /* Report receive DMA is finished */
+ s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START;
+ allwinner_sun8i_emac_update_irq(s);
+
+ return size;
+}
+
+static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
+{
+ NetClientState *nc = qemu_get_queue(s->nic);
+ FrameDescriptor desc;
+ size_t bytes = 0;
+ size_t packet_bytes = 0;
+ size_t transmitted = 0;
+ static uint8_t packet_buf[2048];
+
+ s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
+
+ /* Read all transmit descriptors */
+ while (s->tx_desc_curr != 0) {
+
+ /* Read from physical memory into packet buffer */
+ bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
+ if (bytes + packet_bytes > sizeof(packet_buf)) {
+ desc.status |= TX_DESC_STATUS_LENGTH_ERR;
+ break;
+ }
+ cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
+ packet_bytes += bytes;
+ desc.status &= ~DESC_STATUS_CTL;
+ allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
+
+ /* After the last descriptor, send the packet */
+ if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
+ if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
+ net_checksum_calculate(packet_buf, packet_bytes);
+ }
+
+ qemu_send_packet(nc, packet_buf, packet_bytes);
+ trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
+ bytes);
+
+ packet_bytes = 0;
+ transmitted++;
+ }
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
+ }
+
+ /* Raise transmit completed interrupt */
+ if (transmitted > 0) {
+ s->int_sta |= INT_STA_TX;
+ s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START;
+ allwinner_sun8i_emac_update_irq(s);
+ }
+}
+
+static void allwinner_sun8i_emac_reset(DeviceState *dev)
+{
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
+ NetClientState *nc = qemu_get_queue(s->nic);
+
+ trace_allwinner_sun8i_emac_reset();
+
+ s->mii_cmd = 0;
+ s->mii_data = 0;
+ s->basic_ctl0 = 0;
+ s->basic_ctl1 = REG_BASIC_CTL_1_RST;
+ s->int_en = 0;
+ s->int_sta = 0;
+ s->frm_flt = 0;
+ s->rx_ctl0 = 0;
+ s->rx_ctl1 = RX_CTL1_RX_MD;
+ s->rx_desc_head = 0;
+ s->rx_desc_curr = 0;
+ s->tx_ctl0 = 0;
+ s->tx_ctl1 = 0;
+ s->tx_desc_head = 0;
+ s->tx_desc_curr = 0;
+ s->tx_flowctl = 0;
+
+ allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
+}
+
+static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
+ uint64_t value = 0;
+ FrameDescriptor desc;
+
+ switch (offset) {
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
+ value = s->basic_ctl0;
+ break;
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
+ value = s->basic_ctl1;
+ break;
+ case REG_INT_STA: /* Interrupt Status */
+ value = s->int_sta;
+ break;
+ case REG_INT_EN: /* Interupt Enable */
+ value = s->int_en;
+ break;
+ case REG_TX_CTL_0: /* Transmit Control 0 */
+ value = s->tx_ctl0;
+ break;
+ case REG_TX_CTL_1: /* Transmit Control 1 */
+ value = s->tx_ctl1;
+ break;
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
+ value = s->tx_flowctl;
+ break;
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
+ value = s->tx_desc_head;
+ break;
+ case REG_RX_CTL_0: /* Receive Control 0 */
+ value = s->rx_ctl0;
+ break;
+ case REG_RX_CTL_1: /* Receive Control 1 */
+ value = s->rx_ctl1;
+ break;
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
+ value = s->rx_desc_head;
+ break;
+ case REG_FRM_FLT: /* Receive Frame Filter */
+ value = s->frm_flt;
+ break;
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
+ break;
+ case REG_MII_CMD: /* Management Interface Command */
+ value = s->mii_cmd;
+ break;
+ case REG_MII_DATA: /* Management Interface Data */
+ value = s->mii_data;
+ break;
+ case REG_ADDR_HIGH: /* MAC Address High */
+ value = *(((uint32_t *) (s->conf.macaddr.a)) + 1);
+ break;
+ case REG_ADDR_LOW: /* MAC Address Low */
+ value = *(uint32_t *) (s->conf.macaddr.a);
+ break;
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
+ break;
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
+ value = s->tx_desc_curr;
+ break;
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
+ if (s->tx_desc_curr != 0) {
+ cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
+ value = desc.addr;
+ } else {
+ value = 0;
+ }
+ break;
+ case REG_RX_DMA_STA: /* Receive DMA Status */
+ break;
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
+ value = s->rx_desc_curr;
+ break;
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
+ if (s->rx_desc_curr != 0) {
+ cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
+ value = desc.addr;
+ } else {
+ value = 0;
+ }
+ break;
+ case REG_RGMII_STA: /* RGMII Status */
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
+ "EMAC register 0x" TARGET_FMT_plx "\n",
+ offset);
+ }
+
+ trace_allwinner_sun8i_emac_read(offset, value);
+ return value;
+}
+
+static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
+ NetClientState *nc = qemu_get_queue(s->nic);
+
+ trace_allwinner_sun8i_emac_write(offset, value);
+
+ switch (offset) {
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
+ s->basic_ctl0 = value;
+ break;
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
+ if (value & BASIC_CTL1_SOFTRST) {
+ allwinner_sun8i_emac_reset(DEVICE(s));
+ value &= ~BASIC_CTL1_SOFTRST;
+ }
+ s->basic_ctl1 = value;
+ if (allwinner_sun8i_emac_can_receive(nc)) {
+ qemu_flush_queued_packets(nc);
+ }
+ break;
+ case REG_INT_STA: /* Interrupt Status */
+ s->int_sta &= ~value;
+ allwinner_sun8i_emac_update_irq(s);
+ break;
+ case REG_INT_EN: /* Interrupt Enable */
+ s->int_en = value;
+ allwinner_sun8i_emac_update_irq(s);
+ break;
+ case REG_TX_CTL_0: /* Transmit Control 0 */
+ s->tx_ctl0 = value;
+ break;
+ case REG_TX_CTL_1: /* Transmit Control 1 */
+ s->tx_ctl1 = value;
+ if (value & TX_CTL1_TX_DMA_EN) {
+ allwinner_sun8i_emac_transmit(s);
+ }
+ break;
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
+ s->tx_flowctl = value;
+ break;
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
+ s->tx_desc_head = value;
+ s->tx_desc_curr = value;
+ break;
+ case REG_RX_CTL_0: /* Receive Control 0 */
+ s->rx_ctl0 = value;
+ break;
+ case REG_RX_CTL_1: /* Receive Control 1 */
+ s->rx_ctl1 = value | RX_CTL1_RX_MD;
+ if ((value & RX_CTL1_RX_DMA_EN) &&
+ allwinner_sun8i_emac_can_receive(nc)) {
+ qemu_flush_queued_packets(nc);
+ }
+ break;
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
+ s->rx_desc_head = value;
+ s->rx_desc_curr = value;
+ break;
+ case REG_FRM_FLT: /* Receive Frame Filter */
+ s->frm_flt = value;
+ break;
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
+ break;
+ case REG_MII_CMD: /* Management Interface Command */
+ s->mii_cmd = value & ~MII_CMD_PHY_BUSY;
+ allwinner_sun8i_emac_mii_cmd(s);
+ break;
+ case REG_MII_DATA: /* Management Interface Data */
+ s->mii_data = value;
+ break;
+ case REG_ADDR_HIGH: /* MAC Address High */
+ s->conf.macaddr.a[4] = (value & 0xff);
+ s->conf.macaddr.a[5] = (value & 0xff00) >> 8;
+ break;
+ case REG_ADDR_LOW: /* MAC Address Low */
+ s->conf.macaddr.a[0] = (value & 0xff);
+ s->conf.macaddr.a[1] = (value & 0xff00) >> 8;
+ s->conf.macaddr.a[2] = (value & 0xff0000) >> 16;
+ s->conf.macaddr.a[3] = (value & 0xff000000) >> 24;
+ break;
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
+ case REG_RX_DMA_STA: /* Receive DMA Status */
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
+ case REG_RGMII_STA: /* RGMII Status */
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
+ "EMAC register 0x" TARGET_FMT_plx "\n",
+ offset);
+ }
+}
+
+static void allwinner_sun8i_emac_set_link(NetClientState *nc)
+{
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
+
+ trace_allwinner_sun8i_emac_set_link(!nc->link_down);
+ allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
+}
+
+static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
+ .read = allwinner_sun8i_emac_read,
+ .write = allwinner_sun8i_emac_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static NetClientInfo net_allwinner_sun8i_emac_info = {
+ .type = NET_CLIENT_DRIVER_NIC,
+ .size = sizeof(NICState),
+ .can_receive = allwinner_sun8i_emac_can_receive,
+ .receive = allwinner_sun8i_emac_receive,
+ .link_status_changed = allwinner_sun8i_emac_set_link,
+};
+
+static void allwinner_sun8i_emac_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(obj);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops,
+ s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
+{
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
+
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
+ s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
+ object_get_typename(OBJECT(dev)), dev->id, s);
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
+}
+
+static Property allwinner_sun8i_emac_properties[] = {
+ DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
+ DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
+{
+ AwSun8iEmacState *s = opaque;
+
+ allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_aw_emac = {
+ .name = "allwinner-sun8i-emac",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = allwinner_sun8i_emac_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_data, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_st, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
+ VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
+ VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
+ VMSTATE_UINT32(int_en, AwSun8iEmacState),
+ VMSTATE_UINT32(int_sta, AwSun8iEmacState),
+ VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = allwinner_sun8i_emac_realize;
+ dc->reset = allwinner_sun8i_emac_reset;
+ dc->vmsd = &vmstate_aw_emac;
+ device_class_set_props(dc, allwinner_sun8i_emac_properties);
+}
+
+static const TypeInfo allwinner_sun8i_emac_info = {
+ .name = TYPE_AW_SUN8I_EMAC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AwSun8iEmacState),
+ .instance_init = allwinner_sun8i_emac_init,
+ .class_init = allwinner_sun8i_emac_class_init,
+};
+
+static void allwinner_sun8i_emac_register_types(void)
+{
+ type_register_static(&allwinner_sun8i_emac_info);
+}
+
+type_init(allwinner_sun8i_emac_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index abb2c031bc..2de06c464f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -299,6 +299,7 @@ config ALLWINNER_A10
config ALLWINNER_H3
bool
select ALLWINNER_A10_PIT
+ select ALLWINNER_SUN8I_EMAC
select SERIAL
select ARM_TIMER
select ARM_GIC
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
index 54411d3dcc..e43c96dae0 100644
--- a/hw/net/Kconfig
+++ b/hw/net/Kconfig
@@ -79,6 +79,9 @@ config MIPSNET
config ALLWINNER_EMAC
bool
+config ALLWINNER_SUN8I_EMAC
+ bool
+
config IMX_FEC
bool
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
index 991c46c773..af4d194866 100644
--- a/hw/net/Makefile.objs
+++ b/hw/net/Makefile.objs
@@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
common-obj-$(CONFIG_MIPSNET) += mipsnet.o
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
+common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o
common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
common-obj-$(CONFIG_CADENCE) += cadence_gem.o
diff --git a/hw/net/trace-events b/hw/net/trace-events
index 42066fcf66..b925100ba7 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -1,5 +1,15 @@
# See docs/devel/tracing.txt for syntax documentation.
+# allwinner-sun8i-emac.c
+allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
+allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
+allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
+allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
+allwinner_sun8i_emac_reset(void) "HW reset"
+allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
+allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
+allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
+
# etraxfs_eth.c
mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 10/18] hw/arm/allwinner-h3: add Boot ROM support
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (8 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 09/18] hw/arm/allwinner-h3: add EMAC ethernet device Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 11/18] hw/arm/allwinner-h3: add SDRAM controller device Niek Linnenbank
` (7 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
A real Allwinner H3 SoC contains a Boot ROM which is the
first code that runs right after the SoC is powered on.
The Boot ROM is responsible for loading user code (e.g. a bootloader)
from any of the supported external devices and writing the downloaded
code to internal SRAM. After loading the SoC begins executing the code
written to SRAM.
This commits adds emulation of the Boot ROM firmware setup functionality
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
sizes larger than 32KiB. For reference, this behaviour is documented
by the Linux Sunxi project wiki at:
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++
hw/arm/allwinner-h3.c | 18 ++++++++++++++++++
hw/arm/orangepi.c | 5 +++++
3 files changed, 44 insertions(+)
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index f9b9a02373..d338003724 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -46,6 +46,7 @@
#include "hw/sd/allwinner-sdhost.h"
#include "hw/net/allwinner-sun8i-emac.h"
#include "target/arm/cpu.h"
+#include "sysemu/block-backend.h"
/**
* Allwinner H3 device list
@@ -129,4 +130,24 @@ typedef struct AwH3State {
MemoryRegion sram_c;
} AwH3State;
+/**
+ * Emulate Boot ROM firmware setup functionality.
+ *
+ * A real Allwinner H3 SoC contains a Boot ROM
+ * which is the first code that runs right after
+ * the SoC is powered on. The Boot ROM is responsible
+ * for loading user code (e.g. a bootloader) from any
+ * of the supported external devices and writing the
+ * downloaded code to internal SRAM. After loading the SoC
+ * begins executing the code written to SRAM.
+ *
+ * This function emulates the Boot ROM by copying 32 KiB
+ * of data from the given block device and writes it to
+ * the start of the first internal SRAM memory.
+ *
+ * @s: Allwinner H3 state object pointer
+ * @blk: Block backend device object pointer
+ */
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
+
#endif /* HW_ARM_ALLWINNER_H3_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index d1245d2b01..56b5c563a8 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -29,6 +29,7 @@
#include "hw/char/serial.h"
#include "hw/misc/unimp.h"
#include "hw/usb/hcd-ehci.h"
+#include "hw/loader.h"
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
@@ -170,6 +171,23 @@ enum {
AW_H3_GIC_NUM_SPI = 128
};
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
+{
+ const int64_t rom_size = 32 * KiB;
+ uint8_t *buffer = g_new0(uint8_t, rom_size);
+
+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
+ __func__);
+ return;
+ }
+
+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
+ rom_size, s->memmap[AW_H3_SRAM_A1],
+ NULL, NULL, NULL, NULL, false);
+ g_free(buffer);
+}
+
static void allwinner_h3_init(Object *obj)
{
AwH3State *s = AW_H3(obj);
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index d5cfc1f611..8a2b8919c9 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -95,6 +95,11 @@ static void orangepi_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
machine->ram);
+ /* Load target kernel or start using BootROM */
+ if (!machine->kernel_filename && blk_is_available(blk)) {
+ /* Use Boot ROM to copy data from SD card to SRAM */
+ allwinner_h3_bootrom_setup(h3, blk);
+ }
orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
orangepi_binfo.ram_size = machine->ram_size;
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 11/18] hw/arm/allwinner-h3: add SDRAM controller device
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (9 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 10/18] hw/arm/allwinner-h3: add Boot ROM support Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 12/18] hw/arm/allwinner: add RTC device support Niek Linnenbank
` (6 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3 SDRAM controller.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
include/hw/arm/allwinner-h3.h | 5 +
include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++
hw/arm/allwinner-h3.c | 19 +-
hw/arm/orangepi.c | 6 +
hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/trace-events | 10 +
7 files changed, 502 insertions(+), 3 deletions(-)
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
create mode 100644 hw/misc/allwinner-h3-dramc.c
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index d338003724..065d020c73 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -41,6 +41,7 @@
#include "hw/intc/arm_gic.h"
#include "hw/misc/allwinner-h3-ccu.h"
#include "hw/misc/allwinner-cpucfg.h"
+#include "hw/misc/allwinner-h3-dramc.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "hw/misc/allwinner-sid.h"
#include "hw/sd/allwinner-sdhost.h"
@@ -80,6 +81,9 @@ enum {
AW_H3_UART2,
AW_H3_UART3,
AW_H3_EMAC,
+ AW_H3_DRAMCOM,
+ AW_H3_DRAMCTL,
+ AW_H3_DRAMPHY,
AW_H3_GIC_DIST,
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
@@ -120,6 +124,7 @@ typedef struct AwH3State {
AwA10PITState timer;
AwH3ClockCtlState ccu;
AwCpuCfgState cpucfg;
+ AwH3DramCtlState dramc;
AwH3SysCtrlState sysctrl;
AwSidState sid;
AwSdHostState mmc0;
diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h
new file mode 100644
index 0000000000..bacdf236b7
--- /dev/null
+++ b/include/hw/misc/allwinner-h3-dramc.h
@@ -0,0 +1,106 @@
+/*
+ * Allwinner H3 SDRAM Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
+#define HW_MISC_ALLWINNER_H3_DRAMC_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "exec/hwaddr.h"
+
+/**
+ * Constants
+ * @{
+ */
+
+/** Highest register address used by DRAMCOM module */
+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
+
+/** Total number of known DRAMCOM registers */
+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
+ sizeof(uint32_t))
+
+/** Highest register address used by DRAMCTL module */
+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
+
+/** Total number of known DRAMCTL registers */
+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
+ sizeof(uint32_t))
+
+/** Highest register address used by DRAMPHY module */
+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
+
+/** Total number of known DRAMPHY registers */
+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
+ sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
+#define AW_H3_DRAMC(obj) \
+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
+
+/** @} */
+
+/**
+ * Allwinner H3 SDRAM Controller object instance state.
+ */
+typedef struct AwH3DramCtlState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Physical base address for start of RAM */
+ hwaddr ram_addr;
+
+ /** Total RAM size in megabytes */
+ uint32_t ram_size;
+
+ /**
+ * @name Memory Regions
+ * @{
+ */
+
+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
+
+ /** @} */
+
+ /**
+ * @name Hardware Registers
+ * @{
+ */
+
+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
+
+ /** @} */
+
+} AwH3DramCtlState;
+
+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 56b5c563a8..0e0fea6223 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -56,6 +56,9 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_UART2] = 0x01c28800,
[AW_H3_UART3] = 0x01c28c00,
[AW_H3_EMAC] = 0x01c30000,
+ [AW_H3_DRAMCOM] = 0x01c62000,
+ [AW_H3_DRAMCTL] = 0x01c63000,
+ [AW_H3_DRAMPHY] = 0x01c65000,
[AW_H3_GIC_DIST] = 0x01c81000,
[AW_H3_GIC_CPU] = 0x01c82000,
[AW_H3_GIC_HYP] = 0x01c84000,
@@ -110,9 +113,6 @@ struct AwH3Unimplemented {
{ "scr", 0x01c2c400, 1 * KiB },
{ "gpu", 0x01c40000, 64 * KiB },
{ "hstmr", 0x01c60000, 4 * KiB },
- { "dramcom", 0x01c62000, 4 * KiB },
- { "dramctl0", 0x01c63000, 4 * KiB },
- { "dramphy0", 0x01c65000, 4 * KiB },
{ "spi0", 0x01c68000, 4 * KiB },
{ "spi1", 0x01c69000, 4 * KiB },
{ "csi", 0x01cb0000, 320 * KiB },
@@ -229,6 +229,13 @@ static void allwinner_h3_init(Object *obj)
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
TYPE_AW_SUN8I_EMAC);
+
+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
+ TYPE_AW_H3_DRAMC);
+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
+ "ram-addr", &error_abort);
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
+ "ram-size", &error_abort);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -413,6 +420,12 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
+ /* DRAMC */
+ qdev_init_nofail(DEVICE(&s->dramc));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
+
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
create_unimplemented_device(unimplemented[i].device_name,
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 8a2b8919c9..f57870973e 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -78,6 +78,12 @@ static void orangepi_init(MachineState *machine)
/* Setup EMAC properties */
object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
+ /* DRAMC */
+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],
+ "ram-addr", &error_abort);
+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",
+ &error_abort);
+
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
new file mode 100644
index 0000000000..2b5260260e
--- /dev/null
+++ b/hw/misc/allwinner-h3-dramc.c
@@ -0,0 +1,358 @@
+/*
+ * Allwinner H3 SDRAM Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/error-report.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "exec/address-spaces.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "hw/misc/allwinner-h3-dramc.h"
+#include "trace.h"
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+/* DRAMCOM register offsets */
+enum {
+ REG_DRAMCOM_CR = 0x0000, /* Control Register */
+};
+
+/* DRAMCTL register offsets */
+enum {
+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */
+};
+
+/* DRAMCTL register flags */
+enum {
+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
+};
+
+enum {
+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
+};
+
+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
+ uint8_t bank_bits, uint16_t page_size)
+{
+ /*
+ * This function simulates row addressing behavior when bootloader
+ * software attempts to detect the amount of available SDRAM. In U-Boot
+ * the controller is configured with the widest row addressing available.
+ * Then a pattern is written to RAM at an offset on the row boundary size.
+ * If the value read back equals the value read back from the
+ * start of RAM, the bootloader knows the amount of row bits.
+ *
+ * This function inserts a mirrored memory region when the configured row
+ * bits are not matching the actual emulated memory, to simulate the
+ * same behavior on hardware as expected by the bootloader.
+ */
+ uint8_t row_bits_actual = 0;
+
+ /* Calculate the actual row bits using the ram_size property */
+ for (uint8_t i = 8; i < 12; i++) {
+ if (1 << i == s->ram_size) {
+ row_bits_actual = i + 3;
+ break;
+ }
+ }
+
+ if (s->ram_size == (1 << (row_bits - 3))) {
+ /* When row bits is the expected value, remove the mirror */
+ memory_region_set_enabled(&s->row_mirror_alias, false);
+ trace_allwinner_h3_dramc_rowmirror_disable();
+
+ } else if (row_bits_actual) {
+ /* Row bits not matching ram_size, install the rows mirror */
+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
+ bank_bits)) * page_size);
+
+ memory_region_set_enabled(&s->row_mirror_alias, true);
+ memory_region_set_address(&s->row_mirror_alias, row_mirror);
+
+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
+ }
+}
+
+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
+
+ return s->dramcom[idx];
+}
+
+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ trace_allwinner_h3_dramcom_write(offset, val, size);
+
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ switch (offset) {
+ case REG_DRAMCOM_CR: /* Control Register */
+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
+ ((val >> 2) & 0x1) + 2,
+ 1 << (((val >> 8) & 0xf) + 3));
+ break;
+ default:
+ break;
+ };
+
+ s->dramcom[idx] = (uint32_t) val;
+}
+
+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
+
+ return s->dramctl[idx];
+}
+
+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ trace_allwinner_h3_dramctl_write(offset, val, size);
+
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ switch (offset) {
+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */
+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
+ break;
+ default:
+ break;
+ }
+
+ s->dramctl[idx] = (uint32_t) val;
+}
+
+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
+
+ return s->dramphy[idx];
+}
+
+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ trace_allwinner_h3_dramphy_write(offset, val, size);
+
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ s->dramphy[idx] = (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_h3_dramcom_ops = {
+ .read = allwinner_h3_dramcom_read,
+ .write = allwinner_h3_dramcom_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static const MemoryRegionOps allwinner_h3_dramctl_ops = {
+ .read = allwinner_h3_dramctl_read,
+ .write = allwinner_h3_dramctl_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static const MemoryRegionOps allwinner_h3_dramphy_ops = {
+ .read = allwinner_h3_dramphy_read,
+ .write = allwinner_h3_dramphy_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static void allwinner_h3_dramc_reset(DeviceState *dev)
+{
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
+
+ /* Set default values for registers */
+ memset(&s->dramcom, 0, sizeof(s->dramcom));
+ memset(&s->dramctl, 0, sizeof(s->dramctl));
+ memset(&s->dramphy, 0, sizeof(s->dramphy));
+}
+
+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
+{
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
+
+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
+ for (uint8_t i = 8; i < 13; i++) {
+ if (1 << i == s->ram_size) {
+ break;
+ } else if (i == 12) {
+ error_report("%s: ram-size %u MiB is not supported",
+ __func__, s->ram_size);
+ exit(1);
+ }
+ }
+
+ /* Setup row mirror mappings */
+ memory_region_init_ram(&s->row_mirror, OBJECT(s),
+ "allwinner-h3-dramc.row-mirror",
+ 4 * KiB, &error_abort);
+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
+ &s->row_mirror, 10);
+
+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
+ "allwinner-h3-dramc.row-mirror-alias",
+ &s->row_mirror, 0, 4 * KiB);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ s->ram_addr + 1 * MiB,
+ &s->row_mirror_alias, 10);
+ memory_region_set_enabled(&s->row_mirror_alias, false);
+}
+
+static void allwinner_h3_dramc_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwH3DramCtlState *s = AW_H3_DRAMC(obj);
+
+ /* DRAMCOM registers */
+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
+ &allwinner_h3_dramcom_ops, s,
+ TYPE_AW_H3_DRAMC, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->dramcom_iomem);
+
+ /* DRAMCTL registers */
+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
+ &allwinner_h3_dramctl_ops, s,
+ TYPE_AW_H3_DRAMC, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->dramctl_iomem);
+
+ /* DRAMPHY registers */
+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
+ &allwinner_h3_dramphy_ops, s,
+ TYPE_AW_H3_DRAMC, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->dramphy_iomem);
+}
+
+static Property allwinner_h3_dramc_properties[] = {
+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static const VMStateDescription allwinner_h3_dramc_vmstate = {
+ .name = "allwinner-h3-dramc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),
+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),
+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = allwinner_h3_dramc_reset;
+ dc->vmsd = &allwinner_h3_dramc_vmstate;
+ dc->realize = allwinner_h3_dramc_realize;
+ device_class_set_props(dc, allwinner_h3_dramc_properties);
+}
+
+static const TypeInfo allwinner_h3_dramc_info = {
+ .name = TYPE_AW_H3_DRAMC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_h3_dramc_init,
+ .instance_size = sizeof(AwH3DramCtlState),
+ .class_init = allwinner_h3_dramc_class_init,
+};
+
+static void allwinner_h3_dramc_register(void)
+{
+ type_register_static(&allwinner_h3_dramc_info);
+}
+
+type_init(allwinner_h3_dramc_register)
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index daa734036e..68aae2eabb 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -30,6 +30,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 4f38328d9c..a5862b2bed 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -5,6 +5,16 @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+# allwinner-h3-dramc.c
+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+
# allwinner-sid.c
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 12/18] hw/arm/allwinner: add RTC device support
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (10 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 11/18] hw/arm/allwinner-h3: add SDRAM controller device Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 13/18] tests/boot_linux_console: Add a quick test for the OrangePi PC board Niek Linnenbank
` (5 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
for non-volatile system date and time keeping. This commit adds a generic
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
The following RTC functionality and features are implemented:
* Year-Month-Day read/write
* Hour-Minute-Second read/write
* General Purpose storage
The following boards are extended with the RTC device:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
include/hw/arm/allwinner-a10.h | 2 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/rtc/allwinner-rtc.h | 134 +++++++++++
hw/arm/allwinner-a10.c | 8 +
hw/arm/allwinner-h3.c | 9 +-
hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++
hw/rtc/Makefile.objs | 1 +
hw/rtc/trace-events | 4 +
8 files changed, 571 insertions(+), 1 deletion(-)
create mode 100644 include/hw/rtc/allwinner-rtc.h
create mode 100644 hw/rtc/allwinner-rtc.c
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index ae33a84b18..77c82a9982 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -11,6 +11,7 @@
#include "hw/ide/ahci.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
+#include "hw/rtc/allwinner-rtc.h"
#include "target/arm/cpu.h"
@@ -33,6 +34,7 @@ typedef struct AwA10State {
AwEmacState emac;
AllwinnerAHCIState sata;
AwSdHostState mmc0;
+ AwRtcState rtc;
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];
OHCISysBusState ohci[AW_A10_NUM_USB];
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 065d020c73..82e4e59216 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -46,6 +46,7 @@
#include "hw/misc/allwinner-sid.h"
#include "hw/sd/allwinner-sdhost.h"
#include "hw/net/allwinner-sun8i-emac.h"
+#include "hw/rtc/allwinner-rtc.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@@ -88,6 +89,7 @@ enum {
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
AW_H3_GIC_VCPU,
+ AW_H3_RTC,
AW_H3_CPUCFG,
AW_H3_SDRAM
};
@@ -129,6 +131,7 @@ typedef struct AwH3State {
AwSidState sid;
AwSdHostState mmc0;
AwSun8iEmacState emac;
+ AwRtcState rtc;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h
new file mode 100644
index 0000000000..7893f74795
--- /dev/null
+++ b/include/hw/rtc/allwinner-rtc.h
@@ -0,0 +1,134 @@
+/*
+ * Allwinner Real Time Clock emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_RTC_H
+#define HW_MISC_ALLWINNER_RTC_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * Constants
+ * @{
+ */
+
+/** Highest register address used by RTC device */
+#define AW_RTC_REGS_MAXADDR (0x200)
+
+/** Total number of known registers */
+#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * Object model types
+ * @{
+ */
+
+/** Generic Allwinner RTC device (abstract) */
+#define TYPE_AW_RTC "allwinner-rtc"
+
+/** Allwinner RTC sun4i family (A10, A12) */
+#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
+
+/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
+#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
+
+/** Allwinner RTC sun7i family (A20) */
+#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
+
+/** @} */
+
+/**
+ * Object model macros
+ * @{
+ */
+
+#define AW_RTC(obj) \
+ OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC)
+#define AW_RTC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC)
+#define AW_RTC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC)
+
+/** @} */
+
+/**
+ * Allwinner RTC per-object instance state.
+ */
+typedef struct AwRtcState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /**
+ * Actual year represented by the device when year counter is zero
+ *
+ * Can be overridden by the user using the corresponding 'base-year'
+ * property. The base year used by the target OS driver can vary, for
+ * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
+ */
+ int base_year;
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_RTC_REGS_NUM];
+
+} AwRtcState;
+
+/**
+ * Allwinner RTC class-level struct.
+ *
+ * This struct is filled by each sunxi device specific code
+ * such that the generic code can use this struct to support
+ * all devices.
+ */
+typedef struct AwRtcClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ /** Defines device specific register map */
+ const uint8_t *regmap;
+
+ /** Size of the regmap in bytes */
+ size_t regmap_size;
+
+ /**
+ * Read device specific register
+ *
+ * @offset: register offset to read
+ * @return true if register read successful, false otherwise
+ */
+ bool (*read)(AwRtcState *s, uint32_t offset);
+
+ /**
+ * Write device specific register
+ *
+ * @offset: register offset to write
+ * @data: value to set in register
+ * @return true if register write successful, false otherwise
+ */
+ bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
+
+} AwRtcClass;
+
+#endif /* HW_MISC_ALLWINNER_RTC_H */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index dc62c76416..62a67a3e1a 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -35,6 +35,7 @@
#define AW_A10_EHCI_BASE 0x01c14000
#define AW_A10_OHCI_BASE 0x01c14400
#define AW_A10_SATA_BASE 0x01c18000
+#define AW_A10_RTC_BASE 0x01c20d00
static void aw_a10_init(Object *obj)
{
@@ -68,6 +69,9 @@ static void aw_a10_init(Object *obj)
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
TYPE_AW_SDHOST_SUN4I);
+
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
+ TYPE_AW_RTC_SUN4I);
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -175,6 +179,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
"sd-bus", &error_abort);
+
+ /* RTC */
+ qdev_init_nofail(DEVICE(&s->rtc));
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
}
static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 0e0fea6223..f1edb679d5 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -63,6 +63,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_GIC_CPU] = 0x01c82000,
[AW_H3_GIC_HYP] = 0x01c84000,
[AW_H3_GIC_VCPU] = 0x01c86000,
+ [AW_H3_RTC] = 0x01f00000,
[AW_H3_CPUCFG] = 0x01f01c00,
[AW_H3_SDRAM] = 0x40000000
};
@@ -118,7 +119,6 @@ struct AwH3Unimplemented {
{ "csi", 0x01cb0000, 320 * KiB },
{ "tve", 0x01e00000, 64 * KiB },
{ "hdmi", 0x01ee0000, 128 * KiB },
- { "rtc", 0x01f00000, 1 * KiB },
{ "r_timer", 0x01f00800, 1 * KiB },
{ "r_intc", 0x01f00c00, 1 * KiB },
{ "r_wdog", 0x01f01000, 1 * KiB },
@@ -236,6 +236,9 @@ static void allwinner_h3_init(Object *obj)
"ram-addr", &error_abort);
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
"ram-size", &error_abort);
+
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
+ TYPE_AW_RTC_SUN6I);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -426,6 +429,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
+ /* RTC */
+ qdev_init_nofail(DEVICE(&s->rtc));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
+
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
create_unimplemented_device(unimplemented[i].device_name,
diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c
new file mode 100644
index 0000000000..5606a51d5c
--- /dev/null
+++ b/hw/rtc/allwinner-rtc.c
@@ -0,0 +1,411 @@
+/*
+ * Allwinner Real Time Clock emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu-common.h"
+#include "hw/qdev-properties.h"
+#include "hw/rtc/allwinner-rtc.h"
+#include "trace.h"
+
+/* RTC registers */
+enum {
+ REG_LOSC = 1, /* Low Oscillator Control */
+ REG_YYMMDD, /* RTC Year-Month-Day */
+ REG_HHMMSS, /* RTC Hour-Minute-Second */
+ REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
+ REG_ALARM1_EN, /* Alarm1 Enable */
+ REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
+ REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
+ REG_GP0, /* General Purpose Register 0 */
+ REG_GP1, /* General Purpose Register 1 */
+ REG_GP2, /* General Purpose Register 2 */
+ REG_GP3, /* General Purpose Register 3 */
+
+ /* sun4i registers */
+ REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
+ REG_CPUCFG, /* CPU Configuration Register */
+
+ /* sun6i registers */
+ REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
+ REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
+ REG_ALARM0_COUNTER, /* Alarm0 Counter */
+ REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
+ REG_ALARM0_ENABLE, /* Alarm0 Enable */
+ REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
+ REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
+ REG_ALARM_CONFIG, /* Alarm Config */
+ REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
+ REG_GP4, /* General Purpose Register 4 */
+ REG_GP5, /* General Purpose Register 5 */
+ REG_GP6, /* General Purpose Register 6 */
+ REG_GP7, /* General Purpose Register 7 */
+ REG_RTC_DBG, /* RTC Debug Register */
+ REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
+ REG_VDD_RTC, /* VDD RTC Regulate Register */
+ REG_IC_CHARA, /* IC Characteristics Register */
+};
+
+/* RTC register flags */
+enum {
+ REG_LOSC_YMD = (1 << 7),
+ REG_LOSC_HMS = (1 << 8),
+};
+
+/* RTC sun4i register map (offset to name) */
+const uint8_t allwinner_rtc_sun4i_regmap[] = {
+ [0x0000] = REG_LOSC,
+ [0x0004] = REG_YYMMDD,
+ [0x0008] = REG_HHMMSS,
+ [0x000C] = REG_ALARM1_DDHHMMSS,
+ [0x0010] = REG_ALARM1_WKHHMMSS,
+ [0x0014] = REG_ALARM1_EN,
+ [0x0018] = REG_ALARM1_IRQ_EN,
+ [0x001C] = REG_ALARM1_IRQ_STA,
+ [0x0020] = REG_GP0,
+ [0x0024] = REG_GP1,
+ [0x0028] = REG_GP2,
+ [0x002C] = REG_GP3,
+ [0x003C] = REG_CPUCFG,
+};
+
+/* RTC sun6i register map (offset to name) */
+const uint8_t allwinner_rtc_sun6i_regmap[] = {
+ [0x0000] = REG_LOSC,
+ [0x0004] = REG_LOSC_AUTOSTA,
+ [0x0008] = REG_INT_OSC_PRE,
+ [0x0010] = REG_YYMMDD,
+ [0x0014] = REG_HHMMSS,
+ [0x0020] = REG_ALARM0_COUNTER,
+ [0x0024] = REG_ALARM0_CUR_VLU,
+ [0x0028] = REG_ALARM0_ENABLE,
+ [0x002C] = REG_ALARM0_IRQ_EN,
+ [0x0030] = REG_ALARM0_IRQ_STA,
+ [0x0040] = REG_ALARM1_WKHHMMSS,
+ [0x0044] = REG_ALARM1_EN,
+ [0x0048] = REG_ALARM1_IRQ_EN,
+ [0x004C] = REG_ALARM1_IRQ_STA,
+ [0x0050] = REG_ALARM_CONFIG,
+ [0x0060] = REG_LOSC_OUT_GATING,
+ [0x0100] = REG_GP0,
+ [0x0104] = REG_GP1,
+ [0x0108] = REG_GP2,
+ [0x010C] = REG_GP3,
+ [0x0110] = REG_GP4,
+ [0x0114] = REG_GP5,
+ [0x0118] = REG_GP6,
+ [0x011C] = REG_GP7,
+ [0x0170] = REG_RTC_DBG,
+ [0x0180] = REG_GPL_HOLD_OUT,
+ [0x0190] = REG_VDD_RTC,
+ [0x01F0] = REG_IC_CHARA,
+};
+
+static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
+{
+ /* no sun4i specific registers currently implemented */
+ return false;
+}
+
+static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
+ uint32_t data)
+{
+ /* no sun4i specific registers currently implemented */
+ return false;
+}
+
+static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
+{
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
+
+ switch (c->regmap[offset]) {
+ case REG_GP4: /* General Purpose Register 4 */
+ case REG_GP5: /* General Purpose Register 5 */
+ case REG_GP6: /* General Purpose Register 6 */
+ case REG_GP7: /* General Purpose Register 7 */
+ return true;
+ default:
+ break;
+ }
+ return false;
+}
+
+static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
+ uint32_t data)
+{
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
+
+ switch (c->regmap[offset]) {
+ case REG_GP4: /* General Purpose Register 4 */
+ case REG_GP5: /* General Purpose Register 5 */
+ case REG_GP6: /* General Purpose Register 6 */
+ case REG_GP7: /* General Purpose Register 7 */
+ return true;
+ default:
+ break;
+ }
+ return false;
+}
+
+static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AwRtcState *s = AW_RTC(opaque);
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
+ uint64_t val = 0;
+
+ if (offset >= c->regmap_size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ if (!c->regmap[offset]) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ switch (c->regmap[offset]) {
+ case REG_LOSC: /* Low Oscillator Control */
+ val = s->regs[REG_LOSC];
+ s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS);
+ break;
+ case REG_YYMMDD: /* RTC Year-Month-Day */
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
+ case REG_GP0: /* General Purpose Register 0 */
+ case REG_GP1: /* General Purpose Register 1 */
+ case REG_GP2: /* General Purpose Register 2 */
+ case REG_GP3: /* General Purpose Register 3 */
+ val = s->regs[c->regmap[offset]];
+ break;
+ default:
+ if (!c->read(s, offset)) {
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ }
+ val = s->regs[c->regmap[offset]];
+ break;
+ }
+
+ trace_allwinner_rtc_read(offset, val);
+ return val;
+}
+
+static void allwinner_rtc_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwRtcState *s = AW_RTC(opaque);
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
+
+ if (offset >= c->regmap_size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ if (!c->regmap[offset]) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ trace_allwinner_rtc_write(offset, val);
+
+ switch (c->regmap[offset]) {
+ case REG_YYMMDD: /* RTC Year-Month-Day */
+ s->regs[REG_YYMMDD] = val;
+ s->regs[REG_LOSC] |= REG_LOSC_YMD;
+ break;
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
+ s->regs[REG_HHMMSS] = val;
+ s->regs[REG_LOSC] |= REG_LOSC_HMS;
+ break;
+ case REG_GP0: /* General Purpose Register 0 */
+ case REG_GP1: /* General Purpose Register 1 */
+ case REG_GP2: /* General Purpose Register 2 */
+ case REG_GP3: /* General Purpose Register 3 */
+ s->regs[c->regmap[offset]] = val;
+ break;
+ default:
+ if (!c->write(s, offset, val)) {
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_rtc_ops = {
+ .read = allwinner_rtc_read,
+ .write = allwinner_rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static void allwinner_rtc_reset(DeviceState *dev)
+{
+ AwRtcState *s = AW_RTC(dev);
+ struct tm now;
+
+ /* Clear registers */
+ memset(s->regs, 0, sizeof(s->regs));
+
+ /* Get current datetime */
+ qemu_get_timedate(&now, 0);
+
+ /* Set RTC with current datetime */
+ if (s->base_year > 1900) {
+ s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) |
+ ((now.tm_mon + 1) << 8) |
+ now.tm_mday;
+ s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) |
+ (now.tm_hour << 16) |
+ (now.tm_min << 8) |
+ now.tm_sec;
+ }
+}
+
+static void allwinner_rtc_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwRtcState *s = AW_RTC(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
+ TYPE_AW_RTC, 1 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_rtc_vmstate = {
+ .name = "allwinner-rtc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property allwinner_rtc_properties[] = {
+ DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = allwinner_rtc_reset;
+ dc->vmsd = &allwinner_rtc_vmstate;
+ device_class_set_props(dc, allwinner_rtc_properties);
+}
+
+static void allwinner_rtc_sun4i_init(Object *obj)
+{
+ AwRtcState *s = AW_RTC(obj);
+ s->base_year = 2010;
+}
+
+static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
+{
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
+
+ arc->regmap = allwinner_rtc_sun4i_regmap;
+ arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap);
+ arc->read = allwinner_rtc_sun4i_read;
+ arc->write = allwinner_rtc_sun4i_write;
+}
+
+static void allwinner_rtc_sun6i_init(Object *obj)
+{
+ AwRtcState *s = AW_RTC(obj);
+ s->base_year = 1970;
+}
+
+static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
+{
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
+
+ arc->regmap = allwinner_rtc_sun6i_regmap;
+ arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap);
+ arc->read = allwinner_rtc_sun6i_read;
+ arc->write = allwinner_rtc_sun6i_write;
+}
+
+static void allwinner_rtc_sun7i_init(Object *obj)
+{
+ AwRtcState *s = AW_RTC(obj);
+ s->base_year = 1970;
+}
+
+static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
+{
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
+ allwinner_rtc_sun4i_class_init(klass, arc);
+}
+
+static const TypeInfo allwinner_rtc_info = {
+ .name = TYPE_AW_RTC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_rtc_init,
+ .instance_size = sizeof(AwRtcState),
+ .class_init = allwinner_rtc_class_init,
+ .class_size = sizeof(AwRtcClass),
+ .abstract = true,
+};
+
+static const TypeInfo allwinner_rtc_sun4i_info = {
+ .name = TYPE_AW_RTC_SUN4I,
+ .parent = TYPE_AW_RTC,
+ .class_init = allwinner_rtc_sun4i_class_init,
+ .instance_init = allwinner_rtc_sun4i_init,
+};
+
+static const TypeInfo allwinner_rtc_sun6i_info = {
+ .name = TYPE_AW_RTC_SUN6I,
+ .parent = TYPE_AW_RTC,
+ .class_init = allwinner_rtc_sun6i_class_init,
+ .instance_init = allwinner_rtc_sun6i_init,
+};
+
+static const TypeInfo allwinner_rtc_sun7i_info = {
+ .name = TYPE_AW_RTC_SUN7I,
+ .parent = TYPE_AW_RTC,
+ .class_init = allwinner_rtc_sun7i_class_init,
+ .instance_init = allwinner_rtc_sun7i_init,
+};
+
+static void allwinner_rtc_register(void)
+{
+ type_register_static(&allwinner_rtc_info);
+ type_register_static(&allwinner_rtc_sun4i_info);
+ type_register_static(&allwinner_rtc_sun6i_info);
+ type_register_static(&allwinner_rtc_sun7i_info);
+}
+
+type_init(allwinner_rtc_register)
diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs
index aa208d0d10..e4c1b8617c 100644
--- a/hw/rtc/Makefile.objs
+++ b/hw/rtc/Makefile.objs
@@ -12,3 +12,4 @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o
common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o
diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events
index c9894e1747..1bc7147d0e 100644
--- a/hw/rtc/trace-events
+++ b/hw/rtc/trace-events
@@ -1,5 +1,9 @@
# See docs/devel/tracing.txt for syntax documentation.
+# allwinner-rtc.c
+allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
+allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
+
# sun4v-rtc.c
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 13/18] tests/boot_linux_console: Add a quick test for the OrangePi PC board
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (11 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 12/18] hw/arm/allwinner: add RTC device support Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 14/18] tests/boot_linux_console: Add initrd test for the Orange Pi " Niek Linnenbank
` (4 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, Philippe Mathieu-Daudé,
b.galvani, Niek Linnenbank, qemu-arm, imammedo, philmd
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ make check-venv
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
console: Memory policy: Data cache writealloc
console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000'
console: cma: Failed to reserve 128 MiB
console: psci: probing for conduit method from DT.
console: psci: PSCIv0.2 detected in firmware.
console: psci: Using standard PSCI v0.2 function IDs
console: psci: Trusted OS migration not required
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
console: Kernel command line: printk.time=0 console=ttyS0,115200
PASS (8.59 s)
JOB TIME : 8.81 s
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index 34d37eba3b..6f5af582f3 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -507,6 +507,31 @@ class BootLinuxConsole(Test):
exec_command_and_wait_for_pattern(self, 'reboot',
'reboot: Restarting system')
+ def test_arm_orangepi(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:orangepi-pc
+ """
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+ kernel_path = self.extract_from_deb(deb_path,
+ '/boot/vmlinuz-4.20.7-sunxi')
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
+
+ self.vm.set_console()
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=ttyS0,115200n8 '
+ 'earlycon=uart,mmio32,0x1c28000')
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', dtb_path,
+ '-append', kernel_command_line)
+ self.vm.launch()
+ console_pattern = 'Kernel command line: %s' % kernel_command_line
+ self.wait_for_console_pattern(console_pattern)
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=arch:s390x
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 14/18] tests/boot_linux_console: Add initrd test for the Orange Pi PC board
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (12 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 13/18] tests/boot_linux_console: Add a quick test for the OrangePi PC board Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 15/18] tests/boot_linux_console: Add a SD card test for the OrangePi " Niek Linnenbank
` (3 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, Philippe Mathieu-Daudé,
b.galvani, Niek Linnenbank, qemu-arm, imammedo, philmd
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: Trying to unpack rootfs image as initramfs...
console: Freeing initrd memory: 3256K
console: Freeing unused kernel memory: 1024K
console: Run /init as init process
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
console: Starting logging: OK
console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
console: done.
console: Starting network: OK
console: Found console ttyS0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: Boot successful.
console: cat /proc/cpuinfo
console: / # cat /proc/cpuinfo
console: processor : 0
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
[...]
console: processor : 3
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
console: Hardware : Allwinner sun8i Family
console: Revision : 0000
console: Serial : 0000000000000000
console: cat /proc/iomem
console: / # cat /proc/iomem
console: 01000000-010fffff : clock@1000000
console: 01c00000-01c00fff : system-control@1c00000
console: 01c02000-01c02fff : dma-controller@1c02000
[...]
console: reboot
console: / # reboot
console: / # Found console ttyS0
console: Stopping network: OK
console: hrtimer: interrupt took 21852064 ns
console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read)
console: done.
console: Stopping logging: OK
console: umount: devtmpfs busy - remounted read-only
console: umount: can't unmount /: Invalid argument
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
PASS (48.32 s)
JOB TIME : 49.16 s
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index 6f5af582f3..dabc8ef2af 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -532,6 +532,46 @@ class BootLinuxConsole(Test):
console_pattern = 'Kernel command line: %s' % kernel_command_line
self.wait_for_console_pattern(console_pattern)
+ def test_arm_orangepi_initrd(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:orangepi-pc
+ """
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+ kernel_path = self.extract_from_deb(deb_path,
+ '/boot/vmlinuz-4.20.7-sunxi')
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+ 'arm/rootfs-armv7a.cpio.gz')
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+ self.vm.set_console()
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=ttyS0,115200 '
+ 'panic=-1 noreboot')
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', dtb_path,
+ '-initrd', initrd_path,
+ '-append', kernel_command_line,
+ '-no-reboot')
+ self.vm.launch()
+ self.wait_for_console_pattern('Boot successful.')
+
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+ 'Allwinner sun8i Family')
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+ 'system-control@1c00000')
+ exec_command_and_wait_for_pattern(self, 'reboot',
+ 'reboot: Restarting system')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=arch:s390x
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 15/18] tests/boot_linux_console: Add a SD card test for the OrangePi PC board
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (13 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 14/18] tests/boot_linux_console: Add initrd test for the Orange Pi " Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 16/18] tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC Niek Linnenbank
` (2 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, Philippe Mathieu-Daudé,
b.galvani, Niek Linnenbank, qemu-arm, imammedo, philmd
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
[...]
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0)
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
console: ledtrig-cpu: registered to indicate activity on CPUs
console: hidraw: raw HID events driver (C) Jiri Kosina
console: usbcore: registered new interface driver usbhid
console: usbhid: USB HID core driver
console: Initializing XFRM netlink socket
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
console: NET: Registered protocol family 10
console: mmc0: host does not support reading read-only switch, assuming write-enable
console: mmc0: Problem switching card into high-speed mode!
console: mmc0: new SD card at address 4567
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
[...]
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
console: Run /sbin/init as init process
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl
console: Starting syslogd: OK
console: Starting klogd: OK
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
console: /bin/sh: can't access tty; job control turned off
console: cat /proc/partitions
console: / # cat /proc/partitions
console: major minor #blocks name
console: 1 0 4096 ram0
console: 1 1 4096 ram1
console: 1 2 4096 ram2
console: 1 3 4096 ram3
console: 179 0 61440 mmcblk0
console: reboot
console: / # reboot
console: umount: devtmpfs busy - remounted read-only
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
JOB TIME : 68.64 s
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index dabc8ef2af..7ef69c7bac 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -572,6 +572,47 @@ class BootLinuxConsole(Test):
exec_command_and_wait_for_pattern(self, 'reboot',
'reboot: Restarting system')
+ def test_arm_orangepi_sd(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:orangepi-pc
+ """
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+ kernel_path = self.extract_from_deb(deb_path,
+ '/boot/vmlinuz-4.20.7-sunxi')
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
+ rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
+ 'kci-2019.02/armel/base/rootfs.ext2.xz')
+ rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061'
+ rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
+
+ self.vm.set_console()
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=ttyS0,115200 '
+ 'root=/dev/mmcblk0 rootwait rw '
+ 'panic=-1 noreboot')
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', dtb_path,
+ '-drive', 'file=' + rootfs_path + ',if=sd,format=raw',
+ '-append', kernel_command_line,
+ '-no-reboot')
+ self.vm.launch()
+ shell_ready = "/bin/sh: can't access tty; job control turned off"
+ self.wait_for_console_pattern(shell_ready)
+
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+ 'Allwinner sun8i Family')
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
+ 'mmcblk0')
+ exec_command_and_wait_for_pattern(self, 'reboot',
+ 'reboot: Restarting system')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=arch:s390x
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 16/18] tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (14 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 15/18] tests/boot_linux_console: Add a SD card test for the OrangePi " Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 17/18] tests/boot_linux_console: Test booting NetBSD via U-Boot " Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 18/18] docs: add Orange Pi PC document Niek Linnenbank
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, Philippe Mathieu-Daudé,
b.galvani, Niek Linnenbank, qemu-arm, imammedo, philmd
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This test boots Ubuntu Bionic on a OrangePi PC board.
As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.
It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The Ubuntu image is downloaded from:
https://dl.armbian.com/orangepipc/Bionic_current
This test can be run using:
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
avocado --show=app,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
console: DRAM: 1024 MiB
console: Failed to set core voltage! Can't set CPU frequency
console: Trying to boot from MMC1
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology
console: CPU: Allwinner H3 (SUN8I 0000)
console: Model: Xunlong Orange Pi PC
console: DRAM: 1 GiB
console: MMC: mmc@1c0f000: 0
[...]
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)
console: done.
console: Begin: Running /scripts/local-bottom ... done.
console: Begin: Running /scripts/init-bottom ... done.
console: systemd[1]: systemd 237 running in system mode. (...)
console: systemd[1]: Detected architecture arm.
console: Welcome to Ubuntu 18.04.3 LTS!
console: systemd[1]: Set hostname to <orangepipc>.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: changed test to boot from SD card via BootROM, added check for 7z]
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index 7ef69c7bac..a70ac4a6cc 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -19,7 +19,13 @@ from avocado_qemu import exec_command_and_wait_for_pattern
from avocado_qemu import wait_for_console_pattern
from avocado.utils import process
from avocado.utils import archive
+from avocado.utils.path import find_command, CmdNotFoundError
+P7ZIP_AVAILABLE = True
+try:
+ find_command('7z')
+except CmdNotFoundError:
+ P7ZIP_AVAILABLE = False
class BootLinuxConsole(Test):
"""
@@ -613,6 +619,48 @@ class BootLinuxConsole(Test):
exec_command_and_wait_for_pattern(self, 'reboot',
'reboot: Restarting system')
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
+ def test_arm_orangepi_bionic(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:orangepi-pc
+ """
+
+ # This test download a 196MB compressed image and expand it to 932MB...
+ image_url = ('https://dl.armbian.com/orangepipc/archive/'
+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
+ image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'
+ image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)
+ image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'
+ image_path = os.path.join(self.workdir, image_name)
+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
+
+ self.vm.set_console()
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
+ '-nic', 'user',
+ '-no-reboot')
+ self.vm.launch()
+
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=ttyS0,115200 '
+ 'loglevel=7 '
+ 'nosmp '
+ 'systemd.default_timeout_start_sec=9000 '
+ 'systemd.mask=armbian-zram-config.service '
+ 'systemd.mask=armbian-ramlog.service')
+
+ self.wait_for_console_pattern('U-Boot SPL')
+ self.wait_for_console_pattern('Autoboot in ')
+ exec_command_and_wait_for_pattern(self, ' ', '=>')
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
+ kernel_command_line + "'", '=>')
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
+
+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +
+ 'to <orangepipc>')
+ self.wait_for_console_pattern('Starting Load Kernel Modules...')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=arch:s390x
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 17/18] tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (15 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 16/18] tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 18/18] docs: add Orange Pi PC document Niek Linnenbank
17 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, Philippe Mathieu-Daudé,
b.galvani, Niek Linnenbank, qemu-arm, imammedo, philmd
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This test boots U-Boot then NetBSD (stored on a SD card) on
a OrangePi PC board.
As it requires ~1.3GB of storage, it is disabled by default.
U-Boot is built by the Debian project [1], and the SD card image
is provided by the NetBSD organization [2].
Once the compressed SD card image is downloaded (304MB) and
extracted, this test is fast:
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
avocado --show=app,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
console: DRAM: 1024 MiB
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology
console: CPU: Allwinner H3 (SUN8I 0000)
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
console: scanning usb for storage devices... 0 Storage Device(s) found
console: Hit any key to stop autoboot: 0
console: => setenv bootargs root=ld0a
console: => setenv kernel netbsd-GENERIC.ub
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
console: => boot
console: ## Booting kernel from Legacy Image at 42000000 ...
console: Image Name: NetBSD/earmv7hf 9.0_RC1
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
console: XIP Kernel Image (no loading done)
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
console: Starting kernel ...
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC
console: [ 1.0000000] total memory = 1024 MB
console: [ 1.0000000] avail memory = 1003 MB
console: [ 1.0000000] armfdt0 (root)
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
...
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log.
console: [ 3.1179868] boot device: ld0
console: [ 3.1470623] root on ld0a dumps on ld0b
console: [ 3.2464436] root file system type: ffs
console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules
console: Mon Feb 17 20:33:35 UTC 2020
console: Starting root file system check:
PASS (35.96 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
JOB TIME : 36.09 s
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
This test is based on a description from Niek Linnenbank from [4].
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year]
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index a70ac4a6cc..4f09e559c8 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -16,6 +16,7 @@ import shutil
from avocado import skipUnless
from avocado_qemu import Test
from avocado_qemu import exec_command_and_wait_for_pattern
+from avocado_qemu import interrupt_interactive_console_until_pattern
from avocado_qemu import wait_for_console_pattern
from avocado.utils import process
from avocado.utils import archive
@@ -661,6 +662,75 @@ class BootLinuxConsole(Test):
'to <orangepipc>')
self.wait_for_console_pattern('Starting Load Kernel Modules...')
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
+ def test_arm_orangepi_uboot_netbsd9(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:orangepi-pc
+ """
+ # This test download a 304MB compressed image and expand it to 1.3GB...
+ deb_url = ('http://snapshot.debian.org/archive/debian/'
+ '20200108T145233Z/pool/main/u/u-boot/'
+ 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb')
+ deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99'
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+ # We use the common OrangePi PC 'plus' build of U-Boot for our secondary
+ # program loader (SPL). We will then set the path to the more specific
+ # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt,
+ # before to boot NetBSD.
+ uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin'
+ uboot_path = self.extract_from_deb(deb_path, uboot_path)
+ image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/'
+ 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz')
+ image_hash = '2babb29d36d8360adcb39c09e31060945259917a'
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
+ image_path = os.path.join(self.workdir, 'armv7.img')
+ image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path
+ archive.gzip_uncompress(image_path_gz, image_path)
+
+ # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc
+ with open(uboot_path, 'rb') as f_in:
+ with open(image_path, 'r+b') as f_out:
+ f_out.seek(8 * 1024)
+ shutil.copyfileobj(f_in, f_out)
+
+ # Extend image, to avoid that NetBSD thinks the partition
+ # inside the image is larger than device size itself
+ f_out.seek(0, 2)
+ f_out.seek(64 * 1024 * 1024, 1)
+ f_out.write(bytearray([0x00]))
+
+ self.vm.set_console()
+ self.vm.add_args('-nic', 'user',
+ '-drive', image_drive_args,
+ '-global', 'allwinner-rtc.base-year=2000',
+ '-no-reboot')
+ self.vm.launch()
+ wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1')
+ interrupt_interactive_console_until_pattern(self,
+ 'Hit any key to stop autoboot:',
+ 'switch to partitions #0, OK')
+
+ exec_command_and_wait_for_pattern(self, '', '=>')
+ cmd = 'setenv bootargs root=ld0a'
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
+ cmd = 'setenv kernel netbsd-GENERIC.ub'
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
+ cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb'
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
+ cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; "
+ "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; "
+ "fdt addr ${fdt_addr_r}; "
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}'")
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
+
+ exec_command_and_wait_for_pattern(self, 'boot',
+ 'Booting kernel from Legacy Image')
+ wait_for_console_pattern(self, 'Starting kernel ...')
+ wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)')
+ # Wait for user-space
+ wait_for_console_pattern(self, 'Starting root file system check')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=arch:s390x
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
` (16 preceding siblings ...)
2020-03-01 21:50 ` [PATCH v6 17/18] tests/boot_linux_console: Test booting NetBSD via U-Boot " Niek Linnenbank
@ 2020-03-01 21:50 ` Niek Linnenbank
2020-03-04 10:35 ` Alex Bennée
17 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-01 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, alex.bennee, jasowang, b.galvani, Niek Linnenbank,
qemu-arm, imammedo, philmd
The Xunlong Orange Pi PC machine is a functional ARM machine
based on the Allwinner H3 System-on-Chip. It supports mainline
Linux, U-Boot, NetBSD and is covered by acceptance tests.
This commit adds a documentation text file with a description
of the machine and instructions for the user.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
---
docs/orangepi.rst | 226 ++++++++++++++++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 227 insertions(+)
create mode 100644 docs/orangepi.rst
diff --git a/docs/orangepi.rst b/docs/orangepi.rst
new file mode 100644
index 0000000000..a9b46f553c
--- /dev/null
+++ b/docs/orangepi.rst
@@ -0,0 +1,226 @@
+=========================
+Orange Pi PC Machine Type
+=========================
+
+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
+based embedded computer with mainline support in both U-Boot
+and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
+various other I/O.
+
+Supported devices
+-----------------
+
+The Orange Pi PC machine supports the following devices:
+
+ * SMP (Quad Core Cortex A7)
+ * Generic Interrupt Controller configuration
+ * SRAM mappings
+ * SDRAM controller
+ * Real Time Clock
+ * Timer device (re-used from Allwinner A10)
+ * UART
+ * SD/MMC storage controller
+ * EMAC ethernet
+ * USB 2.0 interfaces
+ * Clock Control Unit
+ * System Control module
+ * Security Identifier device
+
+Limitations
+-----------
+
+Currently, Orange Pi PC does *not* support the following features:
+
+- Graphical output via HDMI, GPU and/or the Display Engine
+- Audio output
+- Hardware Watchdog
+
+Also see the 'unimplemented' array in the Allwinner H3 SoC module
+for a complete list of unimplemented I/O devices:
+ ./hw/arm/allwinner-h3.c
+
+Using the Orange Pi PC machine type
+-----------------------------------
+
+Boot options
+~~~~~~~~~~~~
+
+The Orange Pi PC machine can start using the standard -kernel functionality
+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC
+machine can also emulate the BootROM which is present on an actual Allwinner H3
+based SoC, which loads the bootloader from a SD card, specified via the -sd argument
+to qemu-system-arm.
+
+Machine-specific options
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following machine-specific options are supported:
+
+- allwinner-rtc.base-year=YYYY
+
+ The Allwinner RTC device is automatically created by the Orange Pi PC machine
+ and uses a default base year value which can be overridden using the 'base-year' property.
+ The base year is the actual represented year when the RTC year value is zero.
+ This option can be used in case the target operating system driver uses a different
+ base year value. The minimum value for the base year is 1900.
+
+- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff
+
+ The Security Identifier value can be read by the guest.
+ For example, U-Boot uses it to determine a unique MAC address.
+
+The above machine-specific options can be specified in qemu-system-arm
+via the '-global' argument, for example:
+
+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \
+ -global allwinner-rtc.base-year=2000
+
+Running mainline Linux
+~~~~~~~~~~~~~~~~~~~~~~
+
+Mainline Linux kernels from 4.19 up to latest master are known to work.
+To build a Linux mainline kernel that can be booted by the Orange Pi PC machine,
+simply configure the kernel using the sunxi_defconfig configuration:
+
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig
+
+To be able to use USB storage, you need to manually enable the corresponding
+configuration item. Start the kconfig configuration tool:
+
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig
+
+Navigate to the following item, enable it and save your configuration:
+
+ Device Drivers > USB support > USB Mass Storage support
+
+Build the Linux kernel with:
+
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make
+
+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use:
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -kernel /path/to/linux/arch/arm/boot/zImage \
+ -append 'console=ttyS0,115200' \
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
+
+Orange Pi PC images
+~~~~~~~~~~~~~~~~~~~
+
+Note that the mainline kernel does not have a root filesystem. You may provide it
+with an official Orange Pi PC image from the official website:
+
+ http://www.orangepi.org/downloadresources/
+
+Another possibility is to run an Armbian image for Orange Pi PC which
+can be downloaded from:
+
+ https://www.armbian.com/orange-pi-pc/
+
+Alternatively, you can also choose to build you own image with buildroot
+using the orangepi_pc_defconfig. Also see https://buildroot.org for more information.
+
+You can choose to attach the selected image either as an SD card or as USB mass storage.
+For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd
+argument and provide the proper root= kernel parameter:
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -kernel /path/to/linux/arch/arm/boot/zImage \
+ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
+
+To attach the image as an USB mass storage device to the machine,
+simply append to the command:
+
+ -drive if=none,id=stick,file=myimage.img \
+ -device usb-storage,bus=usb-bus.0,drive=stick
+
+Instead of providing a custom Linux kernel via the -kernel command you may also
+choose to let the Orange Pi PC machine load the bootloader from SD card, just like
+a real board would do using the BootROM. Simply pass the selected image via the -sd
+argument and remove the -kernel, -append, -dbt and -initrd arguments:
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img
+
+Note that both the official Orange Pi PC images and Armbian images start
+a lot of userland programs via systemd. Depending on the host hardware and OS,
+they may be slow to emulate, especially due to emulating the 4 cores.
+To help reduce the performance slow down due to emulating the 4 cores, you can
+give the following kernel parameters (or via -append):
+
+ => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200'
+
+Running U-Boot
+~~~~~~~~~~~~~~
+
+U-Boot mainline can be build and configured using the orangepi_pc_defconfig
+using similar commands as describe above for Linux. Note that it is recommended
+for development/testing to select the following configuration setting in U-Boot:
+
+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB
+
+To start U-Boot using the Orange Pi PC machine, provide the
+u-boot binary to the -kernel argument:
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -kernel /path/to/uboot/u-boot -sd disk.img
+
+Use the following U-boot commands to load and boot a Linux kernel from SD card:
+
+ -> setenv bootargs console=ttyS0,115200
+ -> ext2load mmc 0 0x42000000 zImage
+ -> ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
+ -> bootz 0x42000000 - 0x43000000
+
+Running NetBSD
+~~~~~~~~~~~~~~
+
+The NetBSD operating system also includes support for Allwinner H3 based boards,
+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC
+board and provides a fully working system with serial console, networking and storage.
+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:
+
+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz
+
+The image requires manually installing U-Boot in the image. Build U-Boot with
+the orangepi_pc_defconfig configuration as described in the previous section.
+Next, unzip the NetBSD image and write the U-Boot binary including SPL using:
+
+ $ gunzip armv7.img.gz
+ $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc
+
+Finally, before starting the machine the SD image must be extended such
+that the NetBSD kernel will not conclude the NetBSD partition is larger than
+the emulated SD card:
+
+ $ dd if=/dev/zero bs=1M count=64 >> armv7.img
+
+Start the machine using the following command:
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -sd armv7.img -global allwinner-rtc.base-year=2000
+
+At the U-Boot stage, interrupt the automatic boot process by pressing a key
+and set the following environment variables before booting:
+
+ => setenv bootargs root=ld0a
+ => setenv kernel netbsd-GENERIC.ub
+ => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
+ => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}'
+
+Optionally you may save the environment variables to SD card with 'saveenv'.
+To continue booting simply give the 'boot' command and NetBSD boots.
+
+Orange Pi PC acceptance tests
+-----------------------------
+
+The Orange Pi PC machine has several acceptance tests included.
+To run the whole set of tests, build QEMU from source and simply
+provide the following command:
+
+ $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \
+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
diff --git a/MAINTAINERS b/MAINTAINERS
index 02ecba8d9c..643906bd18 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -497,6 +497,7 @@ S: Maintained
F: hw/*/allwinner-h3*
F: include/hw/*/allwinner-h3*
F: hw/arm/orangepi.c
+F: docs/orangepi.rst
ARM PrimeCell and CMSDK devices
M: Peter Maydell <peter.maydell@linaro.org>
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH v6 01/18] hw/arm: add Allwinner H3 System-on-Chip
2020-03-01 21:50 ` [PATCH v6 01/18] hw/arm: add Allwinner H3 System-on-Chip Niek Linnenbank
@ 2020-03-03 10:53 ` Alex Bennée
0 siblings, 0 replies; 42+ messages in thread
From: Alex Bennée @ 2020-03-03 10:53 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> The Allwinner H3 is a System on Chip containing four ARM Cortex A7
> processor cores. Features and specifications include DDR2/DDR3 memory,
> SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
> various I/O modules. This commit adds support for the Allwinner H3
> System on Chip.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 02/18] hw/arm: add Xunlong Orange Pi PC machine
2020-03-01 21:50 ` [PATCH v6 02/18] hw/arm: add Xunlong Orange Pi PC machine Niek Linnenbank
@ 2020-03-03 11:02 ` Alex Bennée
0 siblings, 0 replies; 42+ messages in thread
From: Alex Bennée @ 2020-03-03 11:02 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> based embedded computer with mainline support in both U-Boot
> and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
> 1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
> various other I/O. This commit add support for the Xunlong
> Orange Pi PC machine.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/arm/orangepi.c | 89 ++++++++++++++++++++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> hw/arm/Makefile.objs | 2 +-
> 3 files changed, 91 insertions(+), 1 deletion(-)
> create mode 100644 hw/arm/orangepi.c
>
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> new file mode 100644
> index 0000000000..19adfca917
> --- /dev/null
> +++ b/hw/arm/orangepi.c
> @@ -0,0 +1,89 @@
> +/*
> + * Orange Pi emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "exec/address-spaces.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "hw/sysbus.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/arm/allwinner-h3.h"
> +#include "sysemu/sysemu.h"
> +
> +static struct arm_boot_info orangepi_binfo = {
> + .nb_cpus = AW_H3_NUM_CPUS,
> +};
> +
> +static void orangepi_init(MachineState *machine)
> +{
> + AwH3State *h3;
> +
> + /* BIOS is not supported by this board */
> + if (bios_name) {
> + error_report("BIOS not supported for this machine");
> + exit(1);
> + }
> +
> + /* This board has fixed size RAM */
> + if (machine->ram_size != 1 * GiB) {
> + error_report("This machine can only be used with 1GiB of RAM");
> + exit(1);
> + }
> +
> + /* Only allow Cortex-A7 for this board */
> + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
> + error_report("This board can only be used with cortex-a7 CPU");
> + exit(1);
> + }
> +
> + h3 = AW_H3(object_new(TYPE_AW_H3));
> +
> + /* Setup timer properties */
> + object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
> + &error_abort);
> + object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
> + &error_abort);
> +
> + /* Mark H3 object realized */
> + object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
> +
> + /* SDRAM */
> + memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
> + machine->ram);
> +
> + orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
> + orangepi_binfo.ram_size = machine->ram_size;
> + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
> +}
> +
> +static void orangepi_machine_init(MachineClass *mc)
> +{
> + mc->desc = "Orange Pi PC";
> + mc->init = orangepi_init;
> + mc->min_cpus = AW_H3_NUM_CPUS;
> + mc->max_cpus = AW_H3_NUM_CPUS;
> + mc->default_cpus = AW_H3_NUM_CPUS;
> + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
> + mc->default_ram_size = 1 * GiB;
> + mc->default_ram_id = "orangepi.ram";
> +}
> +
> +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d5c0c25cc4..02ecba8d9c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -496,6 +496,7 @@ L: qemu-arm@nongnu.org
> S: Maintained
> F: hw/*/allwinner-h3*
> F: include/hw/*/allwinner-h3*
> +F: hw/arm/orangepi.c
>
> ARM PrimeCell and CMSDK devices
> M: Peter Maydell <peter.maydell@linaro.org>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index ae577e875f..534a6a119e 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -35,7 +35,7 @@ obj-$(CONFIG_DIGIC) += digic.o
> obj-$(CONFIG_OMAP) += omap1.o omap2.o
> obj-$(CONFIG_STRONGARM) += strongarm.o
> obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
> -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
> +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o
> obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
> obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
> obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 03/18] hw/arm/allwinner-h3: add Clock Control Unit
2020-03-01 21:50 ` [PATCH v6 03/18] hw/arm/allwinner-h3: add Clock Control Unit Niek Linnenbank
@ 2020-03-03 11:10 ` Alex Bennée
0 siblings, 0 replies; 42+ messages in thread
From: Alex Bennée @ 2020-03-03 11:10 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> The Clock Control Unit is responsible for clock signal generation,
> configuration and distribution in the Allwinner H3 System on Chip.
> This commit adds support for the Clock Control Unit which emulates
> a simple read/write register interface.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 04/18] hw/arm/allwinner-h3: add USB host controller
2020-03-01 21:50 ` [PATCH v6 04/18] hw/arm/allwinner-h3: add USB host controller Niek Linnenbank
@ 2020-03-03 11:11 ` Alex Bennée
0 siblings, 0 replies; 42+ messages in thread
From: Alex Bennée @ 2020-03-03 11:11 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> The Allwinner H3 System on Chip contains multiple USB 2.0 bus
> connections which provide software access using the Enhanced
> Host Controller Interface (EHCI) and Open Host Controller
> Interface (OHCI) interfaces. This commit adds support for
> both interfaces in the Allwinner H3 System on Chip.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 05/18] hw/arm/allwinner-h3: add System Control module
2020-03-01 21:50 ` [PATCH v6 05/18] hw/arm/allwinner-h3: add System Control module Niek Linnenbank
@ 2020-03-03 12:01 ` Alex Bennée
0 siblings, 0 replies; 42+ messages in thread
From: Alex Bennée @ 2020-03-03 12:01 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> The Allwinner H3 System on Chip has an System Control
> module that provides system wide generic controls and
> device information. This commit adds support for the
> Allwinner H3 System Control module.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/arm/allwinner-h3.h | 3 +
> include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
> hw/arm/allwinner-h3.c | 9 +-
> hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
> hw/misc/Makefile.objs | 1 +
> 5 files changed, 219 insertions(+), 1 deletion(-)
> create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
> create mode 100644 hw/misc/allwinner-h3-sysctrl.c
>
> diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
> index 4f4dcbcd17..43500c4262 100644
> --- a/include/hw/arm/allwinner-h3.h
> +++ b/include/hw/arm/allwinner-h3.h
> @@ -40,6 +40,7 @@
> #include "hw/timer/allwinner-a10-pit.h"
> #include "hw/intc/arm_gic.h"
> #include "hw/misc/allwinner-h3-ccu.h"
> +#include "hw/misc/allwinner-h3-sysctrl.h"
> #include "target/arm/cpu.h"
>
> /**
> @@ -56,6 +57,7 @@ enum {
> AW_H3_SRAM_A1,
> AW_H3_SRAM_A2,
> AW_H3_SRAM_C,
> + AW_H3_SYSCTRL,
> AW_H3_EHCI0,
> AW_H3_OHCI0,
> AW_H3_EHCI1,
> @@ -108,6 +110,7 @@ typedef struct AwH3State {
> const hwaddr *memmap;
> AwA10PITState timer;
> AwH3ClockCtlState ccu;
> + AwH3SysCtrlState sysctrl;
> GICState gic;
> MemoryRegion sram_a1;
> MemoryRegion sram_a2;
> diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h
> new file mode 100644
> index 0000000000..af4119e026
> --- /dev/null
> +++ b/include/hw/misc/allwinner-h3-sysctrl.h
> @@ -0,0 +1,67 @@
> +/*
> + * Allwinner H3 System Control emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
> +#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
> +
> +#include "qom/object.h"
> +#include "hw/sysbus.h"
> +
> +/**
> + * @name Constants
> + * @{
> + */
> +
> +/** Highest register address used by System Control device */
> +#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
> +
> +/** Total number of known registers */
> +#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
> + sizeof(uint32_t)) + 1)
> +
> +/** @} */
> +
> +/**
> + * @name Object model
> + * @{
> + */
> +
> +#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
> +#define AW_H3_SYSCTRL(obj) \
> + OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
> +
> +/** @} */
> +
> +/**
> + * Allwinner H3 System Control object instance state
> + */
> +typedef struct AwH3SysCtrlState {
> + /*< private >*/
> + SysBusDevice parent_obj;
> + /*< public >*/
> +
> + /** Maps I/O registers in physical memory */
> + MemoryRegion iomem;
> +
> + /** Array of hardware registers */
> + uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
> +
> +} AwH3SysCtrlState;
> +
> +#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> index c205f06738..0aa46712db 100644
> --- a/hw/arm/allwinner-h3.c
> +++ b/hw/arm/allwinner-h3.c
> @@ -37,6 +37,7 @@ const hwaddr allwinner_h3_memmap[] = {
> [AW_H3_SRAM_A1] = 0x00000000,
> [AW_H3_SRAM_A2] = 0x00044000,
> [AW_H3_SRAM_C] = 0x00010000,
> + [AW_H3_SYSCTRL] = 0x01c00000,
> [AW_H3_EHCI0] = 0x01c1a000,
> [AW_H3_OHCI0] = 0x01c1a400,
> [AW_H3_EHCI1] = 0x01c1b000,
> @@ -66,7 +67,6 @@ struct AwH3Unimplemented {
> } unimplemented[] = {
> { "d-engine", 0x01000000, 4 * MiB },
> { "d-inter", 0x01400000, 128 * KiB },
> - { "syscon", 0x01c00000, 4 * KiB },
> { "dma", 0x01c02000, 4 * KiB },
> { "nfdc", 0x01c03000, 4 * KiB },
> { "ts", 0x01c06000, 4 * KiB },
> @@ -192,6 +192,9 @@ static void allwinner_h3_init(Object *obj)
>
> sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
> TYPE_AW_H3_CCU);
> +
> + sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
> + TYPE_AW_H3_SYSCTRL);
> }
>
> static void allwinner_h3_realize(DeviceState *dev, Error **errp)
> @@ -301,6 +304,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
> qdev_init_nofail(DEVICE(&s->ccu));
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
>
> + /* System Control */
> + qdev_init_nofail(DEVICE(&s->sysctrl));
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
> +
> /* Universal Serial Bus */
> sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
> qdev_get_gpio_in(DEVICE(&s->gic),
> diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
> new file mode 100644
> index 0000000000..1d07efa880
> --- /dev/null
> +++ b/hw/misc/allwinner-h3-sysctrl.c
> @@ -0,0 +1,140 @@
> +/*
> + * Allwinner H3 System Control emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "hw/sysbus.h"
> +#include "migration/vmstate.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "hw/misc/allwinner-h3-sysctrl.h"
> +
> +/* System Control register offsets */
> +enum {
> + REG_VER = 0x24, /* Version */
> + REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
> +};
> +
> +#define REG_INDEX(offset) (offset / sizeof(uint32_t))
> +
> +/* System Control register reset values */
> +enum {
> + REG_VER_RST = 0x0,
> + REG_EMAC_PHY_CLK_RST = 0x58000,
> +};
> +
> +static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
> + const uint32_t idx = REG_INDEX(offset);
> +
> + if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
> + __func__, (uint32_t)offset);
> + return 0;
> + }
> +
> + return s->regs[idx];
> +}
> +
> +static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
> + const uint32_t idx = REG_INDEX(offset);
> +
> + if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
> + __func__, (uint32_t)offset);
> + return;
> + }
> +
> + switch (offset) {
> + case REG_VER: /* Version */
> + break;
> + default:
> + s->regs[idx] = (uint32_t) val;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
> + .read = allwinner_h3_sysctrl_read,
> + .write = allwinner_h3_sysctrl_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> + .impl.min_access_size = 4,
> +};
> +
> +static void allwinner_h3_sysctrl_reset(DeviceState *dev)
> +{
> + AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
> +
> + /* Set default values for registers */
> + s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
> + s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
> +}
> +
> +static void allwinner_h3_sysctrl_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
> +
> + /* Memory mapping */
> + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
> + TYPE_AW_H3_SYSCTRL, 4 * KiB);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
> + .name = "allwinner-h3-sysctrl",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->reset = allwinner_h3_sysctrl_reset;
> + dc->vmsd = &allwinner_h3_sysctrl_vmstate;
> +}
> +
> +static const TypeInfo allwinner_h3_sysctrl_info = {
> + .name = TYPE_AW_H3_SYSCTRL,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_init = allwinner_h3_sysctrl_init,
> + .instance_size = sizeof(AwH3SysCtrlState),
> + .class_init = allwinner_h3_sysctrl_class_init,
> +};
> +
> +static void allwinner_h3_sysctrl_register(void)
> +{
> + type_register_static(&allwinner_h3_sysctrl_info);
> +}
> +
> +type_init(allwinner_h3_sysctrl_register)
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index 5e635b74d5..63b2e528f9 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) += macio/
> common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
>
> common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
> +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
> common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
> common-obj-$(CONFIG_NSERIES) += cbus.o
> common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module
2020-03-01 21:50 ` [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module Niek Linnenbank
@ 2020-03-03 12:09 ` Alex Bennée
2020-03-03 20:15 ` Niek Linnenbank
0 siblings, 1 reply; 42+ messages in thread
From: Alex Bennée @ 2020-03-03 12:09 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> Various Allwinner System on Chip designs contain multiple processors
> that can be configured and reset using the generic CPU Configuration
> module interface. This commit adds support for the Allwinner CPU
> configuration interface which emulates the following features:
>
> * CPU reset
> * CPU status
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
<snip>
> +
> +/* CPUCFG constants */
> +enum {
> + CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
> +};
> +
> +static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
> +{
> + int ret;
> +
> + trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
> +
> + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
> + CPU_EXCEPTION_LEVEL_ON_RESET, false);
According to the arm_set_cpu_on code:
if (!target_aa64 && arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64)) {
/*
* For now we don't support booting an AArch64 CPU in AArch32 mode
* TODO: We should add this support later
*/
qemu_log_mask(LOG_UNIMP,
"[ARM]%s: Starting AArch64 CPU %" PRId64
" in AArch32 mode is not supported yet\n",
__func__, cpuid);
return QEMU_ARM_POWERCTL_INVALID_PARAM;
}
Do you really want to reboot in aarch32 mode on a reset? If so we should
fix the TODO.
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 08/18] hw/arm/allwinner: add SD/MMC host controller
2020-03-01 21:50 ` [PATCH v6 08/18] hw/arm/allwinner: add SD/MMC host controller Niek Linnenbank
@ 2020-03-03 12:34 ` Alex Bennée
0 siblings, 0 replies; 42+ messages in thread
From: Alex Bennée @ 2020-03-03 12:34 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> The Allwinner System on Chip families sun4i and above contain
> an integrated storage controller for Secure Digital (SD) and
> Multi Media Card (MMC) interfaces. This commit adds support
> for the Allwinner SD/MMC storage controller with the following
> emulated features:
>
> * DMA transfers
> * Direct FIFO I/O
> * Short/Long format command responses
> * Auto-Stop command (CMD12)
> * Insert & remove card detection
>
> The following boards are extended with the SD host controller:
>
> * Cubieboard (hw/arm/cubieboard.c)
> * Orange Pi PC (hw/arm/orangepi.c)
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module
2020-03-03 12:09 ` Alex Bennée
@ 2020-03-03 20:15 ` Niek Linnenbank
2020-03-09 11:18 ` Peter Maydell
0 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-03 20:15 UTC (permalink / raw)
To: Alex Bennée
Cc: Peter Maydell, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 3194 bytes --]
Hi Alex,
First thanks for all your reviews, I'll add the tags in the next version of
this series.
On Tue, Mar 3, 2020 at 1:09 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
>
> > Various Allwinner System on Chip designs contain multiple processors
> > that can be configured and reset using the generic CPU Configuration
> > module interface. This commit adds support for the Allwinner CPU
> > configuration interface which emulates the following features:
> >
> > * CPU reset
> > * CPU status
> >
> > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> <snip>
> > +
> > +/* CPUCFG constants */
> > +enum {
> > + CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
> > +};
> > +
> > +static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
> > +{
> > + int ret;
> > +
> > + trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
> > +
> > + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
> > + CPU_EXCEPTION_LEVEL_ON_RESET, false);
>
> According to the arm_set_cpu_on code:
>
> if (!target_aa64 && arm_feature(&target_cpu->env,
> ARM_FEATURE_AARCH64)) {
> /*
> * For now we don't support booting an AArch64 CPU in AArch32 mode
> * TODO: We should add this support later
> */
> qemu_log_mask(LOG_UNIMP,
> "[ARM]%s: Starting AArch64 CPU %" PRId64
> " in AArch32 mode is not supported yet\n",
> __func__, cpuid);
> return QEMU_ARM_POWERCTL_INVALID_PARAM;
> }
>
> Do you really want to reboot in aarch32 mode on a reset? If so we should
> fix the TODO.
>
Very good remark, I'll try to clarify what I did here. In earlier version
of this series, I made this CPU Configuration Module specific
to the Allwinner H3 SoC, as I thought it was a SoC specific component.
Later I discovered that the CPU Configuration Module is
actually a generic Allwinner component and used in multiple SoCs. Taking
that into account, I renamed it to allwinner-cpucfg.c and
updated the comments/docs. That way it should be re-usable in future SoC
modules.
The Allwinner H3 has four ARM Cortex-A7 cores and are 32-bit, so in the
early version I filled the @target_aa64 parameter with false to
keep it in 32-bit mode. And for usage in the current Allwinner H3 SoC that
is sufficient, but as soon as a potential new SoC implementation
with a 64-bit CPU starts to use this module, the hardcoded @target_aa64
parameter will become a problem.
And the TODO inside the arm_set_cpu_on() function I was not yet aware of as
well, so that will also need to be resolved
indeed once this module is going to be used for a new SoC with a 64-bit CPU.
Maybe I should just use some function to check if the current emulated CPU
its 32-bit or 64-bit and use that for @target_aa64?
That way the CPU Configuration Module itself should be ready for 64-bit and
the TODO for arm_set_cpu_on() can be
resolved in a later series for newer SoCs.
Regards,
Niek
>
> --
> Alex Bennée
>
--
Niek Linnenbank
[-- Attachment #2: Type: text/html, Size: 4438 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-01 21:50 ` [PATCH v6 18/18] docs: add Orange Pi PC document Niek Linnenbank
@ 2020-03-04 10:35 ` Alex Bennée
2020-03-04 20:55 ` Niek Linnenbank
0 siblings, 1 reply; 42+ messages in thread
From: Alex Bennée @ 2020-03-04 10:35 UTC (permalink / raw)
To: Niek Linnenbank
Cc: peter.maydell, jasowang, qemu-devel, b.galvani, qemu-arm,
imammedo, philmd
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> The Xunlong Orange Pi PC machine is a functional ARM machine
> based on the Allwinner H3 System-on-Chip. It supports mainline
> Linux, U-Boot, NetBSD and is covered by acceptance tests.
>
> This commit adds a documentation text file with a description
> of the machine and instructions for the user.
This is great, thanks for taking the time to include documentation.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
> docs/orangepi.rst | 226
> ++++++++++++++++++++++++++++++++++++++++++++++
I suspect there is a better place to put this is than the top level. I
wonder if it should be docs/specs?
> MAINTAINERS | 1 +
> 2 files changed, 227 insertions(+)
> create mode 100644 docs/orangepi.rst
>
> diff --git a/docs/orangepi.rst b/docs/orangepi.rst
> new file mode 100644
> index 0000000000..a9b46f553c
> --- /dev/null
> +++ b/docs/orangepi.rst
> @@ -0,0 +1,226 @@
> +=========================
> +Orange Pi PC Machine Type
> +=========================
> +
> +The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> +based embedded computer with mainline support in both U-Boot
> +and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
> +1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
> +various other I/O.
When Peter's document PR goes in later this week there will also be a:
docs/system/target-arm.rst
which would benefit from a section for the Orange Pi in it.
> +
> +Supported devices
> +-----------------
> +
> +The Orange Pi PC machine supports the following devices:
> +
> + * SMP (Quad Core Cortex A7)
> + * Generic Interrupt Controller configuration
> + * SRAM mappings
> + * SDRAM controller
> + * Real Time Clock
> + * Timer device (re-used from Allwinner A10)
> + * UART
> + * SD/MMC storage controller
> + * EMAC ethernet
Do we ever exercise the ethernet in the acceptance tests? I see we have
some that boots a full OS but boot console only seems to touch the
serial console.
<snip>
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-04 10:35 ` Alex Bennée
@ 2020-03-04 20:55 ` Niek Linnenbank
2020-03-09 11:21 ` Peter Maydell
2020-03-09 19:35 ` Niek Linnenbank
0 siblings, 2 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-04 20:55 UTC (permalink / raw)
To: Alex Bennée
Cc: Peter Maydell, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 3390 bytes --]
Hello Alex,
On Wed, Mar 4, 2020 at 11:35 AM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
>
> > The Xunlong Orange Pi PC machine is a functional ARM machine
> > based on the Allwinner H3 System-on-Chip. It supports mainline
> > Linux, U-Boot, NetBSD and is covered by acceptance tests.
> >
> > This commit adds a documentation text file with a description
> > of the machine and instructions for the user.
>
> This is great, thanks for taking the time to include documentation.
>
Sure, I'm happy to contribute it. I tried to include most relevant
information
in there for developers and potential users of the machine. If something is
missing
just let me know and I'll make an update for it.
>
> >
> > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> > ---
> > docs/orangepi.rst | 226
> > ++++++++++++++++++++++++++++++++++++++++++++++
>
> I suspect there is a better place to put this is than the top level. I
> wonder if it should be docs/specs?
>
Yeah I'm fine to move it to a different subdirectory if needed. Right now
its placed in docs,
as it seems that documents for machines are also placed there, for example
docs/microvm.rst
>
> > MAINTAINERS | 1 +
> > 2 files changed, 227 insertions(+)
> > create mode 100644 docs/orangepi.rst
> >
> > diff --git a/docs/orangepi.rst b/docs/orangepi.rst
> > new file mode 100644
> > index 0000000000..a9b46f553c
> > --- /dev/null
> > +++ b/docs/orangepi.rst
> > @@ -0,0 +1,226 @@
> > +=========================
> > +Orange Pi PC Machine Type
> > +=========================
> > +
> > +The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> > +based embedded computer with mainline support in both U-Boot
> > +and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
> > +1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
> > +various other I/O.
>
> When Peter's document PR goes in later this week there will also be a:
>
> docs/system/target-arm.rst
>
> which would benefit from a section for the Orange Pi in it.
>
Nice, I'll have a look at it when it gets merged and add a section for
Orange Pi.
I'll try to include that in the next version of this series.
>
> > +
> > +Supported devices
> > +-----------------
> > +
> > +The Orange Pi PC machine supports the following devices:
> > +
> > + * SMP (Quad Core Cortex A7)
> > + * Generic Interrupt Controller configuration
> > + * SRAM mappings
> > + * SDRAM controller
> > + * Real Time Clock
> > + * Timer device (re-used from Allwinner A10)
> > + * UART
> > + * SD/MMC storage controller
> > + * EMAC ethernet
>
> Do we ever exercise the ethernet in the acceptance tests? I see we have
> some that boots a full OS but boot console only seems to touch the
> serial console.
>
Good point. Currently in the acceptance tests U-Boot and Linux detect
the ethernet device, but there are no explicit checks for that in the
acceptance tests
nor any actual packet transmission.
I'll try to extend the current tests in the next version of this series to
include some
basic checks for the ethernet device, perhaps with DHCP or a ping.
I'm open to suggestions for the preferred way to do this.
Regards,
Niek
>
> <snip>
>
> --
> Alex Bennée
>
--
Niek Linnenbank
[-- Attachment #2: Type: text/html, Size: 5099 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module
2020-03-03 20:15 ` Niek Linnenbank
@ 2020-03-09 11:18 ` Peter Maydell
2020-03-10 19:30 ` Niek Linnenbank
0 siblings, 1 reply; 42+ messages in thread
From: Peter Maydell @ 2020-03-09 11:18 UTC (permalink / raw)
To: Niek Linnenbank
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
On Tue, 3 Mar 2020 at 20:15, Niek Linnenbank <nieklinnenbank@gmail.com> wrote:
> On Tue, Mar 3, 2020 at 1:09 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
>> > +static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
>> > +{
>> > + int ret;
>> > +
>> > + trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
>> > +
>> > + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
>> > + CPU_EXCEPTION_LEVEL_ON_RESET, false);
>>
>> According to the arm_set_cpu_on code:
>>
>> if (!target_aa64 && arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64)) {
>> /*
>> * For now we don't support booting an AArch64 CPU in AArch32 mode
>> * TODO: We should add this support later
>> */
>> qemu_log_mask(LOG_UNIMP,
>> "[ARM]%s: Starting AArch64 CPU %" PRId64
>> " in AArch32 mode is not supported yet\n",
>> __func__, cpuid);
>> return QEMU_ARM_POWERCTL_INVALID_PARAM;
>> }
>>
>> Do you really want to reboot in aarch32 mode on a reset? If so we should
>> fix the TODO.
>
> The Allwinner H3 has four ARM Cortex-A7 cores and are 32-bit, so in the
> early version I filled the @target_aa64 parameter with false to
> keep it in 32-bit mode. And for usage in the current Allwinner H3 SoC
> that is sufficient, but as soon as a potential new SoC implementation
> with a 64-bit CPU starts to use this module, the hardcoded @target_aa64
> parameter will become a problem.
> Maybe I should just use some function to check if the current emulated
> CPU its 32-bit or 64-bit and use that for @target_aa64?
If the intended behaviour is "just power on the CPU into EL3
in the aarch32/aarch64 state it would naturally have out of reset"
then you can get the right value to pass to target_aa64 like this:
ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id));
if (!target_cpu) {
/*
* handle the case of "guest wrote bogus value to RST_CTRL
* field, probably by returning doing nothing
*/
}
target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64);
Or if the required behaviour for a 64-bit CPU is more complicated
you can just assert or something with a comment that this would need
updating if we ever modelled a 64-bit Allwinner SoC.
thanks
-- PMM
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-04 20:55 ` Niek Linnenbank
@ 2020-03-09 11:21 ` Peter Maydell
2020-03-09 19:38 ` Niek Linnenbank
2020-03-09 19:35 ` Niek Linnenbank
1 sibling, 1 reply; 42+ messages in thread
From: Peter Maydell @ 2020-03-09 11:21 UTC (permalink / raw)
To: Niek Linnenbank
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
On Wed, 4 Mar 2020 at 20:55, Niek Linnenbank <nieklinnenbank@gmail.com> wrote:
>
> Hello Alex,
>
> On Wed, Mar 4, 2020 at 11:35 AM Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>>
>> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
>> > ---
>> > docs/orangepi.rst | 226
>> > ++++++++++++++++++++++++++++++++++++++++++++++
>>
>> I suspect there is a better place to put this is than the top level. I
>> wonder if it should be docs/specs?
>
>
> Yeah I'm fine to move it to a different subdirectory if needed. Right now its placed in docs,
> as it seems that documents for machines are also placed there, for example docs/microvm.rst
The only things in the top level docs/ are a handful of
legacy-ish files that went there because we didn't yet have
a better place to put them. We should avoid increasing the
number of orphan files in the top level (and indeed should
try to move the existing orphans elsewhere).
>> When Peter's document PR goes in later this week there will also be a:
>>
>> docs/system/target-arm.rst
>>
>> which would benefit from a section for the Orange Pi in it.
Yes, this is now the right place to put arm board-specific
documentation (the rearranging and conversion from texinfo
is now in master). I should move microvm.rst's contents there
I guess.
thanks
-- PMM
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-04 20:55 ` Niek Linnenbank
2020-03-09 11:21 ` Peter Maydell
@ 2020-03-09 19:35 ` Niek Linnenbank
2020-03-10 8:15 ` Alex Bennée
1 sibling, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-09 19:35 UTC (permalink / raw)
To: Alex Bennée
Cc: Peter Maydell, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 4207 bytes --]
Hi Alex,
On Wed, Mar 4, 2020 at 9:55 PM Niek Linnenbank <nieklinnenbank@gmail.com>
wrote:
> Hello Alex,
>
> On Wed, Mar 4, 2020 at 11:35 AM Alex Bennée <alex.bennee@linaro.org>
> wrote:
>
>>
>> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
>>
>> > The Xunlong Orange Pi PC machine is a functional ARM machine
>> > based on the Allwinner H3 System-on-Chip. It supports mainline
>> > Linux, U-Boot, NetBSD and is covered by acceptance tests.
>> >
>> > This commit adds a documentation text file with a description
>> > of the machine and instructions for the user.
>>
>> This is great, thanks for taking the time to include documentation.
>>
>
> Sure, I'm happy to contribute it. I tried to include most relevant
> information
> in there for developers and potential users of the machine. If something
> is missing
> just let me know and I'll make an update for it.
>
>
>>
>> >
>> > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
>> > ---
>> > docs/orangepi.rst | 226
>> > ++++++++++++++++++++++++++++++++++++++++++++++
>>
>> I suspect there is a better place to put this is than the top level. I
>> wonder if it should be docs/specs?
>>
>
> Yeah I'm fine to move it to a different subdirectory if needed. Right now
> its placed in docs,
> as it seems that documents for machines are also placed there, for example
> docs/microvm.rst
>
>
>>
>> > MAINTAINERS | 1 +
>> > 2 files changed, 227 insertions(+)
>> > create mode 100644 docs/orangepi.rst
>> >
>> > diff --git a/docs/orangepi.rst b/docs/orangepi.rst
>> > new file mode 100644
>> > index 0000000000..a9b46f553c
>> > --- /dev/null
>> > +++ b/docs/orangepi.rst
>> > @@ -0,0 +1,226 @@
>> > +=========================
>> > +Orange Pi PC Machine Type
>> > +=========================
>> > +
>> > +The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
>> > +based embedded computer with mainline support in both U-Boot
>> > +and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
>> > +1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
>> > +various other I/O.
>>
>> When Peter's document PR goes in later this week there will also be a:
>>
>> docs/system/target-arm.rst
>>
>> which would benefit from a section for the Orange Pi in it.
>>
>
> Nice, I'll have a look at it when it gets merged and add a section for
> Orange Pi.
> I'll try to include that in the next version of this series.
>
>
>>
>> > +
>> > +Supported devices
>> > +-----------------
>> > +
>> > +The Orange Pi PC machine supports the following devices:
>> > +
>> > + * SMP (Quad Core Cortex A7)
>> > + * Generic Interrupt Controller configuration
>> > + * SRAM mappings
>> > + * SDRAM controller
>> > + * Real Time Clock
>> > + * Timer device (re-used from Allwinner A10)
>> > + * UART
>> > + * SD/MMC storage controller
>> > + * EMAC ethernet
>>
>> Do we ever exercise the ethernet in the acceptance tests? I see we have
>> some that boots a full OS but boot console only seems to touch the
>> serial console.
>>
>
> Good point. Currently in the acceptance tests U-Boot and Linux detect
> the ethernet device, but there are no explicit checks for that in the
> acceptance tests
> nor any actual packet transmission.
>
> I'll try to extend the current tests in the next version of this series to
> include some
> basic checks for the ethernet device, perhaps with DHCP or a ping.
> I'm open to suggestions for the preferred way to do this.
>
FYI, I added some coverage for the ethernet device by extending the
test_arm_orangepi_sd test with a few lines like:
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up', 'eth0:
Link is Up')
+ exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
+ 'udhcpc: lease of
10.0.2.15 obtained')
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
+ '3 packets transmitted, 3 packets received, 0% packet loss')
Regards,
Niek
> Regards,
> Niek
>
>
>
>
>
>
>>
>> <snip>
>>
>> --
>> Alex Bennée
>>
>
>
> --
> Niek Linnenbank
>
>
--
Niek Linnenbank
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 11:21 ` Peter Maydell
@ 2020-03-09 19:38 ` Niek Linnenbank
2020-03-09 19:42 ` Peter Maydell
0 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-09 19:38 UTC (permalink / raw)
To: Peter Maydell
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 1728 bytes --]
Hi Peter,
On Mon, Mar 9, 2020 at 12:22 PM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Wed, 4 Mar 2020 at 20:55, Niek Linnenbank <nieklinnenbank@gmail.com>
> wrote:
> >
> > Hello Alex,
> >
> > On Wed, Mar 4, 2020 at 11:35 AM Alex Bennée <alex.bennee@linaro.org>
> wrote:
> >>
> >>
> >> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> >> > ---
> >> > docs/orangepi.rst | 226
> >> > ++++++++++++++++++++++++++++++++++++++++++++++
> >>
> >> I suspect there is a better place to put this is than the top level. I
> >> wonder if it should be docs/specs?
> >
> >
> > Yeah I'm fine to move it to a different subdirectory if needed. Right
> now its placed in docs,
> > as it seems that documents for machines are also placed there, for
> example docs/microvm.rst
>
> The only things in the top level docs/ are a handful of
> legacy-ish files that went there because we didn't yet have
> a better place to put them. We should avoid increasing the
> number of orphan files in the top level (and indeed should
> try to move the existing orphans elsewhere).
>
> >> When Peter's document PR goes in later this week there will also be a:
> >>
> >> docs/system/target-arm.rst
> >>
> >> which would benefit from a section for the Orange Pi in it.
>
> Yes, this is now the right place to put arm board-specific
> documentation (the rearranging and conversion from texinfo
> is now in master). I should move microvm.rst's contents there
> I guess.
>
OK, I'll move orangepi.rst to docs/system/orangepi.rst and add a short
section
about the Orange Pi PC machine to docs/system/target-arm.rst as well.
Regards,
Niek
>
> thanks
> -- PMM
>
--
Niek Linnenbank
[-- Attachment #2: Type: text/html, Size: 2778 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 19:38 ` Niek Linnenbank
@ 2020-03-09 19:42 ` Peter Maydell
2020-03-09 20:05 ` Niek Linnenbank
0 siblings, 1 reply; 42+ messages in thread
From: Peter Maydell @ 2020-03-09 19:42 UTC (permalink / raw)
To: Niek Linnenbank
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
On Mon, 9 Mar 2020 at 19:38, Niek Linnenbank <nieklinnenbank@gmail.com> wrote:
> On Mon, Mar 9, 2020 at 12:22 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>> Yes, this is now the right place to put arm board-specific
>> documentation (the rearranging and conversion from texinfo
>> is now in master). I should move microvm.rst's contents there
>> I guess.
>
>
> OK, I'll move orangepi.rst to docs/system/orangepi.rst and add a short section
> about the Orange Pi PC machine to docs/system/target-arm.rst as well.
You should include/reference the orangepi.rst from target-arm.rst, I think --
that's where the per-board docs would belong in the structure we have.
If you just drop a .rst file into the docs directory somewhere it won't
actually go into the documentation and instead Sphinx will error
out about it not being in the table of contents anywhere.
(I'll have a look at microvm.rst to see how best to make the structure
work -- at the moment it kind of assumes there board documentation
is always quite short so they're all in one file.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 19:42 ` Peter Maydell
@ 2020-03-09 20:05 ` Niek Linnenbank
2020-03-09 20:12 ` Peter Maydell
0 siblings, 1 reply; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-09 20:05 UTC (permalink / raw)
To: Peter Maydell
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 1859 bytes --]
On Mon, Mar 9, 2020 at 8:43 PM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Mon, 9 Mar 2020 at 19:38, Niek Linnenbank <nieklinnenbank@gmail.com>
> wrote:
> > On Mon, Mar 9, 2020 at 12:22 PM Peter Maydell <peter.maydell@linaro.org>
> wrote:
> >> Yes, this is now the right place to put arm board-specific
> >> documentation (the rearranging and conversion from texinfo
> >> is now in master). I should move microvm.rst's contents there
> >> I guess.
> >
> >
> > OK, I'll move orangepi.rst to docs/system/orangepi.rst and add a short
> section
> > about the Orange Pi PC machine to docs/system/target-arm.rst as well.
>
> You should include/reference the orangepi.rst from target-arm.rst, I think
> --
> that's where the per-board docs would belong in the structure we have.
> If you just drop a .rst file into the docs directory somewhere it won't
> actually go into the documentation and instead Sphinx will error
> out about it not being in the table of contents anywhere.
>
Ah now I see what is going on here. So the new rst files are ment to
automatically generate
documentation in various formats using the Python sphinx tool, correct?
I played around a bit with running 'make html' and using the include
directive you suggested in
the target-arm.rst file like:
.. include:: orangepi.rst
That seems to work. And, now I also see that the orangepi.rst file contains
rst syntax errors which
I need to resolve. I'll make sure those are resolved in the next version.
>
> (I'll have a look at microvm.rst to see how best to make the structure
> work -- at the moment it kind of assumes there board documentation
> is always quite short so they're all in one file.)
>
Yeah that is fine Peter. If you have any update on that later, I'll adjust
the orangepi.rst file to fit in as well.
Regards,
Niek
>
> thanks
> -- PMM
>
--
Niek Linnenbank
[-- Attachment #2: Type: text/html, Size: 3017 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 20:05 ` Niek Linnenbank
@ 2020-03-09 20:12 ` Peter Maydell
2020-03-09 20:47 ` Niek Linnenbank
2020-03-09 22:01 ` Peter Maydell
0 siblings, 2 replies; 42+ messages in thread
From: Peter Maydell @ 2020-03-09 20:12 UTC (permalink / raw)
To: Niek Linnenbank
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
On Mon, 9 Mar 2020 at 20:05, Niek Linnenbank <nieklinnenbank@gmail.com> wrote:
> Ah now I see what is going on here. So the new rst files are ment to automatically generate
> documentation in various formats using the Python sphinx tool, correct?
Yep. Assuming you have Sphinx installed, "make" should build the
documentation as well as the executables (ie you don't need
specifically 'make html').
> I played around a bit with running 'make html' and using the include directive you suggested in
> the target-arm.rst file like:
>
> .. include:: orangepi.rst
I'm currently writing a patchset which splits the existing
target-arm.rst into a bunch of per-board files in
docs/system/arm/. If that patchset goes in before you
roll the next verison of the series then it should
just be a matter of putting orangepi.rst in the
docs/system/arm/ directory and adding a line to the
table-of-contents in docs/system/target-arm.rst.
If you're ready to send out the next version before that,
then leave it with the include:: directive and we can
fix it up to the new structure later.
thanks
-- PMM
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 20:12 ` Peter Maydell
@ 2020-03-09 20:47 ` Niek Linnenbank
2020-03-09 22:01 ` Peter Maydell
1 sibling, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-09 20:47 UTC (permalink / raw)
To: Peter Maydell
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 1361 bytes --]
On Mon, Mar 9, 2020 at 9:12 PM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Mon, 9 Mar 2020 at 20:05, Niek Linnenbank <nieklinnenbank@gmail.com>
> wrote:
> > Ah now I see what is going on here. So the new rst files are ment to
> automatically generate
> > documentation in various formats using the Python sphinx tool, correct?
>
> Yep. Assuming you have Sphinx installed, "make" should build the
> documentation as well as the executables (ie you don't need
> specifically 'make html').
>
> > I played around a bit with running 'make html' and using the include
> directive you suggested in
> > the target-arm.rst file like:
> >
> > .. include:: orangepi.rst
>
> I'm currently writing a patchset which splits the existing
> target-arm.rst into a bunch of per-board files in
> docs/system/arm/. If that patchset goes in before you
> roll the next verison of the series then it should
> just be a matter of putting orangepi.rst in the
> docs/system/arm/ directory and adding a line to the
> table-of-contents in docs/system/target-arm.rst.
>
Ah yes, that makes sense indeed. I'll keep an eye out for your new patchset.
> If you're ready to send out the next version before that,
> then leave it with the include:: directive and we can
> fix it up to the new structure later.
>
OK Peter!
Regards,
Niek
> thanks
> -- PMM
>
--
Niek Linnenbank
[-- Attachment #2: Type: text/html, Size: 2377 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 20:12 ` Peter Maydell
2020-03-09 20:47 ` Niek Linnenbank
@ 2020-03-09 22:01 ` Peter Maydell
2020-03-10 19:09 ` Niek Linnenbank
1 sibling, 1 reply; 42+ messages in thread
From: Peter Maydell @ 2020-03-09 22:01 UTC (permalink / raw)
To: Niek Linnenbank
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
On Mon, 9 Mar 2020 at 20:12, Peter Maydell <peter.maydell@linaro.org> wrote:
> If you're ready to send out the next version before that,
> then leave it with the include:: directive and we can
> fix it up to the new structure later.
PS: in case you weren't aware, softfreeze for the 5.0 release
is 17th March, so if this series is going to go in for 5.0
then (a) people interested in reviewing it should hurry up
and review patches 9..18 and (b) the final version would
need to be on the list sometime this week so it can go into
a pull request by the 17th.
It's no big deal if it goes into 5.1 instead I guess,
but it feels like the series is nearly ready so I figured
I'd set out the timeline if people want to push to get it
into 5.0.
thanks
-- PMM
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 19:35 ` Niek Linnenbank
@ 2020-03-10 8:15 ` Alex Bennée
2020-03-10 19:10 ` Niek Linnenbank
0 siblings, 1 reply; 42+ messages in thread
From: Alex Bennée @ 2020-03-10 8:15 UTC (permalink / raw)
To: Niek Linnenbank
Cc: Peter Maydell, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> Hi Alex,
>
> On Wed, Mar 4, 2020 at 9:55 PM Niek Linnenbank <nieklinnenbank@gmail.com>
> wrote:
>
>> Hello Alex,
>>
>> On Wed, Mar 4, 2020 at 11:35 AM Alex Bennée <alex.bennee@linaro.org>
>> wrote:
>>
>>>
>>> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
>>>
>>> > The Xunlong Orange Pi PC machine is a functional ARM machine
>>> > based on the Allwinner H3 System-on-Chip. It supports mainline
>>> > Linux, U-Boot, NetBSD and is covered by acceptance tests.
>>> >
>>> > This commit adds a documentation text file with a description
>>> > of the machine and instructions for the user.
>>>
>>> This is great, thanks for taking the time to include documentation.
>>>
>>
>> Sure, I'm happy to contribute it. I tried to include most relevant
>> information
>> in there for developers and potential users of the machine. If something
>> is missing
>> just let me know and I'll make an update for it.
>>
>>
>>>
>>> >
>>> > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
>>> > ---
>>> > docs/orangepi.rst | 226
>>> > ++++++++++++++++++++++++++++++++++++++++++++++
>>>
>>> I suspect there is a better place to put this is than the top level. I
>>> wonder if it should be docs/specs?
>>>
>>
>> Yeah I'm fine to move it to a different subdirectory if needed. Right now
>> its placed in docs,
>> as it seems that documents for machines are also placed there, for example
>> docs/microvm.rst
>>
>>
>>>
>>> > MAINTAINERS | 1 +
>>> > 2 files changed, 227 insertions(+)
>>> > create mode 100644 docs/orangepi.rst
>>> >
>>> > diff --git a/docs/orangepi.rst b/docs/orangepi.rst
>>> > new file mode 100644
>>> > index 0000000000..a9b46f553c
>>> > --- /dev/null
>>> > +++ b/docs/orangepi.rst
>>> > @@ -0,0 +1,226 @@
>>> > +=========================
>>> > +Orange Pi PC Machine Type
>>> > +=========================
>>> > +
>>> > +The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
>>> > +based embedded computer with mainline support in both U-Boot
>>> > +and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
>>> > +1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
>>> > +various other I/O.
>>>
>>> When Peter's document PR goes in later this week there will also be a:
>>>
>>> docs/system/target-arm.rst
>>>
>>> which would benefit from a section for the Orange Pi in it.
>>>
>>
>> Nice, I'll have a look at it when it gets merged and add a section for
>> Orange Pi.
>> I'll try to include that in the next version of this series.
>>
>>
>>>
>>> > +
>>> > +Supported devices
>>> > +-----------------
>>> > +
>>> > +The Orange Pi PC machine supports the following devices:
>>> > +
>>> > + * SMP (Quad Core Cortex A7)
>>> > + * Generic Interrupt Controller configuration
>>> > + * SRAM mappings
>>> > + * SDRAM controller
>>> > + * Real Time Clock
>>> > + * Timer device (re-used from Allwinner A10)
>>> > + * UART
>>> > + * SD/MMC storage controller
>>> > + * EMAC ethernet
>>>
>>> Do we ever exercise the ethernet in the acceptance tests? I see we have
>>> some that boots a full OS but boot console only seems to touch the
>>> serial console.
>>>
>>
>> Good point. Currently in the acceptance tests U-Boot and Linux detect
>> the ethernet device, but there are no explicit checks for that in the
>> acceptance tests
>> nor any actual packet transmission.
>>
>> I'll try to extend the current tests in the next version of this series to
>> include some
>> basic checks for the ethernet device, perhaps with DHCP or a ping.
>> I'm open to suggestions for the preferred way to do this.
>>
>
> FYI, I added some coverage for the ethernet device by extending the
> test_arm_orangepi_sd test with a few lines like:
>
> + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up', 'eth0:
> Link is Up')
> + exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
> + 'udhcpc: lease of
> 10.0.2.15 obtained')
> + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
> + '3 packets transmitted, 3 packets received, 0% packet loss')
>
That will work as a smoke test. Are you going to re-spin this week so we
can get the final reviews done?
> Regards,
> Niek
>
>
>> Regards,
>> Niek
>>
>>
>>
>>
>>
>>
>>>
>>> <snip>
>>>
>>> --
>>> Alex Bennée
>>>
>>
>>
>> --
>> Niek Linnenbank
>>
>>
--
Alex Bennée
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-09 22:01 ` Peter Maydell
@ 2020-03-10 19:09 ` Niek Linnenbank
0 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-10 19:09 UTC (permalink / raw)
To: Peter Maydell
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 1386 bytes --]
Hi Peter,
On Mon, Mar 9, 2020 at 11:01 PM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Mon, 9 Mar 2020 at 20:12, Peter Maydell <peter.maydell@linaro.org>
> wrote:
> > If you're ready to send out the next version before that,
> > then leave it with the include:: directive and we can
> > fix it up to the new structure later.
>
> PS: in case you weren't aware, softfreeze for the 5.0 release
> is 17th March, so if this series is going to go in for 5.0
> then (a) people interested in reviewing it should hurry up
> and review patches 9..18 and (b) the final version would
> need to be on the list sometime this week so it can go into
> a pull request by the 17th.
>
Ah I was not aware of that date indeed! Yes, ofcourse, if we can get the
remaining parts reviewed as well to include it in 5.0, that would be great.
As a side note, I'm basically doing this project in my spare time in the
(late) evenings (Amsterdam timezone),
so I'll make sure to reserve some extra time the coming days so I can reply
and respin fast if needed.
I'm finalizing & testing the v7 update now and will send it out in a few
hours to the list.
Regards,
Niek
>
> It's no big deal if it goes into 5.1 instead I guess,
> but it feels like the series is nearly ready so I figured
> I'd set out the timeline if people want to push to get it
> into 5.0.
>
> thanks
> -- PMM
>
--
Niek Linnenbank
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 18/18] docs: add Orange Pi PC document
2020-03-10 8:15 ` Alex Bennée
@ 2020-03-10 19:10 ` Niek Linnenbank
0 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-10 19:10 UTC (permalink / raw)
To: Alex Bennée
Cc: Peter Maydell, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 5219 bytes --]
On Tue, Mar 10, 2020 at 9:16 AM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
>
> > Hi Alex,
> >
> > On Wed, Mar 4, 2020 at 9:55 PM Niek Linnenbank <nieklinnenbank@gmail.com
> >
> > wrote:
> >
> >> Hello Alex,
> >>
> >> On Wed, Mar 4, 2020 at 11:35 AM Alex Bennée <alex.bennee@linaro.org>
> >> wrote:
> >>
> >>>
> >>> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> >>>
> >>> > The Xunlong Orange Pi PC machine is a functional ARM machine
> >>> > based on the Allwinner H3 System-on-Chip. It supports mainline
> >>> > Linux, U-Boot, NetBSD and is covered by acceptance tests.
> >>> >
> >>> > This commit adds a documentation text file with a description
> >>> > of the machine and instructions for the user.
> >>>
> >>> This is great, thanks for taking the time to include documentation.
> >>>
> >>
> >> Sure, I'm happy to contribute it. I tried to include most relevant
> >> information
> >> in there for developers and potential users of the machine. If something
> >> is missing
> >> just let me know and I'll make an update for it.
> >>
> >>
> >>>
> >>> >
> >>> > Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> >>> > ---
> >>> > docs/orangepi.rst | 226
> >>> > ++++++++++++++++++++++++++++++++++++++++++++++
> >>>
> >>> I suspect there is a better place to put this is than the top level. I
> >>> wonder if it should be docs/specs?
> >>>
> >>
> >> Yeah I'm fine to move it to a different subdirectory if needed. Right
> now
> >> its placed in docs,
> >> as it seems that documents for machines are also placed there, for
> example
> >> docs/microvm.rst
> >>
> >>
> >>>
> >>> > MAINTAINERS | 1 +
> >>> > 2 files changed, 227 insertions(+)
> >>> > create mode 100644 docs/orangepi.rst
> >>> >
> >>> > diff --git a/docs/orangepi.rst b/docs/orangepi.rst
> >>> > new file mode 100644
> >>> > index 0000000000..a9b46f553c
> >>> > --- /dev/null
> >>> > +++ b/docs/orangepi.rst
> >>> > @@ -0,0 +1,226 @@
> >>> > +=========================
> >>> > +Orange Pi PC Machine Type
> >>> > +=========================
> >>> > +
> >>> > +The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> >>> > +based embedded computer with mainline support in both U-Boot
> >>> > +and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
> >>> > +1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
> >>> > +various other I/O.
> >>>
> >>> When Peter's document PR goes in later this week there will also be a:
> >>>
> >>> docs/system/target-arm.rst
> >>>
> >>> which would benefit from a section for the Orange Pi in it.
> >>>
> >>
> >> Nice, I'll have a look at it when it gets merged and add a section for
> >> Orange Pi.
> >> I'll try to include that in the next version of this series.
> >>
> >>
> >>>
> >>> > +
> >>> > +Supported devices
> >>> > +-----------------
> >>> > +
> >>> > +The Orange Pi PC machine supports the following devices:
> >>> > +
> >>> > + * SMP (Quad Core Cortex A7)
> >>> > + * Generic Interrupt Controller configuration
> >>> > + * SRAM mappings
> >>> > + * SDRAM controller
> >>> > + * Real Time Clock
> >>> > + * Timer device (re-used from Allwinner A10)
> >>> > + * UART
> >>> > + * SD/MMC storage controller
> >>> > + * EMAC ethernet
> >>>
> >>> Do we ever exercise the ethernet in the acceptance tests? I see we have
> >>> some that boots a full OS but boot console only seems to touch the
> >>> serial console.
> >>>
> >>
> >> Good point. Currently in the acceptance tests U-Boot and Linux detect
> >> the ethernet device, but there are no explicit checks for that in the
> >> acceptance tests
> >> nor any actual packet transmission.
> >>
> >> I'll try to extend the current tests in the next version of this series
> to
> >> include some
> >> basic checks for the ethernet device, perhaps with DHCP or a ping.
> >> I'm open to suggestions for the preferred way to do this.
> >>
> >
> > FYI, I added some coverage for the ethernet device by extending the
> > test_arm_orangepi_sd test with a few lines like:
> >
> > + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up',
> 'eth0:
> > Link is Up')
> > + exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
> > + 'udhcpc: lease of
> > 10.0.2.15 obtained')
> > + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
> > + '3 packets transmitted, 3 packets received, 0% packet loss')
> >
>
> That will work as a smoke test. Are you going to re-spin this week so we
> can get the final reviews done?
>
OK Alex!
Yes, as I just replied to Peter as well, I'm finalizing / testing the v7
update now and will send it to the list in a few hours.
I'll reserve some extra time the coming days so I can reply & respin
quickly.
Regards,
Niek
>
> > Regards,
> > Niek
> >
> >
> >> Regards,
> >> Niek
> >>
> >>
> >>
> >>
> >>
> >>
> >>>
> >>> <snip>
> >>>
> >>> --
> >>> Alex Bennée
> >>>
> >>
> >>
> >> --
> >> Niek Linnenbank
> >>
> >>
>
>
> --
> Alex Bennée
>
--
Niek Linnenbank
[-- Attachment #2: Type: text/html, Size: 7828 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module
2020-03-09 11:18 ` Peter Maydell
@ 2020-03-10 19:30 ` Niek Linnenbank
0 siblings, 0 replies; 42+ messages in thread
From: Niek Linnenbank @ 2020-03-10 19:30 UTC (permalink / raw)
To: Peter Maydell
Cc: Alex Bennée, Jason Wang, QEMU Developers, Beniamino Galvani,
qemu-arm, Igor Mammedov, Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 2827 bytes --]
On Mon, Mar 9, 2020 at 12:18 PM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Tue, 3 Mar 2020 at 20:15, Niek Linnenbank <nieklinnenbank@gmail.com>
> wrote:
> > On Tue, Mar 3, 2020 at 1:09 PM Alex Bennée <alex.bennee@linaro.org>
> wrote:
> >> Niek Linnenbank <nieklinnenbank@gmail.com> writes:
> >> > +static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t
> cpu_id)
> >> > +{
> >> > + int ret;
> >> > +
> >> > + trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
> >> > +
> >> > + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
> >> > + CPU_EXCEPTION_LEVEL_ON_RESET, false);
> >>
> >> According to the arm_set_cpu_on code:
> >>
> >> if (!target_aa64 && arm_feature(&target_cpu->env,
> ARM_FEATURE_AARCH64)) {
> >> /*
> >> * For now we don't support booting an AArch64 CPU in AArch32
> mode
> >> * TODO: We should add this support later
> >> */
> >> qemu_log_mask(LOG_UNIMP,
> >> "[ARM]%s: Starting AArch64 CPU %" PRId64
> >> " in AArch32 mode is not supported yet\n",
> >> __func__, cpuid);
> >> return QEMU_ARM_POWERCTL_INVALID_PARAM;
> >> }
> >>
> >> Do you really want to reboot in aarch32 mode on a reset? If so we should
> >> fix the TODO.
> >
> > The Allwinner H3 has four ARM Cortex-A7 cores and are 32-bit, so in the
> > early version I filled the @target_aa64 parameter with false to
> > keep it in 32-bit mode. And for usage in the current Allwinner H3 SoC
> > that is sufficient, but as soon as a potential new SoC implementation
> > with a 64-bit CPU starts to use this module, the hardcoded @target_aa64
> > parameter will become a problem.
>
> > Maybe I should just use some function to check if the current emulated
> > CPU its 32-bit or 64-bit and use that for @target_aa64?
>
> If the intended behaviour is "just power on the CPU into EL3
> in the aarch32/aarch64 state it would naturally have out of reset"
> then you can get the right value to pass to target_aa64 like this:
>
> ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id));
>
> if (!target_cpu) {
> /*
> * handle the case of "guest wrote bogus value to RST_CTRL
> * field, probably by returning doing nothing
> */
> }
> target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64);
>
>
Thanks for explaining Peter. This solution is working fine. I'm including
it in the v7 respin.
Regards,
Niek
> Or if the required behaviour for a 64-bit CPU is more complicated
> you can just assert or something with a comment that this would need
> updating if we ever modelled a 64-bit Allwinner SoC.
>
> thanks
> -- PMM
>
--
Niek Linnenbank
[-- Attachment #2: Type: text/html, Size: 4138 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2020-03-10 19:31 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-01 21:50 [PATCH v6 00/18] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 01/18] hw/arm: add Allwinner H3 System-on-Chip Niek Linnenbank
2020-03-03 10:53 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 02/18] hw/arm: add Xunlong Orange Pi PC machine Niek Linnenbank
2020-03-03 11:02 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 03/18] hw/arm/allwinner-h3: add Clock Control Unit Niek Linnenbank
2020-03-03 11:10 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 04/18] hw/arm/allwinner-h3: add USB host controller Niek Linnenbank
2020-03-03 11:11 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 05/18] hw/arm/allwinner-h3: add System Control module Niek Linnenbank
2020-03-03 12:01 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 06/18] hw/arm/allwinner: add CPU Configuration module Niek Linnenbank
2020-03-03 12:09 ` Alex Bennée
2020-03-03 20:15 ` Niek Linnenbank
2020-03-09 11:18 ` Peter Maydell
2020-03-10 19:30 ` Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 07/18] hw/arm/allwinner: add Security Identifier device Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 08/18] hw/arm/allwinner: add SD/MMC host controller Niek Linnenbank
2020-03-03 12:34 ` Alex Bennée
2020-03-01 21:50 ` [PATCH v6 09/18] hw/arm/allwinner-h3: add EMAC ethernet device Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 10/18] hw/arm/allwinner-h3: add Boot ROM support Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 11/18] hw/arm/allwinner-h3: add SDRAM controller device Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 12/18] hw/arm/allwinner: add RTC device support Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 13/18] tests/boot_linux_console: Add a quick test for the OrangePi PC board Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 14/18] tests/boot_linux_console: Add initrd test for the Orange Pi " Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 15/18] tests/boot_linux_console: Add a SD card test for the OrangePi " Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 16/18] tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 17/18] tests/boot_linux_console: Test booting NetBSD via U-Boot " Niek Linnenbank
2020-03-01 21:50 ` [PATCH v6 18/18] docs: add Orange Pi PC document Niek Linnenbank
2020-03-04 10:35 ` Alex Bennée
2020-03-04 20:55 ` Niek Linnenbank
2020-03-09 11:21 ` Peter Maydell
2020-03-09 19:38 ` Niek Linnenbank
2020-03-09 19:42 ` Peter Maydell
2020-03-09 20:05 ` Niek Linnenbank
2020-03-09 20:12 ` Peter Maydell
2020-03-09 20:47 ` Niek Linnenbank
2020-03-09 22:01 ` Peter Maydell
2020-03-10 19:09 ` Niek Linnenbank
2020-03-09 19:35 ` Niek Linnenbank
2020-03-10 8:15 ` Alex Bennée
2020-03-10 19:10 ` Niek Linnenbank
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