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* [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries
@ 2020-03-02  9:19 Peter Seiderer
  2020-03-02  9:19 ` [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags Peter Seiderer
  2020-03-02 10:17 ` [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries Peter Seiderer
  0 siblings, 2 replies; 6+ messages in thread
From: Peter Seiderer @ 2020-03-02  9:19 UTC (permalink / raw)
  To: buildroot

Add BR2_GCC_TARGET_ARCH entries, determined by (gcc-9.2.0)
	$ ./host/bin/arm-buildroot-linux-gnueabihf-gcc -Q -mcpu=$(BR2_GCC_TARGET_CPU) --help=target | grep march

Or (for cortex-m3/cortex-m4/cortex-m7):
	$ ./host/bin/arm-buildroot-linux-gnueabihf-gcc -Q -mcpu=$(BR2_GCC_TARGET_CPU) -mthumb --help=target | grep march

Or (where indicated):
	$ ./host/bin/arm-buildroot-linux-gnueabihf-gcc -Q -mcpu=$(BR2_GCC_TARGET_CPU) -msoft-float --help=target | grep march

The soft/hard float flags could be determined from
the arch/Config.in.arm processor definitions or the given
isa_bit_... flags from build/host-gcc-final-9.2.0/build/gcc/arm-cpu-cdata.h.

Signed-off-by: Peter Seiderer <ps.report@gmx.net>
---
Notes:
  - Fix ToDo's for unknown cpus
  - Add BR2_GCC_TARGET_ARCH for other archs?

Changes v1 -> v2:
  - new patch
---
 arch/Config.in.arm | 72 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index 4c0910e4f8..24f550287d 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -898,6 +898,78 @@ config BR2_GCC_TARGET_CPU
 	# armv8.4a
 	default "saphira"	if BR2_saphira
 
+config BR2_GCC_TARGET_ARCH
+	# armv4
+	default "armv4t"		if BR2_arm920t
+	default "armv4t"		if BR2_arm922t
+	default "armv4"			if BR2_fa526
+	default "armv4"			if BR2_strongarm
+	# armv5
+	default "armv5tej+fp"		if BR2_arm926t
+	default "iwmmxt"		if BR2_iwmmxt
+	default "armv5te"		if BR2_xscale # -msoft-float
+	# armv6
+	default "armv6j"		if BR2_arm1136j_s # -msoft-float
+	default "armv6j+fp"		if BR2_arm1136jf_s
+	default "armv6kz"		if BR2_arm1176jz_s # -msoft-float
+	default "armv6kz+fp"		if BR2_arm1176jzf_s
+	default "armv6k+fp"		if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
+	default "armv6k"		if BR2_arm11mpcore # -msoft-float
+	# armv7a
+	default "armv7-a+mp+sec+fp"	if BR2_cortex_a5
+	default "armv7ve+vfpv3-d16"	if BR2_cortex_a7
+	default "armv7-a+sec+fp"	if BR2_cortex_a8
+	default "armv7-a+mp+sec+fp"	if BR2_cortex_a9
+	default "armv7ve+vfpv3-d16"	if BR2_cortex_a12
+	default "armv7ve+vfpv3-d16"	if BR2_cortex_a15
+	default "armv7ve+vfpv3-d16"	if BR2_cortex_a15_a7
+	default "armv7ve+vfpv3-d16"	if BR2_cortex_a17
+	default "armv7ve+vfpv3-d16"	if BR2_cortex_a17_a7
+	default "armv7-a+mp+sec+fp"	if BR2_pj4
+	# armv7m
+	default "armv7-m"		if BR2_cortex_m3
+	default "armv7e-m+fp.dp"	if BR2_cortex_m4
+	default "armv7e-m+fp.dp"	if BR2_cortex_m7
+	# armv8a
+	default "armv8-a+crc+simd"	if BR2_cortex_a32
+	default "armv8-a+crc+simd"	if BR2_cortex_a35
+	default "armv8-a+crc+simd"	if BR2_cortex_a53
+	default "armv8-a+crc+simd"	if BR2_cortex_a57
+	default "armv8-a+crc+simd"	if BR2_cortex_a57_a53
+	default "armv8-a+crc+simd"	if BR2_cortex_a72
+	default "armv8-a+crc+simd"	if BR2_cortex_a72_a53
+	default "armv8-a+crc+simd"	if BR2_cortex_a73
+	default "armv8-a+crc+simd"	if BR2_cortex_a73_a35
+	default "armv8-a+crc+simd"	if BR2_cortex_a73_a53
+	default "armv8-a+crc+simd"	if BR2_emag # ToDo: error: unrecognized -mcpu target: emag
+	default "armv8-a+crc+simd"	if BR2_exynos_m1
+	default "armv8-a"		if BR2_falkor # ToDo: error: unrecognized -mcpu target: falkor
+	default "armv8-a"		if BR2_phecda # ToDo: error: unrecognized -mcpu target: phecda
+	default "armv8-a"		if BR2_qdf24xx # ToDo: error: unrecognized -mcpu target: qdf24xx
+	default "armv8-a"		if BR2_thunderx && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: thunderx
+	default "armv8-a"		if BR2_thunderx && BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: octeontx
+	default "armv8-a"		if BR2_thunderxt81 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: thunderxt81
+	default "armv8-a"		if BR2_thunderxt81 && BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: octeontx81
+	default "armv8-a"		if BR2_thunderxt83 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: thunderxt83
+	default "armv8-a"		if BR2_thunderxt83 && BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: octeontx83
+	default "armv8-a"		if BR2_thunderxt88 # ToDo: error: unrecognized -mcpu target: thunderxt88
+	default "armv8-a"		if BR2_thunderxt88p1 # ToDo: error: unrecognized -mcpu target: thunderxt88p1
+	default "armv8-a+simd"		if BR2_xgene1
+	# armv8.1a
+	default "armv8.1-a"		if BR2_thunderx2t99 # ToDo: error: unrecognized -mcpu target: thunderx2t99
+	default "armv8.1-a"		if BR2_thunderx2t99p1 # ToDo: error: unrecognized -mcpu target: thunderx2t99p1
+	default "armv8.1-a"		if BR2_vulcan # ToDo: error: unrecognized -mcpu target: vulcan
+	# armv8.2a
+	default "armv8.2-a+simd"	if BR2_cortex_a55
+	default "armv8.2-a+simd"	if BR2_cortex_a75
+	default "armv8.2-a+simd"	if BR2_cortex_a75_a55
+	default "armv8.2-a+simd"	if BR2_cortex_a76
+	default "armv8.2-a+simd"	if BR2_cortex_a76_a55
+	default "armv8.2-a+simd"	if BR2_neoverse_n1
+	default "armv8.2-a"		if BR2_tsv110 # ToDo: error: unrecognized -mcpu target: tsv110
+	# armv8.4a
+	default "armv8.4-a"		if BR2_saphira # ToDo: error: unrecognized -mcpu target: saphira
+
 config BR2_GCC_TARGET_ABI
 	default "aapcs-linux"	if BR2_arm || BR2_armeb
 	default "lp64"		if BR2_aarch64 || BR2_aarch64_be
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags
  2020-03-02  9:19 [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries Peter Seiderer
@ 2020-03-02  9:19 ` Peter Seiderer
  2020-03-02 13:30   ` Thomas Petazzoni
  2020-03-02 10:17 ` [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries Peter Seiderer
  1 sibling, 1 reply; 6+ messages in thread
From: Peter Seiderer @ 2020-03-02  9:19 UTC (permalink / raw)
  To: buildroot

The qt5webengine configure simple takes QT_ARCH ('arm') to determine the
chromium compiler flags and uses some hard coded ARMv7 default values
for the compiler command line: '... -march=armv7-a -mfloat-abi=hard
-mtune=generic-armv7-a -mfpu=vfpv3-d16 ...'.

This results e.g. in an illegal instruction failure for rpi zero
(reported on the mailing list, see [1]).

Custom values could be set in the file src/3rdparty/chromium/build/config/arm.gni
(as tested by an proof-of-concept patch [2]).

[1] http://lists.busybox.net/pipermail/buildroot/2020-February/274587.html
[2] http://lists.busybox.net/pipermail/buildroot/2020-February/274586.html

Signed-off-by: Peter Seiderer <ps.report@gmx.net>
---
Changes v1 -> v2:
  - use new introduced BR2_GCC_TARGET_ARCH for arm_arch as the
    previous simple approach did not work (alternative would
    be to extract the arch at runtime via gcc invocation)

package/qt5/qt5webengine: fix chromium arm compile flags (change to BR2_GCC_TARGET_ARCH)

Signed-off-by: Peter Seiderer <ps.report@gmx.net>
---
 package/qt5/qt5webengine/qt5webengine.mk | 69 ++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/package/qt5/qt5webengine/qt5webengine.mk b/package/qt5/qt5webengine/qt5webengine.mk
index 898725937b..9596c8f178 100644
--- a/package/qt5/qt5webengine/qt5webengine.mk
+++ b/package/qt5/qt5webengine/qt5webengine.mk
@@ -63,7 +63,76 @@ QT5WEBENGINE_PRE_CONFIGURE_HOOKS += QT5WEBENGINE_CREATE_HOST_PKG_CONFIG
 QT5WEBENGINE_ENV += GN_PKG_CONFIG_HOST=$(@D)/host-bin/host-pkg-config
 endif
 
+# configure arm architecture paramter for chromium compile
+ifeq ($(BR2_arm),y)
+ifeq ($(BR2_ARM_CPU_ARMV4),y)
+define QT5WEBENGINE_CONFIGURE_ARM_VERSION
+	$(SED) 's/^    arm_version = 7$$/    arm_version = 4/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+endif
+
+ifeq ($(BR2_ARM_CPU_ARMV5),y)
+define QT5WEBENGINE_CONFIGURE_ARM_VERSION
+	$(SED) 's/^    arm_version = 7$$/    arm_version = 5/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+endif
+
+ifeq ($(BR2_ARM_CPU_ARMV6),y)
+define QT5WEBENGINE_CONFIGURE_ARM_VERSION
+	$(SED) 's/^    arm_version = 7$$/    arm_version = 6/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+endif
+
+# no entriy for BR2_ARM_CPU_ARMV7A/BR2_ARM_CPU_ARMV7M, arm_vesion = 7 is already set as default
+
+ifeq ($(BR2_ARM_CPU_ARMV8A),y)
+define QT5WEBENGINE_CONFIGURE_ARM_VERSION
+	$(SED) 's/^    arm_version = 7$$/    arm_version = 8/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+endif
+
+define QT5WEBENGINE_CONFIGURE_ARM_ARCH
+	$(SED) 's/^    arm_arch = ""$$/    arm_arch = $(BR2_GCC_TARGET_ARCH)/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+
+define QT5WEBENGINE_CONFIGURE_ARM_FPU
+	$(SED) 's/^    arm_fpu = ""$$/    arm_fpu = $(BR2_GCC_TARGET_FPU)/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+
+define QT5WEBENGINE_CONFIGURE_ARM_FLOAT_ABI
+	$(SED) 's/^    arm_float_abi = ""$$/    arm_float_abi = $(BR2_GCC_TARGET_FLOAT_ABI)/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+
+define QT5WEBENGINE_CONFIGURE_ARM_TUNE
+	$(SED) 's/^    arm_tune = ""$$/    arm_tune = $(BR2_GCC_TARGET_CPU)/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+
+ifeq ($(BR2_ARM_CPU_HAS_NEON),y)
+define QT5WEBENGINE_CONFIGURE_ARM_NEON
+	$(SED) 's/^    arm_use_neon = ""$$/    arm_use_neon = "true"/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+	$(SED) 's/^    arm_optionally_use_neon = false$$/    arm_optionally_use_neon = true/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+else
+define QT5WEBENGINE_CONFIGURE_ARM_NEON
+	$(SED) 's/^    arm_use_neon = ""$$/    arm_use_neon = "false"/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+endif
+
+ifeq ($(BR2_ARM_CPU_HAS_THUMB),)
+define QT5WEBENGINE_CONFIGURE_ARM_THUMB
+	$(SED) 's/^    arm_use_thumb = true$$/    arm_use_thumb = false/' $(@D)/src/3rdparty/chromium/build/config/arm.gni
+endef
+endif
+endif
+
 define QT5WEBENGINE_CONFIGURE_CMDS
+	$(QT5WEBENGINE_CONFIGURE_ARM_VERSION)
+	$(QT5WEBENGINE_CONFIGURE_ARM_ARCH)
+	$(QT5WEBENGINE_CONFIGURE_ARM_FPU)
+	$(QT5WEBENGINE_CONFIGURE_ARM_FLOAT_ABI)
+	$(QT5WEBENGINE_CONFIGURE_ARM_TUNE)
+	$(QT5WEBENGINE_CONFIGURE_ARM_NEON)
+	$(QT5WEBENGINE_CONFIGURE_ARM_THUMB)
 	(cd $(@D); $(TARGET_MAKE_ENV) $(QT5WEBENGINE_ENV) $(HOST_DIR)/bin/qmake $(QT5WEBENGINE_QMAKEFLAGS))
 endef
 
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries
  2020-03-02  9:19 [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries Peter Seiderer
  2020-03-02  9:19 ` [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags Peter Seiderer
@ 2020-03-02 10:17 ` Peter Seiderer
  1 sibling, 0 replies; 6+ messages in thread
From: Peter Seiderer @ 2020-03-02 10:17 UTC (permalink / raw)
  To: buildroot

On Mon,  2 Mar 2020 10:19:25 +0100, Peter Seiderer <ps.report@gmx.net> wrote:

> Add BR2_GCC_TARGET_ARCH entries, determined by (gcc-9.2.0)

Argh..., should have been BR2_GCC_TARGET_ARM_ARCH (not the already existing BR2_GCC_TARGET_ARCH)....

Regards,
Peter

> 	$ ./host/bin/arm-buildroot-linux-gnueabihf-gcc -Q -mcpu=$(BR2_GCC_TARGET_CPU) --help=target | grep march
>
> Or (for cortex-m3/cortex-m4/cortex-m7):
> 	$ ./host/bin/arm-buildroot-linux-gnueabihf-gcc -Q -mcpu=$(BR2_GCC_TARGET_CPU) -mthumb --help=target | grep march
>
> Or (where indicated):
> 	$ ./host/bin/arm-buildroot-linux-gnueabihf-gcc -Q -mcpu=$(BR2_GCC_TARGET_CPU) -msoft-float --help=target | grep march
>
> The soft/hard float flags could be determined from
> the arch/Config.in.arm processor definitions or the given
> isa_bit_... flags from build/host-gcc-final-9.2.0/build/gcc/arm-cpu-cdata.h.
>
> Signed-off-by: Peter Seiderer <ps.report@gmx.net>
> ---
> Notes:
>   - Fix ToDo's for unknown cpus
>   - Add BR2_GCC_TARGET_ARCH for other archs?
>
> Changes v1 -> v2:
>   - new patch
> ---
>  arch/Config.in.arm | 72 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
>
> diff --git a/arch/Config.in.arm b/arch/Config.in.arm
> index 4c0910e4f8..24f550287d 100644
> --- a/arch/Config.in.arm
> +++ b/arch/Config.in.arm
> @@ -898,6 +898,78 @@ config BR2_GCC_TARGET_CPU
>  	# armv8.4a
>  	default "saphira"	if BR2_saphira
>
> +config BR2_GCC_TARGET_ARCH
> +	# armv4
> +	default "armv4t"		if BR2_arm920t
> +	default "armv4t"		if BR2_arm922t
> +	default "armv4"			if BR2_fa526
> +	default "armv4"			if BR2_strongarm
> +	# armv5
> +	default "armv5tej+fp"		if BR2_arm926t
> +	default "iwmmxt"		if BR2_iwmmxt
> +	default "armv5te"		if BR2_xscale # -msoft-float
> +	# armv6
> +	default "armv6j"		if BR2_arm1136j_s # -msoft-float
> +	default "armv6j+fp"		if BR2_arm1136jf_s
> +	default "armv6kz"		if BR2_arm1176jz_s # -msoft-float
> +	default "armv6kz+fp"		if BR2_arm1176jzf_s
> +	default "armv6k+fp"		if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
> +	default "armv6k"		if BR2_arm11mpcore # -msoft-float
> +	# armv7a
> +	default "armv7-a+mp+sec+fp"	if BR2_cortex_a5
> +	default "armv7ve+vfpv3-d16"	if BR2_cortex_a7
> +	default "armv7-a+sec+fp"	if BR2_cortex_a8
> +	default "armv7-a+mp+sec+fp"	if BR2_cortex_a9
> +	default "armv7ve+vfpv3-d16"	if BR2_cortex_a12
> +	default "armv7ve+vfpv3-d16"	if BR2_cortex_a15
> +	default "armv7ve+vfpv3-d16"	if BR2_cortex_a15_a7
> +	default "armv7ve+vfpv3-d16"	if BR2_cortex_a17
> +	default "armv7ve+vfpv3-d16"	if BR2_cortex_a17_a7
> +	default "armv7-a+mp+sec+fp"	if BR2_pj4
> +	# armv7m
> +	default "armv7-m"		if BR2_cortex_m3
> +	default "armv7e-m+fp.dp"	if BR2_cortex_m4
> +	default "armv7e-m+fp.dp"	if BR2_cortex_m7
> +	# armv8a
> +	default "armv8-a+crc+simd"	if BR2_cortex_a32
> +	default "armv8-a+crc+simd"	if BR2_cortex_a35
> +	default "armv8-a+crc+simd"	if BR2_cortex_a53
> +	default "armv8-a+crc+simd"	if BR2_cortex_a57
> +	default "armv8-a+crc+simd"	if BR2_cortex_a57_a53
> +	default "armv8-a+crc+simd"	if BR2_cortex_a72
> +	default "armv8-a+crc+simd"	if BR2_cortex_a72_a53
> +	default "armv8-a+crc+simd"	if BR2_cortex_a73
> +	default "armv8-a+crc+simd"	if BR2_cortex_a73_a35
> +	default "armv8-a+crc+simd"	if BR2_cortex_a73_a53
> +	default "armv8-a+crc+simd"	if BR2_emag # ToDo: error: unrecognized -mcpu target: emag
> +	default "armv8-a+crc+simd"	if BR2_exynos_m1
> +	default "armv8-a"		if BR2_falkor # ToDo: error: unrecognized -mcpu target: falkor
> +	default "armv8-a"		if BR2_phecda # ToDo: error: unrecognized -mcpu target: phecda
> +	default "armv8-a"		if BR2_qdf24xx # ToDo: error: unrecognized -mcpu target: qdf24xx
> +	default "armv8-a"		if BR2_thunderx && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: thunderx
> +	default "armv8-a"		if BR2_thunderx && BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: octeontx
> +	default "armv8-a"		if BR2_thunderxt81 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: thunderxt81
> +	default "armv8-a"		if BR2_thunderxt81 && BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: octeontx81
> +	default "armv8-a"		if BR2_thunderxt83 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: thunderxt83
> +	default "armv8-a"		if BR2_thunderxt83 && BR2_TOOLCHAIN_GCC_AT_LEAST_9 # ToDo: error: unrecognized -mcpu target: octeontx83
> +	default "armv8-a"		if BR2_thunderxt88 # ToDo: error: unrecognized -mcpu target: thunderxt88
> +	default "armv8-a"		if BR2_thunderxt88p1 # ToDo: error: unrecognized -mcpu target: thunderxt88p1
> +	default "armv8-a+simd"		if BR2_xgene1
> +	# armv8.1a
> +	default "armv8.1-a"		if BR2_thunderx2t99 # ToDo: error: unrecognized -mcpu target: thunderx2t99
> +	default "armv8.1-a"		if BR2_thunderx2t99p1 # ToDo: error: unrecognized -mcpu target: thunderx2t99p1
> +	default "armv8.1-a"		if BR2_vulcan # ToDo: error: unrecognized -mcpu target: vulcan
> +	# armv8.2a
> +	default "armv8.2-a+simd"	if BR2_cortex_a55
> +	default "armv8.2-a+simd"	if BR2_cortex_a75
> +	default "armv8.2-a+simd"	if BR2_cortex_a75_a55
> +	default "armv8.2-a+simd"	if BR2_cortex_a76
> +	default "armv8.2-a+simd"	if BR2_cortex_a76_a55
> +	default "armv8.2-a+simd"	if BR2_neoverse_n1
> +	default "armv8.2-a"		if BR2_tsv110 # ToDo: error: unrecognized -mcpu target: tsv110
> +	# armv8.4a
> +	default "armv8.4-a"		if BR2_saphira # ToDo: error: unrecognized -mcpu target: saphira
> +
>  config BR2_GCC_TARGET_ABI
>  	default "aapcs-linux"	if BR2_arm || BR2_armeb
>  	default "lp64"		if BR2_aarch64 || BR2_aarch64_be

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags
  2020-03-02  9:19 ` [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags Peter Seiderer
@ 2020-03-02 13:30   ` Thomas Petazzoni
  2020-03-02 22:01     ` Peter Seiderer
  0 siblings, 1 reply; 6+ messages in thread
From: Thomas Petazzoni @ 2020-03-02 13:30 UTC (permalink / raw)
  To: buildroot

On Mon,  2 Mar 2020 10:19:26 +0100
Peter Seiderer <ps.report@gmx.net> wrote:

> The qt5webengine configure simple takes QT_ARCH ('arm') to determine the
> chromium compiler flags and uses some hard coded ARMv7 default values
> for the compiler command line: '... -march=armv7-a -mfloat-abi=hard
> -mtune=generic-armv7-a -mfpu=vfpv3-d16 ...'.
> 
> This results e.g. in an illegal instruction failure for rpi zero
> (reported on the mailing list, see [1]).
> 
> Custom values could be set in the file src/3rdparty/chromium/build/config/arm.gni
> (as tested by an proof-of-concept patch [2]).
> 
> [1] http://lists.busybox.net/pipermail/buildroot/2020-February/274587.html
> [2] http://lists.busybox.net/pipermail/buildroot/2020-February/274586.html
> 
> Signed-off-by: Peter Seiderer <ps.report@gmx.net>

Could we instead ask this thing to not do all this sorcery, and instead
just use the compiler as-is, without passing crazy
architecture-specific compiler flags ?

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags
  2020-03-02 13:30   ` Thomas Petazzoni
@ 2020-03-02 22:01     ` Peter Seiderer
  2020-03-03  8:00       ` Thomas Petazzoni
  0 siblings, 1 reply; 6+ messages in thread
From: Peter Seiderer @ 2020-03-02 22:01 UTC (permalink / raw)
  To: buildroot

Hello Thomas,

On Mon, 2 Mar 2020 14:30:07 +0100, Thomas Petazzoni <thomas.petazzoni@bootlin.com> wrote:

> On Mon,  2 Mar 2020 10:19:26 +0100
> Peter Seiderer <ps.report@gmx.net> wrote:
>
> > The qt5webengine configure simple takes QT_ARCH ('arm') to determine the
> > chromium compiler flags and uses some hard coded ARMv7 default values
> > for the compiler command line: '... -march=armv7-a -mfloat-abi=hard
> > -mtune=generic-armv7-a -mfpu=vfpv3-d16 ...'.
> >
> > This results e.g. in an illegal instruction failure for rpi zero
> > (reported on the mailing list, see [1]).
> >
> > Custom values could be set in the file src/3rdparty/chromium/build/config/arm.gni
> > (as tested by an proof-of-concept patch [2]).
> >
> > [1] http://lists.busybox.net/pipermail/buildroot/2020-February/274587.html
> > [2] http://lists.busybox.net/pipermail/buildroot/2020-February/274586.html
> >
> > Signed-off-by: Peter Seiderer <ps.report@gmx.net>
>
> Could we instead ask this thing to not do all this sorcery, and instead
> just use the compiler as-is, without passing crazy
> architecture-specific compiler flags ?

Disabled all march/mfloat-abi/mtune/mfpu flags with the following patch:

--- a/src/3rdparty/chromium/build/config/compiler/BUILD.gn
+++ b/src/3rdparty/chromium/build/config/compiler/BUILD.gn
@@ -672,7 +672,7 @@ config("compiler") {
     # TODO(pcc): The contents of .ARM.attributes should be based on the
     # -march flag passed at compile time (see llvm.org/pr36291).
     if (current_cpu == "arm") {
-      ldflags += [ "-march=$arm_arch" ]
+#      ldflags += [ "-march=$arm_arch" ]
     }
   }

@@ -752,13 +752,13 @@ config("compiler_cpu_abi") {
         ldflags += [ "--target=arm-linux-gnueabihf" ]
       }
       if (!is_nacl) {
-        cflags += [
-          "-march=$arm_arch",
-          "-mfloat-abi=$arm_float_abi",
-        ]
+#        cflags += [
+#          "-march=$arm_arch",
+#          "-mfloat-abi=$arm_float_abi",
+#        ]
       }
       if (arm_tune != "") {
-        cflags += [ "-mtune=$arm_tune" ]
+#        cflags += [ "-mtune=$arm_tune" ]
       }
     } else if (current_cpu == "arm64") {
       if (is_clang && !is_android && !is_nacl && !is_fuchsia) {
@@ -1130,7 +1130,8 @@ config("clang_revision") {

 config("compiler_arm_fpu") {
   if (current_cpu == "arm" && !is_ios && !is_nacl) {
-    cflags = [ "-mfpu=$arm_fpu" ]
+#    cflags = [ "-mfpu=$arm_fpu" ]
+    cflags = [ ]
     asmflags = cflags
   }
 }

Quick (if you call can call it quick with miniumum 50 minutes compile time)
worked for a buildroot toolchain (which defaults to the right cpu) and
the rpi zero testcase..., but now no buildroot specific flags are
used for the compile (no optimize, no custom, no cpu type etc.)...,
will work with compilers with the right default values...

Not sure if other optional compiles depend on the right setting
of one of the arm_... parameters...

Regards,
Peter

>
> Thomas

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags
  2020-03-02 22:01     ` Peter Seiderer
@ 2020-03-03  8:00       ` Thomas Petazzoni
  0 siblings, 0 replies; 6+ messages in thread
From: Thomas Petazzoni @ 2020-03-03  8:00 UTC (permalink / raw)
  To: buildroot

Hello Peter,

On Mon, 2 Mar 2020 23:01:55 +0100
Peter Seiderer <ps.report@gmx.net> wrote:

> > Could we instead ask this thing to not do all this sorcery, and instead
> > just use the compiler as-is, without passing crazy
> > architecture-specific compiler flags ?  
> 
> Disabled all march/mfloat-abi/mtune/mfpu flags with the following patch:

[...]

Thanks for this work! To me this feels like a better solution, even
though it's annoying to maintain such a local patch. I assume there's
pretty much zero chance to get this merged by upstream Chromium, and
then back into the qt5webengine code anyway.

> Quick (if you call can call it quick with miniumum 50 minutes compile time)
> worked for a buildroot toolchain (which defaults to the right cpu) and
> the rpi zero testcase..., but now no buildroot specific flags are
> used for the compile (no optimize, no custom, no cpu type etc.)...,
> will work with compilers with the right default values...

The CPU type is encoded into the compiler wrapper. So it's really only
the optimization/debug flags that you will be missing.

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-03-03  8:00 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-02  9:19 [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries Peter Seiderer
2020-03-02  9:19 ` [Buildroot] [RFC v2 2/2] package/qt5webengine: fix chromium arm compile flags Peter Seiderer
2020-03-02 13:30   ` Thomas Petazzoni
2020-03-02 22:01     ` Peter Seiderer
2020-03-03  8:00       ` Thomas Petazzoni
2020-03-02 10:17 ` [Buildroot] [RFC v2 1/2] arch/Config.in.arm: add BR2_GCC_TARGET_ARCH entries Peter Seiderer

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