From: "Mylène Josserand" <mylene.josserand@collabora.com> To: linux@armlinux.org.uk, heiko@sntech.de, mturquette@baylibre.com, sboyd@kernel.org Cc: mylene.josserand@collabora.com, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-clk@vger.kernel.org Subject: [PATCH 2/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Date: Mon, 2 Mar 2020 16:57:03 +0100 [thread overview] Message-ID: <20200302155703.278421-3-mylene.josserand@collabora.com> (raw) In-Reply-To: <20200302155703.278421-1-mylene.josserand@collabora.com> The revision rk3288w has a different clock tree about "hclk_vio" clock, according to the BSP kernel code [1]. This patch handles this difference by detecting which SOC it is and creating the div accordingly. [1]: https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/clk/rockchip/clk-rk3288.c#L960..L964 Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com> --- drivers/clk/rockchip/clk-rk3288.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index cc2a177bbdbf..e7d6e3a095a5 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -10,6 +10,7 @@ #include <linux/of_address.h> #include <linux/syscore_ops.h> #include <dt-bindings/clock/rk3288-cru.h> +#include <soc/rockchip/revision.h> #include "clk.h" #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4) @@ -425,8 +426,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(3), 0, GFLAGS), - DIV(0, "hclk_vio", "aclk_vio0", 0, - RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 2, GFLAGS), @@ -819,6 +818,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS), }; +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio1", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), +}; + +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio0", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), +}; + static const char *const rk3288_critical_clocks[] __initconst = { "aclk_cpu", "aclk_peri", @@ -931,6 +940,14 @@ static void __init rk3288_clk_init(struct device_node *np) return; } + /* Check for the rk3288w revision as Clock tree is different */ + if (soc_is_rk3288w()) + rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch, + ARRAY_SIZE(rk3288w_hclkvio_branch)); + else + rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch, + ARRAY_SIZE(rk3288_hclkvio_branch)); + rockchip_clk_register_plls(ctx, rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS1); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: "Mylène Josserand" <mylene.josserand@collabora.com> To: linux@armlinux.org.uk, heiko@sntech.de, mturquette@baylibre.com, sboyd@kernel.org Cc: mylene.josserand@collabora.com, kernel@collabora.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 2/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Date: Mon, 2 Mar 2020 16:57:03 +0100 [thread overview] Message-ID: <20200302155703.278421-3-mylene.josserand@collabora.com> (raw) In-Reply-To: <20200302155703.278421-1-mylene.josserand@collabora.com> The revision rk3288w has a different clock tree about "hclk_vio" clock, according to the BSP kernel code [1]. This patch handles this difference by detecting which SOC it is and creating the div accordingly. [1]: https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/clk/rockchip/clk-rk3288.c#L960..L964 Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com> --- drivers/clk/rockchip/clk-rk3288.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index cc2a177bbdbf..e7d6e3a095a5 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -10,6 +10,7 @@ #include <linux/of_address.h> #include <linux/syscore_ops.h> #include <dt-bindings/clock/rk3288-cru.h> +#include <soc/rockchip/revision.h> #include "clk.h" #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4) @@ -425,8 +426,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(3), 0, GFLAGS), - DIV(0, "hclk_vio", "aclk_vio0", 0, - RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 2, GFLAGS), @@ -819,6 +818,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS), }; +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio1", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), +}; + +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio0", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), +}; + static const char *const rk3288_critical_clocks[] __initconst = { "aclk_cpu", "aclk_peri", @@ -931,6 +940,14 @@ static void __init rk3288_clk_init(struct device_node *np) return; } + /* Check for the rk3288w revision as Clock tree is different */ + if (soc_is_rk3288w()) + rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch, + ARRAY_SIZE(rk3288w_hclkvio_branch)); + else + rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch, + ARRAY_SIZE(rk3288_hclkvio_branch)); + rockchip_clk_register_plls(ctx, rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS1); -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-02 15:58 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-02 15:57 [PATCH 0/2] ARM: Add Rockchip rk3288w support Mylène Josserand 2020-03-02 15:57 ` Mylène Josserand 2020-03-02 15:57 ` [PATCH 1/2] ARM: Rockchip: Handle rk3288/rk3288w revision Mylène Josserand 2020-03-02 15:57 ` Mylène Josserand 2020-03-04 10:59 ` Heiko Stübner 2020-03-04 10:59 ` Heiko Stübner 2020-03-05 0:03 ` Ezequiel Garcia 2020-03-05 0:03 ` Ezequiel Garcia 2020-03-05 0:51 ` Heiko Stübner 2020-03-05 0:51 ` Heiko Stübner 2020-03-05 11:32 ` Ezequiel Garcia 2020-03-05 11:32 ` Ezequiel Garcia 2020-03-05 11:35 ` Ezequiel Garcia 2020-03-05 11:35 ` Ezequiel Garcia 2020-03-06 2:44 ` Kever Yang 2020-03-06 2:44 ` Kever Yang 2020-03-06 10:30 ` Ezequiel Garcia 2020-03-06 10:30 ` Ezequiel Garcia 2020-03-06 10:45 ` Geert Uytterhoeven 2020-03-06 10:45 ` Geert Uytterhoeven 2020-03-26 13:50 ` Mylene Josserand 2020-03-26 13:50 ` Mylene Josserand 2020-03-26 15:31 ` Geert Uytterhoeven 2020-03-26 15:31 ` Geert Uytterhoeven 2020-03-27 6:20 ` Mylene Josserand 2020-03-27 6:20 ` Mylene Josserand 2020-03-02 15:57 ` Mylène Josserand [this message] 2020-03-02 15:57 ` [PATCH 2/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Mylène Josserand 2020-03-04 5:34 ` kbuild test robot 2020-03-04 5:34 ` kbuild test robot 2020-03-04 5:34 ` kbuild test robot 2020-03-04 5:34 ` kbuild test robot
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