From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PULL 11/38] target/riscv: Add Hypervisor CSR access functions
Date: Mon, 2 Mar 2020 16:48:21 -0800 [thread overview]
Message-ID: <20200303004848.136788-12-palmerdabbelt@google.com> (raw)
In-Reply-To: <20200303004848.136788-1-palmerdabbelt@google.com>
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/csr.c | 136 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 134 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c63b2f980c..bee639e92e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -98,6 +98,20 @@ static int smode(CPURISCVState *env, int csrno)
return -!riscv_has_ext(env, RVS);
}
+static int hmode(CPURISCVState *env, int csrno)
+{
+ if (riscv_has_ext(env, RVS) &&
+ riscv_has_ext(env, RVH)) {
+ /* Hypervisor extension is supported */
+ if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ env->priv == PRV_M) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -226,8 +240,9 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
/* Machine constants */
-#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
-#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
+#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
+#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
+#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
static const target_ulong delegable_ints = S_MODE_INTERRUPTS;
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS;
@@ -257,6 +272,7 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
+static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
#if defined(TARGET_RISCV32)
static const char valid_vm_1_09[16] = {
@@ -756,6 +772,112 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+/* Hypervisor Extensions */
+static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hstatus;
+ return 0;
+}
+
+static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hstatus = val;
+ return 0;
+}
+
+static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hedeleg;
+ return 0;
+}
+
+static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hedeleg = val;
+ return 0;
+}
+
+static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hideleg;
+ return 0;
+}
+
+static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hideleg = val;
+ return 0;
+}
+
+static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret = rmw_mip(env, 0, ret_value, new_value,
+ write_mask & hip_writable_mask);
+
+ return ret;
+}
+
+static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mie & VS_MODE_INTERRUPTS;
+ return 0;
+}
+
+static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
+ return write_mie(env, CSR_MIE, newval);
+}
+
+static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hcounteren;
+ return 0;
+}
+
+static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hcounteren = val;
+ return 0;
+}
+
+static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->htval;
+ return 0;
+}
+
+static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->htval = val;
+ return 0;
+}
+
+static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->htinst;
+ return 0;
+}
+
+static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->htinst = val;
+ return 0;
+}
+
+static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hgatp;
+ return 0;
+}
+
+static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hgatp = val;
+ return 0;
+}
+
/* Physical Memory Protection */
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -959,6 +1081,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor Protection and Translation */
[CSR_SATP] = { smode, read_satp, write_satp },
+ [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
+ [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
+ [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
+ [CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
+ [CSR_HIE] = { hmode, read_hie, write_hie },
+ [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
+ [CSR_HTVAL] = { hmode, read_htval, write_htval },
+ [CSR_HTINST] = { hmode, read_htinst, write_htinst },
+ [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
--
2.25.0.265.gbab2e86ba0-goog
next prev parent reply other threads:[~2020-03-03 0:52 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 0:48 [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3 Palmer Dabbelt
2020-03-03 0:48 ` [PULL 01/38] target/riscv: Convert MIP CSR to target_ulong Palmer Dabbelt
2020-03-03 0:48 ` [PULL 02/38] target/riscv: Add the Hypervisor extension Palmer Dabbelt
2020-03-03 0:48 ` [PULL 03/38] target/riscv: Add the Hypervisor CSRs to CPUState Palmer Dabbelt
2020-03-03 0:48 ` [PULL 04/38] target/riscv: Add support for the new execption numbers Palmer Dabbelt
2020-03-05 16:44 ` Peter Maydell
2020-03-05 16:44 ` Peter Maydell
2020-03-05 16:46 ` Alistair Francis
2020-03-05 16:46 ` Alistair Francis
2020-03-05 16:51 ` Palmer Dabbelt
2020-03-03 0:48 ` [PULL 05/38] target/riscv: Rename the H irqs to VS irqs Palmer Dabbelt
2020-03-03 0:48 ` [PULL 06/38] target/riscv: Add the virtulisation mode Palmer Dabbelt
2020-03-03 0:48 ` [PULL 07/38] target/riscv: Add the force HS exception mode Palmer Dabbelt
2020-03-03 0:48 ` [PULL 08/38] target/riscv: Fix CSR perm checking for HS mode Palmer Dabbelt
2020-03-03 0:48 ` [PULL 09/38] target/riscv: Print priv and virt in disas log Palmer Dabbelt
2020-03-03 0:48 ` [PULL 10/38] target/riscv: Dump Hypervisor registers if enabled Palmer Dabbelt
2020-03-03 0:48 ` Palmer Dabbelt [this message]
2020-03-03 0:48 ` [PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses Palmer Dabbelt
2020-03-03 0:48 ` [PULL 13/38] target/riscv: Add Hypervisor machine " Palmer Dabbelt
2020-03-03 0:48 ` [PULL 14/38] target/riscv: Add virtual register swapping function Palmer Dabbelt
2020-03-03 0:48 ` [PULL 15/38] target/riscv: Set VS bits in mideleg for Hyp extension Palmer Dabbelt
2020-03-03 0:48 ` [PULL 16/38] target/riscv: Extend the MIE CSR to support virtulisation Palmer Dabbelt
2020-03-03 0:48 ` [PULL 17/38] target/riscv: Extend the SIP " Palmer Dabbelt
2020-03-03 0:48 ` [PULL 18/38] target/riscv: Add support for virtual interrupt setting Palmer Dabbelt
2020-03-03 0:48 ` [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes Palmer Dabbelt
2020-03-03 0:48 ` [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1 Palmer Dabbelt
2020-03-03 0:48 ` [PULL 21/38] target/riscv: Add hypvervisor trap support Palmer Dabbelt
2020-03-03 0:48 ` [PULL 22/38] target/riscv: Add Hypervisor trap return support Palmer Dabbelt
2020-03-03 0:48 ` [PULL 23/38] target/riscv: Add hfence instructions Palmer Dabbelt
2020-03-03 0:48 ` [PULL 24/38] target/riscv: Remove the hret instruction Palmer Dabbelt
2020-03-03 0:48 ` [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled Palmer Dabbelt
2020-03-03 0:48 ` [PULL 26/38] target/riscv: Disable guest FP support based on virtual status Palmer Dabbelt
2020-03-03 0:48 ` [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty Palmer Dabbelt
2020-03-03 0:48 ` [PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops Palmer Dabbelt
2020-03-03 0:48 ` [PULL 29/38] target/riscv: Allow specifying MMU stage Palmer Dabbelt
2020-03-03 0:48 ` [PULL 30/38] target/riscv: Implement second stage MMU Palmer Dabbelt
2020-03-03 0:48 ` [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails Palmer Dabbelt
2020-03-03 0:48 ` [PULL 32/38] target/riscv: Set htval and mtval2 on execptions Palmer Dabbelt
2020-03-03 0:48 ` [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR Palmer Dabbelt
2020-03-03 0:48 ` [PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Palmer Dabbelt
2020-03-03 0:48 ` [PULL 35/38] target/riscv: Allow enabling the Hypervisor extension Palmer Dabbelt
2020-03-03 0:48 ` [PULL 36/38] riscv: virt: Allow PCI address 0 Palmer Dabbelt
2020-03-03 0:48 ` [PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode Palmer Dabbelt
2020-03-03 0:48 ` [PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation Palmer Dabbelt
2020-03-03 12:03 ` [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3 Peter Maydell
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