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From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org,          qemu-devel@nongnu.org,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops
Date: Mon,  2 Mar 2020 16:48:38 -0800	[thread overview]
Message-ID: <20200303004848.136788-29-palmerdabbelt@google.com> (raw)
In-Reply-To: <20200303004848.136788-1-palmerdabbelt@google.com>

From: Alistair Francis <alistair.francis@wdc.com>

mark_fs_dirty() is the only place in translate.c that uses the
virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and
HSTATUS.SPRV when setting the bool as this is used for performing
floating point operations when V=0.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/translate.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3ce86adb89..b51ab92068 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -751,7 +751,21 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
     ctx->priv_ver = env->priv_ver;
 #if !defined(CONFIG_USER_ONLY)
-    ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+    if (riscv_has_ext(env, RVH)) {
+        ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+        if (env->priv_ver == PRV_M &&
+            get_field(env->mstatus, MSTATUS_MPRV) &&
+            get_field(env->mstatus, MSTATUS_MPV)) {
+            ctx->virt_enabled = true;
+        } else if (env->priv == PRV_S &&
+                   !riscv_cpu_virt_enabled(env) &&
+                   get_field(env->hstatus, HSTATUS_SPRV) &&
+                   get_field(env->hstatus, HSTATUS_SPV)) {
+            ctx->virt_enabled = true;
+        }
+    } else {
+        ctx->virt_enabled = false;
+    }
 #else
     ctx->virt_enabled = false;
 #endif
-- 
2.25.0.265.gbab2e86ba0-goog



  parent reply	other threads:[~2020-03-03  1:04 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-03  0:48 [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3 Palmer Dabbelt
2020-03-03  0:48 ` [PULL 01/38] target/riscv: Convert MIP CSR to target_ulong Palmer Dabbelt
2020-03-03  0:48 ` [PULL 02/38] target/riscv: Add the Hypervisor extension Palmer Dabbelt
2020-03-03  0:48 ` [PULL 03/38] target/riscv: Add the Hypervisor CSRs to CPUState Palmer Dabbelt
2020-03-03  0:48 ` [PULL 04/38] target/riscv: Add support for the new execption numbers Palmer Dabbelt
2020-03-05 16:44   ` Peter Maydell
2020-03-05 16:44     ` Peter Maydell
2020-03-05 16:46     ` Alistair Francis
2020-03-05 16:46       ` Alistair Francis
2020-03-05 16:51     ` Palmer Dabbelt
2020-03-03  0:48 ` [PULL 05/38] target/riscv: Rename the H irqs to VS irqs Palmer Dabbelt
2020-03-03  0:48 ` [PULL 06/38] target/riscv: Add the virtulisation mode Palmer Dabbelt
2020-03-03  0:48 ` [PULL 07/38] target/riscv: Add the force HS exception mode Palmer Dabbelt
2020-03-03  0:48 ` [PULL 08/38] target/riscv: Fix CSR perm checking for HS mode Palmer Dabbelt
2020-03-03  0:48 ` [PULL 09/38] target/riscv: Print priv and virt in disas log Palmer Dabbelt
2020-03-03  0:48 ` [PULL 10/38] target/riscv: Dump Hypervisor registers if enabled Palmer Dabbelt
2020-03-03  0:48 ` [PULL 11/38] target/riscv: Add Hypervisor CSR access functions Palmer Dabbelt
2020-03-03  0:48 ` [PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses Palmer Dabbelt
2020-03-03  0:48 ` [PULL 13/38] target/riscv: Add Hypervisor machine " Palmer Dabbelt
2020-03-03  0:48 ` [PULL 14/38] target/riscv: Add virtual register swapping function Palmer Dabbelt
2020-03-03  0:48 ` [PULL 15/38] target/riscv: Set VS bits in mideleg for Hyp extension Palmer Dabbelt
2020-03-03  0:48 ` [PULL 16/38] target/riscv: Extend the MIE CSR to support virtulisation Palmer Dabbelt
2020-03-03  0:48 ` [PULL 17/38] target/riscv: Extend the SIP " Palmer Dabbelt
2020-03-03  0:48 ` [PULL 18/38] target/riscv: Add support for virtual interrupt setting Palmer Dabbelt
2020-03-03  0:48 ` [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes Palmer Dabbelt
2020-03-03  0:48 ` [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1 Palmer Dabbelt
2020-03-03  0:48 ` [PULL 21/38] target/riscv: Add hypvervisor trap support Palmer Dabbelt
2020-03-03  0:48 ` [PULL 22/38] target/riscv: Add Hypervisor trap return support Palmer Dabbelt
2020-03-03  0:48 ` [PULL 23/38] target/riscv: Add hfence instructions Palmer Dabbelt
2020-03-03  0:48 ` [PULL 24/38] target/riscv: Remove the hret instruction Palmer Dabbelt
2020-03-03  0:48 ` [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled Palmer Dabbelt
2020-03-03  0:48 ` [PULL 26/38] target/riscv: Disable guest FP support based on virtual status Palmer Dabbelt
2020-03-03  0:48 ` [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty Palmer Dabbelt
2020-03-03  0:48 ` Palmer Dabbelt [this message]
2020-03-03  0:48 ` [PULL 29/38] target/riscv: Allow specifying MMU stage Palmer Dabbelt
2020-03-03  0:48 ` [PULL 30/38] target/riscv: Implement second stage MMU Palmer Dabbelt
2020-03-03  0:48 ` [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails Palmer Dabbelt
2020-03-03  0:48 ` [PULL 32/38] target/riscv: Set htval and mtval2 on execptions Palmer Dabbelt
2020-03-03  0:48 ` [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR Palmer Dabbelt
2020-03-03  0:48 ` [PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Palmer Dabbelt
2020-03-03  0:48 ` [PULL 35/38] target/riscv: Allow enabling the Hypervisor extension Palmer Dabbelt
2020-03-03  0:48 ` [PULL 36/38] riscv: virt: Allow PCI address 0 Palmer Dabbelt
2020-03-03  0:48 ` [PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode Palmer Dabbelt
2020-03-03  0:48 ` [PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation Palmer Dabbelt
2020-03-03 12:03 ` [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3 Peter Maydell

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