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From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atish.patra@wdc.com>,
	Anup Patel <anup.patel@wdc.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <anup@brainfault.org>
Subject: [PATCH v2 0/3] RISC-V Spike machine improvements
Date: Tue,  3 Mar 2020 19:30:34 +0530	[thread overview]
Message-ID: <20200303140037.85311-1-anup.patel@wdc.com> (raw)

This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs

Changes since v1:
 - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)

Anup Patel (3):
  hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
  hw/riscv/spike: Allow loading firmware separately using -bios option
  hw/riscv/spike: Allow more than one CPUs

 hw/riscv/boot.c         | 13 ++++++++-----
 hw/riscv/sifive_u.c     |  2 +-
 hw/riscv/spike.c        | 26 ++++++++++++++++++++++++--
 hw/riscv/virt.c         |  2 +-
 include/hw/riscv/boot.h |  6 ++++--
 5 files changed, 38 insertions(+), 11 deletions(-)

-- 
2.17.1



WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atish.patra@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v2 0/3] RISC-V Spike machine improvements
Date: Tue,  3 Mar 2020 19:30:34 +0530	[thread overview]
Message-ID: <20200303140037.85311-1-anup.patel@wdc.com> (raw)

This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs

Changes since v1:
 - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)

Anup Patel (3):
  hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
  hw/riscv/spike: Allow loading firmware separately using -bios option
  hw/riscv/spike: Allow more than one CPUs

 hw/riscv/boot.c         | 13 ++++++++-----
 hw/riscv/sifive_u.c     |  2 +-
 hw/riscv/spike.c        | 26 ++++++++++++++++++++++++--
 hw/riscv/virt.c         |  2 +-
 include/hw/riscv/boot.h |  6 ++++--
 5 files changed, 38 insertions(+), 11 deletions(-)

-- 
2.17.1



             reply	other threads:[~2020-03-03 14:02 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-03 14:00 Anup Patel [this message]
2020-03-03 14:00 ` [PATCH v2 0/3] RISC-V Spike machine improvements Anup Patel
2020-03-03 14:00 ` [PATCH v2 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() Anup Patel
2020-03-03 14:00   ` Anup Patel
2020-03-03 14:00 ` [PATCH v2 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option Anup Patel
2020-03-03 14:00   ` Anup Patel
2020-03-03 14:00 ` [PATCH v2 3/3] hw/riscv/spike: Allow more than one CPUs Anup Patel
2020-03-03 14:00   ` Anup Patel

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