* [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver
@ 2020-03-04 16:52 Loic Poulain
2020-03-04 16:52 ` [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Loic Poulain
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Loic Poulain @ 2020-03-04 16:52 UTC (permalink / raw)
To: wsa
Cc: vkoul, bjorn.andersson, robert.foss, linux-arm-msm, linux-i2c,
Loic Poulain, Todor Tomov
This commit adds I2C bus support for the Camera Control Interface
(CCI) I2C controller found on the Qualcomm SoC processors. This I2C
controller supports two masters and they are registered to the core.
CCI versions supported in the driver are MSM8916 and MSM8996.
This is a rework of the patch posted by Vinod:
https://patchwork.kernel.org/patch/10569961/
With additional fixes + most of the comments addressed.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
---
v2: Remove clock rates config from driver (done via assigned clock)
Added CCI timeout recovery from Ricardo's patch:
https://www.spinics.net/lists/linux-i2c/msg36973.html
v3: add sdm845 support
rework cci_init function
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-qcom-cci.c | 787 ++++++++++++++++++++++++++++++++++++++
3 files changed, 798 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-qcom-cci.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 6a0aa76..807a052 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -894,6 +894,16 @@ config I2C_QCOM_GENI
This driver can also be built as a module. If so, the module
will be called i2c-qcom-geni.
+config I2C_QCOM_CCI
+ tristate "Qualcomm Camera Control Interface"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ If you say yes to this option, support will be included for the
+ built-in camera control interface on the Qualcomm SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-qcom-cci.
+
config I2C_QUP
tristate "Qualcomm QUP based I2C controller"
depends on ARCH_QCOM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 3ab8aeb..9028b77 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
+obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c
new file mode 100644
index 0000000..2ef472e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-qcom-cci.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
+// Copyright (c) 2017-19 Linaro Limited.
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#define CCI_HW_VERSION 0x0
+#define CCI_RESET_CMD 0x004
+#define CCI_RESET_CMD_MASK 0x0f73f3f7
+#define CCI_RESET_CMD_M0_MASK 0x000003f1
+#define CCI_RESET_CMD_M1_MASK 0x0003f001
+#define CCI_QUEUE_START 0x008
+#define CCI_HALT_REQ 0x034
+#define CCI_HALT_REQ_I2C_M0_Q0Q1 BIT(0)
+#define CCI_HALT_REQ_I2C_M1_Q0Q1 BIT(1)
+
+#define CCI_I2C_Mm_SCL_CTL(m) (0x100 + 0x100 * (m))
+#define CCI_I2C_Mm_SDA_CTL_0(m) (0x104 + 0x100 * (m))
+#define CCI_I2C_Mm_SDA_CTL_1(m) (0x108 + 0x100 * (m))
+#define CCI_I2C_Mm_SDA_CTL_2(m) (0x10c + 0x100 * (m))
+#define CCI_I2C_Mm_MISC_CTL(m) (0x110 + 0x100 * (m))
+
+#define CCI_I2C_Mm_READ_DATA(m) (0x118 + 0x100 * (m))
+#define CCI_I2C_Mm_READ_BUF_LEVEL(m) (0x11c + 0x100 * (m))
+#define CCI_I2C_Mm_Qn_EXEC_WORD_CNT(m, n) (0x300 + 0x200 * (m) + 0x100 * (n))
+#define CCI_I2C_Mm_Qn_CUR_WORD_CNT(m, n) (0x304 + 0x200 * (m) + 0x100 * (n))
+#define CCI_I2C_Mm_Qn_CUR_CMD(m, n) (0x308 + 0x200 * (m) + 0x100 * (n))
+#define CCI_I2C_Mm_Qn_REPORT_STATUS(m, n) (0x30c + 0x200 * (m) + 0x100 * (n))
+#define CCI_I2C_Mm_Qn_LOAD_DATA(m, n) (0x310 + 0x200 * (m) + 0x100 * (n))
+
+#define CCI_IRQ_GLOBAL_CLEAR_CMD 0xc00
+#define CCI_IRQ_MASK_0 0xc04
+#define CCI_IRQ_MASK_0_I2C_M0_RD_DONE BIT(0)
+#define CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT BIT(4)
+#define CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT BIT(8)
+#define CCI_IRQ_MASK_0_I2C_M1_RD_DONE BIT(12)
+#define CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT BIT(16)
+#define CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT BIT(20)
+#define CCI_IRQ_MASK_0_RST_DONE_ACK BIT(24)
+#define CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK BIT(25)
+#define CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK BIT(26)
+#define CCI_IRQ_MASK_0_I2C_M0_ERROR 0x18000ee6
+#define CCI_IRQ_MASK_0_I2C_M1_ERROR 0x60ee6000
+#define CCI_IRQ_CLEAR_0 0xc08
+#define CCI_IRQ_STATUS_0 0xc0c
+#define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0)
+#define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4)
+#define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8)
+#define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12)
+#define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16)
+#define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20)
+#define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24)
+#define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25)
+#define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26)
+#define CCI_IRQ_STATUS_0_I2C_M0_ERROR 0x18000ee6
+#define CCI_IRQ_STATUS_0_I2C_M1_ERROR 0x60ee6000
+
+#define CCI_TIMEOUT (msecs_to_jiffies(100))
+#define NUM_MASTERS 2
+#define NUM_QUEUES 2
+
+/* Max number of resources + 1 for a NULL terminator */
+#define CCI_RES_MAX 6
+
+
+#define CCI_I2C_SET_PARAM 1
+#define CCI_I2C_REPORT 8
+#define CCI_I2C_WRITE 9
+#define CCI_I2C_READ 10
+
+#define CCI_I2C_REPORT_IRQ_EN BIT(8)
+
+enum {
+ I2C_MODE_STANDARD,
+ I2C_MODE_FAST,
+ I2C_MODE_FAST_PLUS,
+};
+
+enum cci_i2c_queue_t {
+ QUEUE_0,
+ QUEUE_1
+};
+
+struct hw_params {
+ u16 thigh; /* HIGH period of the SCL clock in clock ticks */
+ u16 tlow; /* LOW period of the SCL clock */
+ u16 tsu_sto; /* set-up time for STOP condition */
+ u16 tsu_sta; /* set-up time for a repeated START condition */
+ u16 thd_dat; /* data hold time */
+ u16 thd_sta; /* hold time (repeated) START condition */
+ u16 tbuf; /* bus free time between a STOP and START condition */
+ u8 scl_stretch_en;
+ u16 trdhld;
+ u16 tsp; /* pulse width of spikes suppressed by the input filter */
+};
+
+struct cci;
+
+struct cci_master {
+ struct i2c_adapter adap;
+ u16 master;
+ u8 mode;
+ int status;
+ struct completion irq_complete;
+ struct cci *cci;
+};
+
+struct cci_data {
+ unsigned int num_masters;
+ struct i2c_adapter_quirks quirks;
+ u16 queue_size[NUM_QUEUES];
+ unsigned long cci_clk_rate;
+ struct hw_params params[3];
+};
+
+struct cci {
+ struct device *dev;
+ void __iomem *base;
+ unsigned int irq;
+ const struct cci_data *data;
+ struct clk_bulk_data *clocks;
+ int nclocks;
+ struct cci_master master[NUM_MASTERS];
+};
+
+static irqreturn_t cci_isr(int irq, void *dev)
+{
+ struct cci *cci = dev;
+ u32 val, reset = 0;
+ int ret = IRQ_NONE;
+
+ val = readl(cci->base + CCI_IRQ_STATUS_0);
+ writel(val, cci->base + CCI_IRQ_CLEAR_0);
+ writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);
+
+ if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) {
+ complete(&cci->master[0].irq_complete);
+ if (cci->master[1].master)
+ complete(&cci->master[1].irq_complete);
+ ret = IRQ_HANDLED;
+ }
+
+ if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE ||
+ val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT ||
+ val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) {
+ cci->master[0].status = 0;
+ complete(&cci->master[0].irq_complete);
+ ret = IRQ_HANDLED;
+ }
+
+ if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE ||
+ val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT ||
+ val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) {
+ cci->master[1].status = 0;
+ complete(&cci->master[1].irq_complete);
+ ret = IRQ_HANDLED;
+ }
+
+ if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) {
+ reset = CCI_RESET_CMD_M0_MASK;
+ ret = IRQ_HANDLED;
+ }
+
+ if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) {
+ reset = CCI_RESET_CMD_M1_MASK;
+ ret = IRQ_HANDLED;
+ }
+
+ if (unlikely(reset))
+ writel(reset, cci->base + CCI_RESET_CMD);
+
+ if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) {
+ dev_err_ratelimited(cci->dev, "Master 0 error 0x%08x\n", val);
+ cci->master[0].status = -EIO;
+ writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ);
+ ret = IRQ_HANDLED;
+ }
+
+ if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) {
+ dev_err_ratelimited(cci->dev, "Master 1 error 0x%08x\n", val);
+ cci->master[1].status = -EIO;
+ writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
+ ret = IRQ_HANDLED;
+ }
+
+ return ret;
+}
+
+static int cci_halt(struct cci *cci, u8 master_num)
+{
+ struct cci_master *master;
+ u32 val;
+
+ if (master_num > 1) {
+ dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num);
+ return -EINVAL;
+ }
+
+ val = BIT(master_num);
+ master = &cci->master[master_num];
+
+ reinit_completion(&master->irq_complete);
+ writel(val, cci->base + CCI_HALT_REQ);
+
+ if (!wait_for_completion_timeout(&master->irq_complete, CCI_TIMEOUT)) {
+ dev_err(cci->dev, "CCI halt timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int cci_reset(struct cci *cci)
+{
+ /*
+ * we reset the whole controller, here and for implicity use
+ * master[0].xxx for waiting on it.
+ */
+ reinit_completion(&cci->master[0].irq_complete);
+ writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD);
+
+ if (!wait_for_completion_timeout(&cci->master[0].irq_complete,
+ CCI_TIMEOUT)) {
+ dev_err(cci->dev, "CCI reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int cci_init(struct cci *cci)
+{
+ u32 val = CCI_IRQ_MASK_0_I2C_M0_RD_DONE |
+ CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT |
+ CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT |
+ CCI_IRQ_MASK_0_I2C_M1_RD_DONE |
+ CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT |
+ CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT |
+ CCI_IRQ_MASK_0_RST_DONE_ACK |
+ CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK |
+ CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK |
+ CCI_IRQ_MASK_0_I2C_M0_ERROR |
+ CCI_IRQ_MASK_0_I2C_M1_ERROR;
+ int i;
+
+ writel(val, cci->base + CCI_IRQ_MASK_0);
+
+ for (i = 0; i < cci->data->num_masters; i++) {
+ int mode = cci->master[i].mode;
+ const struct hw_params *hw = &cci->data->params[mode];
+
+ val = hw->thigh << 16 | hw->tlow;
+ writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));;
+
+ val = hw->tsu_sto << 16 | hw->tsu_sta;
+ writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i));
+
+ val = hw->thd_dat << 16 | hw->thd_sta;
+ writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i));
+
+ val = hw->tbuf;
+ writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i));
+
+ val = hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp;
+ writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i));
+ }
+
+ return 0;
+}
+
+static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
+{
+ u32 val;
+ int ret;
+
+ val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
+ writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
+
+ reinit_completion(&cci->master[master].irq_complete);
+ val = BIT(master * 2 + queue);
+ writel(val, cci->base + CCI_QUEUE_START);
+
+ if (!wait_for_completion_timeout(&cci->master[master].irq_complete,
+ CCI_TIMEOUT)) {
+ dev_err(cci->dev, "master %d queue %d timeout\n",
+ master, queue);
+ cci_reset(cci);
+ cci_init(cci);
+ return -ETIMEDOUT;
+ }
+
+ ret = cci->master[master].status;
+ if (ret < 0)
+ dev_err(cci->dev, "master %d queue %d error %d\n",
+ master, queue, ret);
+
+ return ret;
+}
+
+static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
+{
+ u32 val;
+
+ val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
+ if (val == cci->data->queue_size[queue])
+ return -EINVAL;
+
+ if (!val)
+ return 0;
+
+ val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
+ writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
+
+ return cci_run_queue(cci, master, queue);
+}
+
+static int cci_i2c_read(struct cci *cci, u16 master,
+ u16 addr, u8 *buf, u16 len)
+{
+ u32 val, words_read, words_exp;
+ u8 queue = QUEUE_1;
+ int i, index = 0, ret;
+ bool first = true;
+
+ /*
+ * Call validate queue to make sure queue is empty before starting.
+ * This is to avoid overflow / underflow of queue.
+ */
+ ret = cci_validate_queue(cci, master, queue);
+ if (ret < 0)
+ return ret;
+
+ val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
+ writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
+
+ val = CCI_I2C_READ | len << 4;
+ writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
+
+ ret = cci_run_queue(cci, master, queue);
+ if (ret < 0)
+ return ret;
+
+ words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master));
+ words_exp = len / 4 + 1;
+ if (words_read != words_exp) {
+ dev_err(cci->dev, "words read = %d, words expected = %d\n",
+ words_read, words_exp);
+ return -EIO;
+ }
+
+ do {
+ val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master));
+
+ for (i = 0; i < 4 && index < len; i++) {
+ if (first) {
+ first = false;
+ continue;
+ }
+ buf[index++] = (val >> (i * 8)) & 0xff;
+ }
+ } while (--words_read);
+
+ return 0;
+}
+
+static int cci_i2c_write(struct cci *cci, u16 master,
+ u16 addr, u8 *buf, u16 len)
+{
+ u8 queue = QUEUE_0;
+ u8 load[12] = { 0 };
+ int i = 0, j, ret;
+ u32 val;
+
+ /*
+ * Call validate queue to make sure queue is empty before starting.
+ * This is to avoid overflow / underflow of queue.
+ */
+ ret = cci_validate_queue(cci, master, queue);
+ if (ret < 0)
+ return ret;
+
+ val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
+ writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
+
+ load[i++] = CCI_I2C_WRITE | len << 4;
+
+ for (j = 0; j < len; j++)
+ load[i++] = buf[j];
+
+ for (j = 0; j < i; j += 4) {
+ val = load[j];
+ val |= load[j + 1] << 8;
+ val |= load[j + 2] << 16;
+ val |= load[j + 3] << 24;
+ writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
+ }
+
+ val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
+ writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
+
+ return cci_run_queue(cci, master, queue);
+}
+
+static int cci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+ struct cci_master *cci_master = i2c_get_adapdata(adap);
+ struct cci *cci = cci_master->cci;
+ int i, ret;
+
+ ret = pm_runtime_get_sync(cci->dev);
+ if (ret < 0)
+ goto err;
+
+ for (i = 0; i < num; i++) {
+ if (msgs[i].flags & I2C_M_RD)
+ ret = cci_i2c_read(cci, cci_master->master,
+ msgs[i].addr, msgs[i].buf,
+ msgs[i].len);
+ else
+ ret = cci_i2c_write(cci, cci_master->master,
+ msgs[i].addr, msgs[i].buf,
+ msgs[i].len);
+
+ if (ret < 0) {
+ dev_err(cci->dev, "cci i2c xfer error %d", ret);
+ break;
+ }
+ }
+
+ if (!ret)
+ ret = num;
+
+err:
+ pm_runtime_mark_last_busy(cci->dev);
+ pm_runtime_put_autosuspend(cci->dev);
+
+ return ret;
+}
+
+static u32 cci_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C;
+}
+
+static const struct i2c_algorithm cci_algo = {
+ .master_xfer = cci_xfer,
+ .functionality = cci_func,
+};
+
+static int cci_enable_clocks(struct cci *cci)
+{
+ int ret;
+
+ ret = clk_bulk_prepare_enable(cci->nclocks, cci->clocks);
+ if (ret < 0)
+ dev_err(cci->dev, "Bulk clock prepare failed: %d\n", ret);
+
+ return ret;
+}
+
+static void cci_disable_clocks(struct cci *cci)
+{
+ clk_bulk_disable_unprepare(cci->nclocks, cci->clocks);
+}
+
+#ifdef CONFIG_PM
+static int cci_suspend_runtime(struct device *dev)
+{
+ struct cci *cci = dev_get_drvdata(dev);
+
+ dev_dbg(dev, "Supend invoked\n");
+ cci_disable_clocks(cci);
+ return 0;
+}
+
+static int cci_resume_runtime(struct device *dev)
+{
+ struct cci *cci = dev_get_drvdata(dev);
+ int ret;
+
+ dev_dbg(dev, "Resume invoked\n");
+ ret = cci_enable_clocks(cci);
+ if (ret)
+ return ret;
+
+ cci_init(cci);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static int cci_suspend(struct device *dev)
+{
+ if (!pm_runtime_suspended(dev))
+ return cci_suspend_runtime(dev);
+
+ return 0;
+}
+
+static int cci_resume(struct device *dev)
+{
+ cci_resume_runtime(dev);
+ pm_runtime_mark_last_busy(dev);
+ pm_request_autosuspend(dev);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops qcom_cci_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(cci_suspend, cci_resume)
+ SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL)
+};
+
+static int cci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *of_node = NULL;
+ unsigned long cci_clk_rate = 0;
+ struct resource *r;
+ struct cci *cci;
+ int ret = 0, i;
+ u32 val;
+
+ cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL);
+ if (!cci)
+ return -ENOMEM;
+
+ cci->dev = dev;
+ platform_set_drvdata(pdev, cci);
+ cci->data = device_get_match_data(&pdev->dev);
+ if (!cci->data) {
+ dev_err(&pdev->dev, "Driver data is null, abort\n");
+ return -EIO;
+ }
+
+ for (i = 0; i < cci->data->num_masters; i++) {
+ cci->master[i].adap.quirks = &cci->data->quirks;
+ cci->master[i].adap.algo = &cci_algo;
+ cci->master[i].adap.dev.parent = cci->dev;
+ cci->master[i].master = i;
+ cci->master[i].cci = cci;
+
+ i2c_set_adapdata(&cci->master[i].adap, &cci->master[i]);
+ snprintf(cci->master[i].adap.name,
+ sizeof(cci->master[i].adap.name),
+ "Qualcomm Camera Control Interface: %d", i);
+
+ /* find the child node for i2c-bus as we are on cci node */
+ of_node = of_get_next_available_child(dev->of_node, of_node);
+ if (!of_node) {
+ dev_err(dev, "Missing i2c-bus@%d child node\n", i);
+ return -EINVAL;
+ }
+ cci->master[i].adap.dev.of_node = of_node;
+
+ cci->master[i].mode = I2C_MODE_STANDARD;
+ ret = of_property_read_u32(of_node, "clock-frequency", &val);
+ if (!ret) {
+ if (val == 400000)
+ cci->master[i].mode = I2C_MODE_FAST;
+ else if (val == 1000000)
+ cci->master[i].mode = I2C_MODE_FAST_PLUS;
+ }
+
+ init_completion(&cci->master[i].irq_complete);
+ }
+
+ /* Memory */
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ cci->base = devm_ioremap_resource(dev, r);
+ if (IS_ERR(cci->base))
+ return PTR_ERR(cci->base);
+
+ /* Interrupt */
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "missing IRQ: %d\n", ret);
+ return ret;
+ }
+ cci->irq = ret;
+
+ ret = devm_request_irq(dev, cci->irq, cci_isr,
+ IRQF_TRIGGER_RISING, dev_name(dev), cci);
+ if (ret < 0) {
+ dev_err(dev, "request_irq failed, ret: %d\n", ret);
+ return ret;
+ }
+
+ disable_irq(cci->irq);
+
+ /* Clocks */
+
+ ret = devm_clk_bulk_get_all(dev, &cci->clocks);
+ if (ret < 1) {
+ dev_err(dev, "failed to get clocks %d\n", ret);
+ return ret;
+ }
+ cci->nclocks = ret;
+
+ /* Retrieve CCI clock rate */
+ for (i = 0; i < cci->nclocks; i++) {
+ if (!strncmp(cci->clocks[i].id, "cci", 4)) {
+ cci_clk_rate = clk_get_rate(cci->clocks[i].clk);
+ break;
+ }
+ }
+
+ if (cci_clk_rate != cci->data->cci_clk_rate) {
+ /* cci clock set by the bootloader or via assigned clock rate
+ * in DT.
+ */
+ dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n",
+ cci_clk_rate, cci->data->cci_clk_rate);
+ }
+
+ ret = cci_enable_clocks(cci);
+ if (ret < 0)
+ return ret;
+
+ val = readl_relaxed(cci->base + CCI_HW_VERSION);
+ dev_info(dev, "%s: CCI HW version = 0x%08x", __func__, val);
+
+ enable_irq(cci->irq);
+
+ ret = cci_reset(cci);
+ if (ret < 0)
+ goto error;
+
+ ret = cci_init(cci);
+ if (ret < 0)
+ goto error;
+
+ for (i = 0; i < cci->data->num_masters; i++) {
+ ret = i2c_add_adapter(&cci->master[i].adap);
+ if (ret < 0)
+ goto error_i2c;
+ }
+
+ pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ return 0;
+
+error_i2c:
+ for (; i >= 0; i--)
+ i2c_del_adapter(&cci->master[i].adap);
+error:
+ disable_irq(cci->irq);
+ cci_disable_clocks(cci);
+
+ return ret;
+}
+
+static int cci_remove(struct platform_device *pdev)
+{
+ struct cci *cci = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < cci->data->num_masters; i++) {
+ i2c_del_adapter(&cci->master[i].adap);
+ cci_halt(cci, i);
+ }
+
+ disable_irq(cci->irq);
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+
+ return 0;
+}
+
+static const struct cci_data cci_v1_data = {
+ .num_masters = 1,
+ .queue_size = { 64, 16 },
+ .quirks = {
+ .max_write_len = 10,
+ .max_read_len = 12,
+ },
+ .cci_clk_rate = 19200000,
+ .params[I2C_MODE_STANDARD] = {
+ .thigh = 78,
+ .tlow = 114,
+ .tsu_sto = 28,
+ .tsu_sta = 28,
+ .thd_dat = 10,
+ .thd_sta = 77,
+ .tbuf = 118,
+ .scl_stretch_en = 0,
+ .trdhld = 6,
+ .tsp = 1
+ },
+ .params[I2C_MODE_FAST] = {
+ .thigh = 20,
+ .tlow = 28,
+ .tsu_sto = 21,
+ .tsu_sta = 21,
+ .thd_dat = 13,
+ .thd_sta = 18,
+ .tbuf = 32,
+ .scl_stretch_en = 0,
+ .trdhld = 6,
+ .tsp = 3
+ },
+};
+
+static const struct cci_data cci_v2_data = {
+ .num_masters = 2,
+ .queue_size = { 64, 16 },
+ .quirks = {
+ .max_write_len = 11,
+ .max_read_len = 12,
+ },
+ .cci_clk_rate = 37500000,
+ .params[I2C_MODE_STANDARD] = {
+ .thigh = 201,
+ .tlow = 174,
+ .tsu_sto = 204,
+ .tsu_sta = 231,
+ .thd_dat = 22,
+ .thd_sta = 162,
+ .tbuf = 227,
+ .scl_stretch_en = 0,
+ .trdhld = 6,
+ .tsp = 3
+ },
+ .params[I2C_MODE_FAST] = {
+ .thigh = 38,
+ .tlow = 56,
+ .tsu_sto = 40,
+ .tsu_sta = 40,
+ .thd_dat = 22,
+ .thd_sta = 35,
+ .tbuf = 62,
+ .scl_stretch_en = 0,
+ .trdhld = 6,
+ .tsp = 3
+ },
+ .params[I2C_MODE_FAST_PLUS] = {
+ .thigh = 16,
+ .tlow = 22,
+ .tsu_sto = 17,
+ .tsu_sta = 18,
+ .thd_dat = 16,
+ .thd_sta = 15,
+ .tbuf = 24,
+ .scl_stretch_en = 0,
+ .trdhld = 3,
+ .tsp = 3
+ },
+};
+
+static const struct of_device_id cci_dt_match[] = {
+ { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data},
+ { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data},
+ { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data},
+ {}
+};
+MODULE_DEVICE_TABLE(of, cci_dt_match);
+
+static struct platform_driver qcom_cci_driver = {
+ .probe = cci_probe,
+ .remove = cci_remove,
+ .driver = {
+ .name = "i2c-qcom-cci",
+ .of_match_table = cci_dt_match,
+ .pm = &qcom_cci_pm,
+ },
+};
+
+module_platform_driver(qcom_cci_driver);
+
+MODULE_DESCRIPTION("Qualcomm Camera Control Interface driver");
+MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
+MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller 2020-03-04 16:52 [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Loic Poulain @ 2020-03-04 16:52 ` Loic Poulain 2020-03-04 19:05 ` Robert Foss 2020-03-04 16:52 ` [PATCH v3 3/3] arm64: dts: msm8916: Add CCI node Loic Poulain ` (3 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Loic Poulain @ 2020-03-04 16:52 UTC (permalink / raw) To: wsa Cc: vkoul, bjorn.andersson, robert.foss, linux-arm-msm, linux-i2c, Todor Tomov From: Todor Tomov <todor.tomov@linaro.org> Add DT binding document for Qualcomm Camera Control Interface (CCI) I2C controller. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> --- v2: Fix subnode properties, remove mandatory clock names v3: Add sdm845 compatible string .../devicetree/bindings/i2c/i2c-qcom-cci.txt | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt new file mode 100644 index 0000000..c6668b7 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt @@ -0,0 +1,92 @@ +Qualcomm Camera Control Interface (CCI) I2C controller + +PROPERTIES: + +- compatible: + Usage: required + Value type: <string> + Definition: must be one of: + "qcom,msm8916-cci" + "qcom,msm8996-cci" + "qcom,sdm845-cci" + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: base address CCI I2C controller and length of memory + mapped region. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: specifies the CCI I2C interrupt. The format of the + specifier is defined by the binding document describing + the node's interrupt parent. + +- clocks: + Usage: required + Value type: <prop-encoded-array> + Definition: a list of phandle, should contain an entry for each + entries in clock-names. + +- clock-names + Usage: required + Value type: <string> + Definition: a list of clock names, must include "cci" clock. + +- power-domains + Usage: required for "qcom,msm8996-cci" + Value type: <prop-encoded-array> + Definition: + +SUBNODES: + +The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and +sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1". + +PROPERTIES: + +- reg: + Usage: required + Value type: <u32> + Definition: Index of the CCI bus/master + +- clock-frequency: + Usage: optional + Value type: <u32> + Definition: Desired I2C bus clock frequency in Hz, defaults to 100 + kHz if omitted. + +Example: + + cci@a0c000 { + compatible = "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa0c000 0x1000>; + interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, + <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "mmss_mmagic_ahb", + "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + + i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller 2020-03-04 16:52 ` [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Loic Poulain @ 2020-03-04 19:05 ` Robert Foss 2020-03-04 19:44 ` Robert Foss 0 siblings, 1 reply; 16+ messages in thread From: Robert Foss @ 2020-03-04 19:05 UTC (permalink / raw) To: Loic Poulain Cc: wsa, vkoul, Bjorn Andersson, linux-arm-msm, linux-i2c, Todor Tomov Signed-off-by: Robert Foss <robert.foss@linaro.org> On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@linaro.org> wrote: > > From: Todor Tomov <todor.tomov@linaro.org> > > Add DT binding document for Qualcomm Camera Control Interface (CCI) > I2C controller. > > Signed-off-by: Todor Tomov <todor.tomov@linaro.org> > Signed-off-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > v2: Fix subnode properties, remove mandatory clock names > v3: Add sdm845 compatible string > > .../devicetree/bindings/i2c/i2c-qcom-cci.txt | 92 ++++++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt > new file mode 100644 > index 0000000..c6668b7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt > @@ -0,0 +1,92 @@ > +Qualcomm Camera Control Interface (CCI) I2C controller > + > +PROPERTIES: > + > +- compatible: > + Usage: required > + Value type: <string> > + Definition: must be one of: > + "qcom,msm8916-cci" > + "qcom,msm8996-cci" > + "qcom,sdm845-cci" > + > +- reg > + Usage: required > + Value type: <prop-encoded-array> > + Definition: base address CCI I2C controller and length of memory > + mapped region. > + > +- interrupts: > + Usage: required > + Value type: <prop-encoded-array> > + Definition: specifies the CCI I2C interrupt. The format of the > + specifier is defined by the binding document describing > + the node's interrupt parent. > + > +- clocks: > + Usage: required > + Value type: <prop-encoded-array> > + Definition: a list of phandle, should contain an entry for each > + entries in clock-names. > + > +- clock-names > + Usage: required > + Value type: <string> > + Definition: a list of clock names, must include "cci" clock. > + > +- power-domains > + Usage: required for "qcom,msm8996-cci" > + Value type: <prop-encoded-array> > + Definition: > + > +SUBNODES: > + > +The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and > +sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1". > + > +PROPERTIES: > + > +- reg: > + Usage: required > + Value type: <u32> > + Definition: Index of the CCI bus/master > + > +- clock-frequency: > + Usage: optional > + Value type: <u32> > + Definition: Desired I2C bus clock frequency in Hz, defaults to 100 > + kHz if omitted. > + > +Example: > + > + cci@a0c000 { > + compatible = "qcom,msm8996-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xa0c000 0x1000>; > + interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; > + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, > + <&mmcc CAMSS_TOP_AHB_CLK>, > + <&mmcc CAMSS_CCI_AHB_CLK>, > + <&mmcc CAMSS_CCI_CLK>, > + <&mmcc CAMSS_AHB_CLK>; > + clock-names = "mmss_mmagic_ahb", > + "camss_top_ahb", > + "cci_ahb", > + "cci", > + "camss_ahb"; > + > + i2c-bus@0 { > + reg = <0>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c-bus@1 { > + reg = <1>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller 2020-03-04 19:05 ` Robert Foss @ 2020-03-04 19:44 ` Robert Foss 0 siblings, 0 replies; 16+ messages in thread From: Robert Foss @ 2020-03-04 19:44 UTC (permalink / raw) To: Loic Poulain Cc: wsa, vkoul, Bjorn Andersson, linux-arm-msm, linux-i2c, Todor Tomov Let me revise that, feel free to add by r-b. Reviewed-by: Robert Foss <robert.foss@linaro.org> On Wed, 4 Mar 2020 at 20:05, Robert Foss <robert.foss@linaro.org> wrote: > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@linaro.org> wrote: > > > > From: Todor Tomov <todor.tomov@linaro.org> > > > > Add DT binding document for Qualcomm Camera Control Interface (CCI) > > I2C controller. > > > > Signed-off-by: Todor Tomov <todor.tomov@linaro.org> > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > v2: Fix subnode properties, remove mandatory clock names > > v3: Add sdm845 compatible string > > > > .../devicetree/bindings/i2c/i2c-qcom-cci.txt | 92 ++++++++++++++++++++++ > > 1 file changed, 92 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt > > > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt > > new file mode 100644 > > index 0000000..c6668b7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt > > @@ -0,0 +1,92 @@ > > +Qualcomm Camera Control Interface (CCI) I2C controller > > + > > +PROPERTIES: > > + > > +- compatible: > > + Usage: required > > + Value type: <string> > > + Definition: must be one of: > > + "qcom,msm8916-cci" > > + "qcom,msm8996-cci" > > + "qcom,sdm845-cci" > > + > > +- reg > > + Usage: required > > + Value type: <prop-encoded-array> > > + Definition: base address CCI I2C controller and length of memory > > + mapped region. > > + > > +- interrupts: > > + Usage: required > > + Value type: <prop-encoded-array> > > + Definition: specifies the CCI I2C interrupt. The format of the > > + specifier is defined by the binding document describing > > + the node's interrupt parent. > > + > > +- clocks: > > + Usage: required > > + Value type: <prop-encoded-array> > > + Definition: a list of phandle, should contain an entry for each > > + entries in clock-names. > > + > > +- clock-names > > + Usage: required > > + Value type: <string> > > + Definition: a list of clock names, must include "cci" clock. > > + > > +- power-domains > > + Usage: required for "qcom,msm8996-cci" > > + Value type: <prop-encoded-array> > > + Definition: > > + > > +SUBNODES: > > + > > +The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and > > +sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1". > > + > > +PROPERTIES: > > + > > +- reg: > > + Usage: required > > + Value type: <u32> > > + Definition: Index of the CCI bus/master > > + > > +- clock-frequency: > > + Usage: optional > > + Value type: <u32> > > + Definition: Desired I2C bus clock frequency in Hz, defaults to 100 > > + kHz if omitted. > > + > > +Example: > > + > > + cci@a0c000 { > > + compatible = "qcom,msm8996-cci"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0xa0c000 0x1000>; > > + interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; > > + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, > > + <&mmcc CAMSS_TOP_AHB_CLK>, > > + <&mmcc CAMSS_CCI_AHB_CLK>, > > + <&mmcc CAMSS_CCI_CLK>, > > + <&mmcc CAMSS_AHB_CLK>; > > + clock-names = "mmss_mmagic_ahb", > > + "camss_top_ahb", > > + "cci_ahb", > > + "cci", > > + "camss_ahb"; > > + > > + i2c-bus@0 { > > + reg = <0>; > > + clock-frequency = <400000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + i2c-bus@1 { > > + reg = <1>; > > + clock-frequency = <400000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + }; > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] arm64: dts: msm8916: Add CCI node 2020-03-04 16:52 [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Loic Poulain 2020-03-04 16:52 ` [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Loic Poulain @ 2020-03-04 16:52 ` Loic Poulain 2020-03-04 19:08 ` Robert Foss 2020-03-04 19:04 ` [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Robert Foss ` (2 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Loic Poulain @ 2020-03-04 16:52 UTC (permalink / raw) To: wsa Cc: vkoul, bjorn.andersson, robert.foss, linux-arm-msm, linux-i2c, Loic Poulain The msm8916 CCI controller provides one CCI/I2C bus. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> --- v2: add this patch in the series v3: add only cci node for now arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8686e10..985cb5f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1451,6 +1451,33 @@ }; }; + cci@1b0c000 { + compatible = "qcom,msm8916-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1b0c000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@1b00000 { compatible = "qcom,msm8916-camss"; reg = <0x1b0ac00 0x200>, -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/3] arm64: dts: msm8916: Add CCI node 2020-03-04 16:52 ` [PATCH v3 3/3] arm64: dts: msm8916: Add CCI node Loic Poulain @ 2020-03-04 19:08 ` Robert Foss 2020-03-04 19:45 ` Robert Foss 0 siblings, 1 reply; 16+ messages in thread From: Robert Foss @ 2020-03-04 19:08 UTC (permalink / raw) To: Loic Poulain; +Cc: wsa, vkoul, Bjorn Andersson, linux-arm-msm, linux-i2c Due to lack of suitable hardware, I currently can't test the msm8916, but I have written similar DT nodes for the sdm845, which indeed work properly. Signed-off-by: Robert Foss <robert.foss@linaro.org> On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@linaro.org> wrote: > > The msm8916 CCI controller provides one CCI/I2C bus. > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> > --- > v2: add this patch in the series > v3: add only cci node for now > > arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 8686e10..985cb5f 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -1451,6 +1451,33 @@ > }; > }; > > + cci@1b0c000 { > + compatible = "qcom,msm8916-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1b0c000 0x1000>; > + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; > + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, > + <&gcc GCC_CAMSS_CCI_AHB_CLK>, > + <&gcc GCC_CAMSS_CCI_CLK>, > + <&gcc GCC_CAMSS_AHB_CLK>; > + clock-names = "camss_top_ahb", "cci_ahb", > + "cci", "camss_ahb"; > + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, > + <&gcc GCC_CAMSS_CCI_CLK>; > + assigned-clock-rates = <80000000>, <19200000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&cci0_default>; > + status = "disabled"; > + > + cci0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > camss: camss@1b00000 { > compatible = "qcom,msm8916-camss"; > reg = <0x1b0ac00 0x200>, > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/3] arm64: dts: msm8916: Add CCI node 2020-03-04 19:08 ` Robert Foss @ 2020-03-04 19:45 ` Robert Foss 0 siblings, 0 replies; 16+ messages in thread From: Robert Foss @ 2020-03-04 19:45 UTC (permalink / raw) To: Loic Poulain; +Cc: wsa, vkoul, Bjorn Andersson, linux-arm-msm, linux-i2c I've had looked this too, and please ignore my sob, and feel free to add my r-b. Reviewed-by: Robert Foss <robert.foss@linaro.org> On Wed, 4 Mar 2020 at 20:08, Robert Foss <robert.foss@linaro.org> wrote: > > Due to lack of suitable hardware, I currently can't test the msm8916, > but I have written similar DT nodes for the sdm845, which indeed work properly. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@linaro.org> wrote: > > > > The msm8916 CCI controller provides one CCI/I2C bus. > > > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> > > --- > > v2: add this patch in the series > > v3: add only cci node for now > > > > arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++ > > 1 file changed, 27 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > index 8686e10..985cb5f 100644 > > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > @@ -1451,6 +1451,33 @@ > > }; > > }; > > > > + cci@1b0c000 { > > + compatible = "qcom,msm8916-cci"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x1b0c000 0x1000>; > > + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; > > + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, > > + <&gcc GCC_CAMSS_CCI_AHB_CLK>, > > + <&gcc GCC_CAMSS_CCI_CLK>, > > + <&gcc GCC_CAMSS_AHB_CLK>; > > + clock-names = "camss_top_ahb", "cci_ahb", > > + "cci", "camss_ahb"; > > + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, > > + <&gcc GCC_CAMSS_CCI_CLK>; > > + assigned-clock-rates = <80000000>, <19200000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&cci0_default>; > > + status = "disabled"; > > + > > + cci0: i2c-bus@0 { > > + reg = <0>; > > + clock-frequency = <400000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + }; > > + > > camss: camss@1b00000 { > > compatible = "qcom,msm8916-camss"; > > reg = <0x1b0ac00 0x200>, > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver 2020-03-04 16:52 [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Loic Poulain 2020-03-04 16:52 ` [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Loic Poulain 2020-03-04 16:52 ` [PATCH v3 3/3] arm64: dts: msm8916: Add CCI node Loic Poulain @ 2020-03-04 19:04 ` Robert Foss 2020-03-05 6:25 ` kbuild test robot 2020-03-05 6:25 ` kbuild test robot 4 siblings, 0 replies; 16+ messages in thread From: Robert Foss @ 2020-03-04 19:04 UTC (permalink / raw) To: Loic Poulain Cc: wsa, vkoul, Bjorn Andersson, linux-arm-msm, linux-i2c, Todor Tomov Thanks for submitting this. I've built & run this series on the SDM845/db845c, and I can confirm that camera modules (ov7251) probes and comes up correctly. Tested-by: Robert Foss <robert.foss@linaro.org> On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@linaro.org> wrote: > > This commit adds I2C bus support for the Camera Control Interface > (CCI) I2C controller found on the Qualcomm SoC processors. This I2C > controller supports two masters and they are registered to the core. > > CCI versions supported in the driver are MSM8916 and MSM8996. Add SDM845 to the commit comment. > > This is a rework of the patch posted by Vinod: > https://patchwork.kernel.org/patch/10569961/ > > With additional fixes + most of the comments addressed. > > Signed-off-by: Todor Tomov <todor.tomov@linaro.org> > Signed-off-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> > --- > v2: Remove clock rates config from driver (done via assigned clock) > Added CCI timeout recovery from Ricardo's patch: > https://www.spinics.net/lists/linux-i2c/msg36973.html > v3: add sdm845 support > rework cci_init function > > drivers/i2c/busses/Kconfig | 10 + > drivers/i2c/busses/Makefile | 1 + > drivers/i2c/busses/i2c-qcom-cci.c | 787 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 798 insertions(+) > create mode 100644 drivers/i2c/busses/i2c-qcom-cci.c > > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig > index 6a0aa76..807a052 100644 > --- a/drivers/i2c/busses/Kconfig > +++ b/drivers/i2c/busses/Kconfig > @@ -894,6 +894,16 @@ config I2C_QCOM_GENI > This driver can also be built as a module. If so, the module > will be called i2c-qcom-geni. > > +config I2C_QCOM_CCI > + tristate "Qualcomm Camera Control Interface" > + depends on ARCH_QCOM || COMPILE_TEST > + help > + If you say yes to this option, support will be included for the > + built-in camera control interface on the Qualcomm SoCs. > + > + This driver can also be built as a module. If so, the module > + will be called i2c-qcom-cci. > + > config I2C_QUP > tristate "Qualcomm QUP based I2C controller" > depends on ARCH_QCOM > diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile > index 3ab8aeb..9028b77 100644 > --- a/drivers/i2c/busses/Makefile > +++ b/drivers/i2c/busses/Makefile > @@ -92,6 +92,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o > obj-$(CONFIG_I2C_PXA) += i2c-pxa.o > obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o > obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o > +obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o > obj-$(CONFIG_I2C_QUP) += i2c-qup.o > obj-$(CONFIG_I2C_RIIC) += i2c-riic.o > obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o > diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c > new file mode 100644 > index 0000000..2ef472e > --- /dev/null > +++ b/drivers/i2c/busses/i2c-qcom-cci.c > @@ -0,0 +1,787 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. > +// Copyright (c) 2017-19 Linaro Limited. > + > +#include <linux/clk.h> > +#include <linux/completion.h> > +#include <linux/i2c.h> > +#include <linux/io.h> > +#include <linux/interrupt.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > + > +#define CCI_HW_VERSION 0x0 > +#define CCI_RESET_CMD 0x004 > +#define CCI_RESET_CMD_MASK 0x0f73f3f7 > +#define CCI_RESET_CMD_M0_MASK 0x000003f1 > +#define CCI_RESET_CMD_M1_MASK 0x0003f001 > +#define CCI_QUEUE_START 0x008 > +#define CCI_HALT_REQ 0x034 > +#define CCI_HALT_REQ_I2C_M0_Q0Q1 BIT(0) > +#define CCI_HALT_REQ_I2C_M1_Q0Q1 BIT(1) > + > +#define CCI_I2C_Mm_SCL_CTL(m) (0x100 + 0x100 * (m)) > +#define CCI_I2C_Mm_SDA_CTL_0(m) (0x104 + 0x100 * (m)) > +#define CCI_I2C_Mm_SDA_CTL_1(m) (0x108 + 0x100 * (m)) > +#define CCI_I2C_Mm_SDA_CTL_2(m) (0x10c + 0x100 * (m)) > +#define CCI_I2C_Mm_MISC_CTL(m) (0x110 + 0x100 * (m)) > + > +#define CCI_I2C_Mm_READ_DATA(m) (0x118 + 0x100 * (m)) > +#define CCI_I2C_Mm_READ_BUF_LEVEL(m) (0x11c + 0x100 * (m)) > +#define CCI_I2C_Mm_Qn_EXEC_WORD_CNT(m, n) (0x300 + 0x200 * (m) + 0x100 * (n)) > +#define CCI_I2C_Mm_Qn_CUR_WORD_CNT(m, n) (0x304 + 0x200 * (m) + 0x100 * (n)) > +#define CCI_I2C_Mm_Qn_CUR_CMD(m, n) (0x308 + 0x200 * (m) + 0x100 * (n)) > +#define CCI_I2C_Mm_Qn_REPORT_STATUS(m, n) (0x30c + 0x200 * (m) + 0x100 * (n)) > +#define CCI_I2C_Mm_Qn_LOAD_DATA(m, n) (0x310 + 0x200 * (m) + 0x100 * (n)) > + > +#define CCI_IRQ_GLOBAL_CLEAR_CMD 0xc00 > +#define CCI_IRQ_MASK_0 0xc04 > +#define CCI_IRQ_MASK_0_I2C_M0_RD_DONE BIT(0) > +#define CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT BIT(4) > +#define CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT BIT(8) > +#define CCI_IRQ_MASK_0_I2C_M1_RD_DONE BIT(12) > +#define CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT BIT(16) > +#define CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT BIT(20) > +#define CCI_IRQ_MASK_0_RST_DONE_ACK BIT(24) > +#define CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK BIT(25) > +#define CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK BIT(26) > +#define CCI_IRQ_MASK_0_I2C_M0_ERROR 0x18000ee6 > +#define CCI_IRQ_MASK_0_I2C_M1_ERROR 0x60ee6000 > +#define CCI_IRQ_CLEAR_0 0xc08 > +#define CCI_IRQ_STATUS_0 0xc0c > +#define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0) > +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4) > +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8) > +#define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12) > +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16) > +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20) > +#define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24) > +#define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25) > +#define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26) > +#define CCI_IRQ_STATUS_0_I2C_M0_ERROR 0x18000ee6 > +#define CCI_IRQ_STATUS_0_I2C_M1_ERROR 0x60ee6000 > + > +#define CCI_TIMEOUT (msecs_to_jiffies(100)) > +#define NUM_MASTERS 2 > +#define NUM_QUEUES 2 > + > +/* Max number of resources + 1 for a NULL terminator */ > +#define CCI_RES_MAX 6 > + > + > +#define CCI_I2C_SET_PARAM 1 > +#define CCI_I2C_REPORT 8 > +#define CCI_I2C_WRITE 9 > +#define CCI_I2C_READ 10 > + > +#define CCI_I2C_REPORT_IRQ_EN BIT(8) > + > +enum { > + I2C_MODE_STANDARD, > + I2C_MODE_FAST, > + I2C_MODE_FAST_PLUS, > +}; > + > +enum cci_i2c_queue_t { > + QUEUE_0, > + QUEUE_1 > +}; > + > +struct hw_params { > + u16 thigh; /* HIGH period of the SCL clock in clock ticks */ > + u16 tlow; /* LOW period of the SCL clock */ > + u16 tsu_sto; /* set-up time for STOP condition */ > + u16 tsu_sta; /* set-up time for a repeated START condition */ > + u16 thd_dat; /* data hold time */ > + u16 thd_sta; /* hold time (repeated) START condition */ > + u16 tbuf; /* bus free time between a STOP and START condition */ > + u8 scl_stretch_en; > + u16 trdhld; > + u16 tsp; /* pulse width of spikes suppressed by the input filter */ > +}; > + > +struct cci; > + > +struct cci_master { > + struct i2c_adapter adap; > + u16 master; > + u8 mode; > + int status; > + struct completion irq_complete; > + struct cci *cci; > +}; > + > +struct cci_data { > + unsigned int num_masters; > + struct i2c_adapter_quirks quirks; > + u16 queue_size[NUM_QUEUES]; > + unsigned long cci_clk_rate; > + struct hw_params params[3]; > +}; > + > +struct cci { > + struct device *dev; > + void __iomem *base; > + unsigned int irq; > + const struct cci_data *data; > + struct clk_bulk_data *clocks; > + int nclocks; > + struct cci_master master[NUM_MASTERS]; > +}; > + > +static irqreturn_t cci_isr(int irq, void *dev) > +{ > + struct cci *cci = dev; > + u32 val, reset = 0; > + int ret = IRQ_NONE; > + > + val = readl(cci->base + CCI_IRQ_STATUS_0); > + writel(val, cci->base + CCI_IRQ_CLEAR_0); > + writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); > + > + if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) { > + complete(&cci->master[0].irq_complete); > + if (cci->master[1].master) > + complete(&cci->master[1].irq_complete); > + ret = IRQ_HANDLED; > + } > + > + if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE || > + val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT || > + val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) { > + cci->master[0].status = 0; > + complete(&cci->master[0].irq_complete); > + ret = IRQ_HANDLED; > + } > + > + if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE || > + val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT || > + val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) { > + cci->master[1].status = 0; > + complete(&cci->master[1].irq_complete); > + ret = IRQ_HANDLED; > + } > + > + if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) { > + reset = CCI_RESET_CMD_M0_MASK; > + ret = IRQ_HANDLED; > + } > + > + if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) { > + reset = CCI_RESET_CMD_M1_MASK; > + ret = IRQ_HANDLED; > + } > + > + if (unlikely(reset)) > + writel(reset, cci->base + CCI_RESET_CMD); > + > + if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) { > + dev_err_ratelimited(cci->dev, "Master 0 error 0x%08x\n", val); > + cci->master[0].status = -EIO; > + writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ); > + ret = IRQ_HANDLED; > + } > + > + if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) { > + dev_err_ratelimited(cci->dev, "Master 1 error 0x%08x\n", val); > + cci->master[1].status = -EIO; > + writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ); > + ret = IRQ_HANDLED; > + } > + > + return ret; > +} > + > +static int cci_halt(struct cci *cci, u8 master_num) > +{ > + struct cci_master *master; > + u32 val; > + > + if (master_num > 1) { > + dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num); > + return -EINVAL; > + } > + > + val = BIT(master_num); > + master = &cci->master[master_num]; > + > + reinit_completion(&master->irq_complete); > + writel(val, cci->base + CCI_HALT_REQ); > + > + if (!wait_for_completion_timeout(&master->irq_complete, CCI_TIMEOUT)) { > + dev_err(cci->dev, "CCI halt timeout\n"); > + return -ETIMEDOUT; > + } > + > + return 0; > +} > + > +static int cci_reset(struct cci *cci) > +{ > + /* > + * we reset the whole controller, here and for implicity use > + * master[0].xxx for waiting on it. > + */ > + reinit_completion(&cci->master[0].irq_complete); > + writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD); > + > + if (!wait_for_completion_timeout(&cci->master[0].irq_complete, > + CCI_TIMEOUT)) { > + dev_err(cci->dev, "CCI reset timeout\n"); > + return -ETIMEDOUT; > + } > + > + return 0; > +} > + > +static int cci_init(struct cci *cci) > +{ > + u32 val = CCI_IRQ_MASK_0_I2C_M0_RD_DONE | > + CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT | > + CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT | > + CCI_IRQ_MASK_0_I2C_M1_RD_DONE | > + CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT | > + CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT | > + CCI_IRQ_MASK_0_RST_DONE_ACK | > + CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK | > + CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK | > + CCI_IRQ_MASK_0_I2C_M0_ERROR | > + CCI_IRQ_MASK_0_I2C_M1_ERROR; > + int i; > + > + writel(val, cci->base + CCI_IRQ_MASK_0); > + > + for (i = 0; i < cci->data->num_masters; i++) { > + int mode = cci->master[i].mode; > + const struct hw_params *hw = &cci->data->params[mode]; > + > + val = hw->thigh << 16 | hw->tlow; > + writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));; > + > + val = hw->tsu_sto << 16 | hw->tsu_sta; > + writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i)); > + > + val = hw->thd_dat << 16 | hw->thd_sta; > + writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i)); > + > + val = hw->tbuf; > + writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i)); > + > + val = hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp; > + writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i)); > + } > + > + return 0; > +} > + > +static int cci_run_queue(struct cci *cci, u8 master, u8 queue) > +{ > + u32 val; > + int ret; > + > + val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue)); > + writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue)); > + > + reinit_completion(&cci->master[master].irq_complete); > + val = BIT(master * 2 + queue); > + writel(val, cci->base + CCI_QUEUE_START); > + > + if (!wait_for_completion_timeout(&cci->master[master].irq_complete, > + CCI_TIMEOUT)) { > + dev_err(cci->dev, "master %d queue %d timeout\n", > + master, queue); > + cci_reset(cci); > + cci_init(cci); > + return -ETIMEDOUT; > + } > + > + ret = cci->master[master].status; > + if (ret < 0) > + dev_err(cci->dev, "master %d queue %d error %d\n", > + master, queue, ret); > + > + return ret; > +} > + > +static int cci_validate_queue(struct cci *cci, u8 master, u8 queue) > +{ > + u32 val; > + > + val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue)); > + if (val == cci->data->queue_size[queue]) > + return -EINVAL; > + > + if (!val) > + return 0; > + > + val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN; > + writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); > + > + return cci_run_queue(cci, master, queue); > +} > + > +static int cci_i2c_read(struct cci *cci, u16 master, > + u16 addr, u8 *buf, u16 len) > +{ > + u32 val, words_read, words_exp; > + u8 queue = QUEUE_1; > + int i, index = 0, ret; > + bool first = true; > + > + /* > + * Call validate queue to make sure queue is empty before starting. > + * This is to avoid overflow / underflow of queue. > + */ > + ret = cci_validate_queue(cci, master, queue); > + if (ret < 0) > + return ret; > + > + val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4; > + writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); > + > + val = CCI_I2C_READ | len << 4; > + writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); > + > + ret = cci_run_queue(cci, master, queue); > + if (ret < 0) > + return ret; > + > + words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master)); > + words_exp = len / 4 + 1; > + if (words_read != words_exp) { > + dev_err(cci->dev, "words read = %d, words expected = %d\n", > + words_read, words_exp); > + return -EIO; > + } > + > + do { > + val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master)); > + > + for (i = 0; i < 4 && index < len; i++) { > + if (first) { > + first = false; > + continue; > + } > + buf[index++] = (val >> (i * 8)) & 0xff; > + } > + } while (--words_read); > + > + return 0; > +} > + > +static int cci_i2c_write(struct cci *cci, u16 master, > + u16 addr, u8 *buf, u16 len) > +{ > + u8 queue = QUEUE_0; > + u8 load[12] = { 0 }; > + int i = 0, j, ret; > + u32 val; > + > + /* > + * Call validate queue to make sure queue is empty before starting. > + * This is to avoid overflow / underflow of queue. > + */ > + ret = cci_validate_queue(cci, master, queue); > + if (ret < 0) > + return ret; > + > + val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4; > + writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); > + > + load[i++] = CCI_I2C_WRITE | len << 4; > + > + for (j = 0; j < len; j++) > + load[i++] = buf[j]; > + > + for (j = 0; j < i; j += 4) { > + val = load[j]; > + val |= load[j + 1] << 8; > + val |= load[j + 2] << 16; > + val |= load[j + 3] << 24; > + writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); > + } > + > + val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN; > + writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); > + > + return cci_run_queue(cci, master, queue); > +} > + > +static int cci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) > +{ > + struct cci_master *cci_master = i2c_get_adapdata(adap); > + struct cci *cci = cci_master->cci; > + int i, ret; > + > + ret = pm_runtime_get_sync(cci->dev); > + if (ret < 0) > + goto err; > + > + for (i = 0; i < num; i++) { > + if (msgs[i].flags & I2C_M_RD) > + ret = cci_i2c_read(cci, cci_master->master, > + msgs[i].addr, msgs[i].buf, > + msgs[i].len); > + else > + ret = cci_i2c_write(cci, cci_master->master, > + msgs[i].addr, msgs[i].buf, > + msgs[i].len); > + > + if (ret < 0) { > + dev_err(cci->dev, "cci i2c xfer error %d", ret); > + break; > + } > + } > + > + if (!ret) > + ret = num; > + > +err: > + pm_runtime_mark_last_busy(cci->dev); > + pm_runtime_put_autosuspend(cci->dev); > + > + return ret; > +} > + > +static u32 cci_func(struct i2c_adapter *adap) > +{ > + return I2C_FUNC_I2C; > +} > + > +static const struct i2c_algorithm cci_algo = { > + .master_xfer = cci_xfer, > + .functionality = cci_func, > +}; > + > +static int cci_enable_clocks(struct cci *cci) > +{ > + int ret; > + > + ret = clk_bulk_prepare_enable(cci->nclocks, cci->clocks); > + if (ret < 0) > + dev_err(cci->dev, "Bulk clock prepare failed: %d\n", ret); > + > + return ret; > +} > + > +static void cci_disable_clocks(struct cci *cci) > +{ > + clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); > +} > + > +#ifdef CONFIG_PM > +static int cci_suspend_runtime(struct device *dev) > +{ > + struct cci *cci = dev_get_drvdata(dev); > + > + dev_dbg(dev, "Supend invoked\n"); > + cci_disable_clocks(cci); > + return 0; > +} > + > +static int cci_resume_runtime(struct device *dev) > +{ > + struct cci *cci = dev_get_drvdata(dev); > + int ret; > + > + dev_dbg(dev, "Resume invoked\n"); > + ret = cci_enable_clocks(cci); > + if (ret) > + return ret; > + > + cci_init(cci); > + return 0; > +} > +#endif > + > +#ifdef CONFIG_PM_SLEEP > +static int cci_suspend(struct device *dev) > +{ > + if (!pm_runtime_suspended(dev)) > + return cci_suspend_runtime(dev); > + > + return 0; > +} > + > +static int cci_resume(struct device *dev) > +{ > + cci_resume_runtime(dev); > + pm_runtime_mark_last_busy(dev); > + pm_request_autosuspend(dev); > + > + return 0; > +} > +#endif > + > +static const struct dev_pm_ops qcom_cci_pm = { > + SET_SYSTEM_SLEEP_PM_OPS(cci_suspend, cci_resume) > + SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL) > +}; > + > +static int cci_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct device_node *of_node = NULL; > + unsigned long cci_clk_rate = 0; > + struct resource *r; > + struct cci *cci; > + int ret = 0, i; > + u32 val; > + > + cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL); > + if (!cci) > + return -ENOMEM; > + > + cci->dev = dev; > + platform_set_drvdata(pdev, cci); > + cci->data = device_get_match_data(&pdev->dev); > + if (!cci->data) { > + dev_err(&pdev->dev, "Driver data is null, abort\n"); > + return -EIO; > + } > + > + for (i = 0; i < cci->data->num_masters; i++) { > + cci->master[i].adap.quirks = &cci->data->quirks; > + cci->master[i].adap.algo = &cci_algo; > + cci->master[i].adap.dev.parent = cci->dev; > + cci->master[i].master = i; > + cci->master[i].cci = cci; > + > + i2c_set_adapdata(&cci->master[i].adap, &cci->master[i]); > + snprintf(cci->master[i].adap.name, > + sizeof(cci->master[i].adap.name), > + "Qualcomm Camera Control Interface: %d", i); > + > + /* find the child node for i2c-bus as we are on cci node */ > + of_node = of_get_next_available_child(dev->of_node, of_node); > + if (!of_node) { > + dev_err(dev, "Missing i2c-bus@%d child node\n", i); > + return -EINVAL; > + } > + cci->master[i].adap.dev.of_node = of_node; > + > + cci->master[i].mode = I2C_MODE_STANDARD; > + ret = of_property_read_u32(of_node, "clock-frequency", &val); > + if (!ret) { > + if (val == 400000) > + cci->master[i].mode = I2C_MODE_FAST; > + else if (val == 1000000) > + cci->master[i].mode = I2C_MODE_FAST_PLUS; > + } > + > + init_completion(&cci->master[i].irq_complete); > + } > + > + /* Memory */ > + > + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + cci->base = devm_ioremap_resource(dev, r); > + if (IS_ERR(cci->base)) > + return PTR_ERR(cci->base); > + > + /* Interrupt */ > + > + ret = platform_get_irq(pdev, 0); > + if (ret < 0) { > + dev_err(dev, "missing IRQ: %d\n", ret); > + return ret; > + } > + cci->irq = ret; > + > + ret = devm_request_irq(dev, cci->irq, cci_isr, > + IRQF_TRIGGER_RISING, dev_name(dev), cci); > + if (ret < 0) { > + dev_err(dev, "request_irq failed, ret: %d\n", ret); > + return ret; > + } > + > + disable_irq(cci->irq); > + > + /* Clocks */ > + > + ret = devm_clk_bulk_get_all(dev, &cci->clocks); > + if (ret < 1) { > + dev_err(dev, "failed to get clocks %d\n", ret); > + return ret; > + } > + cci->nclocks = ret; > + > + /* Retrieve CCI clock rate */ > + for (i = 0; i < cci->nclocks; i++) { > + if (!strncmp(cci->clocks[i].id, "cci", 4)) { > + cci_clk_rate = clk_get_rate(cci->clocks[i].clk); > + break; > + } > + } > + > + if (cci_clk_rate != cci->data->cci_clk_rate) { > + /* cci clock set by the bootloader or via assigned clock rate > + * in DT. > + */ > + dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n", > + cci_clk_rate, cci->data->cci_clk_rate); > + } > + > + ret = cci_enable_clocks(cci); > + if (ret < 0) > + return ret; > + > + val = readl_relaxed(cci->base + CCI_HW_VERSION); > + dev_info(dev, "%s: CCI HW version = 0x%08x", __func__, val); > + > + enable_irq(cci->irq); > + > + ret = cci_reset(cci); > + if (ret < 0) > + goto error; > + > + ret = cci_init(cci); > + if (ret < 0) > + goto error; > + > + for (i = 0; i < cci->data->num_masters; i++) { > + ret = i2c_add_adapter(&cci->master[i].adap); > + if (ret < 0) > + goto error_i2c; > + } > + > + pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); > + pm_runtime_use_autosuspend(dev); > + pm_runtime_set_active(dev); > + pm_runtime_enable(dev); > + > + return 0; > + > +error_i2c: > + for (; i >= 0; i--) > + i2c_del_adapter(&cci->master[i].adap); > +error: > + disable_irq(cci->irq); > + cci_disable_clocks(cci); > + > + return ret; > +} > + > +static int cci_remove(struct platform_device *pdev) > +{ > + struct cci *cci = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < cci->data->num_masters; i++) { > + i2c_del_adapter(&cci->master[i].adap); > + cci_halt(cci, i); > + } > + > + disable_irq(cci->irq); > + pm_runtime_disable(&pdev->dev); > + pm_runtime_set_suspended(&pdev->dev); > + > + return 0; > +} > + > +static const struct cci_data cci_v1_data = { > + .num_masters = 1, > + .queue_size = { 64, 16 }, > + .quirks = { > + .max_write_len = 10, > + .max_read_len = 12, > + }, > + .cci_clk_rate = 19200000, > + .params[I2C_MODE_STANDARD] = { > + .thigh = 78, > + .tlow = 114, > + .tsu_sto = 28, > + .tsu_sta = 28, > + .thd_dat = 10, > + .thd_sta = 77, > + .tbuf = 118, > + .scl_stretch_en = 0, > + .trdhld = 6, > + .tsp = 1 > + }, > + .params[I2C_MODE_FAST] = { > + .thigh = 20, > + .tlow = 28, > + .tsu_sto = 21, > + .tsu_sta = 21, > + .thd_dat = 13, > + .thd_sta = 18, > + .tbuf = 32, > + .scl_stretch_en = 0, > + .trdhld = 6, > + .tsp = 3 > + }, > +}; > + > +static const struct cci_data cci_v2_data = { > + .num_masters = 2, > + .queue_size = { 64, 16 }, > + .quirks = { > + .max_write_len = 11, > + .max_read_len = 12, > + }, > + .cci_clk_rate = 37500000, > + .params[I2C_MODE_STANDARD] = { > + .thigh = 201, > + .tlow = 174, > + .tsu_sto = 204, > + .tsu_sta = 231, > + .thd_dat = 22, > + .thd_sta = 162, > + .tbuf = 227, > + .scl_stretch_en = 0, > + .trdhld = 6, > + .tsp = 3 > + }, > + .params[I2C_MODE_FAST] = { > + .thigh = 38, > + .tlow = 56, > + .tsu_sto = 40, > + .tsu_sta = 40, > + .thd_dat = 22, > + .thd_sta = 35, > + .tbuf = 62, > + .scl_stretch_en = 0, > + .trdhld = 6, > + .tsp = 3 > + }, > + .params[I2C_MODE_FAST_PLUS] = { > + .thigh = 16, > + .tlow = 22, > + .tsu_sto = 17, > + .tsu_sta = 18, > + .thd_dat = 16, > + .thd_sta = 15, > + .tbuf = 24, > + .scl_stretch_en = 0, > + .trdhld = 3, > + .tsp = 3 > + }, > +}; > + > +static const struct of_device_id cci_dt_match[] = { > + { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data}, > + { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data}, > + { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data}, > + {} > +}; > +MODULE_DEVICE_TABLE(of, cci_dt_match); > + > +static struct platform_driver qcom_cci_driver = { > + .probe = cci_probe, > + .remove = cci_remove, > + .driver = { > + .name = "i2c-qcom-cci", > + .of_match_table = cci_dt_match, > + .pm = &qcom_cci_pm, > + }, > +}; > + > +module_platform_driver(qcom_cci_driver); > + > +MODULE_DESCRIPTION("Qualcomm Camera Control Interface driver"); > +MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); > +MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); > +MODULE_LICENSE("GPL v2"); > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver 2020-03-04 16:52 [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Loic Poulain 2020-03-04 16:52 ` [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Loic Poulain @ 2020-03-05 6:25 ` kbuild test robot 2020-03-04 19:04 ` [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Robert Foss ` (2 subsequent siblings) 4 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2020-03-05 6:25 UTC (permalink / raw) To: Loic Poulain Cc: kbuild-all, wsa, vkoul, bjorn.andersson, robert.foss, linux-arm-msm, linux-i2c, Loic Poulain, Todor Tomov Hi Loic, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on wsa/i2c/for-next] [also build test WARNING on robh/for-next v5.6-rc4 next-20200304] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Loic-Poulain/i2c-Add-Qualcomm-CCI-I2C-driver/20200305-051618 base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@intel.com> coccinelle warnings: (new ones prefixed by >>) >> drivers/i2c/busses/i2c-qcom-cci.c:261:49-50: Unneeded semicolon Please review and possibly fold the followup patch. --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver @ 2020-03-05 6:25 ` kbuild test robot 0 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2020-03-05 6:25 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 1015 bytes --] Hi Loic, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on wsa/i2c/for-next] [also build test WARNING on robh/for-next v5.6-rc4 next-20200304] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Loic-Poulain/i2c-Add-Qualcomm-CCI-I2C-driver/20200305-051618 base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@intel.com> coccinelle warnings: (new ones prefixed by >>) >> drivers/i2c/busses/i2c-qcom-cci.c:261:49-50: Unneeded semicolon Please review and possibly fold the followup patch. --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver @ 2020-03-05 6:25 ` kbuild test robot 0 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2020-03-05 6:25 UTC (permalink / raw) Cc: kbuild-all, wsa, vkoul, bjorn.andersson, robert.foss, linux-arm-msm, linux-i2c, Loic Poulain, Todor Tomov Hi Loic, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on wsa/i2c/for-next] [also build test WARNING on robh/for-next v5.6-rc4 next-20200304] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Loic-Poulain/i2c-Add-Qualcomm-CCI-I2C-driver/20200305-051618 base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@intel.com> coccinelle warnings: (new ones prefixed by >>) >> drivers/i2c/busses/i2c-qcom-cci.c:261:49-50: Unneeded semicolon Please review and possibly fold the followup patch. --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] i2c: fix semicolon.cocci warnings 2020-03-04 16:52 [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Loic Poulain 2020-03-04 16:52 ` [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Loic Poulain @ 2020-03-05 6:25 ` kbuild test robot 2020-03-04 19:04 ` [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Robert Foss ` (2 subsequent siblings) 4 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2020-03-05 6:25 UTC (permalink / raw) To: Loic Poulain Cc: kbuild-all, wsa, vkoul, bjorn.andersson, robert.foss, linux-arm-msm, linux-i2c, Loic Poulain, Todor Tomov From: kbuild test robot <lkp@intel.com> drivers/i2c/busses/i2c-qcom-cci.c:261:49-50: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 7c495c97e573 ("i2c: Add Qualcomm CCI I2C driver") CC: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: kbuild test robot <lkp@intel.com> --- url: https://github.com/0day-ci/linux/commits/Loic-Poulain/i2c-Add-Qualcomm-CCI-I2C-driver/20200305-051618 base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next i2c-qcom-cci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -258,7 +258,7 @@ static int cci_init(struct cci *cci) const struct hw_params *hw = &cci->data->params[mode]; val = hw->thigh << 16 | hw->tlow; - writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));; + writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i)); val = hw->tsu_sto << 16 | hw->tsu_sta; writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i)); ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] i2c: fix semicolon.cocci warnings @ 2020-03-05 6:25 ` kbuild test robot 0 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2020-03-05 6:25 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 1076 bytes --] From: kbuild test robot <lkp@intel.com> drivers/i2c/busses/i2c-qcom-cci.c:261:49-50: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 7c495c97e573 ("i2c: Add Qualcomm CCI I2C driver") CC: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: kbuild test robot <lkp@intel.com> --- url: https://github.com/0day-ci/linux/commits/Loic-Poulain/i2c-Add-Qualcomm-CCI-I2C-driver/20200305-051618 base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next i2c-qcom-cci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -258,7 +258,7 @@ static int cci_init(struct cci *cci) const struct hw_params *hw = &cci->data->params[mode]; val = hw->thigh << 16 | hw->tlow; - writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));; + writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i)); val = hw->tsu_sto << 16 | hw->tsu_sta; writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i)); ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] i2c: fix semicolon.cocci warnings @ 2020-03-05 6:25 ` kbuild test robot 0 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2020-03-05 6:25 UTC (permalink / raw) Cc: kbuild-all, wsa, vkoul, bjorn.andersson, robert.foss, linux-arm-msm, linux-i2c, Loic Poulain, Todor Tomov From: kbuild test robot <lkp@intel.com> drivers/i2c/busses/i2c-qcom-cci.c:261:49-50: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 7c495c97e573 ("i2c: Add Qualcomm CCI I2C driver") CC: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: kbuild test robot <lkp@intel.com> --- url: https://github.com/0day-ci/linux/commits/Loic-Poulain/i2c-Add-Qualcomm-CCI-I2C-driver/20200305-051618 base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next i2c-qcom-cci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -258,7 +258,7 @@ static int cci_init(struct cci *cci) const struct hw_params *hw = &cci->data->params[mode]; val = hw->thigh << 16 | hw->tlow; - writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));; + writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i)); val = hw->tsu_sto << 16 | hw->tsu_sta; writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i)); ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/1] i2c: Add Omnivision OV5670 5M sensor support 2017-06-14 1:39 ` chiranjeevi.rapolu @ 2017-06-14 13:47 kbuild test robot 2017-06-14 1:39 ` chiranjeevi.rapolu 0 siblings, 1 reply; 16+ messages in thread From: kbuild test robot @ 2017-06-14 13:47 UTC (permalink / raw) To: chiranjeevi.rapolu Cc: kbuild-all, linux-media, sakari.ailus, tfiga, jian.xu.zheng, rajmohan.mani, hyungwoo.yang, Chiranjeevi Rapolu Hi Chiranjeevi, [auto build test WARNING on linuxtv-media/master] [also build test WARNING on v4.12-rc5 next-20170614] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/chiranjeevi-rapolu-intel-com/i2c-Add-Omnivision-OV5670-5M-sensor-support/20170614-195050 base: git://linuxtv.org/media_tree.git master coccinelle warnings: (new ones prefixed by >>) >> drivers/media/i2c/ov5670.c:2577:3-8: No need to set .owner here. The core will do it. -- >> drivers/media/i2c/ov5670.c:2001:2-3: Unneeded semicolon drivers/media/i2c/ov5670.c:2033:2-3: Unneeded semicolon Please review and possibly fold the followup patch. --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/1] i2c: Add Omnivision OV5670 5M sensor support @ 2017-06-14 1:39 ` chiranjeevi.rapolu 2017-06-14 13:47 ` [PATCH] i2c: fix semicolon.cocci warnings kbuild test robot 0 siblings, 1 reply; 16+ messages in thread From: chiranjeevi.rapolu @ 2017-06-14 1:39 UTC (permalink / raw) To: linux-media, sakari.ailus, tfiga Cc: jian.xu.zheng, rajmohan.mani, hyungwoo.yang, Chiranjeevi Rapolu From: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Provides single source pad with up to 2592x1944 pixels at 10-bit raw bayer format over MIPI CSI2 two lanes at 640Mbps/lane. The driver supports following features: - up to 30fps at 5M pixels - manual exposure - digital/analog gain - V-blank/H-blank - test pattern - media controller - runtime pm Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> --- drivers/media/i2c/Kconfig | 12 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/ov5670.c | 2591 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2604 insertions(+) create mode 100644 drivers/media/i2c/ov5670.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index c380e24..55e1877 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -573,6 +573,18 @@ config VIDEO_OV5647 To compile this driver as a module, choose M here: the module will be called ov5647. +config VIDEO_OV5670 + tristate "OmniVision OV5670 sensor support" + depends on I2C && VIDEO_V4L2 + depends on MEDIA_CAMERA_SUPPORT + select V4L2_FWNODE + ---help--- + This is a Video4Linux2 sensor-level driver for the OmniVision + OV5670 camera. + + To compile this driver as a module, choose M here: the + module will be called ov5670. + config VIDEO_OV7640 tristate "OmniVision OV7640 sensor support" depends on I2C && VIDEO_V4L2 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 62323ec..de95651 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o obj-$(CONFIG_VIDEO_OV2640) += ov2640.o obj-$(CONFIG_VIDEO_OV5645) += ov5645.o obj-$(CONFIG_VIDEO_OV5647) += ov5647.o +obj-$(CONFIG_VIDEO_OV5670) += ov5670.o obj-$(CONFIG_VIDEO_OV7640) += ov7640.o obj-$(CONFIG_VIDEO_OV7670) += ov7670.o obj-$(CONFIG_VIDEO_OV9650) += ov9650.o diff --git a/drivers/media/i2c/ov5670.c b/drivers/media/i2c/ov5670.c new file mode 100644 index 0000000..64bb858 --- /dev/null +++ b/drivers/media/i2c/ov5670.c @@ -0,0 +1,2591 @@ +/* + * Copyright (c) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/acpi.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> + +#define OV5670_REG_CHIP_ID 0x300a +#define OV5670_CHIP_ID 0x005670 + +#define OV5670_REG_MODE_SELECT 0x0100 +#define OV5670_MODE_STANDBY 0x00 +#define OV5670_MODE_STREAMING 0x01 + +#define OV5670_REG_SOFTWARE_RST 0x0103 +#define OV5670_SOFTWARE_RST 0x01 + +/* vertical-timings from sensor */ +#define OV5670_REG_VTS 0x380e +#define OV5670_VTS_30FPS 0x0808 /* default for 30 fps */ +#define OV5670_VTS_MAX 0x7fff +#define OV5670_VBLANK_MIN 56 + +/* horizontal-timings from sensor */ +#define OV5670_MAX_PPL 3408 /* Maximum pixels per line */ + +/* Exposure controls from sensor */ +#define OV5670_REG_EXPOSURE 0x3500 +#define OV5670_EXPOSURE_MIN 0 +#define OV5670_EXPOSURE_MAX 1048575 +#define OV5670_EXPOSURE_STEP 1 +#define OV5670_EXPOSURE_DEFAULT 31872 + +/* Analog gain controls from sensor */ +#define OV5670_REG_ANALOG_GAIN 0x3508 +#define ANALOG_GAIN_MIN 0 +#define ANALOG_GAIN_MAX 8191 +#define ANALOG_GAIN_STEP 1 +#define ANALOG_GAIN_DEFAULT 128 + +/* Digital gain controls from sensor */ +#define OV5670_REG_R_DGTL_GAIN 0x5032 +#define OV5670_REG_G_DGTL_GAIN 0x5034 +#define OV5670_REG_B_DGTL_GAIN 0x5036 +#define OV5670_DGTL_GAIN_MIN 0 +#define OV5670_DGTL_GAIN_MAX 4095 +#define OV5670_DGTL_GAIN_STEP 1 +#define OV5670_DGTL_GAIN_DEFAULT 1024 + +/* Test Pattern Control */ +#define OV5670_REG_TEST_PATTERN 0x4303 +#define OV5670_TEST_PATTERN_ENABLE BIT(3) +#define OV5670_REG_TEST_PATTERN_CTRL 0x4320 + +#define OV5670_REG_VALUE_08BIT 1 +#define OV5670_REG_VALUE_16BIT 2 +#define OV5670_REG_VALUE_24BIT 3 + +struct ov5670_reg { + u16 address; + u8 val; +}; + +struct ov5670_reg_list { + u32 num_of_regs; + const struct ov5670_reg *regs; +}; + +struct ov5670_link_freq_config { + u32 pixel_rate; + const struct ov5670_reg_list reg_list; +}; + +struct ov5670_mode { + /* Frame width in pixels */ + u32 width; + + /* Frame height in pixels */ + u32 height; + + /* Vertical timining size */ + u32 vts; + + /* Initial number of frames to skip to avoid garbage in the frames */ + u32 skip_frames; + + /* Link frequency needed for this resolution */ + u32 link_freq_index; + + /* Sensor register settings for this resolution */ + const struct ov5670_reg_list reg_list; +}; + +static const struct ov5670_reg mipi_data_rate_840mbps[] = { + {0x0300, 0x04}, + {0x0301, 0x00}, + {0x0302, 0x84}, + {0x0303, 0x00}, + {0x0304, 0x03}, + {0x0305, 0x01}, + {0x0306, 0x01}, + {0x030a, 0x00}, + {0x030b, 0x00}, + {0x030c, 0x00}, + {0x030d, 0x26}, + {0x030e, 0x00}, + {0x030f, 0x06}, + {0x0312, 0x01}, + {0x3031, 0x0a}, +}; + +static const struct ov5670_reg mode_2592x1944_regs[] = { + {0x3000, 0x00}, + {0x3002, 0x21}, + {0x3005, 0xf0}, + {0x3007, 0x00}, + {0x3015, 0x0f}, + {0x3018, 0x32}, + {0x301a, 0xf0}, + {0x301b, 0xf0}, + {0x301c, 0xf0}, + {0x301d, 0xf0}, + {0x301e, 0xf0}, + {0x3030, 0x00}, + {0x3031, 0x0a}, + {0x303c, 0xff}, + {0x303e, 0xff}, + {0x3040, 0xf0}, + {0x3041, 0x00}, + {0x3042, 0xf0}, + {0x3106, 0x11}, + {0x3500, 0x00}, + {0x3501, 0x7c}, + {0x3502, 0x80}, + {0x3503, 0x04}, + {0x3504, 0x03}, + {0x3505, 0x83}, + {0x3508, 0x04}, + {0x3509, 0x00}, + {0x350e, 0x04}, + {0x350f, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3601, 0xc8}, + {0x3610, 0x88}, + {0x3612, 0x48}, + {0x3614, 0x5b}, + {0x3615, 0x96}, + {0x3621, 0xd0}, + {0x3622, 0x00}, + {0x3623, 0x00}, + {0x3633, 0x13}, + {0x3634, 0x13}, + {0x3635, 0x13}, + {0x3636, 0x13}, + {0x3645, 0x13}, + {0x3646, 0x82}, + {0x3650, 0x00}, + {0x3652, 0xff}, + {0x3655, 0x20}, + {0x3656, 0xff}, + {0x365a, 0xff}, + {0x365e, 0xff}, + {0x3668, 0x00}, + {0x366a, 0x07}, + {0x366e, 0x10}, + {0x366d, 0x00}, + {0x366f, 0x80}, + {0x3700, 0x28}, + {0x3701, 0x10}, + {0x3702, 0x3a}, + {0x3703, 0x19}, + {0x3704, 0x10}, + {0x3705, 0x00}, + {0x3706, 0x66}, + {0x3707, 0x08}, + {0x3708, 0x34}, + {0x3709, 0x40}, + {0x370a, 0x01}, + {0x370b, 0x1b}, + {0x3714, 0x24}, + {0x371a, 0x3e}, + {0x3733, 0x00}, + {0x3734, 0x00}, + {0x373a, 0x05}, + {0x373b, 0x06}, + {0x373c, 0x0a}, + {0x373f, 0xa0}, + {0x3755, 0x00}, + {0x3758, 0x00}, + {0x375b, 0x0e}, + {0x3766, 0x5f}, + {0x3768, 0x00}, + {0x3769, 0x22}, + {0x3773, 0x08}, + {0x3774, 0x1f}, + {0x3776, 0x06}, + {0x37a0, 0x88}, + {0x37a1, 0x5c}, + {0x37a7, 0x88}, + {0x37a8, 0x70}, + {0x37aa, 0x88}, + {0x37ab, 0x48}, + {0x37b3, 0x66}, + {0x37c2, 0x04}, + {0x37c5, 0x00}, + {0x37c8, 0x00}, + {0x3800, 0x00}, + {0x3801, 0x0c}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x33}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3808, 0x0a}, + {0x3809, 0x20}, + {0x380a, 0x07}, + {0x380b, 0x98}, + {0x380c, 0x06}, + {0x380d, 0x90}, + {0x380e, 0x07}, + {0x380f, 0xb8}, + {0x3811, 0x04}, + {0x3813, 0x02}, + {0x3814, 0x01}, + {0x3815, 0x01}, + {0x3816, 0x00}, + {0x3817, 0x00}, + {0x3818, 0x00}, + {0x3819, 0x00}, + {0x3820, 0x84}, + {0x3821, 0x46}, + {0x3822, 0x48}, + {0x3826, 0x00}, + {0x3827, 0x08}, + {0x382a, 0x01}, + {0x382b, 0x01}, + {0x3830, 0x08}, + {0x3836, 0x02}, + {0x3837, 0x00}, + {0x3838, 0x10}, + {0x3841, 0xff}, + {0x3846, 0x48}, + {0x3861, 0x00}, + {0x3862, 0x04}, + {0x3863, 0x06}, + {0x3a11, 0x01}, + {0x3a12, 0x78}, + {0x3b00, 0x00}, + {0x3b02, 0x00}, + {0x3b03, 0x00}, + {0x3b04, 0x00}, + {0x3b05, 0x00}, + {0x3c00, 0x89}, + {0x3c01, 0xab}, + {0x3c02, 0x01}, + {0x3c03, 0x00}, + {0x3c04, 0x00}, + {0x3c05, 0x03}, + {0x3c06, 0x00}, + {0x3c07, 0x05}, + {0x3c0c, 0x00}, + {0x3c0d, 0x00}, + {0x3c0e, 0x00}, + {0x3c0f, 0x00}, + {0x3c40, 0x00}, + {0x3c41, 0xa3}, + {0x3c43, 0x7d}, + {0x3c45, 0xd7}, + {0x3c47, 0xfc}, + {0x3c50, 0x05}, + {0x3c52, 0xaa}, + {0x3c54, 0x71}, + {0x3c56, 0x80}, + {0x3d85, 0x17}, + {0x3f03, 0x00}, + {0x3f0a, 0x00}, + {0x3f0b, 0x00}, + {0x4001, 0x60}, + {0x4009, 0x0d}, + {0x4020, 0x00}, + {0x4021, 0x00}, + {0x4022, 0x00}, + {0x4023, 0x00}, + {0x4024, 0x00}, + {0x4025, 0x00}, + {0x4026, 0x00}, + {0x4027, 0x00}, + {0x4028, 0x00}, + {0x4029, 0x00}, + {0x402a, 0x00}, + {0x402b, 0x00}, + {0x402c, 0x00}, + {0x402d, 0x00}, + {0x402e, 0x00}, + {0x402f, 0x00}, + {0x4040, 0x00}, + {0x4041, 0x03}, + {0x4042, 0x00}, + {0x4043, 0x7A}, + {0x4044, 0x00}, + {0x4045, 0x7A}, + {0x4046, 0x00}, + {0x4047, 0x7A}, + {0x4048, 0x00}, + {0x4049, 0x7A}, + {0x4307, 0x30}, + {0x4500, 0x58}, + {0x4501, 0x04}, + {0x4502, 0x40}, + {0x4503, 0x10}, + {0x4508, 0xaa}, + {0x4509, 0xaa}, + {0x450a, 0x00}, + {0x450b, 0x00}, + {0x4600, 0x01}, + {0x4601, 0x03}, + {0x4700, 0xa4}, + {0x4800, 0x4c}, + {0x4816, 0x53}, + {0x481f, 0x40}, + {0x4837, 0x13}, + {0x5000, 0x56}, + {0x5001, 0x01}, + {0x5002, 0x28}, + {0x5004, 0x0c}, + {0x5006, 0x0c}, + {0x5007, 0xe0}, + {0x5008, 0x01}, + {0x5009, 0xb0}, + {0x5901, 0x00}, + {0x5a01, 0x00}, + {0x5a03, 0x00}, + {0x5a04, 0x0c}, + {0x5a05, 0xe0}, + {0x5a06, 0x09}, + {0x5a07, 0xb0}, + {0x5a08, 0x06}, + {0x5e00, 0x00}, + {0x3734, 0x40}, + {0x5b00, 0x01}, + {0x5b01, 0x10}, + {0x5b02, 0x01}, + {0x5b03, 0xdb}, + {0x3d8c, 0x71}, + {0x3d8d, 0xea}, + {0x4017, 0x08}, + {0x3618, 0x2a}, + {0x5780, 0x3e}, + {0x5781, 0x0f}, + {0x5782, 0x44}, + {0x5783, 0x02}, + {0x5784, 0x01}, + {0x5785, 0x01}, + {0x5786, 0x00}, + {0x5787, 0x04}, + {0x5788, 0x02}, + {0x5789, 0x0f}, + {0x578a, 0xfd}, + {0x578b, 0xf5}, + {0x578c, 0xf5}, + {0x578d, 0x03}, + {0x578e, 0x08}, + {0x578f, 0x0c}, + {0x5790, 0x08}, + {0x5791, 0x06}, + {0x5792, 0x00}, + {0x5793, 0x52}, + {0x5794, 0xa3}, + {0x3503, 0x00} +}; + +static const struct ov5670_reg mode_1296x972_regs[] = { + {0x3000, 0x00}, + {0x3002, 0x21}, + {0x3005, 0xf0}, + {0x3007, 0x00}, + {0x3015, 0x0f}, + {0x3018, 0x32}, + {0x301a, 0xf0}, + {0x301b, 0xf0}, + {0x301c, 0xf0}, + {0x301d, 0xf0}, + {0x301e, 0xf0}, + {0x3030, 0x00}, + {0x3031, 0x0a}, + {0x303c, 0xff}, + {0x303e, 0xff}, + {0x3040, 0xf0}, + {0x3041, 0x00}, + {0x3042, 0xf0}, + {0x3106, 0x11}, + {0x3500, 0x00}, + {0x3501, 0x7c}, + {0x3502, 0x80}, + {0x3503, 0x04}, + {0x3504, 0x03}, + {0x3505, 0x83}, + {0x3508, 0x07}, + {0x3509, 0x80}, + {0x350e, 0x04}, + {0x350f, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3601, 0xc8}, + {0x3610, 0x88}, + {0x3612, 0x48}, + {0x3614, 0x5b}, + {0x3615, 0x96}, + {0x3621, 0xd0}, + {0x3622, 0x00}, + {0x3623, 0x00}, + {0x3633, 0x13}, + {0x3634, 0x13}, + {0x3635, 0x13}, + {0x3636, 0x13}, + {0x3645, 0x13}, + {0x3646, 0x82}, + {0x3650, 0x00}, + {0x3652, 0xff}, + {0x3655, 0x20}, + {0x3656, 0xff}, + {0x365a, 0xff}, + {0x365e, 0xff}, + {0x3668, 0x00}, + {0x366a, 0x07}, + {0x366e, 0x08}, + {0x366d, 0x00}, + {0x366f, 0x80}, + {0x3700, 0x28}, + {0x3701, 0x10}, + {0x3702, 0x3a}, + {0x3703, 0x19}, + {0x3704, 0x10}, + {0x3705, 0x00}, + {0x3706, 0x66}, + {0x3707, 0x08}, + {0x3708, 0x34}, + {0x3709, 0x40}, + {0x370a, 0x01}, + {0x370b, 0x1b}, + {0x3714, 0x24}, + {0x371a, 0x3e}, + {0x3733, 0x00}, + {0x3734, 0x00}, + {0x373a, 0x05}, + {0x373b, 0x06}, + {0x373c, 0x0a}, + {0x373f, 0xa0}, + {0x3755, 0x00}, + {0x3758, 0x00}, + {0x375b, 0x0e}, + {0x3766, 0x5f}, + {0x3768, 0x00}, + {0x3769, 0x22}, + {0x3773, 0x08}, + {0x3774, 0x1f}, + {0x3776, 0x06}, + {0x37a0, 0x88}, + {0x37a1, 0x5c}, + {0x37a7, 0x88}, + {0x37a8, 0x70}, + {0x37aa, 0x88}, + {0x37ab, 0x48}, + {0x37b3, 0x66}, + {0x37c2, 0x04}, + {0x37c5, 0x00}, + {0x37c8, 0x00}, + {0x3800, 0x00}, + {0x3801, 0x0c}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x33}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3808, 0x05}, + {0x3809, 0x10}, + {0x380a, 0x03}, + {0x380b, 0xcc}, + {0x380c, 0x06}, + {0x380d, 0x90}, + {0x380e, 0x07}, + {0x380f, 0xb8}, + {0x3811, 0x04}, + {0x3813, 0x04}, + {0x3814, 0x03}, + {0x3815, 0x01}, + {0x3816, 0x00}, + {0x3817, 0x00}, + {0x3818, 0x00}, + {0x3819, 0x00}, + {0x3820, 0x94}, + {0x3821, 0x47}, + {0x3822, 0x48}, + {0x3826, 0x00}, + {0x3827, 0x08}, + {0x382a, 0x03}, + {0x382b, 0x01}, + {0x3830, 0x08}, + {0x3836, 0x02}, + {0x3837, 0x00}, + {0x3838, 0x10}, + {0x3841, 0xff}, + {0x3846, 0x48}, + {0x3861, 0x00}, + {0x3862, 0x04}, + {0x3863, 0x06}, + {0x3a11, 0x01}, + {0x3a12, 0x78}, + {0x3b00, 0x00}, + {0x3b02, 0x00}, + {0x3b03, 0x00}, + {0x3b04, 0x00}, + {0x3b05, 0x00}, + {0x3c00, 0x89}, + {0x3c01, 0xab}, + {0x3c02, 0x01}, + {0x3c03, 0x00}, + {0x3c04, 0x00}, + {0x3c05, 0x03}, + {0x3c06, 0x00}, + {0x3c07, 0x05}, + {0x3c0c, 0x00}, + {0x3c0d, 0x00}, + {0x3c0e, 0x00}, + {0x3c0f, 0x00}, + {0x3c40, 0x00}, + {0x3c41, 0xa3}, + {0x3c43, 0x7d}, + {0x3c45, 0xd7}, + {0x3c47, 0xfc}, + {0x3c50, 0x05}, + {0x3c52, 0xaa}, + {0x3c54, 0x71}, + {0x3c56, 0x80}, + {0x3d85, 0x17}, + {0x3f03, 0x00}, + {0x3f0a, 0x00}, + {0x3f0b, 0x00}, + {0x4001, 0x60}, + {0x4009, 0x05}, + {0x4020, 0x00}, + {0x4021, 0x00}, + {0x4022, 0x00}, + {0x4023, 0x00}, + {0x4024, 0x00}, + {0x4025, 0x00}, + {0x4026, 0x00}, + {0x4027, 0x00}, + {0x4028, 0x00}, + {0x4029, 0x00}, + {0x402a, 0x00}, + {0x402b, 0x00}, + {0x402c, 0x00}, + {0x402d, 0x00}, + {0x402e, 0x00}, + {0x402f, 0x00}, + {0x4040, 0x00}, + {0x4041, 0x03}, + {0x4042, 0x00}, + {0x4043, 0x7A}, + {0x4044, 0x00}, + {0x4045, 0x7A}, + {0x4046, 0x00}, + {0x4047, 0x7A}, + {0x4048, 0x00}, + {0x4049, 0x7A}, + {0x4307, 0x30}, + {0x4500, 0x58}, + {0x4501, 0x04}, + {0x4502, 0x48}, + {0x4503, 0x10}, + {0x4508, 0x55}, + {0x4509, 0x55}, + {0x450a, 0x00}, + {0x450b, 0x00}, + {0x4600, 0x00}, + {0x4601, 0x81}, + {0x4700, 0xa4}, + {0x4800, 0x4c}, + {0x4816, 0x53}, + {0x481f, 0x40}, + {0x4837, 0x13}, + {0x5000, 0x56}, + {0x5001, 0x01}, + {0x5002, 0x28}, + {0x5004, 0x0c}, + {0x5006, 0x0c}, + {0x5007, 0xe0}, + {0x5008, 0x01}, + {0x5009, 0xb0}, + {0x5901, 0x00}, + {0x5a01, 0x00}, + {0x5a03, 0x00}, + {0x5a04, 0x0c}, + {0x5a05, 0xe0}, + {0x5a06, 0x09}, + {0x5a07, 0xb0}, + {0x5a08, 0x06}, + {0x5e00, 0x00}, + {0x3734, 0x40}, + {0x5b00, 0x01}, + {0x5b01, 0x10}, + {0x5b02, 0x01}, + {0x5b03, 0xdb}, + {0x3d8c, 0x71}, + {0x3d8d, 0xea}, + {0x4017, 0x10}, + {0x3618, 0x2a}, + {0x5780, 0x3e}, + {0x5781, 0x0f}, + {0x5782, 0x44}, + {0x5783, 0x02}, + {0x5784, 0x01}, + {0x5785, 0x01}, + {0x5786, 0x00}, + {0x5787, 0x04}, + {0x5788, 0x02}, + {0x5789, 0x0f}, + {0x578a, 0xfd}, + {0x578b, 0xf5}, + {0x578c, 0xf5}, + {0x578d, 0x03}, + {0x578e, 0x08}, + {0x578f, 0x0c}, + {0x5790, 0x08}, + {0x5791, 0x04}, + {0x5792, 0x00}, + {0x5793, 0x52}, + {0x5794, 0xa3}, + {0x3503, 0x00} +}; + +static const struct ov5670_reg mode_648x486_regs[] = { + {0x3000, 0x00}, + {0x3002, 0x21}, + {0x3005, 0xf0}, + {0x3007, 0x00}, + {0x3015, 0x0f}, + {0x3018, 0x32}, + {0x301a, 0xf0}, + {0x301b, 0xf0}, + {0x301c, 0xf0}, + {0x301d, 0xf0}, + {0x301e, 0xf0}, + {0x3030, 0x00}, + {0x3031, 0x0a}, + {0x303c, 0xff}, + {0x303e, 0xff}, + {0x3040, 0xf0}, + {0x3041, 0x00}, + {0x3042, 0xf0}, + {0x3106, 0x11}, + {0x3500, 0x00}, + {0x3501, 0x7c}, + {0x3502, 0x80}, + {0x3503, 0x04}, + {0x3504, 0x03}, + {0x3505, 0x83}, + {0x3508, 0x04}, + {0x3509, 0x00}, + {0x350e, 0x04}, + {0x350f, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3601, 0xc8}, + {0x3610, 0x88}, + {0x3612, 0x48}, + {0x3614, 0x5b}, + {0x3615, 0x96}, + {0x3621, 0xd0}, + {0x3622, 0x00}, + {0x3623, 0x04}, + {0x3633, 0x13}, + {0x3634, 0x13}, + {0x3635, 0x13}, + {0x3636, 0x13}, + {0x3645, 0x13}, + {0x3646, 0x82}, + {0x3650, 0x00}, + {0x3652, 0xff}, + {0x3655, 0x20}, + {0x3656, 0xff}, + {0x365a, 0xff}, + {0x365e, 0xff}, + {0x3668, 0x00}, + {0x366a, 0x07}, + {0x366e, 0x08}, + {0x366d, 0x00}, + {0x366f, 0x80}, + {0x3700, 0x28}, + {0x3701, 0x10}, + {0x3702, 0x3a}, + {0x3703, 0x19}, + {0x3704, 0x10}, + {0x3705, 0x00}, + {0x3706, 0x66}, + {0x3707, 0x08}, + {0x3708, 0x34}, + {0x3709, 0x40}, + {0x370a, 0x01}, + {0x370b, 0x1b}, + {0x3714, 0x24}, + {0x371a, 0x3e}, + {0x3733, 0x00}, + {0x3734, 0x00}, + {0x373a, 0x05}, + {0x373b, 0x06}, + {0x373c, 0x0a}, + {0x373f, 0xa0}, + {0x3755, 0x00}, + {0x3758, 0x00}, + {0x375b, 0x0e}, + {0x3766, 0x5f}, + {0x3768, 0x00}, + {0x3769, 0x22}, + {0x3773, 0x08}, + {0x3774, 0x1f}, + {0x3776, 0x06}, + {0x37a0, 0x88}, + {0x37a1, 0x5c}, + {0x37a7, 0x88}, + {0x37a8, 0x70}, + {0x37aa, 0x88}, + {0x37ab, 0x48}, + {0x37b3, 0x66}, + {0x37c2, 0x04}, + {0x37c5, 0x00}, + {0x37c8, 0x00}, + {0x3800, 0x00}, + {0x3801, 0x0c}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x33}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3808, 0x02}, + {0x3809, 0x88}, + {0x380a, 0x01}, + {0x380b, 0xe6}, + {0x380c, 0x06}, + {0x380d, 0x90}, + {0x380e, 0x07}, + {0x380f, 0xb8}, + {0x3811, 0x04}, + {0x3813, 0x02}, + {0x3814, 0x07}, + {0x3815, 0x01}, + {0x3816, 0x00}, + {0x3817, 0x00}, + {0x3818, 0x00}, + {0x3819, 0x00}, + {0x3820, 0x94}, + {0x3821, 0xc6}, + {0x3822, 0x48}, + {0x3826, 0x00}, + {0x3827, 0x08}, + {0x382a, 0x07}, + {0x382b, 0x01}, + {0x3830, 0x08}, + {0x3836, 0x02}, + {0x3837, 0x00}, + {0x3838, 0x10}, + {0x3841, 0xff}, + {0x3846, 0x48}, + {0x3861, 0x00}, + {0x3862, 0x04}, + {0x3863, 0x06}, + {0x3a11, 0x01}, + {0x3a12, 0x78}, + {0x3b00, 0x00}, + {0x3b02, 0x00}, + {0x3b03, 0x00}, + {0x3b04, 0x00}, + {0x3b05, 0x00}, + {0x3c00, 0x89}, + {0x3c01, 0xab}, + {0x3c02, 0x01}, + {0x3c03, 0x00}, + {0x3c04, 0x00}, + {0x3c05, 0x03}, + {0x3c06, 0x00}, + {0x3c07, 0x05}, + {0x3c0c, 0x00}, + {0x3c0d, 0x00}, + {0x3c0e, 0x00}, + {0x3c0f, 0x00}, + {0x3c40, 0x00}, + {0x3c41, 0xa3}, + {0x3c43, 0x7d}, + {0x3c45, 0xd7}, + {0x3c47, 0xfc}, + {0x3c50, 0x05}, + {0x3c52, 0xaa}, + {0x3c54, 0x71}, + {0x3c56, 0x80}, + {0x3d85, 0x17}, + {0x3f03, 0x00}, + {0x3f0a, 0x00}, + {0x3f0b, 0x00}, + {0x4001, 0x60}, + {0x4009, 0x05}, + {0x4020, 0x00}, + {0x4021, 0x00}, + {0x4022, 0x00}, + {0x4023, 0x00}, + {0x4024, 0x00}, + {0x4025, 0x00}, + {0x4026, 0x00}, + {0x4027, 0x00}, + {0x4028, 0x00}, + {0x4029, 0x00}, + {0x402a, 0x00}, + {0x402b, 0x00}, + {0x402c, 0x00}, + {0x402d, 0x00}, + {0x402e, 0x00}, + {0x402f, 0x00}, + {0x4040, 0x00}, + {0x4041, 0x03}, + {0x4042, 0x00}, + {0x4043, 0x7A}, + {0x4044, 0x00}, + {0x4045, 0x7A}, + {0x4046, 0x00}, + {0x4047, 0x7A}, + {0x4048, 0x00}, + {0x4049, 0x7A}, + {0x4307, 0x30}, + {0x4500, 0x58}, + {0x4501, 0x04}, + {0x4502, 0x40}, + {0x4503, 0x10}, + {0x4508, 0x55}, + {0x4509, 0x55}, + {0x450a, 0x02}, + {0x450b, 0x00}, + {0x4600, 0x00}, + {0x4601, 0x40}, + {0x4700, 0xa4}, + {0x4800, 0x4c}, + {0x4816, 0x53}, + {0x481f, 0x40}, + {0x4837, 0x13}, + {0x5000, 0x56}, + {0x5001, 0x01}, + {0x5002, 0x28}, + {0x5004, 0x0c}, + {0x5006, 0x0c}, + {0x5007, 0xe0}, + {0x5008, 0x01}, + {0x5009, 0xb0}, + {0x5901, 0x00}, + {0x5a01, 0x00}, + {0x5a03, 0x00}, + {0x5a04, 0x0c}, + {0x5a05, 0xe0}, + {0x5a06, 0x09}, + {0x5a07, 0xb0}, + {0x5a08, 0x06}, + {0x5e00, 0x00}, + {0x3734, 0x40}, + {0x5b00, 0x01}, + {0x5b01, 0x10}, + {0x5b02, 0x01}, + {0x5b03, 0xdb}, + {0x3d8c, 0x71}, + {0x3d8d, 0xea}, + {0x4017, 0x10}, + {0x3618, 0x2a}, + {0x5780, 0x3e}, + {0x5781, 0x0f}, + {0x5782, 0x44}, + {0x5783, 0x02}, + {0x5784, 0x01}, + {0x5785, 0x01}, + {0x5786, 0x00}, + {0x5787, 0x04}, + {0x5788, 0x02}, + {0x5789, 0x0f}, + {0x578a, 0xfd}, + {0x578b, 0xf5}, + {0x578c, 0xf5}, + {0x578d, 0x03}, + {0x578e, 0x08}, + {0x578f, 0x0c}, + {0x5790, 0x08}, + {0x5791, 0x06}, + {0x5792, 0x00}, + {0x5793, 0x52}, + {0x5794, 0xa3}, + {0x3503, 0x00} +}; + +static const struct ov5670_reg mode_2560x1440_regs[] = { + {0x3000, 0x00}, + {0x3002, 0x21}, + {0x3005, 0xf0}, + {0x3007, 0x00}, + {0x3015, 0x0f}, + {0x3018, 0x32}, + {0x301a, 0xf0}, + {0x301b, 0xf0}, + {0x301c, 0xf0}, + {0x301d, 0xf0}, + {0x301e, 0xf0}, + {0x3030, 0x00}, + {0x3031, 0x0a}, + {0x303c, 0xff}, + {0x303e, 0xff}, + {0x3040, 0xf0}, + {0x3041, 0x00}, + {0x3042, 0xf0}, + {0x3106, 0x11}, + {0x3500, 0x00}, + {0x3501, 0x7c}, + {0x3502, 0x80}, + {0x3503, 0x04}, + {0x3504, 0x03}, + {0x3505, 0x83}, + {0x3508, 0x04}, + {0x3509, 0x00}, + {0x350e, 0x04}, + {0x350f, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3601, 0xc8}, + {0x3610, 0x88}, + {0x3612, 0x48}, + {0x3614, 0x5b}, + {0x3615, 0x96}, + {0x3621, 0xd0}, + {0x3622, 0x00}, + {0x3623, 0x00}, + {0x3633, 0x13}, + {0x3634, 0x13}, + {0x3635, 0x13}, + {0x3636, 0x13}, + {0x3645, 0x13}, + {0x3646, 0x82}, + {0x3650, 0x00}, + {0x3652, 0xff}, + {0x3655, 0x20}, + {0x3656, 0xff}, + {0x365a, 0xff}, + {0x365e, 0xff}, + {0x3668, 0x00}, + {0x366a, 0x07}, + {0x366e, 0x10}, + {0x366d, 0x00}, + {0x366f, 0x80}, + {0x3700, 0x28}, + {0x3701, 0x10}, + {0x3702, 0x3a}, + {0x3703, 0x19}, + {0x3704, 0x10}, + {0x3705, 0x00}, + {0x3706, 0x66}, + {0x3707, 0x08}, + {0x3708, 0x34}, + {0x3709, 0x40}, + {0x370a, 0x01}, + {0x370b, 0x1b}, + {0x3714, 0x24}, + {0x371a, 0x3e}, + {0x3733, 0x00}, + {0x3734, 0x00}, + {0x373a, 0x05}, + {0x373b, 0x06}, + {0x373c, 0x0a}, + {0x373f, 0xa0}, + {0x3755, 0x00}, + {0x3758, 0x00}, + {0x375b, 0x0e}, + {0x3766, 0x5f}, + {0x3768, 0x00}, + {0x3769, 0x22}, + {0x3773, 0x08}, + {0x3774, 0x1f}, + {0x3776, 0x06}, + {0x37a0, 0x88}, + {0x37a1, 0x5c}, + {0x37a7, 0x88}, + {0x37a8, 0x70}, + {0x37aa, 0x88}, + {0x37ab, 0x48}, + {0x37b3, 0x66}, + {0x37c2, 0x04}, + {0x37c5, 0x00}, + {0x37c8, 0x00}, + {0x3800, 0x00}, + {0x3801, 0x0c}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x33}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3808, 0x0a}, + {0x3809, 0x00}, + {0x380a, 0x05}, + {0x380b, 0xa0}, + {0x380c, 0x06}, + {0x380d, 0x90}, + {0x380e, 0x07}, + {0x380f, 0xb8}, + {0x3811, 0x04}, + {0x3813, 0x02}, + {0x3814, 0x01}, + {0x3815, 0x01}, + {0x3816, 0x00}, + {0x3817, 0x00}, + {0x3818, 0x00}, + {0x3819, 0x00}, + {0x3820, 0x84}, + {0x3821, 0x46}, + {0x3822, 0x48}, + {0x3826, 0x00}, + {0x3827, 0x08}, + {0x382a, 0x01}, + {0x382b, 0x01}, + {0x3830, 0x08}, + {0x3836, 0x02}, + {0x3837, 0x00}, + {0x3838, 0x10}, + {0x3841, 0xff}, + {0x3846, 0x48}, + {0x3861, 0x00}, + {0x3862, 0x04}, + {0x3863, 0x06}, + {0x3a11, 0x01}, + {0x3a12, 0x78}, + {0x3b00, 0x00}, + {0x3b02, 0x00}, + {0x3b03, 0x00}, + {0x3b04, 0x00}, + {0x3b05, 0x00}, + {0x3c00, 0x89}, + {0x3c01, 0xab}, + {0x3c02, 0x01}, + {0x3c03, 0x00}, + {0x3c04, 0x00}, + {0x3c05, 0x03}, + {0x3c06, 0x00}, + {0x3c07, 0x05}, + {0x3c0c, 0x00}, + {0x3c0d, 0x00}, + {0x3c0e, 0x00}, + {0x3c0f, 0x00}, + {0x3c40, 0x00}, + {0x3c41, 0xa3}, + {0x3c43, 0x7d}, + {0x3c45, 0xd7}, + {0x3c47, 0xfc}, + {0x3c50, 0x05}, + {0x3c52, 0xaa}, + {0x3c54, 0x71}, + {0x3c56, 0x80}, + {0x3d85, 0x17}, + {0x3f03, 0x00}, + {0x3f0a, 0x00}, + {0x3f0b, 0x00}, + {0x4001, 0x60}, + {0x4009, 0x0d}, + {0x4020, 0x00}, + {0x4021, 0x00}, + {0x4022, 0x00}, + {0x4023, 0x00}, + {0x4024, 0x00}, + {0x4025, 0x00}, + {0x4026, 0x00}, + {0x4027, 0x00}, + {0x4028, 0x00}, + {0x4029, 0x00}, + {0x402a, 0x00}, + {0x402b, 0x00}, + {0x402c, 0x00}, + {0x402d, 0x00}, + {0x402e, 0x00}, + {0x402f, 0x00}, + {0x4040, 0x00}, + {0x4041, 0x03}, + {0x4042, 0x00}, + {0x4043, 0x7A}, + {0x4044, 0x00}, + {0x4045, 0x7A}, + {0x4046, 0x00}, + {0x4047, 0x7A}, + {0x4048, 0x00}, + {0x4049, 0x7A}, + {0x4307, 0x30}, + {0x4500, 0x58}, + {0x4501, 0x04}, + {0x4502, 0x40}, + {0x4503, 0x10}, + {0x4508, 0xaa}, + {0x4509, 0xaa}, + {0x450a, 0x00}, + {0x450b, 0x00}, + {0x4600, 0x01}, + {0x4601, 0x00}, + {0x4700, 0xa4}, + {0x4800, 0x4c}, + {0x4816, 0x53}, + {0x481f, 0x40}, + {0x4837, 0x13}, + {0x5000, 0x56}, + {0x5001, 0x01}, + {0x5002, 0x28}, + {0x5004, 0x0c}, + {0x5006, 0x0c}, + {0x5007, 0xe0}, + {0x5008, 0x01}, + {0x5009, 0xb0}, + {0x5901, 0x00}, + {0x5a01, 0x00}, + {0x5a03, 0x00}, + {0x5a04, 0x0c}, + {0x5a05, 0xe0}, + {0x5a06, 0x09}, + {0x5a07, 0xb0}, + {0x5a08, 0x06}, + {0x5e00, 0x00}, + {0x3734, 0x40}, + {0x5b00, 0x01}, + {0x5b01, 0x10}, + {0x5b02, 0x01}, + {0x5b03, 0xdb}, + {0x3d8c, 0x71}, + {0x3d8d, 0xea}, + {0x4017, 0x08}, + {0x3618, 0x2a}, + {0x5780, 0x3e}, + {0x5781, 0x0f}, + {0x5782, 0x44}, + {0x5783, 0x02}, + {0x5784, 0x01}, + {0x5785, 0x01}, + {0x5786, 0x00}, + {0x5787, 0x04}, + {0x5788, 0x02}, + {0x5789, 0x0f}, + {0x578a, 0xfd}, + {0x578b, 0xf5}, + {0x578c, 0xf5}, + {0x578d, 0x03}, + {0x578e, 0x08}, + {0x578f, 0x0c}, + {0x5790, 0x08}, + {0x5791, 0x06}, + {0x5792, 0x00}, + {0x5793, 0x52}, + {0x5794, 0xa3} +}; + +static const struct ov5670_reg mode_1280x720_regs[] = { + {0x3000, 0x00}, + {0x3002, 0x21}, + {0x3005, 0xf0}, + {0x3007, 0x00}, + {0x3015, 0x0f}, + {0x3018, 0x32}, + {0x301a, 0xf0}, + {0x301b, 0xf0}, + {0x301c, 0xf0}, + {0x301d, 0xf0}, + {0x301e, 0xf0}, + {0x3030, 0x00}, + {0x3031, 0x0a}, + {0x303c, 0xff}, + {0x303e, 0xff}, + {0x3040, 0xf0}, + {0x3041, 0x00}, + {0x3042, 0xf0}, + {0x3106, 0x11}, + {0x3500, 0x00}, + {0x3501, 0x7c}, + {0x3502, 0x80}, + {0x3503, 0x04}, + {0x3504, 0x03}, + {0x3505, 0x83}, + {0x3508, 0x04}, + {0x3509, 0x00}, + {0x350e, 0x04}, + {0x350f, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3601, 0xc8}, + {0x3610, 0x88}, + {0x3612, 0x48}, + {0x3614, 0x5b}, + {0x3615, 0x96}, + {0x3621, 0xd0}, + {0x3622, 0x00}, + {0x3623, 0x00}, + {0x3633, 0x13}, + {0x3634, 0x13}, + {0x3635, 0x13}, + {0x3636, 0x13}, + {0x3645, 0x13}, + {0x3646, 0x82}, + {0x3650, 0x00}, + {0x3652, 0xff}, + {0x3655, 0x20}, + {0x3656, 0xff}, + {0x365a, 0xff}, + {0x365e, 0xff}, + {0x3668, 0x00}, + {0x366a, 0x07}, + {0x366e, 0x08}, + {0x366d, 0x00}, + {0x366f, 0x80}, + {0x3700, 0x28}, + {0x3701, 0x10}, + {0x3702, 0x3a}, + {0x3703, 0x19}, + {0x3704, 0x10}, + {0x3705, 0x00}, + {0x3706, 0x66}, + {0x3707, 0x08}, + {0x3708, 0x34}, + {0x3709, 0x40}, + {0x370a, 0x01}, + {0x370b, 0x1b}, + {0x3714, 0x24}, + {0x371a, 0x3e}, + {0x3733, 0x00}, + {0x3734, 0x00}, + {0x373a, 0x05}, + {0x373b, 0x06}, + {0x373c, 0x0a}, + {0x373f, 0xa0}, + {0x3755, 0x00}, + {0x3758, 0x00}, + {0x375b, 0x0e}, + {0x3766, 0x5f}, + {0x3768, 0x00}, + {0x3769, 0x22}, + {0x3773, 0x08}, + {0x3774, 0x1f}, + {0x3776, 0x06}, + {0x37a0, 0x88}, + {0x37a1, 0x5c}, + {0x37a7, 0x88}, + {0x37a8, 0x70}, + {0x37aa, 0x88}, + {0x37ab, 0x48}, + {0x37b3, 0x66}, + {0x37c2, 0x04}, + {0x37c5, 0x00}, + {0x37c8, 0x00}, + {0x3800, 0x00}, + {0x3801, 0x0c}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x33}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3808, 0x05}, + {0x3809, 0x00}, + {0x380a, 0x02}, + {0x380b, 0xd0}, + {0x380c, 0x06}, + {0x380d, 0x90}, + {0x380e, 0x07}, + {0x380f, 0xb8}, + {0x3811, 0x04}, + {0x3813, 0x02}, + {0x3814, 0x03}, + {0x3815, 0x01}, + {0x3816, 0x00}, + {0x3817, 0x00}, + {0x3818, 0x00}, + {0x3819, 0x00}, + {0x3820, 0x94}, + {0x3821, 0x47}, + {0x3822, 0x48}, + {0x3826, 0x00}, + {0x3827, 0x08}, + {0x382a, 0x03}, + {0x382b, 0x01}, + {0x3830, 0x08}, + {0x3836, 0x02}, + {0x3837, 0x00}, + {0x3838, 0x10}, + {0x3841, 0xff}, + {0x3846, 0x48}, + {0x3861, 0x00}, + {0x3862, 0x04}, + {0x3863, 0x06}, + {0x3a11, 0x01}, + {0x3a12, 0x78}, + {0x3b00, 0x00}, + {0x3b02, 0x00}, + {0x3b03, 0x00}, + {0x3b04, 0x00}, + {0x3b05, 0x00}, + {0x3c00, 0x89}, + {0x3c01, 0xab}, + {0x3c02, 0x01}, + {0x3c03, 0x00}, + {0x3c04, 0x00}, + {0x3c05, 0x03}, + {0x3c06, 0x00}, + {0x3c07, 0x05}, + {0x3c0c, 0x00}, + {0x3c0d, 0x00}, + {0x3c0e, 0x00}, + {0x3c0f, 0x00}, + {0x3c40, 0x00}, + {0x3c41, 0xa3}, + {0x3c43, 0x7d}, + {0x3c45, 0xd7}, + {0x3c47, 0xfc}, + {0x3c50, 0x05}, + {0x3c52, 0xaa}, + {0x3c54, 0x71}, + {0x3c56, 0x80}, + {0x3d85, 0x17}, + {0x3f03, 0x00}, + {0x3f0a, 0x00}, + {0x3f0b, 0x00}, + {0x4001, 0x60}, + {0x4009, 0x05}, + {0x4020, 0x00}, + {0x4021, 0x00}, + {0x4022, 0x00}, + {0x4023, 0x00}, + {0x4024, 0x00}, + {0x4025, 0x00}, + {0x4026, 0x00}, + {0x4027, 0x00}, + {0x4028, 0x00}, + {0x4029, 0x00}, + {0x402a, 0x00}, + {0x402b, 0x00}, + {0x402c, 0x00}, + {0x402d, 0x00}, + {0x402e, 0x00}, + {0x402f, 0x00}, + {0x4040, 0x00}, + {0x4041, 0x03}, + {0x4042, 0x00}, + {0x4043, 0x7A}, + {0x4044, 0x00}, + {0x4045, 0x7A}, + {0x4046, 0x00}, + {0x4047, 0x7A}, + {0x4048, 0x00}, + {0x4049, 0x7A}, + {0x4307, 0x30}, + {0x4500, 0x58}, + {0x4501, 0x04}, + {0x4502, 0x48}, + {0x4503, 0x10}, + {0x4508, 0x55}, + {0x4509, 0x55}, + {0x450a, 0x00}, + {0x450b, 0x00}, + {0x4600, 0x00}, + {0x4601, 0x80}, + {0x4700, 0xa4}, + {0x4800, 0x4c}, + {0x4816, 0x53}, + {0x481f, 0x40}, + {0x4837, 0x13}, + {0x5000, 0x56}, + {0x5001, 0x01}, + {0x5002, 0x28}, + {0x5004, 0x0c}, + {0x5006, 0x0c}, + {0x5007, 0xe0}, + {0x5008, 0x01}, + {0x5009, 0xb0}, + {0x5901, 0x00}, + {0x5a01, 0x00}, + {0x5a03, 0x00}, + {0x5a04, 0x0c}, + {0x5a05, 0xe0}, + {0x5a06, 0x09}, + {0x5a07, 0xb0}, + {0x5a08, 0x06}, + {0x5e00, 0x00}, + {0x3734, 0x40}, + {0x5b00, 0x01}, + {0x5b01, 0x10}, + {0x5b02, 0x01}, + {0x5b03, 0xdb}, + {0x3d8c, 0x71}, + {0x3d8d, 0xea}, + {0x4017, 0x10}, + {0x3618, 0x2a}, + {0x5780, 0x3e}, + {0x5781, 0x0f}, + {0x5782, 0x44}, + {0x5783, 0x02}, + {0x5784, 0x01}, + {0x5785, 0x01}, + {0x5786, 0x00}, + {0x5787, 0x04}, + {0x5788, 0x02}, + {0x5789, 0x0f}, + {0x578a, 0xfd}, + {0x578b, 0xf5}, + {0x578c, 0xf5}, + {0x578d, 0x03}, + {0x578e, 0x08}, + {0x578f, 0x0c}, + {0x5790, 0x08}, + {0x5791, 0x06}, + {0x5792, 0x00}, + {0x5793, 0x52}, + {0x5794, 0xa3}, + {0x3503, 0x00} +}; + +static const struct ov5670_reg mode_640x360_regs[] = { + {0x3000, 0x00}, + {0x3002, 0x21}, + {0x3005, 0xf0}, + {0x3007, 0x00}, + {0x3015, 0x0f}, + {0x3018, 0x32}, + {0x301a, 0xf0}, + {0x301b, 0xf0}, + {0x301c, 0xf0}, + {0x301d, 0xf0}, + {0x301e, 0xf0}, + {0x3030, 0x00}, + {0x3031, 0x0a}, + {0x303c, 0xff}, + {0x303e, 0xff}, + {0x3040, 0xf0}, + {0x3041, 0x00}, + {0x3042, 0xf0}, + {0x3106, 0x11}, + {0x3500, 0x00}, + {0x3501, 0x7c}, + {0x3502, 0x80}, + {0x3503, 0x04}, + {0x3504, 0x03}, + {0x3505, 0x83}, + {0x3508, 0x04}, + {0x3509, 0x00}, + {0x350e, 0x04}, + {0x350f, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3601, 0xc8}, + {0x3610, 0x88}, + {0x3612, 0x48}, + {0x3614, 0x5b}, + {0x3615, 0x96}, + {0x3621, 0xd0}, + {0x3622, 0x00}, + {0x3623, 0x04}, + {0x3633, 0x13}, + {0x3634, 0x13}, + {0x3635, 0x13}, + {0x3636, 0x13}, + {0x3645, 0x13}, + {0x3646, 0x82}, + {0x3650, 0x00}, + {0x3652, 0xff}, + {0x3655, 0x20}, + {0x3656, 0xff}, + {0x365a, 0xff}, + {0x365e, 0xff}, + {0x3668, 0x00}, + {0x366a, 0x07}, + {0x366e, 0x08}, + {0x366d, 0x00}, + {0x366f, 0x80}, + {0x3700, 0x28}, + {0x3701, 0x10}, + {0x3702, 0x3a}, + {0x3703, 0x19}, + {0x3704, 0x10}, + {0x3705, 0x00}, + {0x3706, 0x66}, + {0x3707, 0x08}, + {0x3708, 0x34}, + {0x3709, 0x40}, + {0x370a, 0x01}, + {0x370b, 0x1b}, + {0x3714, 0x24}, + {0x371a, 0x3e}, + {0x3733, 0x00}, + {0x3734, 0x00}, + {0x373a, 0x05}, + {0x373b, 0x06}, + {0x373c, 0x0a}, + {0x373f, 0xa0}, + {0x3755, 0x00}, + {0x3758, 0x00}, + {0x375b, 0x0e}, + {0x3766, 0x5f}, + {0x3768, 0x00}, + {0x3769, 0x22}, + {0x3773, 0x08}, + {0x3774, 0x1f}, + {0x3776, 0x06}, + {0x37a0, 0x88}, + {0x37a1, 0x5c}, + {0x37a7, 0x88}, + {0x37a8, 0x70}, + {0x37aa, 0x88}, + {0x37ab, 0x48}, + {0x37b3, 0x66}, + {0x37c2, 0x04}, + {0x37c5, 0x00}, + {0x37c8, 0x00}, + {0x3800, 0x00}, + {0x3801, 0x0c}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x33}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0x68}, + {0x380c, 0x06}, + {0x380d, 0x90}, + {0x380e, 0x07}, + {0x380f, 0xb8}, + {0x3811, 0x04}, + {0x3813, 0x02}, + {0x3814, 0x07}, + {0x3815, 0x01}, + {0x3816, 0x00}, + {0x3817, 0x00}, + {0x3818, 0x00}, + {0x3819, 0x00}, + {0x3820, 0x94}, + {0x3821, 0xc6}, + {0x3822, 0x48}, + {0x3826, 0x00}, + {0x3827, 0x08}, + {0x382a, 0x07}, + {0x382b, 0x01}, + {0x3830, 0x08}, + {0x3836, 0x02}, + {0x3837, 0x00}, + {0x3838, 0x10}, + {0x3841, 0xff}, + {0x3846, 0x48}, + {0x3861, 0x00}, + {0x3862, 0x04}, + {0x3863, 0x06}, + {0x3a11, 0x01}, + {0x3a12, 0x78}, + {0x3b00, 0x00}, + {0x3b02, 0x00}, + {0x3b03, 0x00}, + {0x3b04, 0x00}, + {0x3b05, 0x00}, + {0x3c00, 0x89}, + {0x3c01, 0xab}, + {0x3c02, 0x01}, + {0x3c03, 0x00}, + {0x3c04, 0x00}, + {0x3c05, 0x03}, + {0x3c06, 0x00}, + {0x3c07, 0x05}, + {0x3c0c, 0x00}, + {0x3c0d, 0x00}, + {0x3c0e, 0x00}, + {0x3c0f, 0x00}, + {0x3c40, 0x00}, + {0x3c41, 0xa3}, + {0x3c43, 0x7d}, + {0x3c45, 0xd7}, + {0x3c47, 0xfc}, + {0x3c50, 0x05}, + {0x3c52, 0xaa}, + {0x3c54, 0x71}, + {0x3c56, 0x80}, + {0x3d85, 0x17}, + {0x3f03, 0x00}, + {0x3f0a, 0x00}, + {0x3f0b, 0x00}, + {0x4001, 0x60}, + {0x4009, 0x05}, + {0x4020, 0x00}, + {0x4021, 0x00}, + {0x4022, 0x00}, + {0x4023, 0x00}, + {0x4024, 0x00}, + {0x4025, 0x00}, + {0x4026, 0x00}, + {0x4027, 0x00}, + {0x4028, 0x00}, + {0x4029, 0x00}, + {0x402a, 0x00}, + {0x402b, 0x00}, + {0x402c, 0x00}, + {0x402d, 0x00}, + {0x402e, 0x00}, + {0x402f, 0x00}, + {0x4040, 0x00}, + {0x4041, 0x03}, + {0x4042, 0x00}, + {0x4043, 0x7A}, + {0x4044, 0x00}, + {0x4045, 0x7A}, + {0x4046, 0x00}, + {0x4047, 0x7A}, + {0x4048, 0x00}, + {0x4049, 0x7A}, + {0x4307, 0x30}, + {0x4500, 0x58}, + {0x4501, 0x04}, + {0x4502, 0x40}, + {0x4503, 0x10}, + {0x4508, 0x55}, + {0x4509, 0x55}, + {0x450a, 0x02}, + {0x450b, 0x00}, + {0x4600, 0x00}, + {0x4601, 0x40}, + {0x4700, 0xa4}, + {0x4800, 0x4c}, + {0x4816, 0x53}, + {0x481f, 0x40}, + {0x4837, 0x13}, + {0x5000, 0x56}, + {0x5001, 0x01}, + {0x5002, 0x28}, + {0x5004, 0x0c}, + {0x5006, 0x0c}, + {0x5007, 0xe0}, + {0x5008, 0x01}, + {0x5009, 0xb0}, + {0x5901, 0x00}, + {0x5a01, 0x00}, + {0x5a03, 0x00}, + {0x5a04, 0x0c}, + {0x5a05, 0xe0}, + {0x5a06, 0x09}, + {0x5a07, 0xb0}, + {0x5a08, 0x06}, + {0x5e00, 0x00}, + {0x3734, 0x40}, + {0x5b00, 0x01}, + {0x5b01, 0x10}, + {0x5b02, 0x01}, + {0x5b03, 0xdb}, + {0x3d8c, 0x71}, + {0x3d8d, 0xea}, + {0x4017, 0x10}, + {0x3618, 0x2a}, + {0x5780, 0x3e}, + {0x5781, 0x0f}, + {0x5782, 0x44}, + {0x5783, 0x02}, + {0x5784, 0x01}, + {0x5785, 0x01}, + {0x5786, 0x00}, + {0x5787, 0x04}, + {0x5788, 0x02}, + {0x5789, 0x0f}, + {0x578a, 0xfd}, + {0x578b, 0xf5}, + {0x578c, 0xf5}, + {0x578d, 0x03}, + {0x578e, 0x08}, + {0x578f, 0x0c}, + {0x5790, 0x08}, + {0x5791, 0x06}, + {0x5792, 0x00}, + {0x5793, 0x52}, + {0x5794, 0xa3}, + {0x3503, 0x00} +}; + +static const char * const ov5670_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", +}; + +/* Supported link frequencies */ +#define OV5670_LINK_FREQ_840MBPS 840000000 +#define OV5670_LINK_FREQ_840MBPS_INDEX 0 +static const struct ov5670_link_freq_config link_freq_configs[] = { + { + .pixel_rate = 336000000, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mipi_data_rate_840mbps), + .regs = mipi_data_rate_840mbps, + } + } +}; + +static const const s64 link_freq_menu_items[] = { + OV5670_LINK_FREQ_840MBPS +}; + +/* + * OV5670 sensor supports following resolutions with full FOV: + * 4:3 ==> {2592x1944, 1296x972, 648x486} + * 16:9 ==> {2560x1440, 1280x720, 640x360} + */ +static const struct ov5670_mode supported_modes[] = { + { + .width = 2592, + .height = 1944, + .vts = OV5670_VTS_30FPS, + .skip_frames = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_2592x1944_regs), + .regs = mode_2592x1944_regs, + }, + .link_freq_index = OV5670_LINK_FREQ_840MBPS_INDEX, + }, + { + .width = 1296, + .height = 972, + .vts = OV5670_VTS_30FPS, + .skip_frames = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_1296x972_regs), + .regs = mode_1296x972_regs, + }, + .link_freq_index = OV5670_LINK_FREQ_840MBPS_INDEX, + }, + { + .width = 648, + .height = 486, + .vts = OV5670_VTS_30FPS, + .skip_frames = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_648x486_regs), + .regs = mode_648x486_regs, + }, + .link_freq_index = OV5670_LINK_FREQ_840MBPS_INDEX, + }, + { + .width = 2560, + .height = 1440, + .vts = OV5670_VTS_30FPS, + .skip_frames = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_2560x1440_regs), + .regs = mode_2560x1440_regs, + }, + .link_freq_index = OV5670_LINK_FREQ_840MBPS_INDEX, + }, + { + .width = 1280, + .height = 720, + .vts = OV5670_VTS_30FPS, + .skip_frames = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_1280x720_regs), + .regs = mode_1280x720_regs, + }, + .link_freq_index = OV5670_LINK_FREQ_840MBPS_INDEX, + }, + { + .width = 640, + .height = 360, + .vts = OV5670_VTS_30FPS, + .skip_frames = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_640x360_regs), + .regs = mode_640x360_regs, + }, + .link_freq_index = OV5670_LINK_FREQ_840MBPS_INDEX, + } +}; + +struct ov5670 { + struct v4l2_subdev sd; + struct media_pad pad; + + struct v4l2_ctrl_handler ctrl_handler; + /* V4L2 Controls */ + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *exposure; + + /* Current mode */ + const struct ov5670_mode *cur_mode; + + /* To serialize asynchronus callbacks */ + struct mutex mutex; + + /* Streaming on/off */ + bool streaming; +}; + +#define to_ov5670(_sd) container_of(_sd, struct ov5670, sd) + +/* Read registers up to 4 at a time */ +static int ov5670_read_reg(struct ov5670 *ov5670, u16 reg, unsigned int len, + u32 *val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov5670->sd); + struct i2c_msg msgs[2]; + u8 *data_be_p; + u32 data_be = 0; + u16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +/* Write registers up to 4 at a time */ +static int ov5670_write_reg(struct ov5670 *ov5670, u16 reg, unsigned int len, + u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov5670->sd); + int buf_i; + int val_i; + u8 buf[6]; + u8 *val_p; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val = cpu_to_be32(val); + val_p = (u8 *)&val; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +/* Write a list of registers */ +static int ov5670_write_regs(struct ov5670 *ov5670, + const struct ov5670_reg *regs, unsigned int len) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov5670->sd); + unsigned int i; + int ret; + + for (i = 0; i < len; i++) { + ret = ov5670_write_reg(ov5670, regs[i].address, 1, regs[i].val); + if (ret) { + dev_err_ratelimited( + &client->dev, + "Failed to write reg 0x%4.4x. error = %d\n", + regs[i].address, ret); + + return ret; + } + } + + return 0; +} + +static int ov5670_write_reg_list(struct ov5670 *ov5670, + const struct ov5670_reg_list *r_list) +{ + return ov5670_write_regs(ov5670, r_list->regs, r_list->num_of_regs); +} + +/* Open sub-device */ +static int ov5670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct ov5670 *ov5670 = to_ov5670(sd); + struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd, + fh->pad, + 0); + + mutex_lock(&ov5670->mutex); + + try_fmt->width = ov5670->cur_mode->width; + try_fmt->height = ov5670->cur_mode->height; + try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + try_fmt->field = V4L2_FIELD_NONE; + + /* No crop or compose */ + mutex_unlock(&ov5670->mutex); + + return 0; +} + +static int ov5670_update_digital_gain(struct ov5670 *ov5670, u32 d_gain) +{ + int ret; + + ret = ov5670_write_reg(ov5670, OV5670_REG_R_DGTL_GAIN, + OV5670_REG_VALUE_16BIT, d_gain); + if (ret) + return ret; + + ret = ov5670_write_reg(ov5670, OV5670_REG_G_DGTL_GAIN, + OV5670_REG_VALUE_16BIT, d_gain); + if (ret) + return ret; + + return ov5670_write_reg(ov5670, OV5670_REG_B_DGTL_GAIN, + OV5670_REG_VALUE_16BIT, d_gain); +} + +static int ov5670_enable_test_pattern(struct ov5670 *ov5670, u32 pattern) +{ + u32 val; + int ret; + + /* Set the bayer order that we support */ + ret = ov5670_write_reg(ov5670, OV5670_REG_TEST_PATTERN_CTRL, + OV5670_REG_VALUE_08BIT, 0); + if (ret) + return ret; + + ret = ov5670_read_reg(ov5670, OV5670_REG_TEST_PATTERN, + OV5670_REG_VALUE_08BIT, &val); + if (ret) + return ret; + + if (pattern) + val |= OV5670_TEST_PATTERN_ENABLE; + else + val &= ~OV5670_TEST_PATTERN_ENABLE; + + return ov5670_write_reg(ov5670, OV5670_REG_TEST_PATTERN, + OV5670_REG_VALUE_08BIT, val); +} + +/* Initialize control handlers */ +static int ov5670_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5670 *ov5670 = container_of(ctrl->handler, + struct ov5670, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&ov5670->sd); + s64 max; + int ret; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = ov5670->cur_mode->height + ctrl->val - 8; + /* 4 least significant bits of expsoure are fractional part */ + max = max << 4; + __v4l2_ctrl_modify_range(ov5670->exposure, ov5670->exposure->minimum, + max, ov5670->exposure->step, max); + break; + }; + + /* V4L2 controls values will be applied only when power is already up */ + if (pm_runtime_get_if_in_use(&client->dev) <= 0) + return 0; + + ret = 0; + switch (ctrl->id) { + case V4L2_CID_ANALOGUE_GAIN: + ret = ov5670_write_reg(ov5670, OV5670_REG_ANALOG_GAIN, + OV5670_REG_VALUE_16BIT, ctrl->val); + break; + case V4L2_CID_GAIN: + ret = ov5670_update_digital_gain(ov5670, ctrl->val); + break; + case V4L2_CID_EXPOSURE: + ret = ov5670_write_reg(ov5670, OV5670_REG_EXPOSURE, + OV5670_REG_VALUE_24BIT, ctrl->val); + break; + case V4L2_CID_VBLANK: + /* Update VTS that meets expected vertical blanking */ + ret = ov5670_write_reg(ov5670, OV5670_REG_VTS, + OV5670_REG_VALUE_16BIT, + ov5670->cur_mode->height + ctrl->val); + break; + case V4L2_CID_TEST_PATTERN: + ret = ov5670_enable_test_pattern(ov5670, ctrl->val); + break; + default: + dev_info(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + }; + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops ov5670_ctrl_ops = { + .s_ctrl = ov5670_set_ctrl, +}; + +/* Initialize control handlers */ +static int ov5670_init_controls(struct ov5670 *ov5670) +{ + struct v4l2_ctrl_handler *ctrl_hdlr; + s64 vblank_max; + s64 vblank_def; + int ret; + + ctrl_hdlr = &ov5670->ctrl_handler; + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); + if (ret) + return ret; + + ctrl_hdlr->lock = &ov5670->mutex; + ov5670->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, + &ov5670_ctrl_ops, + V4L2_CID_LINK_FREQ, 0, 0, + link_freq_menu_items); + ov5670->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + /* By default, V4L2_CID_PIXEL_RATE is read only */ + ov5670->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov5670_ctrl_ops, + V4L2_CID_PIXEL_RATE, 0, + OV5670_LINK_FREQ_840MBPS, 1, + link_freq_configs[0].pixel_rate); + + vblank_max = OV5670_VTS_MAX - ov5670->cur_mode->height; + vblank_def = ov5670->cur_mode->vts - ov5670->cur_mode->height; + ov5670->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5670_ctrl_ops, + V4L2_CID_VBLANK, OV5670_VBLANK_MIN, + vblank_max, 1, vblank_def); + + ov5670->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5670_ctrl_ops, + V4L2_CID_HBLANK, + OV5670_MAX_PPL - ov5670->cur_mode->width, + OV5670_MAX_PPL - ov5670->cur_mode->width, 1, + OV5670_MAX_PPL - ov5670->cur_mode->width); + ov5670->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + /* Get min, max, step, default from sensor */ + v4l2_ctrl_new_std(ctrl_hdlr, &ov5670_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + ANALOG_GAIN_MIN, ANALOG_GAIN_MAX, ANALOG_GAIN_STEP, + ANALOG_GAIN_DEFAULT); + + /* Digital gain */ + v4l2_ctrl_new_std(ctrl_hdlr, &ov5670_ctrl_ops, V4L2_CID_GAIN, + OV5670_DGTL_GAIN_MIN, OV5670_DGTL_GAIN_MAX, + OV5670_DGTL_GAIN_STEP, OV5670_DGTL_GAIN_DEFAULT); + + /* Get min, max, step, default from sensor */ + ov5670->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov5670_ctrl_ops, + V4L2_CID_EXPOSURE, + OV5670_EXPOSURE_MIN, + OV5670_EXPOSURE_MAX, + OV5670_EXPOSURE_STEP, + OV5670_EXPOSURE_DEFAULT); + + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov5670_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ov5670_test_pattern_menu) - 1, + 0, 0, ov5670_test_pattern_menu); + + if (ctrl_hdlr->error) { + ret = ctrl_hdlr->error; + goto error; + } + + ov5670->sd.ctrl_handler = ctrl_hdlr; + + return 0; + +error: + v4l2_ctrl_handler_free(ctrl_hdlr); + + return ret; +} + +static int ov5670_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + /* Only one bayer order GRBG is supported */ + if (code->index > 0) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int ov5670_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = supported_modes[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +/* Calculate resolution distance */ +static int ov5670_get_reso_dist(const struct ov5670_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +/* Find the closest supported resolution to the requested resolution */ +static const struct ov5670_mode *ov5670_find_best_fit( + struct ov5670 *ov5670, + struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = ov5670_get_reso_dist(&supported_modes[i], framefmt); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + + return &supported_modes[cur_best_fit]; +} + +static void ov5670_update_pad_format(const struct ov5670_mode *mode, + struct v4l2_subdev_format *fmt) +{ + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; + fmt->format.field = V4L2_FIELD_NONE; +} + +static int ov5670_do_get_pad_format(struct ov5670 *ov5670, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) + fmt->format = *v4l2_subdev_get_try_format(&ov5670->sd, cfg, + fmt->pad); + else + ov5670_update_pad_format(ov5670->cur_mode, fmt); + + return 0; +} + +static int ov5670_get_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov5670 *ov5670 = to_ov5670(sd); + int ret; + + mutex_lock(&ov5670->mutex); + ret = ov5670_do_get_pad_format(ov5670, cfg, fmt); + mutex_unlock(&ov5670->mutex); + + return ret; +} + +static int ov5670_set_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov5670 *ov5670 = to_ov5670(sd); + const struct ov5670_mode *mode; + s64 h_blank; + + mutex_lock(&ov5670->mutex); + + if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) + fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; + + mode = ov5670_find_best_fit(ov5670, fmt); + ov5670_update_pad_format(mode, fmt); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; + } else { + ov5670->cur_mode = mode; + __v4l2_ctrl_s_ctrl(ov5670->link_freq, mode->link_freq_index); + __v4l2_ctrl_s_ctrl_int64( + ov5670->pixel_rate, + link_freq_configs[mode->link_freq_index].pixel_rate); + /* Update limits and set FPS to default */ + __v4l2_ctrl_modify_range( + ov5670->vblank, OV5670_VBLANK_MIN, + OV5670_VTS_MAX - ov5670->cur_mode->height, 1, + ov5670->cur_mode->vts - ov5670->cur_mode->height); + h_blank = OV5670_MAX_PPL - ov5670->cur_mode->width; + __v4l2_ctrl_modify_range(ov5670->hblank, h_blank, h_blank, 1, + h_blank); + } + + mutex_unlock(&ov5670->mutex); + + return 0; +} + +static int ov5670_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov5670 *ov5670 = to_ov5670(sd); + + mutex_lock(&ov5670->mutex); + *frames = ov5670->cur_mode->skip_frames; + mutex_unlock(&ov5670->mutex); + + return 0; +} + +/* Prepare streaming by writing default values and customized values */ +static int ov5670_start_streaming(struct ov5670 *ov5670) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov5670->sd); + const struct ov5670_reg_list *reg_list; + int link_freq_index; + int ret; + + /* Get out of from software reset */ + ret = ov5670_write_reg(ov5670, OV5670_REG_SOFTWARE_RST, + OV5670_REG_VALUE_08BIT, OV5670_SOFTWARE_RST); + if (ret) { + dev_err(&client->dev, "%s failed to set powerup registers\n", + __func__); + return ret; + } + + /* Setup PLL */ + link_freq_index = ov5670->cur_mode->link_freq_index; + reg_list = &link_freq_configs[link_freq_index].reg_list; + ret = ov5670_write_reg_list(ov5670, reg_list); + if (ret) { + dev_err(&client->dev, "%s failed to set plls\n", __func__); + return ret; + } + + /* Apply default values of current mode */ + reg_list = &ov5670->cur_mode->reg_list; + ret = ov5670_write_reg_list(ov5670, reg_list); + if (ret) { + dev_err(&client->dev, "%s failed to set mode\n", __func__); + return ret; + } + + ret = __v4l2_ctrl_handler_setup(ov5670->sd.ctrl_handler); + if (ret) + return ret; + + /* Write stream on list */ + ret = ov5670_write_reg(ov5670, OV5670_REG_MODE_SELECT, + OV5670_REG_VALUE_08BIT, OV5670_MODE_STREAMING); + if (ret) { + dev_err(&client->dev, "%s failed to set stream\n", __func__); + return ret; + } + + ov5670->streaming = 1; + + return 0; +} + +static int ov5670_stop_streaming(struct ov5670 *ov5670) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov5670->sd); + int ret; + + ret = ov5670_write_reg(ov5670, OV5670_REG_MODE_SELECT, + OV5670_REG_VALUE_08BIT, OV5670_MODE_STANDBY); + if (ret) { + dev_err(&client->dev, "%s failed to set stream\n", __func__); + return ret; + } + ov5670->streaming = 0; + + return ret; +} + +static int ov5670_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov5670 *ov5670 = to_ov5670(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + mutex_lock(&ov5670->mutex); + if (ov5670->streaming == enable) + goto unlock_and_return; + + if (enable) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = ov5670_start_streaming(ov5670); + if (ret) + goto error; + } else { + ret = ov5670_stop_streaming(ov5670); + pm_runtime_put(&client->dev); + } + goto unlock_and_return; + +error: + pm_runtime_put(&client->dev); + +unlock_and_return: + mutex_unlock(&ov5670->mutex); + + return ret; +} + +static int __maybe_unused ov5670_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5670 *ov5670 = to_ov5670(sd); + + if (ov5670->streaming) + ov5670_stop_streaming(ov5670); + + return 0; +} + +static int __maybe_unused ov5670_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5670 *ov5670 = to_ov5670(sd); + int ret; + + if (ov5670->streaming) { + ret = ov5670_start_streaming(ov5670); + if (ret) { + ov5670_stop_streaming(ov5670); + return ret; + } + } + + return 0; +} + +/* Verify chip ID */ +static int ov5670_identify_module(struct ov5670 *ov5670) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov5670->sd); + int ret; + u32 val; + + ret = ov5670_read_reg(ov5670, OV5670_REG_CHIP_ID, + OV5670_REG_VALUE_24BIT, &val); + if (ret) + return ret; + + if (val != OV5670_CHIP_ID) { + dev_err(&client->dev, "chip id mismatch: %x!=%x\n", + OV5670_CHIP_ID, val); + return -ENXIO; + } + + return 0; +} + +static const struct v4l2_subdev_video_ops ov5670_video_ops = { + .s_stream = ov5670_set_stream, +}; + +static const struct v4l2_subdev_pad_ops ov5670_pad_ops = { + .enum_mbus_code = ov5670_enum_mbus_code, + .get_fmt = ov5670_get_pad_format, + .set_fmt = ov5670_set_pad_format, + .enum_frame_size = ov5670_enum_frame_size, +}; + +static const struct v4l2_subdev_sensor_ops ov5670_sensor_ops = { + .g_skip_frames = ov5670_get_skip_frames, +}; + +static const struct v4l2_subdev_ops ov5670_subdev_ops = { + .video = &ov5670_video_ops, + .pad = &ov5670_pad_ops, + .sensor = &ov5670_sensor_ops, +}; + +static const struct media_entity_operations ov5670_subdev_entity_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_subdev_internal_ops ov5670_internal_ops = { + .open = ov5670_open, +}; + +static int ov5670_probe(struct i2c_client *client, + const struct i2c_device_id *devid) +{ + struct ov5670 *ov5670; + const char *err_msg; + int ret; + + ov5670 = devm_kzalloc(&client->dev, sizeof(*ov5670), GFP_KERNEL); + if (!ov5670) { + ret = -ENOMEM; + err_msg = "devm_kzalloc() error"; + goto error_print; + } + + /* Initialize subdev */ + v4l2_i2c_subdev_init(&ov5670->sd, client, &ov5670_subdev_ops); + + /* Check module identity */ + ret = ov5670_identify_module(ov5670); + if (ret) { + err_msg = "ov5670_identify_module() error"; + goto error_print; + } + + mutex_init(&ov5670->mutex); + + /* Set default mode to max resolution */ + ov5670->cur_mode = &supported_modes[0]; + + ret = ov5670_init_controls(ov5670); + if (ret) { + err_msg = "ov5670_init_controls() error"; + goto error_mutex_destroy; + } + + ov5670->sd.internal_ops = &ov5670_internal_ops; + ov5670->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + ov5670->sd.entity.ops = &ov5670_subdev_entity_ops; + ov5670->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + /* Source pad initialization */ + ov5670->pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&ov5670->sd.entity, 1, &ov5670->pad); + if (ret) { + err_msg = "media_entity_pads_init() error"; + goto error_handler_free; + } + + /* Async register for subdev */ + ret = v4l2_async_register_subdev(&ov5670->sd); + if (ret < 0) { + err_msg = "v4l2_async_register_subdev() error"; + goto error_entity_cleanup; + } + + ov5670->streaming = 0; + + /* + * Device is already turned on by i2c-core with ACPI domain PM. + * Enable runtime PM and turn off the device. + */ + pm_runtime_get_noresume(&client->dev); + pm_runtime_set_active(&client->dev); + pm_runtime_enable(&client->dev); + pm_runtime_put(&client->dev); + + return 0; + +error_entity_cleanup: + media_entity_cleanup(&ov5670->sd.entity); + +error_handler_free: + v4l2_ctrl_handler_free(ov5670->sd.ctrl_handler); + +error_mutex_destroy: + mutex_destroy(&ov5670->mutex); + +error_print: + dev_err(&client->dev, "%s: %s %d\n", __func__, err_msg, ret); + + return ret; +} + +static int ov5670_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5670 *ov5670 = to_ov5670(sd); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + mutex_destroy(&ov5670->mutex); + + /* + * Disable runtime PM but keep the device turned on. + * i2c-core with ACPI domain PM will turn off the device. + */ + pm_runtime_get_sync(&client->dev); + pm_runtime_disable(&client->dev); + pm_runtime_set_suspended(&client->dev); + pm_runtime_put_noidle(&client->dev); + + return 0; +} + +static const struct i2c_device_id ov5670_id_table[] = { + {"ov5670", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov5670_id_table); + +static const struct dev_pm_ops ov5670_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ov5670_suspend, ov5670_resume) +}; + +#ifdef CONFIG_ACPI +static const struct acpi_device_id ov5670_acpi_ids[] = { + {"INT3479"}, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(acpi, ov5670_acpi_ids); +#endif + +static struct i2c_driver ov5670_i2c_driver = { + .driver = { + .name = "ov5670", + .owner = THIS_MODULE, + .pm = &ov5670_pm_ops, + .acpi_match_table = ACPI_PTR(ov5670_acpi_ids), + }, + .probe = ov5670_probe, + .remove = ov5670_remove, + .id_table = ov5670_id_table, +}; + +module_i2c_driver(ov5670_i2c_driver); + +MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>"); +MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>"); +MODULE_DESCRIPTION("Omnivision ov5670 sensor driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] i2c: fix semicolon.cocci warnings 2017-06-14 1:39 ` chiranjeevi.rapolu @ 2017-06-14 13:47 ` kbuild test robot 0 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2017-06-14 13:47 UTC (permalink / raw) To: chiranjeevi.rapolu Cc: kbuild-all, linux-media, sakari.ailus, tfiga, jian.xu.zheng, rajmohan.mani, hyungwoo.yang, Chiranjeevi Rapolu drivers/media/i2c/ov5670.c:2001:2-3: Unneeded semicolon drivers/media/i2c/ov5670.c:2033:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> --- ov5670.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/media/i2c/ov5670.c +++ b/drivers/media/i2c/ov5670.c @@ -1998,7 +1998,7 @@ static int ov5670_set_ctrl(struct v4l2_c __v4l2_ctrl_modify_range(ov5670->exposure, ov5670->exposure->minimum, max, ov5670->exposure->step, max); break; - }; + } /* V4L2 controls values will be applied only when power is already up */ if (pm_runtime_get_if_in_use(&client->dev) <= 0) @@ -2030,7 +2030,7 @@ static int ov5670_set_ctrl(struct v4l2_c dev_info(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", __func__, ctrl->id, ctrl->val); break; - }; + } pm_runtime_put(&client->dev); ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] [media] i2c: add support for OV13858 sensor 2017-05-23 23:58 ` Hyungwoo Yang @ 2017-05-24 13:58 kbuild test robot 2017-05-23 23:58 ` Hyungwoo Yang 0 siblings, 1 reply; 16+ messages in thread From: kbuild test robot @ 2017-05-24 13:58 UTC (permalink / raw) To: Hyungwoo Yang Cc: kbuild-all, linux-media, sakari.ailus, jian.xu.zheng, hyungwoo.yang Hi Hyungwoo, [auto build test WARNING on linuxtv-media/master] [also build test WARNING on v4.12-rc2 next-20170524] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Hyungwoo-Yang/i2c-add-support-for-OV13858-sensor/20170524-201204 base: git://linuxtv.org/media_tree.git master coccinelle warnings: (new ones prefixed by >>) >> drivers/media/i2c/ov13858.c:1838:3-8: No need to set .owner here. The core will do it. -- >> drivers/media/i2c/ov13858.c:1319:2-3: Unneeded semicolon Please review and possibly fold the followup patch. --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/1] [media] i2c: add support for OV13858 sensor @ 2017-05-23 23:58 ` Hyungwoo Yang 2017-05-24 13:58 ` [PATCH] i2c: fix semicolon.cocci warnings kbuild test robot 0 siblings, 1 reply; 16+ messages in thread From: Hyungwoo Yang @ 2017-05-23 23:58 UTC (permalink / raw) To: linux-media, sakari.ailus; +Cc: jian.xu.zheng, hyungwoo.yang This patch adds driver for Omnivision's ov13858 sensor, the driver supports following features: - manual exposure/analog gain - two link frequencies - media controller support - runtime pm support Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> --- drivers/media/i2c/Kconfig | 8 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/ov13858.c | 1853 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1862 insertions(+) create mode 100644 drivers/media/i2c/ov13858.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index fd181c9..f8c5cca 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -589,6 +589,14 @@ config VIDEO_OV9650 This is a V4L2 sensor-level driver for the Omnivision OV9650 and OV9652 camera sensors. +config VIDEO_OV13858 + tristate "OmniVision OV13858 sensor support" + depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on MEDIA_CAMERA_SUPPORT + ---help--- + This is a Video4Linux2 sensor-level driver for the OmniVision + OV13858 camera. + config VIDEO_VS6624 tristate "ST VS6624 sensor support" depends on VIDEO_V4L2 && I2C diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 62323ec..3f4dc02 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_VIDEO_OV5647) += ov5647.o obj-$(CONFIG_VIDEO_OV7640) += ov7640.o obj-$(CONFIG_VIDEO_OV7670) += ov7670.o obj-$(CONFIG_VIDEO_OV9650) += ov9650.o +obj-$(CONFIG_VIDEO_OV13858) += ov13858.o obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o obj-$(CONFIG_VIDEO_MT9M111) += mt9m111.o obj-$(CONFIG_VIDEO_MT9P031) += mt9p031.o diff --git a/drivers/media/i2c/ov13858.c b/drivers/media/i2c/ov13858.c new file mode 100644 index 0000000..7fc735e --- /dev/null +++ b/drivers/media/i2c/ov13858.c @@ -0,0 +1,1853 @@ +/* + * Copyright (c) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/acpi.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> + +#define OV13858_REG_VALUE_08BIT 1 +#define OV13858_REG_VALUE_16BIT 2 +#define OV13858_REG_VALUE_24BIT 3 + +#define OV13858_REG_MODE_SELECT 0x0100 +#define OV13858_MODE_STANDBY 0x00 +#define OV13858_MODE_STREAMING 0x01 + +#define OV13858_REG_SOFTWARE_RST 0x0103 +#define OV13858_SOFTWARE_RST 0x01 + +/* PLL1 generates PCLK and MIPI_PHY_CLK */ +#define OV13858_REG_PLL1_CTRL_0 0x0300 +#define OV13858_REG_PLL1_CTRL_1 0x0301 +#define OV13858_REG_PLL1_CTRL_2 0x0302 +#define OV13858_REG_PLL1_CTRL_3 0x0303 +#define OV13858_REG_PLL1_CTRL_4 0x0304 +#define OV13858_REG_PLL1_CTRL_5 0x0305 + +/* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */ +#define OV13858_REG_PLL2_CTRL_B 0x030b +#define OV13858_REG_PLL2_CTRL_C 0x030c +#define OV13858_REG_PLL2_CTRL_D 0x030d +#define OV13858_REG_PLL2_CTRL_E 0x030e +#define OV13858_REG_PLL2_CTRL_F 0x030f +#define OV13858_REG_PLL2_CTRL_12 0x0312 +#define OV13858_REG_MIPI_SC_CTRL0 0x3016 +#define OV13858_REG_MIPI_SC_CTRL1 0x3022 + +/* Chip ID */ +#define OV13858_REG_CHIP_ID 0x300a +#define OV13858_CHIP_ID 0x00d855 + +/* Group access */ +#define OV13858_REG_GROUP_ACCESS 0x3208 +#define OV13858_GROUP_HOLD_START(g_id) (0x00 | (g_id)) +#define OV13858_GROUP_HOLD_END(g_id) (0x10 | (g_id)) +#define OV13858_GROUP_LAUNCH(g_id) (0xa0 | (g_id)) +#define OV13858_GROUP_FAST_LAUNCH(g_id) (0xe0 | (g_id)) + +/* H-/V-offset control for expected bayer order */ +#define OV13858_REG_H_OFFSET 0x3810 +#define OV13858_REG_V_OFFSET 0x3812 + +/* V-timing internal */ +#define OV13858_REG_VTS 0x380e +#define OV13858_VTS_30FPS 0x0c8e /* 30 fps */ +#define OV13858_VTS_60FPS 0x0648 /* 60 fps */ +#define OV13858_VTS_MAX 0x7fff + +/* Exposure control */ +#define OV13858_REG_EXPOSURE 0x3500 +#define OV13858_EXP_GAIN_MIN 4 +#define OV13858_EXP_GAIN_MAX (OV13858_VTS_MAX - 8) +#define OV13858_EXP_GAIN_STEP 1 +#define OV13858_EXP_GAIN_DEFAULT 0x640 + +/* Analog gain control */ +#define OV13858_REG_ANALOG_GAIN 0x3508 +#define OV13858_ANA_GAIN_MIN 0 +#define OV13858_ANA_GAIN_MAX 0x1fff +#define OV13858_ANA_GAIN_STEP 1 +#define OV13858_ANA_GAIN_DEFAULT 0x80 + +/* Number of frames to skip */ +#define OV13858_NUM_OF_SKIP_FRAMES 2 + +struct ov13858_reg { + u16 address; + u8 val; +}; + +struct ov13858_reg_list { + u32 num_of_regs; + const struct ov13858_reg *regs; +}; + +/* Link frequency config */ +struct ov13858_link_freq_config { + u32 pixel_rate; + + /* PLL registers for this link frequency */ + struct ov13858_reg_list reg_list; +}; + +/* Mode : resolution and related config&values */ +struct ov13858_mode { + /* Frame width */ + u32 width; + /* Frame height */ + u32 height; + + /* V-timing */ + u32 vts; + + /* Index of Link frequency config to be used */ + u32 link_freq_index; + /* Default register values */ + struct ov13858_reg_list reg_list; +}; + +/* 4224x3136 needs 1080Mbps/lane, 4 lanes */ +static const struct ov13858_reg mipi_data_rate_1080mbps[] = { + /* PLL1 registers */ + {OV13858_REG_PLL1_CTRL_0, 0x07}, + {OV13858_REG_PLL1_CTRL_1, 0x01}, + {OV13858_REG_PLL1_CTRL_2, 0xc2}, + {OV13858_REG_PLL1_CTRL_3, 0x00}, + {OV13858_REG_PLL1_CTRL_4, 0x00}, + {OV13858_REG_PLL1_CTRL_5, 0x01}, + + /* PLL2 registers */ + {OV13858_REG_PLL2_CTRL_B, 0x05}, + {OV13858_REG_PLL2_CTRL_C, 0x01}, + {OV13858_REG_PLL2_CTRL_D, 0x0e}, + {OV13858_REG_PLL2_CTRL_E, 0x05}, + {OV13858_REG_PLL2_CTRL_F, 0x01}, + {OV13858_REG_PLL2_CTRL_12, 0x01}, + {OV13858_REG_MIPI_SC_CTRL0, 0x72}, + {OV13858_REG_MIPI_SC_CTRL1, 0x01}, +}; + +/* + * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane, + * 4 lanes + */ +static const struct ov13858_reg mipi_data_rate_540mbps[] = { + /* PLL1 registers */ + {OV13858_REG_PLL1_CTRL_0, 0x07}, + {OV13858_REG_PLL1_CTRL_1, 0x01}, + {OV13858_REG_PLL1_CTRL_2, 0xc2}, + {OV13858_REG_PLL1_CTRL_3, 0x01}, + {OV13858_REG_PLL1_CTRL_4, 0x00}, + {OV13858_REG_PLL1_CTRL_5, 0x01}, + + /* PLL2 registers */ + {OV13858_REG_PLL2_CTRL_B, 0x05}, + {OV13858_REG_PLL2_CTRL_C, 0x01}, + {OV13858_REG_PLL2_CTRL_D, 0x0e}, + {OV13858_REG_PLL2_CTRL_E, 0x05}, + {OV13858_REG_PLL2_CTRL_F, 0x01}, + {OV13858_REG_PLL2_CTRL_12, 0x01}, + {OV13858_REG_MIPI_SC_CTRL0, 0x72}, + {OV13858_REG_MIPI_SC_CTRL1, 0x01}, +}; + +static const struct ov13858_reg mode_4224x3136_regs[] = { + {0x3013, 0x32}, + {0x301b, 0xf0}, + {0x301f, 0xd0}, + {0x3106, 0x15}, + {0x3107, 0x23}, + {0x350a, 0x00}, + {0x350e, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3600, 0x2b}, + {0x3601, 0x52}, + {0x3602, 0x60}, + {0x3612, 0x05}, + {0x3613, 0xa4}, + {0x3620, 0x80}, + {0x3621, 0x10}, + {0x3622, 0x30}, + {0x3624, 0x1c}, + {0x3640, 0x10}, + {0x3641, 0x70}, + {0x3661, 0x80}, + {0x3662, 0x12}, + {0x3664, 0x73}, + {0x3665, 0xa7}, + {0x366e, 0xff}, + {0x366f, 0xf4}, + {0x3674, 0x00}, + {0x3679, 0x0c}, + {0x367f, 0x01}, + {0x3680, 0x0c}, + {0x3681, 0x50}, + {0x3682, 0x50}, + {0x3683, 0xa9}, + {0x3684, 0xa9}, + {0x3709, 0x5f}, + {0x3714, 0x24}, + {0x371a, 0x3e}, + {0x3737, 0x04}, + {0x3738, 0xcc}, + {0x3739, 0x12}, + {0x373d, 0x26}, + {0x3764, 0x20}, + {0x3765, 0x20}, + {0x37a1, 0x36}, + {0x37a8, 0x3b}, + {0x37ab, 0x31}, + {0x37c2, 0x04}, + {0x37c3, 0xf1}, + {0x37c5, 0x00}, + {0x37d8, 0x03}, + {0x37d9, 0x0c}, + {0x37da, 0xc2}, + {0x37dc, 0x02}, + {0x37e0, 0x00}, + {0x37e1, 0x0a}, + {0x37e2, 0x14}, + {0x37e3, 0x04}, + {0x37e4, 0x2a}, + {0x37e5, 0x03}, + {0x37e6, 0x04}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x00}, + {0x3804, 0x10}, + {0x3805, 0x9f}, + {0x3806, 0x0c}, + {0x3807, 0x5f}, + {0x3808, 0x10}, + {0x3809, 0x80}, + {0x380a, 0x0c}, + {0x380b, 0x40}, + {0x380c, 0x04}, + {0x380d, 0x62}, + {0x380e, 0x0c}, + {0x380f, 0x8e}, + {0x3811, 0x04}, + {0x3813, 0x05}, + {0x3814, 0x01}, + {0x3815, 0x01}, + {0x3816, 0x01}, + {0x3817, 0x01}, + {0x3820, 0xa8}, + {0x3821, 0x00}, + {0x3822, 0xc2}, + {0x3823, 0x18}, + {0x3826, 0x11}, + {0x3827, 0x1c}, + {0x3829, 0x03}, + {0x3832, 0x00}, + {0x3c80, 0x00}, + {0x3c87, 0x01}, + {0x3c8c, 0x19}, + {0x3c8d, 0x1c}, + {0x3c90, 0x00}, + {0x3c91, 0x00}, + {0x3c92, 0x00}, + {0x3c93, 0x00}, + {0x3c94, 0x40}, + {0x3c95, 0x54}, + {0x3c96, 0x34}, + {0x3c97, 0x04}, + {0x3c98, 0x00}, + {0x3d8c, 0x73}, + {0x3d8d, 0xc0}, + {0x3f00, 0x0b}, + {0x3f03, 0x00}, + {0x4001, 0xe0}, + {0x4008, 0x00}, + {0x4009, 0x0f}, + {0x4011, 0xf0}, + {0x4017, 0x08}, + {0x4050, 0x04}, + {0x4051, 0x0b}, + {0x4052, 0x00}, + {0x4053, 0x80}, + {0x4054, 0x00}, + {0x4055, 0x80}, + {0x4056, 0x00}, + {0x4057, 0x80}, + {0x4058, 0x00}, + {0x4059, 0x80}, + {0x405e, 0x20}, + {0x4500, 0x07}, + {0x4503, 0x00}, + {0x450a, 0x04}, + {0x4809, 0x04}, + {0x480c, 0x12}, + {0x481f, 0x30}, + {0x4833, 0x10}, + {0x4837, 0x0e}, + {0x4902, 0x01}, + {0x4d00, 0x03}, + {0x4d01, 0xc9}, + {0x4d02, 0xbc}, + {0x4d03, 0xd7}, + {0x4d04, 0xf0}, + {0x4d05, 0xa2}, + {0x5000, 0xfd}, + {0x5001, 0x01}, + {0x5040, 0x39}, + {0x5041, 0x10}, + {0x5042, 0x10}, + {0x5043, 0x84}, + {0x5044, 0x62}, + {0x5180, 0x00}, + {0x5181, 0x10}, + {0x5182, 0x02}, + {0x5183, 0x0f}, + {0x5200, 0x1b}, + {0x520b, 0x07}, + {0x520c, 0x0f}, + {0x5300, 0x04}, + {0x5301, 0x0c}, + {0x5302, 0x0c}, + {0x5303, 0x0f}, + {0x5304, 0x00}, + {0x5305, 0x70}, + {0x5306, 0x00}, + {0x5307, 0x80}, + {0x5308, 0x00}, + {0x5309, 0xa5}, + {0x530a, 0x00}, + {0x530b, 0xd3}, + {0x530c, 0x00}, + {0x530d, 0xf0}, + {0x530e, 0x01}, + {0x530f, 0x10}, + {0x5310, 0x01}, + {0x5311, 0x20}, + {0x5312, 0x01}, + {0x5313, 0x20}, + {0x5314, 0x01}, + {0x5315, 0x20}, + {0x5316, 0x08}, + {0x5317, 0x08}, + {0x5318, 0x10}, + {0x5319, 0x88}, + {0x531a, 0x88}, + {0x531b, 0xa9}, + {0x531c, 0xaa}, + {0x531d, 0x0a}, + {0x5405, 0x02}, + {0x5406, 0x67}, + {0x5407, 0x01}, + {0x5408, 0x4a}, +}; + +static const struct ov13858_reg mode_2112x1568_regs[] = { + {0x3013, 0x32}, + {0x301b, 0xf0}, + {0x301f, 0xd0}, + {0x3106, 0x15}, + {0x3107, 0x23}, + {0x350a, 0x00}, + {0x350e, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3600, 0x2b}, + {0x3601, 0x52}, + {0x3602, 0x60}, + {0x3612, 0x05}, + {0x3613, 0xa4}, + {0x3620, 0x80}, + {0x3621, 0x10}, + {0x3622, 0x30}, + {0x3624, 0x1c}, + {0x3640, 0x10}, + {0x3641, 0x70}, + {0x3661, 0x80}, + {0x3662, 0x10}, + {0x3664, 0x73}, + {0x3665, 0xa7}, + {0x366e, 0xff}, + {0x366f, 0xf4}, + {0x3674, 0x00}, + {0x3679, 0x0c}, + {0x367f, 0x01}, + {0x3680, 0x0c}, + {0x3681, 0x50}, + {0x3682, 0x50}, + {0x3683, 0xa9}, + {0x3684, 0xa9}, + {0x3709, 0x5f}, + {0x3714, 0x28}, + {0x371a, 0x3e}, + {0x3737, 0x08}, + {0x3738, 0xcc}, + {0x3739, 0x20}, + {0x373d, 0x26}, + {0x3764, 0x20}, + {0x3765, 0x20}, + {0x37a1, 0x36}, + {0x37a8, 0x3b}, + {0x37ab, 0x31}, + {0x37c2, 0x14}, + {0x37c3, 0xf1}, + {0x37c5, 0x00}, + {0x37d8, 0x03}, + {0x37d9, 0x0c}, + {0x37da, 0xc2}, + {0x37dc, 0x02}, + {0x37e0, 0x00}, + {0x37e1, 0x0a}, + {0x37e2, 0x14}, + {0x37e3, 0x08}, + {0x37e4, 0x38}, + {0x37e5, 0x03}, + {0x37e6, 0x08}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x00}, + {0x3804, 0x10}, + {0x3805, 0x9f}, + {0x3806, 0x0c}, + {0x3807, 0x5f}, + {0x3808, 0x08}, + {0x3809, 0x40}, + {0x380a, 0x06}, + {0x380b, 0x20}, + {0x380c, 0x04}, + {0x380d, 0x62}, + {0x380e, 0x0c}, + {0x380f, 0x8e}, + {0x3811, 0x04}, + {0x3813, 0x05}, + {0x3814, 0x03}, + {0x3815, 0x01}, + {0x3816, 0x03}, + {0x3817, 0x01}, + {0x3820, 0xab}, + {0x3821, 0x00}, + {0x3822, 0xc2}, + {0x3823, 0x18}, + {0x3826, 0x04}, + {0x3827, 0x90}, + {0x3829, 0x07}, + {0x3832, 0x00}, + {0x3c80, 0x00}, + {0x3c87, 0x01}, + {0x3c8c, 0x19}, + {0x3c8d, 0x1c}, + {0x3c90, 0x00}, + {0x3c91, 0x00}, + {0x3c92, 0x00}, + {0x3c93, 0x00}, + {0x3c94, 0x40}, + {0x3c95, 0x54}, + {0x3c96, 0x34}, + {0x3c97, 0x04}, + {0x3c98, 0x00}, + {0x3d8c, 0x73}, + {0x3d8d, 0xc0}, + {0x3f00, 0x0b}, + {0x3f03, 0x00}, + {0x4001, 0xe0}, + {0x4008, 0x00}, + {0x4009, 0x0d}, + {0x4011, 0xf0}, + {0x4017, 0x08}, + {0x4050, 0x04}, + {0x4051, 0x0b}, + {0x4052, 0x00}, + {0x4053, 0x80}, + {0x4054, 0x00}, + {0x4055, 0x80}, + {0x4056, 0x00}, + {0x4057, 0x80}, + {0x4058, 0x00}, + {0x4059, 0x80}, + {0x405e, 0x20}, + {0x4500, 0x07}, + {0x4503, 0x00}, + {0x450a, 0x04}, + {0x4809, 0x04}, + {0x480c, 0x12}, + {0x481f, 0x30}, + {0x4833, 0x10}, + {0x4837, 0x1c}, + {0x4902, 0x01}, + {0x4d00, 0x03}, + {0x4d01, 0xc9}, + {0x4d02, 0xbc}, + {0x4d03, 0xd7}, + {0x4d04, 0xf0}, + {0x4d05, 0xa2}, + {0x5000, 0xfd}, + {0x5001, 0x01}, + {0x5040, 0x39}, + {0x5041, 0x10}, + {0x5042, 0x10}, + {0x5043, 0x84}, + {0x5044, 0x62}, + {0x5180, 0x00}, + {0x5181, 0x10}, + {0x5182, 0x02}, + {0x5183, 0x0f}, + {0x5200, 0x1b}, + {0x520b, 0x07}, + {0x520c, 0x0f}, + {0x5300, 0x04}, + {0x5301, 0x0c}, + {0x5302, 0x0c}, + {0x5303, 0x0f}, + {0x5304, 0x00}, + {0x5305, 0x70}, + {0x5306, 0x00}, + {0x5307, 0x80}, + {0x5308, 0x00}, + {0x5309, 0xa5}, + {0x530a, 0x00}, + {0x530b, 0xd3}, + {0x530c, 0x00}, + {0x530d, 0xf0}, + {0x530e, 0x01}, + {0x530f, 0x10}, + {0x5310, 0x01}, + {0x5311, 0x20}, + {0x5312, 0x01}, + {0x5313, 0x20}, + {0x5314, 0x01}, + {0x5315, 0x20}, + {0x5316, 0x08}, + {0x5317, 0x08}, + {0x5318, 0x10}, + {0x5319, 0x88}, + {0x531a, 0x88}, + {0x531b, 0xa9}, + {0x531c, 0xaa}, + {0x531d, 0x0a}, + {0x5405, 0x02}, + {0x5406, 0x67}, + {0x5407, 0x01}, + {0x5408, 0x4a}, +}; + +static const struct ov13858_reg mode_2112x1188_regs[] = { + {0x3013, 0x32}, + {0x301b, 0xf0}, + {0x301f, 0xd0}, + {0x3106, 0x15}, + {0x3107, 0x23}, + {0x350a, 0x00}, + {0x350e, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3600, 0x2b}, + {0x3601, 0x52}, + {0x3602, 0x60}, + {0x3612, 0x05}, + {0x3613, 0xa4}, + {0x3620, 0x80}, + {0x3621, 0x10}, + {0x3622, 0x30}, + {0x3624, 0x1c}, + {0x3640, 0x10}, + {0x3641, 0x70}, + {0x3661, 0x80}, + {0x3662, 0x10}, + {0x3664, 0x73}, + {0x3665, 0xa7}, + {0x366e, 0xff}, + {0x366f, 0xf4}, + {0x3674, 0x00}, + {0x3679, 0x0c}, + {0x367f, 0x01}, + {0x3680, 0x0c}, + {0x3681, 0x50}, + {0x3682, 0x50}, + {0x3683, 0xa9}, + {0x3684, 0xa9}, + {0x3709, 0x5f}, + {0x3714, 0x28}, + {0x371a, 0x3e}, + {0x3737, 0x08}, + {0x3738, 0xcc}, + {0x3739, 0x20}, + {0x373d, 0x26}, + {0x3764, 0x20}, + {0x3765, 0x20}, + {0x37a1, 0x36}, + {0x37a8, 0x3b}, + {0x37ab, 0x31}, + {0x37c2, 0x14}, + {0x37c3, 0xf1}, + {0x37c5, 0x00}, + {0x37d8, 0x03}, + {0x37d9, 0x0c}, + {0x37da, 0xc2}, + {0x37dc, 0x02}, + {0x37e0, 0x00}, + {0x37e1, 0x0a}, + {0x37e2, 0x14}, + {0x37e3, 0x08}, + {0x37e4, 0x38}, + {0x37e5, 0x03}, + {0x37e6, 0x08}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x01}, + {0x3803, 0x84}, + {0x3804, 0x10}, + {0x3805, 0x9f}, + {0x3806, 0x0a}, + {0x3807, 0xd3}, + {0x3808, 0x08}, + {0x3809, 0x40}, + {0x380a, 0x04}, + {0x380b, 0xa4}, + {0x380c, 0x04}, + {0x380d, 0x62}, + {0x380e, 0x0c}, + {0x380f, 0x8e}, + {0x3811, 0x08}, + {0x3813, 0x03}, + {0x3814, 0x03}, + {0x3815, 0x01}, + {0x3816, 0x03}, + {0x3817, 0x01}, + {0x3820, 0xab}, + {0x3821, 0x00}, + {0x3822, 0xc2}, + {0x3823, 0x18}, + {0x3826, 0x04}, + {0x3827, 0x90}, + {0x3829, 0x07}, + {0x3832, 0x00}, + {0x3c80, 0x00}, + {0x3c87, 0x01}, + {0x3c8c, 0x19}, + {0x3c8d, 0x1c}, + {0x3c90, 0x00}, + {0x3c91, 0x00}, + {0x3c92, 0x00}, + {0x3c93, 0x00}, + {0x3c94, 0x40}, + {0x3c95, 0x54}, + {0x3c96, 0x34}, + {0x3c97, 0x04}, + {0x3c98, 0x00}, + {0x3d8c, 0x73}, + {0x3d8d, 0xc0}, + {0x3f00, 0x0b}, + {0x3f03, 0x00}, + {0x4001, 0xe0}, + {0x4008, 0x00}, + {0x4009, 0x0d}, + {0x4011, 0xf0}, + {0x4017, 0x08}, + {0x4050, 0x04}, + {0x4051, 0x0b}, + {0x4052, 0x00}, + {0x4053, 0x80}, + {0x4054, 0x00}, + {0x4055, 0x80}, + {0x4056, 0x00}, + {0x4057, 0x80}, + {0x4058, 0x00}, + {0x4059, 0x80}, + {0x405e, 0x20}, + {0x4500, 0x07}, + {0x4503, 0x00}, + {0x450a, 0x04}, + {0x4809, 0x04}, + {0x480c, 0x12}, + {0x481f, 0x30}, + {0x4833, 0x10}, + {0x4837, 0x1c}, + {0x4902, 0x01}, + {0x4d00, 0x03}, + {0x4d01, 0xc9}, + {0x4d02, 0xbc}, + {0x4d03, 0xd7}, + {0x4d04, 0xf0}, + {0x4d05, 0xa2}, + {0x5000, 0xfd}, + {0x5001, 0x01}, + {0x5040, 0x39}, + {0x5041, 0x10}, + {0x5042, 0x10}, + {0x5043, 0x84}, + {0x5044, 0x62}, + {0x5180, 0x00}, + {0x5181, 0x10}, + {0x5182, 0x02}, + {0x5183, 0x0f}, + {0x5200, 0x1b}, + {0x520b, 0x07}, + {0x520c, 0x0f}, + {0x5300, 0x04}, + {0x5301, 0x0c}, + {0x5302, 0x0c}, + {0x5303, 0x0f}, + {0x5304, 0x00}, + {0x5305, 0x70}, + {0x5306, 0x00}, + {0x5307, 0x80}, + {0x5308, 0x00}, + {0x5309, 0xa5}, + {0x530a, 0x00}, + {0x530b, 0xd3}, + {0x530c, 0x00}, + {0x530d, 0xf0}, + {0x530e, 0x01}, + {0x530f, 0x10}, + {0x5310, 0x01}, + {0x5311, 0x20}, + {0x5312, 0x01}, + {0x5313, 0x20}, + {0x5314, 0x01}, + {0x5315, 0x20}, + {0x5316, 0x08}, + {0x5317, 0x08}, + {0x5318, 0x10}, + {0x5319, 0x88}, + {0x531a, 0x88}, + {0x531b, 0xa9}, + {0x531c, 0xaa}, + {0x531d, 0x0a}, + {0x5405, 0x02}, + {0x5406, 0x67}, + {0x5407, 0x01}, + {0x5408, 0x4a}, +}; + +static const struct ov13858_reg mode_1056x784_regs[] = { + {0x3013, 0x32}, + {0x301b, 0xf0}, + {0x301f, 0xd0}, + {0x3106, 0x15}, + {0x3107, 0x23}, + {0x350a, 0x00}, + {0x350e, 0x00}, + {0x3510, 0x00}, + {0x3511, 0x02}, + {0x3512, 0x00}, + {0x3600, 0x2b}, + {0x3601, 0x52}, + {0x3602, 0x60}, + {0x3612, 0x05}, + {0x3613, 0xa4}, + {0x3620, 0x80}, + {0x3621, 0x10}, + {0x3622, 0x30}, + {0x3624, 0x1c}, + {0x3640, 0x10}, + {0x3641, 0x70}, + {0x3661, 0x80}, + {0x3662, 0x08}, + {0x3664, 0x73}, + {0x3665, 0xa7}, + {0x366e, 0xff}, + {0x366f, 0xf4}, + {0x3674, 0x00}, + {0x3679, 0x0c}, + {0x367f, 0x01}, + {0x3680, 0x0c}, + {0x3681, 0x50}, + {0x3682, 0x50}, + {0x3683, 0xa9}, + {0x3684, 0xa9}, + {0x3709, 0x5f}, + {0x3714, 0x30}, + {0x371a, 0x3e}, + {0x3737, 0x08}, + {0x3738, 0xcc}, + {0x3739, 0x20}, + {0x373d, 0x26}, + {0x3764, 0x20}, + {0x3765, 0x20}, + {0x37a1, 0x36}, + {0x37a8, 0x3b}, + {0x37ab, 0x31}, + {0x37c2, 0x2c}, + {0x37c3, 0xf1}, + {0x37c5, 0x00}, + {0x37d8, 0x03}, + {0x37d9, 0x06}, + {0x37da, 0xc2}, + {0x37dc, 0x02}, + {0x37e0, 0x00}, + {0x37e1, 0x0a}, + {0x37e2, 0x14}, + {0x37e3, 0x08}, + {0x37e4, 0x36}, + {0x37e5, 0x03}, + {0x37e6, 0x08}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x00}, + {0x3804, 0x10}, + {0x3805, 0x9f}, + {0x3806, 0x0c}, + {0x3807, 0x5f}, + {0x3808, 0x04}, + {0x3809, 0x20}, + {0x380a, 0x03}, + {0x380b, 0x10}, + {0x380c, 0x04}, + {0x380d, 0x62}, + {0x380e, 0x0c}, + {0x380f, 0x8e}, + {0x3811, 0x04}, + {0x3813, 0x05}, + {0x3814, 0x07}, + {0x3815, 0x01}, + {0x3816, 0x07}, + {0x3817, 0x01}, + {0x3820, 0xac}, + {0x3821, 0x00}, + {0x3822, 0xc2}, + {0x3823, 0x18}, + {0x3826, 0x04}, + {0x3827, 0x48}, + {0x3829, 0x03}, + {0x3832, 0x00}, + {0x3c80, 0x00}, + {0x3c87, 0x01}, + {0x3c8c, 0x19}, + {0x3c8d, 0x1c}, + {0x3c90, 0x00}, + {0x3c91, 0x00}, + {0x3c92, 0x00}, + {0x3c93, 0x00}, + {0x3c94, 0x40}, + {0x3c95, 0x54}, + {0x3c96, 0x34}, + {0x3c97, 0x04}, + {0x3c98, 0x00}, + {0x3d8c, 0x73}, + {0x3d8d, 0xc0}, + {0x3f00, 0x0b}, + {0x3f03, 0x00}, + {0x4001, 0xe0}, + {0x4008, 0x00}, + {0x4009, 0x05}, + {0x4011, 0xf0}, + {0x4017, 0x08}, + {0x4050, 0x02}, + {0x4051, 0x05}, + {0x4052, 0x00}, + {0x4053, 0x80}, + {0x4054, 0x00}, + {0x4055, 0x80}, + {0x4056, 0x00}, + {0x4057, 0x80}, + {0x4058, 0x00}, + {0x4059, 0x80}, + {0x405e, 0x20}, + {0x4500, 0x07}, + {0x4503, 0x00}, + {0x450a, 0x04}, + {0x4809, 0x04}, + {0x480c, 0x12}, + {0x481f, 0x30}, + {0x4833, 0x10}, + {0x4837, 0x1e}, + {0x4902, 0x02}, + {0x4d00, 0x03}, + {0x4d01, 0xc9}, + {0x4d02, 0xbc}, + {0x4d03, 0xd7}, + {0x4d04, 0xf0}, + {0x4d05, 0xa2}, + {0x5000, 0xfd}, + {0x5001, 0x01}, + {0x5040, 0x39}, + {0x5041, 0x10}, + {0x5042, 0x10}, + {0x5043, 0x84}, + {0x5044, 0x62}, + {0x5180, 0x00}, + {0x5181, 0x10}, + {0x5182, 0x02}, + {0x5183, 0x0f}, + {0x5200, 0x1b}, + {0x520b, 0x07}, + {0x520c, 0x0f}, + {0x5300, 0x04}, + {0x5301, 0x0c}, + {0x5302, 0x0c}, + {0x5303, 0x0f}, + {0x5304, 0x00}, + {0x5305, 0x70}, + {0x5306, 0x00}, + {0x5307, 0x80}, + {0x5308, 0x00}, + {0x5309, 0xa5}, + {0x530a, 0x00}, + {0x530b, 0xd3}, + {0x530c, 0x00}, + {0x530d, 0xf0}, + {0x530e, 0x01}, + {0x530f, 0x10}, + {0x5310, 0x01}, + {0x5311, 0x20}, + {0x5312, 0x01}, + {0x5313, 0x20}, + {0x5314, 0x01}, + {0x5315, 0x20}, + {0x5316, 0x08}, + {0x5317, 0x08}, + {0x5318, 0x10}, + {0x5319, 0x88}, + {0x531a, 0x88}, + {0x531b, 0xa9}, + {0x531c, 0xaa}, + {0x531d, 0x0a}, + {0x5405, 0x02}, + {0x5406, 0x67}, + {0x5407, 0x01}, + {0x5408, 0x4a}, +}; + +/* Configurations for supported link frequencies */ +#define OV13858_NUM_OF_LINK_FREQS 2 +#define OV13858_LINK_FREQ_1080MBPS 1080000000 +#define OV13858_LINK_FREQ_540MBPS 540000000 +#define OV13858_LINK_FREQ_INDEX_0 0 +#define OV13858_LINK_FREQ_INDEX_1 1 + +/* Menu items for LINK_FREQ V4L2 control */ +static const const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = { + OV13858_LINK_FREQ_1080MBPS, + OV13858_LINK_FREQ_540MBPS +}; + +/* Link frequency configs */ +static const struct ov13858_link_freq_config + link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = { + { + .pixel_rate = 864000000, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps), + .regs = mipi_data_rate_1080mbps, + } + }, + { + .pixel_rate = 432000000, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps), + .regs = mipi_data_rate_540mbps, + } + } +}; + +#define OV13858_GET_PIXEL_RATE(index) (link_freq_configs[index].pixel_rate) + +/* Mode configs */ +static const struct ov13858_mode supported_modes[] = { + { + .width = 4224, + .height = 3136, + .vts = OV13858_VTS_30FPS, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs), + .regs = mode_4224x3136_regs, + }, + .link_freq_index = OV13858_LINK_FREQ_INDEX_0, + }, + { + .width = 2112, + .height = 1568, + .vts = OV13858_VTS_30FPS, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs), + .regs = mode_2112x1568_regs, + }, + .link_freq_index = OV13858_LINK_FREQ_INDEX_1, + }, + { + .width = 2112, + .height = 1188, + .vts = OV13858_VTS_30FPS, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs), + .regs = mode_2112x1188_regs, + }, + .link_freq_index = OV13858_LINK_FREQ_INDEX_1, + }, + { + .width = 1056, + .height = 784, + .vts = OV13858_VTS_30FPS, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_1056x784_regs), + .regs = mode_1056x784_regs, + }, + .link_freq_index = OV13858_LINK_FREQ_INDEX_1, + } +}; + +/* Supported raw bayer orders */ +static const u32 supported_bayer_format[] = { + MEDIA_BUS_FMT_SGRBG10_1X10, + MEDIA_BUS_FMT_SRGGB10_1X10, + MEDIA_BUS_FMT_SBGGR10_1X10, + MEDIA_BUS_FMT_SGBRG10_1X10 +}; + +struct ov13858 { + struct v4l2_subdev sd; + struct media_pad pad; + + struct v4l2_ctrl_handler ctrl_handler; + /* Two read only controls */ + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + + /* Current mode */ + const struct ov13858_mode *cur_mode; + + /* Current bayer format */ + u32 cur_bayer_format; + + /* Num of skip frames */ + u32 num_of_skip_frames; + + /* Mutex for serialized access */ + struct mutex mutex; + + /* Streaming on/off */ + bool streaming; +}; + +#define to_ov13858(_sd) container_of(_sd, struct ov13858, sd) + +/* Read registers up to 4 at a time */ +static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 *val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); + struct i2c_msg msgs[2]; + u8 *data_be_p; + int ret; + u32 data_be = 0; + u16 reg_addr_be = cpu_to_be16(reg); + + if (len > 4) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +/* Write registers up to 4 at a time */ +static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); + int buf_i, val_i; + u8 buf[6], *val_p; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + buf_i = 2; + val_p = (u8 *)&val; + val_i = len - 1; + + while (val_i >= 0) + buf[buf_i++] = val_p[val_i--]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +/* Write a list of registers */ +static int ov13858_write_regs(struct ov13858 *ov13858, + const struct ov13858_reg *regs, u32 len) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); + int ret; + u32 i; + + for (i = 0; i < len; i++) { + ret = ov13858_write_reg(ov13858, regs[i].address, 1, + regs[i].val); + if (ret) { + dev_err_ratelimited( + &client->dev, + "Failed to write reg 0x%4.4x. error = %d\n", + regs[i].address, ret); + + return ret; + } + } + + return 0; +} + +static inline int ov13858_write_reg_list(struct ov13858 *ov13858, + const struct ov13858_reg_list *r_list) +{ + return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs); +} + +/* Open sub-device */ +static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct ov13858 *ov13858 = to_ov13858(sd); + struct v4l2_mbus_framefmt *try_fmt; + + mutex_lock(&ov13858->mutex); + + /* Initialize try_fmt */ + try_fmt = v4l2_subdev_get_try_format(sd, fh->pad, 0); + try_fmt->width = ov13858->cur_mode->width; + try_fmt->height = ov13858->cur_mode->height; + try_fmt->code = ov13858->cur_bayer_format; + try_fmt->field = V4L2_FIELD_NONE; + + /* No crop or compose */ + mutex_unlock(&ov13858->mutex); + + return 0; +} + +/* + * Get the index of matched bayer format + */ +static int ov13858_get_bayer_format(u32 format) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(supported_bayer_format); i++) { + if (supported_bayer_format[i] == format) + return i; + } + + return -EINVAL; +} + +/* + * Start register group hold + */ +static inline int ov13858_group_hold_start(struct ov13858 *ov13858, + u8 group_id) +{ + return ov13858_write_reg(ov13858, OV13858_REG_GROUP_ACCESS, + OV13858_REG_VALUE_08BIT, + OV13858_GROUP_HOLD_START(group_id)); +} + +/* + * End register group hold + */ +static inline int ov13858_group_hold_end(struct ov13858 *ov13858, + u8 group_id) +{ + return ov13858_write_reg(ov13858, OV13858_REG_GROUP_ACCESS, + OV13858_REG_VALUE_08BIT, + OV13858_GROUP_HOLD_END(group_id)); +} + +/* + * Launch registers + */ +static inline int ov13858_launch_group(struct ov13858 *ov13858, + u8 group_id) +{ + return ov13858_write_reg(ov13858, OV13858_REG_GROUP_ACCESS, + OV13858_REG_VALUE_08BIT, + OV13858_GROUP_LAUNCH(group_id)); +} + +/* + * This function is called only after powerup to change the default bayer order + * to the user requested order. + */ +static int ov13858_increase_offset(struct ov13858 *ov13858, u16 reg) +{ + int ret; + u32 val; + + ret = ov13858_read_reg(ov13858, reg, OV13858_REG_VALUE_16BIT, &val); + if (ret) + return ret; + + val++; + + return ov13858_write_reg(ov13858, reg, OV13858_REG_VALUE_16BIT, val); +} + +/* + * Change the bayer order to meet the requested one. + */ +static int ov13858_apply_bayer_order(struct ov13858 *ov13858) +{ + int ret; + + switch (ov13858->cur_bayer_format) { + case MEDIA_BUS_FMT_SGRBG10_1X10: + break; + case MEDIA_BUS_FMT_SRGGB10_1X10: + return ov13858_increase_offset(ov13858, OV13858_REG_H_OFFSET); + case MEDIA_BUS_FMT_SGBRG10_1X10: + ret = ov13858_increase_offset(ov13858, OV13858_REG_H_OFFSET); + if (ret) + return ret; + /* no break, for GBRG, we need v offset too */ + case MEDIA_BUS_FMT_SBGGR10_1X10: + return ov13858_increase_offset(ov13858, OV13858_REG_V_OFFSET); + } + + return 0; +} + +/* + * Update analog gain + */ +static inline int ov13858_update_analog_gain(struct ov13858 *ov13858, + struct v4l2_ctrl *ctrl) +{ + return ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN, + OV13858_REG_VALUE_16BIT, ctrl->val); +} + +/* Exposure control */ +static int ov13858_update_exposure(struct ov13858 *ov13858, + struct v4l2_ctrl *ctrl) +{ + int ret; + u32 exposure, new_vts = 0; + + exposure = ctrl->val; + if (exposure > ov13858->cur_mode->vts - 8) + new_vts = exposure + 8; + else + new_vts = ov13858->cur_mode->vts; + + ret = ov13858_group_hold_start(ov13858, 0); + if (ret) + return ret; + + ret = ov13858_write_reg(ov13858, OV13858_REG_VTS, + OV13858_REG_VALUE_16BIT, new_vts); + if (ret) + return ret; + + exposure <<= 4; + ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE, + OV13858_REG_VALUE_24BIT, exposure); + if (ret) + return ret; + + ret = ov13858_group_hold_end(ov13858, 0); + if (ret) + return ret; + + return ov13858_launch_group(ov13858, 0); +} + +/* Initialize control handlers */ +static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov13858 *ov13858 = container_of(ctrl->handler, + struct ov13858, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); + int ret = 0; + + /* Values of V4L2 controls will be applied only when power is up */ + if (atomic_read(&client->dev.power.usage_count) == 0) + return 0; + + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + return ret; + } + + ret = 0; + switch (ctrl->id) { + case V4L2_CID_ANALOGUE_GAIN: + ret = ov13858_update_analog_gain(ov13858, ctrl); + break; + case V4L2_CID_EXPOSURE: + ret = ov13858_update_exposure(ov13858, ctrl); + break; + default: + dev_info(&client->dev, + "ctrl(id:0x%x,val:0x%x) is not handled\n", + ctrl->id, ctrl->val); + break; + }; + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops ov13858_ctrl_ops = { + .s_ctrl = ov13858_set_ctrl, +}; + +/* Initialize control handlers */ +static int ov13858_init_controls(struct ov13858 *ov13858) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); + struct v4l2_ctrl_handler *ctrl_hdlr; + int ret; + + ctrl_hdlr = &ov13858->ctrl_handler; + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 4); + if (ret) + return ret; + + ctrl_hdlr->lock = &ov13858->mutex; + ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, + &ov13858_ctrl_ops, + V4L2_CID_LINK_FREQ, + OV13858_NUM_OF_LINK_FREQS - 1, + 0, + link_freq_menu_items); + ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + /* By default, PIXEL_RATE is read only */ + ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, + V4L2_CID_PIXEL_RATE, 0, + OV13858_GET_PIXEL_RATE(0), 1, + OV13858_GET_PIXEL_RATE(0)); + + v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX, + OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT); + + v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_EXPOSURE, + OV13858_EXP_GAIN_MIN, OV13858_EXP_GAIN_MAX, + OV13858_EXP_GAIN_STEP, OV13858_EXP_GAIN_DEFAULT); + if (ctrl_hdlr->error) { + ret = ctrl_hdlr->error; + dev_err(&client->dev, "%s control init failed (%d)\n", + __func__, ret); + goto error; + } + + ov13858->sd.ctrl_handler = ctrl_hdlr; + + return 0; + +error: + v4l2_ctrl_handler_free(ctrl_hdlr); + + return ret; +} + +static void ov13858_update_pad_format(struct ov13858 *ov13858, + const struct ov13858_mode *mode, + struct v4l2_subdev_format *fmt) +{ + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = ov13858->cur_bayer_format; + fmt->format.field = V4L2_FIELD_NONE; +} + +static int ov13858_do_get_pad_format(struct ov13858 *ov13858, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt; + struct v4l2_subdev *sd = &ov13858->sd; + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + fmt->format = *framefmt; + } else { + ov13858_update_pad_format(ov13858, ov13858->cur_mode, fmt); + } + + return 0; +} + +static int ov13858_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= ARRAY_SIZE(supported_bayer_format)) + return -EINVAL; + + code->code = supported_bayer_format[code->index]; + return 0; +} + +static int ov13858_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (ov13858_get_bayer_format(fse->code) < 0) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = supported_modes[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +static int ov13858_get_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov13858 *ov13858 = to_ov13858(sd); + int ret; + + mutex_lock(&ov13858->mutex); + ret = ov13858_do_get_pad_format(ov13858, cfg, fmt); + mutex_unlock(&ov13858->mutex); + + return ret; +} + +/* + * Calculate resolution distance + */ +static inline int +ov13858_get_resolution_dist(const struct ov13858_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +/* + * Find the closest supported resolution to the requested resolution + */ +static const struct ov13858_mode * +ov13858_find_best_fit(struct ov13858 *ov13858, + struct v4l2_subdev_format *fmt) +{ + int i, dist, cur_best_fit = 0, cur_best_fit_dist = -1; + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = ov13858_get_resolution_dist(&supported_modes[i], + framefmt); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + + return &supported_modes[cur_best_fit]; +} + +static int +ov13858_set_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov13858 *ov13858 = to_ov13858(sd); + const struct ov13858_mode *mode; + struct v4l2_mbus_framefmt *framefmt; + int bayer_index; + + mutex_lock(&ov13858->mutex); + + /* Only raw bayer is supported */ + bayer_index = ov13858_get_bayer_format(fmt->format.code); + if (bayer_index < 0) + bayer_index = 0; /* Not found, suggest GRBG */ + + ov13858->cur_bayer_format = supported_bayer_format[bayer_index]; + mode = ov13858_find_best_fit(ov13858, fmt); + ov13858_update_pad_format(ov13858, mode, fmt); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + *framefmt = fmt->format; + } else { + ov13858->cur_mode = mode; + __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index); + __v4l2_ctrl_s_ctrl_int64( + ov13858->pixel_rate, + OV13858_GET_PIXEL_RATE(mode->link_freq_index)); + } + + mutex_unlock(&ov13858->mutex); + + return 0; +} + +static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov13858 *ov13858 = to_ov13858(sd); + + mutex_lock(&ov13858->mutex); + *frames = ov13858->num_of_skip_frames; + mutex_unlock(&ov13858->mutex); + + return 0; +} + +/* + * Prepare streaming by writing default values and customized values. + * This should be called with ov13858->mutex acquired. + */ +static int ov13858_prepare_streaming(struct ov13858 *ov13858) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); + const struct ov13858_reg_list *reg_list; + int ret, link_freq_index; + + /* Get out of from software reset */ + ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST, + OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST); + if (ret) { + dev_err(&client->dev, "%s failed to set powerup registers\n", + __func__); + return ret; + } + + /* Setup PLL */ + link_freq_index = ov13858->cur_mode->link_freq_index; + reg_list = &link_freq_configs[link_freq_index].reg_list; + ret = ov13858_write_reg_list(ov13858, reg_list); + if (ret) { + dev_err(&client->dev, "%s failed to set plls\n", __func__); + return ret; + } + + /* Apply default values of current mode */ + reg_list = &ov13858->cur_mode->reg_list; + ret = ov13858_write_reg_list(ov13858, reg_list); + if (ret) { + dev_err(&client->dev, "%s failed to set mode\n", __func__); + return ret; + } + + /* Apply customized values from user */ + __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler); + + /* Apply bayer order from user */ + return ov13858_apply_bayer_order(ov13858); +} + +/* Start streaming */ +static inline int ov13858_start_streaming(struct ov13858 *ov13858) +{ + int ret; + + /* Write default & customized values */ + ret = ov13858_prepare_streaming(ov13858); + if (ret) + return ret; + + return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, + OV13858_REG_VALUE_08BIT, + OV13858_MODE_STREAMING); +} + +/* Stop streaming */ +static inline int ov13858_stop_streaming(struct ov13858 *ov13858) +{ + return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, + OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY); +} + +static int ov13858_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov13858 *ov13858 = to_ov13858(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + mutex_lock(&ov13858->mutex); + if (ov13858->streaming == enable) { + mutex_unlock(&ov13858->mutex); + return 0; + } + + if (enable) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto err_unlock; + } + + /* + * Apply default & customized values + * and then start streaming. + */ + ret = ov13858_start_streaming(ov13858); + if (ret) + goto err_rpm_put; + } else { + ret = ov13858_stop_streaming(ov13858); + pm_runtime_put(&client->dev); + } + + ov13858->streaming = enable; + mutex_unlock(&ov13858->mutex); + + return ret; + +err_rpm_put: + pm_runtime_put(&client->dev); +err_unlock: + mutex_unlock(&ov13858->mutex); + + return ret; +} + +#ifdef CONFIG_PM + +static int ov13858_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov13858 *ov13858 = to_ov13858(sd); + + if (ov13858->streaming) + ov13858_stop_streaming(ov13858); + + return 0; +} + +static int ov13858_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov13858 *ov13858 = to_ov13858(sd); + int ret; + + if (ov13858->streaming) { + ret = ov13858_start_streaming(ov13858); + if (ret) + goto error; + } + + return 0; + +error: + ov13858_stop_streaming(ov13858); + ov13858->streaming = 0; + return ret; +} + +#else + +#define ov13858_suspend NULL +#define ov13858_resume NULL + +#endif /* CONFIG_PM */ + +/* Verify chip ID */ +static inline int ov13858_identify_module(struct ov13858 *ov13858) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); + int ret; + u32 val; + + ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID, + OV13858_REG_VALUE_24BIT, &val); + if (ret) + return ret; + + if (val != OV13858_CHIP_ID) { + dev_err(&client->dev, "chip id mismatch: %x!=%x\n", + OV13858_CHIP_ID, val); + return -EIO; + } + + return 0; +} + +static const struct v4l2_subdev_video_ops ov13858_video_ops = { + .s_stream = ov13858_set_stream, +}; + +static const struct v4l2_subdev_pad_ops ov13858_pad_ops = { + .enum_mbus_code = ov13858_enum_mbus_code, + .get_fmt = ov13858_get_pad_format, + .set_fmt = ov13858_set_pad_format, + .enum_frame_size = ov13858_enum_frame_size, +}; + +static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = { + .g_skip_frames = ov13858_get_skip_frames, +}; + +static const struct v4l2_subdev_ops ov13858_subdev_ops = { + .video = &ov13858_video_ops, + .pad = &ov13858_pad_ops, + .sensor = &ov13858_sensor_ops, +}; + +static const struct media_entity_operations ov13858_subdev_entity_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_subdev_internal_ops ov13858_internal_ops = { + .open = ov13858_open, +}; + +static int ov13858_probe(struct i2c_client *client, + const struct i2c_device_id *devid) +{ + struct ov13858 *ov13858; + int ret; + + ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL); + if (!ov13858) + return -ENOMEM; + + /* Initialize subdev */ + v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops); + + /* Check module identity */ + ret = ov13858_identify_module(ov13858); + if (ret) { + dev_err(&client->dev, "failed to find sensor: %d\n", ret); + return ret; + } + + mutex_init(&ov13858->mutex); + + /* Set default mode to max resolution */ + ov13858->cur_mode = &supported_modes[0]; + + /* Set default bayer format with GRBG */ + ov13858->cur_bayer_format = supported_bayer_format[0]; + + /* Set number of frames to skip */ + ov13858->num_of_skip_frames = OV13858_NUM_OF_SKIP_FRAMES; + + ret = ov13858_init_controls(ov13858); + if (ret) + return ret; + + /* Initialize subdev */ + ov13858->sd.internal_ops = &ov13858_internal_ops; + ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + ov13858->sd.entity.ops = &ov13858_subdev_entity_ops; + ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + /* Initialize source pad */ + ov13858->pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad); + if (ret) { + dev_err(&client->dev, "%s failed:%d\n", __func__, ret); + goto error_handler_free; + } + + /* Enable runtime pm management */ + pm_runtime_enable(&client->dev); + + ret = v4l2_async_register_subdev(&ov13858->sd); + if (ret < 0) + goto error_disable_rpm; + + dev_info(&client->dev, "%s done\n", __func__); + + return 0; + +error_disable_rpm: + pm_runtime_disable(&client->dev); + media_entity_cleanup(&ov13858->sd.entity); + +error_handler_free: + v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler); + dev_err(&client->dev, "%s failed:%d\n", __func__, ret); + + return ret; +} + +static int ov13858_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + pm_runtime_disable(&client->dev); + + return 0; +} + +static const struct i2c_device_id ov13858_id_table[] = { + {"ov13858", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov13858_id_table); + +static const struct dev_pm_ops ov13858_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume) +}; + +#ifdef CONFIG_ACPI +static const struct acpi_device_id ov13858_acpi_ids[] = { + {"OVTID858"}, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids); +#endif + +static struct i2c_driver ov13858_i2c_driver = { + .driver = { + .name = "ov13858", + .owner = THIS_MODULE, + .pm = &ov13858_pm_ops, + .acpi_match_table = ACPI_PTR(ov13858_acpi_ids), + }, + .probe = ov13858_probe, + .remove = ov13858_remove, + .id_table = ov13858_id_table, +}; + +module_i2c_driver(ov13858_i2c_driver); + +MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>"); +MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>"); +MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>"); +MODULE_DESCRIPTION("Omnivision ov13858 sensor driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] i2c: fix semicolon.cocci warnings 2017-05-23 23:58 ` Hyungwoo Yang @ 2017-05-24 13:58 ` kbuild test robot 0 siblings, 0 replies; 16+ messages in thread From: kbuild test robot @ 2017-05-24 13:58 UTC (permalink / raw) To: Hyungwoo Yang Cc: kbuild-all, linux-media, sakari.ailus, jian.xu.zheng, hyungwoo.yang drivers/media/i2c/ov13858.c:1319:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Hyungwoo Yang <hyungwoo.yang@intel.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> --- ov13858.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/media/i2c/ov13858.c +++ b/drivers/media/i2c/ov13858.c @@ -1316,7 +1316,7 @@ static int ov13858_set_ctrl(struct v4l2_ "ctrl(id:0x%x,val:0x%x) is not handled\n", ctrl->id, ctrl->val); break; - }; + } pm_runtime_put(&client->dev); ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-03-05 6:25 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-03-04 16:52 [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Loic Poulain 2020-03-04 16:52 ` [PATCH v3 2/3] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Loic Poulain 2020-03-04 19:05 ` Robert Foss 2020-03-04 19:44 ` Robert Foss 2020-03-04 16:52 ` [PATCH v3 3/3] arm64: dts: msm8916: Add CCI node Loic Poulain 2020-03-04 19:08 ` Robert Foss 2020-03-04 19:45 ` Robert Foss 2020-03-04 19:04 ` [PATCH v3 1/3] i2c: Add Qualcomm CCI I2C driver Robert Foss 2020-03-05 6:25 ` kbuild test robot 2020-03-05 6:25 ` kbuild test robot 2020-03-05 6:25 ` kbuild test robot 2020-03-05 6:25 ` [PATCH] i2c: fix semicolon.cocci warnings kbuild test robot 2020-03-05 6:25 ` kbuild test robot 2020-03-05 6:25 ` kbuild test robot -- strict thread matches above, loose matches on Subject: below -- 2017-06-14 13:47 [PATCH v3 1/1] i2c: Add Omnivision OV5670 5M sensor support kbuild test robot 2017-06-14 1:39 ` chiranjeevi.rapolu 2017-06-14 13:47 ` [PATCH] i2c: fix semicolon.cocci warnings kbuild test robot 2017-05-24 13:58 [PATCH 1/1] [media] i2c: add support for OV13858 sensor kbuild test robot 2017-05-23 23:58 ` Hyungwoo Yang 2017-05-24 13:58 ` [PATCH] i2c: fix semicolon.cocci warnings kbuild test robot
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