From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract Date: Mon, 9 Mar 2020 16:20:05 +0800 [thread overview] Message-ID: <20200309082042.12967-24-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200309082042.12967-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 ++ target/riscv/vector_helper.c | 278 ++++++++++++++++++++++++ 4 files changed, 337 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 121e9e57e7..95da00d365 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -674,3 +674,36 @@ DEF_HELPER_6(vmerge_vxm_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmerge_vxm_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmerge_vxm_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmerge_vxm_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vsaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bcb8273bcc..44baadf582 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -402,6 +402,16 @@ vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm vmerge_vvm 010111 . ..... ..... 000 ..... 1010111 @r_vm vmerge_vxm 010111 . ..... ..... 100 ..... 1010111 @r_vm vmerge_vim 010111 . ..... ..... 011 ..... 1010111 @r_vm +vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm +vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm +vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm +vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm +vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm +vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm +vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm +vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm +vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm +vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index aff5ca8663..ad55766b98 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1505,3 +1505,19 @@ static bool opivx_vmerge_check(DisasContext *s, arg_rmrr *a) GEN_OPIVX_TRANS(vmerge_vxm, opivx_vmerge_check) GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vmerge_check) + +/* + *** Vector Fixed-Point Arithmetic Instructions + */ + +/* Vector Single-Width Saturating Add and Subtract */ +GEN_OPIVV_GVEC_TRANS(vsaddu_vv, usadd) +GEN_OPIVV_GVEC_TRANS(vsadd_vv, ssadd) +GEN_OPIVV_GVEC_TRANS(vssubu_vv, ussub) +GEN_OPIVV_GVEC_TRANS(vssub_vv, sssub) +GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) +GEN_OPIVX_TRANS(vsadd_vx, opivx_check) +GEN_OPIVX_TRANS(vssubu_vx, opivx_check) +GEN_OPIVX_TRANS(vssub_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 273b705847..c7b8c1bff4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2013,3 +2013,281 @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb) GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh) GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl) GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq) + +/* + *** Vector Fixed-Point Arithmetic Instructions + */ + +/* Vector Single-Width Saturating Add and Subtract */ +#define OPIVV2_ENV(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX1 s1 = *((T1 *)vs1 + HS1(i)); \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(env, s2, s1); \ +} + +#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs1, vs2, i, env); \ + } \ + if (i != 0) { \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + } \ +} + +static inline uint8_t saddu8(CPURISCVState *env, uint8_t a, uint8_t b) +{ + uint8_t res = a + b; + if (res < a) { + res = UINT8_MAX; + env->vxsat = 0x1; + } + return res; +} +static inline uint16_t saddu16(CPURISCVState *env, uint16_t a, uint16_t b) +{ + uint16_t res = a + b; + if (res < a) { + res = UINT16_MAX; + env->vxsat = 0x1; + } + return res; +} +static inline uint32_t saddu32(CPURISCVState *env, uint32_t a, uint32_t b) +{ + uint32_t res = a + b; + if (res < a) { + res = UINT32_MAX; + env->vxsat = 0x1; + } + return res; +} +static inline uint64_t saddu64(CPURISCVState *env, uint64_t a, uint64_t b) +{ + uint64_t res = a + b; + if (res < a) { + res = UINT64_MAX; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8) +RVVCALL(OPIVV2_ENV, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16) +RVVCALL(OPIVV2_ENV, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32) +RVVCALL(OPIVV2_ENV, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64) +GEN_VEXT_VV_ENV(vsaddu_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vsaddu_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vsaddu_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vsaddu_vv_d, 8, 8, clearq) + +#define OPIVX2_ENV(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_ulong s1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(env, s2, (TX1)(T1)(target_long)s1); \ +} + +#define GEN_VEXT_VX_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, s1, vs2, i, env); \ + } \ + if (i != 0) { \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + } \ +} +RVVCALL(OPIVX2_ENV, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8) +RVVCALL(OPIVX2_ENV, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16) +RVVCALL(OPIVX2_ENV, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32) +RVVCALL(OPIVX2_ENV, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64) +GEN_VEXT_VX_ENV(vsaddu_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vsaddu_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vsaddu_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vsaddu_vx_d, 8, 8, clearq) + +static inline int8_t sadd8(CPURISCVState *env, int8_t a, int8_t b) +{ + int8_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 7 == -1LL) { + res = a > 0 ? INT8_MAX : INT8_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int16_t sadd16(CPURISCVState *env, int16_t a, int16_t b) +{ + int16_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 15 == -1LL) { + res = a > 0 ? INT16_MAX : INT16_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int32_t sadd32(CPURISCVState *env, int32_t a, int32_t b) +{ + int32_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 31 == -1LL) { + res = a > 0 ? INT32_MAX : INT32_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int64_t sadd64(CPURISCVState *env, int64_t a, int64_t b) +{ + int64_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 63 == -1LL) { + res = a > 0 ? INT64_MAX : INT64_MIN; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8) +RVVCALL(OPIVV2_ENV, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16) +RVVCALL(OPIVV2_ENV, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32) +RVVCALL(OPIVV2_ENV, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64) +GEN_VEXT_VV_ENV(vsadd_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vsadd_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vsadd_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vsadd_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8) +RVVCALL(OPIVX2_ENV, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16) +RVVCALL(OPIVX2_ENV, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32) +RVVCALL(OPIVX2_ENV, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64) +GEN_VEXT_VX_ENV(vsadd_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vsadd_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vsadd_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vsadd_vx_d, 8, 8, clearq) + +static inline uint8_t ssubu8(CPURISCVState *env, uint8_t a, uint8_t b) +{ + uint8_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +static inline uint16_t ssubu16(CPURISCVState *env, uint16_t a, uint16_t b) +{ + uint16_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +static inline uint32_t ssubu32(CPURISCVState *env, uint32_t a, uint32_t b) +{ + uint32_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +static inline uint64_t ssubu64(CPURISCVState *env, uint64_t a, uint64_t b) +{ + uint64_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8) +RVVCALL(OPIVV2_ENV, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16) +RVVCALL(OPIVV2_ENV, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32) +RVVCALL(OPIVV2_ENV, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64) +GEN_VEXT_VV_ENV(vssubu_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vssubu_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vssubu_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vssubu_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8) +RVVCALL(OPIVX2_ENV, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16) +RVVCALL(OPIVX2_ENV, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32) +RVVCALL(OPIVX2_ENV, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64) +GEN_VEXT_VX_ENV(vssubu_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vssubu_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vssubu_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vssubu_vx_d, 8, 8, clearq) + +static inline int8_t ssub8(CPURISCVState *env, int8_t a, int8_t b) +{ + int8_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 7 == -1LL) { + res = a > 0 ? INT8_MAX : INT8_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int16_t ssub16(CPURISCVState *env, int16_t a, int16_t b) +{ + int16_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 15 == -1LL) { + res = a > 0 ? INT16_MAX : INT16_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int32_t ssub32(CPURISCVState *env, int32_t a, int32_t b) +{ + int32_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 31 == -1LL) { + res = a > 0 ? INT32_MAX : INT32_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int64_t ssub64(CPURISCVState *env, int64_t a, int64_t b) +{ + int64_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 63 == -1LL) { + res = a > 0 ? INT64_MAX : INT64_MIN; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8) +RVVCALL(OPIVV2_ENV, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16) +RVVCALL(OPIVV2_ENV, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32) +RVVCALL(OPIVV2_ENV, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64) +GEN_VEXT_VV_ENV(vssub_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vssub_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vssub_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vssub_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vssub_vx_b, OP_SSS_B, H1, H1, ssub8) +RVVCALL(OPIVX2_ENV, vssub_vx_h, OP_SSS_H, H2, H2, ssub16) +RVVCALL(OPIVX2_ENV, vssub_vx_w, OP_SSS_W, H4, H4, ssub32) +RVVCALL(OPIVX2_ENV, vssub_vx_d, OP_SSS_D, H8, H8, ssub64) +GEN_VEXT_VX_ENV(vssub_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vssub_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vssub_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vssub_vx_d, 8, 8, clearq) -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, guoren@linux.alibaba.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract Date: Mon, 9 Mar 2020 16:20:05 +0800 [thread overview] Message-ID: <20200309082042.12967-24-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200309082042.12967-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 ++ target/riscv/vector_helper.c | 278 ++++++++++++++++++++++++ 4 files changed, 337 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 121e9e57e7..95da00d365 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -674,3 +674,36 @@ DEF_HELPER_6(vmerge_vxm_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmerge_vxm_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmerge_vxm_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmerge_vxm_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vsaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bcb8273bcc..44baadf582 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -402,6 +402,16 @@ vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm vmerge_vvm 010111 . ..... ..... 000 ..... 1010111 @r_vm vmerge_vxm 010111 . ..... ..... 100 ..... 1010111 @r_vm vmerge_vim 010111 . ..... ..... 011 ..... 1010111 @r_vm +vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm +vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm +vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm +vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm +vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm +vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm +vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm +vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm +vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm +vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index aff5ca8663..ad55766b98 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1505,3 +1505,19 @@ static bool opivx_vmerge_check(DisasContext *s, arg_rmrr *a) GEN_OPIVX_TRANS(vmerge_vxm, opivx_vmerge_check) GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vmerge_check) + +/* + *** Vector Fixed-Point Arithmetic Instructions + */ + +/* Vector Single-Width Saturating Add and Subtract */ +GEN_OPIVV_GVEC_TRANS(vsaddu_vv, usadd) +GEN_OPIVV_GVEC_TRANS(vsadd_vv, ssadd) +GEN_OPIVV_GVEC_TRANS(vssubu_vv, ussub) +GEN_OPIVV_GVEC_TRANS(vssub_vv, sssub) +GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) +GEN_OPIVX_TRANS(vsadd_vx, opivx_check) +GEN_OPIVX_TRANS(vssubu_vx, opivx_check) +GEN_OPIVX_TRANS(vssub_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 273b705847..c7b8c1bff4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2013,3 +2013,281 @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb) GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh) GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl) GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq) + +/* + *** Vector Fixed-Point Arithmetic Instructions + */ + +/* Vector Single-Width Saturating Add and Subtract */ +#define OPIVV2_ENV(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX1 s1 = *((T1 *)vs1 + HS1(i)); \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(env, s2, s1); \ +} + +#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs1, vs2, i, env); \ + } \ + if (i != 0) { \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + } \ +} + +static inline uint8_t saddu8(CPURISCVState *env, uint8_t a, uint8_t b) +{ + uint8_t res = a + b; + if (res < a) { + res = UINT8_MAX; + env->vxsat = 0x1; + } + return res; +} +static inline uint16_t saddu16(CPURISCVState *env, uint16_t a, uint16_t b) +{ + uint16_t res = a + b; + if (res < a) { + res = UINT16_MAX; + env->vxsat = 0x1; + } + return res; +} +static inline uint32_t saddu32(CPURISCVState *env, uint32_t a, uint32_t b) +{ + uint32_t res = a + b; + if (res < a) { + res = UINT32_MAX; + env->vxsat = 0x1; + } + return res; +} +static inline uint64_t saddu64(CPURISCVState *env, uint64_t a, uint64_t b) +{ + uint64_t res = a + b; + if (res < a) { + res = UINT64_MAX; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8) +RVVCALL(OPIVV2_ENV, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16) +RVVCALL(OPIVV2_ENV, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32) +RVVCALL(OPIVV2_ENV, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64) +GEN_VEXT_VV_ENV(vsaddu_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vsaddu_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vsaddu_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vsaddu_vv_d, 8, 8, clearq) + +#define OPIVX2_ENV(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_ulong s1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(env, s2, (TX1)(T1)(target_long)s1); \ +} + +#define GEN_VEXT_VX_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, s1, vs2, i, env); \ + } \ + if (i != 0) { \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + } \ +} +RVVCALL(OPIVX2_ENV, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8) +RVVCALL(OPIVX2_ENV, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16) +RVVCALL(OPIVX2_ENV, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32) +RVVCALL(OPIVX2_ENV, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64) +GEN_VEXT_VX_ENV(vsaddu_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vsaddu_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vsaddu_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vsaddu_vx_d, 8, 8, clearq) + +static inline int8_t sadd8(CPURISCVState *env, int8_t a, int8_t b) +{ + int8_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 7 == -1LL) { + res = a > 0 ? INT8_MAX : INT8_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int16_t sadd16(CPURISCVState *env, int16_t a, int16_t b) +{ + int16_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 15 == -1LL) { + res = a > 0 ? INT16_MAX : INT16_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int32_t sadd32(CPURISCVState *env, int32_t a, int32_t b) +{ + int32_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 31 == -1LL) { + res = a > 0 ? INT32_MAX : INT32_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int64_t sadd64(CPURISCVState *env, int64_t a, int64_t b) +{ + int64_t res = a + b; + if (((res ^ a) & (res ^ b)) >> 63 == -1LL) { + res = a > 0 ? INT64_MAX : INT64_MIN; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8) +RVVCALL(OPIVV2_ENV, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16) +RVVCALL(OPIVV2_ENV, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32) +RVVCALL(OPIVV2_ENV, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64) +GEN_VEXT_VV_ENV(vsadd_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vsadd_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vsadd_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vsadd_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8) +RVVCALL(OPIVX2_ENV, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16) +RVVCALL(OPIVX2_ENV, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32) +RVVCALL(OPIVX2_ENV, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64) +GEN_VEXT_VX_ENV(vsadd_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vsadd_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vsadd_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vsadd_vx_d, 8, 8, clearq) + +static inline uint8_t ssubu8(CPURISCVState *env, uint8_t a, uint8_t b) +{ + uint8_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +static inline uint16_t ssubu16(CPURISCVState *env, uint16_t a, uint16_t b) +{ + uint16_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +static inline uint32_t ssubu32(CPURISCVState *env, uint32_t a, uint32_t b) +{ + uint32_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +static inline uint64_t ssubu64(CPURISCVState *env, uint64_t a, uint64_t b) +{ + uint64_t res = a - b; + if (res > a) { + res = 0; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8) +RVVCALL(OPIVV2_ENV, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16) +RVVCALL(OPIVV2_ENV, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32) +RVVCALL(OPIVV2_ENV, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64) +GEN_VEXT_VV_ENV(vssubu_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vssubu_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vssubu_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vssubu_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8) +RVVCALL(OPIVX2_ENV, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16) +RVVCALL(OPIVX2_ENV, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32) +RVVCALL(OPIVX2_ENV, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64) +GEN_VEXT_VX_ENV(vssubu_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vssubu_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vssubu_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vssubu_vx_d, 8, 8, clearq) + +static inline int8_t ssub8(CPURISCVState *env, int8_t a, int8_t b) +{ + int8_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 7 == -1LL) { + res = a > 0 ? INT8_MAX : INT8_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int16_t ssub16(CPURISCVState *env, int16_t a, int16_t b) +{ + int16_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 15 == -1LL) { + res = a > 0 ? INT16_MAX : INT16_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int32_t ssub32(CPURISCVState *env, int32_t a, int32_t b) +{ + int32_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 31 == -1LL) { + res = a > 0 ? INT32_MAX : INT32_MIN; + env->vxsat = 0x1; + } + return res; +} +static inline int64_t ssub64(CPURISCVState *env, int64_t a, int64_t b) +{ + int64_t res = a - b; + if (((res ^ a) & (a ^ b)) >> 63 == -1LL) { + res = a > 0 ? INT64_MAX : INT64_MIN; + env->vxsat = 0x1; + } + return res; +} +RVVCALL(OPIVV2_ENV, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8) +RVVCALL(OPIVV2_ENV, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16) +RVVCALL(OPIVV2_ENV, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32) +RVVCALL(OPIVV2_ENV, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64) +GEN_VEXT_VV_ENV(vssub_vv_b, 1, 1, clearb) +GEN_VEXT_VV_ENV(vssub_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vssub_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vssub_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_ENV, vssub_vx_b, OP_SSS_B, H1, H1, ssub8) +RVVCALL(OPIVX2_ENV, vssub_vx_h, OP_SSS_H, H2, H2, ssub16) +RVVCALL(OPIVX2_ENV, vssub_vx_w, OP_SSS_W, H4, H4, ssub32) +RVVCALL(OPIVX2_ENV, vssub_vx_d, OP_SSS_D, H8, H8, ssub64) +GEN_VEXT_VX_ENV(vssub_vx_b, 1, 1, clearb) +GEN_VEXT_VX_ENV(vssub_vx_h, 2, 2, clearh) +GEN_VEXT_VX_ENV(vssub_vx_w, 4, 4, clearl) +GEN_VEXT_VX_ENV(vssub_vx_d, 8, 8, clearq) -- 2.23.0
next prev parent reply other threads:[~2020-03-09 8:29 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-09 8:19 [PATCH v3 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 02/60] target/riscv: implementation-defined constant parameters LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 03/60] target/riscv: support vector extension csr LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 04/60] target/riscv: add vector configure instruction LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 05/60] target/riscv: add vector stride load and store instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 06/60] target/riscv: add vector index " LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 07/60] target/riscv: add fault-only-first unit stride load LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 08/60] target/riscv: add vector amo operations LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 09/60] target/riscv: vector single-width integer add and subtract LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 10/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 12/60] target/riscv: vector bitwise logical instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 13/60] target/riscv: vector single-width bit shift instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 14/60] target/riscv: vector narrowing integer right " LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 15/60] target/riscv: vector integer comparison instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:19 ` [PATCH v3 17/60] target/riscv: vector single-width integer multiply instructions LIU Zhiwei 2020-03-09 8:19 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 18/60] target/riscv: vector integer divide instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 19/60] target/riscv: vector widening integer multiply instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 21/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 22/60] target/riscv: vector integer merge and move instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei [this message] 2020-03-09 8:20 ` [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 24/60] target/riscv: vector single-width averaging " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 30/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 32/60] target/riscv: vector widening floating-point multiply LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 34/60] target/riscv: vector widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 35/60] target/riscv: vector floating-point square-root instruction LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 36/60] target/riscv: vector floating-point min/max instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 38/60] target/riscv: vector floating-point compare instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 39/60] target/riscv: vector floating-point classify instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 40/60] target/riscv: vector floating-point merge instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 41/60] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 42/60] target/riscv: widening " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 43/60] target/riscv: narrowing " LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 45/60] target/riscv: vector wideing integer reduction instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 8:20 ` [PATCH v3 48/60] target/riscv: vector mask-register logical instructions LIU Zhiwei 2020-03-09 8:20 ` LIU Zhiwei 2020-03-09 12:13 [PATCH v3 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei 2020-03-09 12:14 ` [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract LIU Zhiwei 2020-03-09 12:14 ` LIU Zhiwei
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