[Intel-gfx] [PATCH 0/7] Gen11 workarounds

[Intel-gfx] [PATCH 0/7] Gen11 workarounds

[Matt Roper]

The first patch here technically impacts all gen8+ platforms, but the
rest of these are specifically for ICL and EHL.

Matt Roper (7):
  drm/i915: Handle all MCR ranges
  drm/i915: Add Wa_1207131216:icl,ehl
  drm/i915: Add Wa_1604278689:icl,ehl
  drm/i915: Add Wa_1406306137:icl,ehl
  drm/i915: Apply Wa_1406680159:icl,ehl as an engine workaround
  drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL
  drm/i915: Add Wa_1409178092:icl,ehl

 .../gpu/drm/i915/gem/i915_gem_object_blt.c    | 14 ++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 56 ++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               |  2 +
 3 files changed, 63 insertions(+), 9 deletions(-)

-- 
2.24.1

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[Intel-gfx] [PATCH 1/7] drm/i915: Handle all MCR ranges

[Matt Roper]

The bspec documents multiple MCR ranges; make sure they're all captured
by the driver.

Bspec: 13991, 52079
Fixes: 592a7c5e082e ("drm/i915: Extend non readable mcr range")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 391f39b1fb26..3e352e2a5b79 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1648,15 +1648,34 @@ create_scratch(struct i915_address_space *vm, int count)
 	return ERR_PTR(err);
 }
 
+static const struct {
+	u32 start;
+	u32 end;
+} mcr_ranges_gen8[] = {
+	{ .start = 0x5500, .end = 0x55ff },
+	{ .start = 0x7000, .end = 0x7fff },
+	{ .start = 0x9400, .end = 0x97ff },
+	{ .start = 0xb000, .end = 0xb3ff },
+	{ .start = 0xe000, .end = 0xe7ff },
+	{},
+};
+
 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 {
+	int i;
+
+	if (INTEL_GEN(i915) < 8)
+		return false;
+
 	/*
-	 * Registers in this range are affected by the MCR selector
+	 * Registers in these ranges are affected by the MCR selector
 	 * which only controls CPU initiated MMIO. Routing does not
 	 * work for CS access so we cannot verify them on this path.
 	 */
-	if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
-		return true;
+	for (i = 0; mcr_ranges_gen8[i].start; i++)
+		if (offset >= mcr_ranges_gen8[i].start &&
+		    offset <= mcr_ranges_gen8[i].end)
+			return true;
 
 	return false;
 }
-- 
2.24.1

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[Intel-gfx] [PATCH 2/7] drm/i915: Add Wa_1207131216:icl,ehl

[Matt Roper]

On gen11 the XY_FAST_COPY_BLT command has some size restrictions on its
usage.  Although this instruction is mainly used by userspace, i915 also
uses it to copy object contents during some selftests, so let's ensure
the restrictions are followed.

Bspec: 6544
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 39b8a055d80a..e00792158f13 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -196,6 +196,17 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
 	return err;
 }
 
+/* Wa_1209644611:icl,ehl */
+static bool wa_1209644611_applies(struct drm_i915_private *i915, u32 size)
+{
+	u32 height = size >> PAGE_SHIFT;
+
+	if (!IS_GEN(i915, 11))
+		return false;
+
+	return height % 4 == 3 && height <= 8;
+}
+
 struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
 					 struct i915_vma *src,
 					 struct i915_vma *dst)
@@ -237,7 +248,8 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
 		size = min_t(u64, rem, block_size);
 		GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
 
-		if (INTEL_GEN(i915) >= 9) {
+		if (INTEL_GEN(i915) >= 9 &&
+		    !wa_1209644611_applies(i915, size)) {
 			*cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
 			*cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
 			*cmd++ = 0;
-- 
2.24.1

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[Intel-gfx] [PATCH 3/7] drm/i915: Add Wa_1604278689:icl,ehl

[Matt Roper]

The bspec description for this workaround tells us to program
0xFFFF_FFFF into both FBC_RT_BASE_ADDR_REGISTER_* registers, but we've
previously found that this leads to failures in CI.  Our suspicion is
that the failures are caused by this valid turning on the "address valid
bit" even though we're intentionally supplying an invalid address.
Experimentation has shown that setting all bits _except_ for the
RT_VALID bit seems to avoid these failures.

v2:
 - Mask off the RT_VALID bit.  Experimentation with CI trybot indicates
   that this is necessary to avoid reset failures on BCS.

Bspec: 11388
Bspec: 33451
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h             | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3e352e2a5b79..1cf931dde0ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -575,6 +575,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	/* allow headerless messages for preemptible GPGPU context */
 	WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
 			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
+
+	/* Wa_1604278689:icl,ehl */
+	wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
+			   0, /* write-only register; skip validation */
+			   0xFFFFFFFF);
+	wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
 }
 
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 79ae9654dac9..92ae96cf5b64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3285,6 +3285,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 /* Framebuffer compression for Ivybridge */
 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
+#define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
 
 #define IPS_CTL		_MMIO(0x43408)
 #define   IPS_ENABLE	(1 << 31)
-- 
2.24.1

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[Intel-gfx] [PATCH 4/7] drm/i915: Add Wa_1406306137:icl,ehl

[Matt Roper]

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h             | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1cf931dde0ca..bd90dc5fb35d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1484,6 +1484,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		/* Wa_1407352427:icl,ehl */
 		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
 			    PSDUNIT_CLKGATE_DIS);
+
+		/* Wa_1406306137:icl,ehl */
+		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 	}
 
 	if (IS_GEN_RANGE(i915, 9, 12)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92ae96cf5b64..b6941da3b588 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9151,6 +9151,7 @@ enum {
 
 #define GEN9_ROW_CHICKEN4		_MMIO(0xe48c)
 #define   GEN12_DISABLE_TDL_PUSH	REG_BIT(9)
+#define   GEN11_DIS_PICK_2ND_EU		REG_BIT(7)
 
 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
-- 
2.24.1

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[Intel-gfx] [PATCH 5/7] drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround

[Matt Roper]

The register this workaround updates is a render engine register in the
MCR range, so we should initialize this in rcs_engine_wa_init() rather
than gt_wa_init().

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
Fixes: 36204d80bacb ("drm/i915/icl: Wa_1406680159")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bd90dc5fb35d..700cb6d1f45e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -917,11 +917,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    MSCUNIT_CLKGATE_DIS);
 
-	/* Wa_1406680159:icl */
-	wa_write_or(wal,
-		    SUBSLICE_UNIT_LEVEL_CLKGATE,
-		    GWUNIT_CLKGATE_DIS);
-
 	/* Wa_1406838659:icl (pre-prod) */
 	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
 		wa_write_or(wal,
@@ -1487,6 +1482,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 		/* Wa_1406306137:icl,ehl */
 		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
+
+		/* Wa_1406680159:icl,ehl */
+		wa_write_or(wal,
+			    SUBSLICE_UNIT_LEVEL_CLKGATE,
+			    GWUNIT_CLKGATE_DIS);
 	}
 
 	if (IS_GEN_RANGE(i915, 9, 12)) {
-- 
2.24.1

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[Intel-gfx] [PATCH 6/7] drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL

[Matt Roper]

This workaround appears under two different numbers (and with somewhat
confused stepping applicability on ICL).  Ultimately it appears we
should just implement this for all stepping of ICL and EHL.

Note that this is identical to Wa_1407928979:tgl that already exists in
our driver too...yet another number referencing the same actual
workaround.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 700cb6d1f45e..a539157dd571 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1487,6 +1487,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    SUBSLICE_UNIT_LEVEL_CLKGATE,
 			    GWUNIT_CLKGATE_DIS);
+
+		/*
+		 * Wa_1408767742:icl[a2..forever],ehl[all]
+		 * Wa_1605460711:icl[a0..c0]
+		 */
+		wa_write_or(wal,
+			    GEN7_FF_THREAD_MODE,
+			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 	}
 
 	if (IS_GEN_RANGE(i915, 9, 12)) {
-- 
2.24.1

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[Intel-gfx] [PATCH 7/7] drm/i915: Add Wa_1409178092:icl,ehl

[Matt Roper]

Note that we used to have this implemented on ICL under a different
number (Wa_1604302699), but it was removed because it vanished from the
bspec and the register update didn't seem to be sticking.  However the
initial implementation of the workaround appears to have been in the
wrong place (not handled as an engine workaround) and might behave
better now that we've had various other updates to our multicast
register handling.

References: f545425a0145 ("drm/i915/icl: Remove Wa_1604302699")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a539157dd571..5e009ee070dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1495,6 +1495,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    GEN7_FF_THREAD_MODE,
 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
+
+		/* Wa_1409178092:icl,ehl */
+		wa_write_or(wal, GEN10_L3_CHICKEN_MODE_REGISTER,
+			    GEN11_I2M_WRITE_DISABLE);
 	}
 
 	if (IS_GEN_RANGE(i915, 9, 12)) {
-- 
2.24.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen11 workarounds

[Patchwork]

== Series Details ==

Series: Gen11 workarounds
URL   : https://patchwork.freedesktop.org/series/74475/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a627f7908723 drm/i915: Handle all MCR ranges
0d45ae1b23d2 drm/i915: Add Wa_1207131216:icl,ehl
ac72d609fb43 drm/i915: Add Wa_1604278689:icl,ehl
0ae22805c1e6 drm/i915: Add Wa_1406306137:icl,ehl
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 16 lines checked
4c3c07b8545b drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround
e92df8bf04c0 drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL
dff1210436d4 drm/i915: Add Wa_1409178092:icl,ehl
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit f545425a0145 ("drm/i915/icl: Remove Wa_1604302699")'
#14: 
References: f545425a0145 ("drm/i915/icl: Remove Wa_1604302699")

total: 1 errors, 0 warnings, 0 checks, 10 lines checked

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Re: [Intel-gfx] [PATCH 2/7] drm/i915: Add Wa_1207131216:icl,ehl

[Mika Kuoppala]

Matt Roper <matthew.d.roper@intel.com> writes:

> On gen11 the XY_FAST_COPY_BLT command has some size restrictions on its
> usage.  Although this instruction is mainly used by userspace, i915 also
> uses it to copy object contents during some selftests, so let's ensure
> the restrictions are followed.
>
> Bspec: 6544
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index 39b8a055d80a..e00792158f13 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -196,6 +196,17 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
>  	return err;
>  }
>  
> +/* Wa_1209644611:icl,ehl */
> +static bool wa_1209644611_applies(struct drm_i915_private *i915, u32 size)
> +{
> +	u32 height = size >> PAGE_SHIFT;
> +
> +	if (!IS_GEN(i915, 11))
> +		return false;
> +
> +	return height % 4 == 3 && height <= 8;

The workaround description matches with this. However the original
sighting was only for Y-Tiled surfaces. I asked for clarification.

If we won't get one, we can play it safe and use this as it is.

-Mika

> +}
> +
>  struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
>  					 struct i915_vma *src,
>  					 struct i915_vma *dst)
> @@ -237,7 +248,8 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
>  		size = min_t(u64, rem, block_size);
>  		GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
>  
> -		if (INTEL_GEN(i915) >= 9) {
> +		if (INTEL_GEN(i915) >= 9 &&
> +		    !wa_1209644611_applies(i915, size)) {
>  			*cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
>  			*cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
>  			*cmd++ = 0;
> -- 
> 2.24.1
>
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Add Wa_1604278689:icl,ehl

[Chris Wilson]

Quoting Matt Roper (2020-03-10 00:49:07)
> The bspec description for this workaround tells us to program
> 0xFFFF_FFFF into both FBC_RT_BASE_ADDR_REGISTER_* registers, but we've
> previously found that this leads to failures in CI.  Our suspicion is
> that the failures are caused by this valid turning on the "address valid
> bit" even though we're intentionally supplying an invalid address.
> Experimentation has shown that setting all bits _except_ for the
> RT_VALID bit seems to avoid these failures.
> 
> v2:
>  - Mask off the RT_VALID bit.  Experimentation with CI trybot indicates
>    that this is necessary to avoid reset failures on BCS.

What reset failures?
 
> Bspec: 11388
> Bspec: 33451
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 1 +
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3e352e2a5b79..1cf931dde0ca 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -575,6 +575,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>         /* allow headerless messages for preemptible GPGPU context */
>         WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
>                           GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> +
> +       /* Wa_1604278689:icl,ehl */
> +       wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> +                          0, /* write-only register; skip validation */
> +                          0xFFFFFFFF);
> +       wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);

Disable first.
-Chris
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Add Wa_1604278689:icl,ehl

[Matt Roper]

On Tue, Mar 10, 2020 at 04:37:52PM +0000, Chris Wilson wrote:
> Quoting Matt Roper (2020-03-10 00:49:07)
> > The bspec description for this workaround tells us to program
> > 0xFFFF_FFFF into both FBC_RT_BASE_ADDR_REGISTER_* registers, but we've
> > previously found that this leads to failures in CI.  Our suspicion is
> > that the failures are caused by this valid turning on the "address valid
> > bit" even though we're intentionally supplying an invalid address.
> > Experimentation has shown that setting all bits _except_ for the
> > RT_VALID bit seems to avoid these failures.
> > 
> > v2:
> >  - Mask off the RT_VALID bit.  Experimentation with CI trybot indicates
> >    that this is necessary to avoid reset failures on BCS.
> 
> What reset failures?

It was back in August, so I think the logs have expired from CI now:

https://patchwork.freedesktop.org/series/65276/#rev1


Matt

>  
> > Bspec: 11388
> > Bspec: 33451
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 1 +
> >  2 files changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 3e352e2a5b79..1cf931dde0ca 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -575,6 +575,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >         /* allow headerless messages for preemptible GPGPU context */
> >         WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> >                           GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> > +
> > +       /* Wa_1604278689:icl,ehl */
> > +       wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> > +                          0, /* write-only register; skip validation */
> > +                          0xFFFFFFFF);
> > +       wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
> 
> Disable first.
> -Chris

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds

[Patchwork]

== Series Details ==

Series: Gen11 workarounds
URL   : https://patchwork.freedesktop.org/series/74475/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8106 -> Patchwork_16900
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16900 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16900, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16900:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@dmabuf:
    - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2] +33 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@dmabuf.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@dmabuf.html

  * igt@i915_selftest@live@memory_region:
    - fi-icl-y:           [PASS][3] -> [DMESG-WARN][4] +35 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@memory_region.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@memory_region.html

  * igt@i915_selftest@live@perf:
    - fi-icl-guc:         [PASS][5] -> [DMESG-WARN][6] +35 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@perf.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@perf.html

  * igt@i915_selftest@live@vma:
    - fi-icl-dsi:         [PASS][7] -> [DMESG-WARN][8] +35 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@vma.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@vma.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@mman:
    - {fi-ehl-1}:         [PASS][9] -> [DMESG-WARN][10] +36 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-ehl-1/igt@i915_selftest@live@mman.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-ehl-1/igt@i915_selftest@live@mman.html

  * {igt@i915_selftest@live@ring_submission}:
    - fi-icl-y:           [PASS][11] -> [DMESG-WARN][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@ring_submission.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@ring_submission.html
    - fi-icl-u2:          [PASS][13] -> [DMESG-WARN][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@ring_submission.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@ring_submission.html
    - fi-icl-dsi:         [PASS][15] -> [DMESG-WARN][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@ring_submission.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@ring_submission.html
    - fi-icl-guc:         [PASS][17] -> [DMESG-WARN][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@ring_submission.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@ring_submission.html

  
Known issues
------------

  Here are the changes found in Patchwork_16900 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-tgl-y:           [PASS][19] -> [FAIL][20] ([CI#94])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live@requests:
    - fi-icl-dsi:         [PASS][21] -> [DMESG-WARN][22] ([fdo#109644] / [fdo#110464])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@requests.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@requests.html
    - fi-icl-u2:          [PASS][23] -> [DMESG-WARN][24] ([fdo#109644] / [fdo#110464])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@requests.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@requests.html
    - fi-icl-y:           [PASS][25] -> [DMESG-WARN][26] ([fdo#109644] / [fdo#110464])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@requests.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@requests.html
    - fi-icl-guc:         [PASS][27] -> [DMESG-WARN][28] ([fdo#109644] / [fdo#110464])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@requests.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [PASS][29] -> [DMESG-WARN][30] ([IGT#4] / [i915#263])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@vgem_basic@dmabuf-fence:
    - fi-tgl-y:           [PASS][31] -> [DMESG-WARN][32] ([CI#94] / [i915#402]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html

  
#### Possible fixes ####

  * igt@gem_flink_basic@bad-open:
    - fi-tgl-y:           [DMESG-WARN][33] ([CI#94] / [i915#402]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_flink_basic@bad-open.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@gem_flink_basic@bad-open.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
  [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
  [fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
  [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 36)
------------------------------

  Additional (3): fi-bdw-5557u fi-cfl-8109u fi-kbl-7500u 
  Missing    (11): fi-bsw-n3050 fi-hsw-4200u fi-skl-6770hq fi-hsw-peppy fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8106 -> Patchwork_16900

  CI-20190529: 20190529
  CI_DRM_8106: 5b0076e8066ea8218e7857ee1aa28b0670acde94 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5504: d6788bf0404f76b66170e18eb26c85004b5ccb25 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16900: a995cd45a7e572470849cf32c088b872f7dd8aa1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a995cd45a7e5 drm/i915: Add Wa_1409178092:icl,ehl
4d09f0159ae0 drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL
e33fb022adac drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround
9a81ad532448 drm/i915: Add Wa_1406306137:icl,ehl
682a3994e88f drm/i915: Add Wa_1604278689:icl,ehl
c6b5ba431538 drm/i915: Add Wa_1207131216:icl,ehl
76da0301fb50 drm/i915: Handle all MCR ranges

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/index.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds

[Souza, Jose]

On Tue, 2020-03-10 at 17:30 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Gen11 workarounds
> URL   : https://patchwork.freedesktop.org/series/74475/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8106 -> Patchwork_16900
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_16900 absolutely need
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the
> changes
>   introduced in Patchwork_16900, please notify your bug team to allow
> them
>   to document this new failure mode, which will reduce false
> positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/index.html
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in
> Patchwork_16900:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@i915_selftest@live@dmabuf:
>     - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2] +33 similar
> issues
>    [1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@dmabuf.html
>    [2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@dmabuf.html

Looks like there some problem with the WAs in patch 4 and 7.

> 
>   * igt@i915_selftest@live@memory_region:
>     - fi-icl-y:           [PASS][3] -> [DMESG-WARN][4] +35 similar
> issues
>    [3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@memory_region.html
>    [4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@memory_region.html
> 
>   * igt@i915_selftest@live@perf:
>     - fi-icl-guc:         [PASS][5] -> [DMESG-WARN][6] +35 similar
> issues
>    [5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@perf.html
>    [6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@perf.html
> 
>   * igt@i915_selftest@live@vma:
>     - fi-icl-dsi:         [PASS][7] -> [DMESG-WARN][8] +35 similar
> issues
>    [7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@vma.html
>    [8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@vma.html
> 
>   
> #### Suppressed ####
> 
>   The following results come from untrusted machines, tests, or
> statuses.
>   They do not affect the overall result.
> 
>   * igt@i915_selftest@live@mman:
>     - {fi-ehl-1}:         [PASS][9] -> [DMESG-WARN][10] +36 similar
> issues
>    [9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-ehl-1/igt@i915_selftest@live@mman.html
>    [10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-ehl-1/igt@i915_selftest@live@mman.html
> 
>   * {igt@i915_selftest@live@ring_submission}:
>     - fi-icl-y:           [PASS][11] -> [DMESG-WARN][12]
>    [11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@ring_submission.html
>    [12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@ring_submission.html
>     - fi-icl-u2:          [PASS][13] -> [DMESG-WARN][14]
>    [13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@ring_submission.html
>    [14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@ring_submission.html
>     - fi-icl-dsi:         [PASS][15] -> [DMESG-WARN][16]
>    [15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@ring_submission.html
>    [16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@ring_submission.html
>     - fi-icl-guc:         [PASS][17] -> [DMESG-WARN][18]
>    [17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@ring_submission.html
>    [18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@ring_submission.html
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_16900 that come from known
> issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_exec_suspend@basic-s4-devices:
>     - fi-tgl-y:           [PASS][19] -> [FAIL][20] ([CI#94])
>    [19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
>    [20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
> 
>   * igt@i915_selftest@live@requests:
>     - fi-icl-dsi:         [PASS][21] -> [DMESG-WARN][22]
> ([fdo#109644] / [fdo#110464])
>    [21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@requests.html
>    [22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@requests.html
>     - fi-icl-u2:          [PASS][23] -> [DMESG-WARN][24]
> ([fdo#109644] / [fdo#110464])
>    [23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@requests.html
>    [24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@requests.html
>     - fi-icl-y:           [PASS][25] -> [DMESG-WARN][26]
> ([fdo#109644] / [fdo#110464])
>    [25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@requests.html
>    [26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@requests.html
>     - fi-icl-guc:         [PASS][27] -> [DMESG-WARN][28]
> ([fdo#109644] / [fdo#110464])
>    [27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@requests.html
>    [28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@requests.html
> 
>   * igt@kms_chamelium@common-hpd-after-suspend:
>     - fi-icl-u2:          [PASS][29] -> [DMESG-WARN][30] ([IGT#4] /
> [i915#263])
>    [29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
>    [30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
> 
>   * igt@vgem_basic@dmabuf-fence:
>     - fi-tgl-y:           [PASS][31] -> [DMESG-WARN][32] ([CI#94] /
> [i915#402]) +1 similar issue
>    [31]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html
>    [32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_flink_basic@bad-open:
>     - fi-tgl-y:           [DMESG-WARN][33] ([CI#94] / [i915#402]) ->
> [PASS][34]
>    [33]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_flink_basic@bad-open.html
>    [34]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@gem_flink_basic@bad-open.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when
> computing
>           the status of the difference (SUCCESS, WARNING, or
> FAILURE).
> 
>   [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
>   [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
>   [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
>   [fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
>   [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
>   [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
> 
> 
> Participating hosts (44 -> 36)
> ------------------------------
> 
>   Additional (3): fi-bdw-5557u fi-cfl-8109u fi-kbl-7500u 
>   Missing    (11): fi-bsw-n3050 fi-hsw-4200u fi-skl-6770hq fi-hsw-
> peppy fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper
> fi-bdw-samus fi-kbl-r 
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_8106 -> Patchwork_16900
> 
>   CI-20190529: 20190529
>   CI_DRM_8106: 5b0076e8066ea8218e7857ee1aa28b0670acde94 @
> git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5504: d6788bf0404f76b66170e18eb26c85004b5ccb25 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_16900: a995cd45a7e572470849cf32c088b872f7dd8aa1 @
> git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> a995cd45a7e5 drm/i915: Add Wa_1409178092:icl,ehl
> 4d09f0159ae0 drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and
> EHL
> e33fb022adac drm/i915: Apply Wa_1406680159:icl, ehl as an engine
> workaround
> 9a81ad532448 drm/i915: Add Wa_1406306137:icl,ehl
> 682a3994e88f drm/i915: Add Wa_1604278689:icl,ehl
> c6b5ba431538 drm/i915: Add Wa_1207131216:icl,ehl
> 76da0301fb50 drm/i915: Handle all MCR ranges
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/index.html
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds

[Matt Roper]

On Tue, Mar 10, 2020 at 03:28:01PM -0700, Souza, Jose wrote:
> On Tue, 2020-03-10 at 17:30 +0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: Gen11 workarounds
> > URL   : https://patchwork.freedesktop.org/series/74475/
> > State : failure
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_8106 -> Patchwork_16900
> > ====================================================
> > 
> > Summary
> > -------
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with Patchwork_16900 absolutely need
> > to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the
> > changes
> >   introduced in Patchwork_16900, please notify your bug team to allow
> > them
> >   to document this new failure mode, which will reduce false
> > positives in CI.
> > 
> >   External URL: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/index.html
> > 
> > Possible new issues
> > -------------------
> > 
> >   Here are the unknown changes that may have been introduced in
> > Patchwork_16900:
> > 
> > ### IGT changes ###
> > 
> > #### Possible regressions ####
> > 
> >   * igt@i915_selftest@live@dmabuf:
> >     - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2] +33 similar
> > issues
> >    [1]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@dmabuf.html
> >    [2]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@dmabuf.html
> 
> Looks like there some problem with the WAs in patch 4 and 7.

Wa_1406306137 should actually move to the context section; that register
is part of the context on gen11, but not on gen12, so I'll do that in
version 2.

Wa_1409178092 had problems when it was first implemented in the driver
(under a different name).  My hope was that other MCR changes (and
moving the WA to the proper place) would fix those problems, but it
still seems that the workaround doesn't stick.  I'll probably just drop
it again in v2 while we seek more guidance from the hardware people.


Matt


> 
> > 
> >   * igt@i915_selftest@live@memory_region:
> >     - fi-icl-y:           [PASS][3] -> [DMESG-WARN][4] +35 similar
> > issues
> >    [3]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@memory_region.html
> >    [4]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@memory_region.html
> > 
> >   * igt@i915_selftest@live@perf:
> >     - fi-icl-guc:         [PASS][5] -> [DMESG-WARN][6] +35 similar
> > issues
> >    [5]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@perf.html
> >    [6]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@perf.html
> > 
> >   * igt@i915_selftest@live@vma:
> >     - fi-icl-dsi:         [PASS][7] -> [DMESG-WARN][8] +35 similar
> > issues
> >    [7]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@vma.html
> >    [8]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@vma.html
> > 
> >   
> > #### Suppressed ####
> > 
> >   The following results come from untrusted machines, tests, or
> > statuses.
> >   They do not affect the overall result.
> > 
> >   * igt@i915_selftest@live@mman:
> >     - {fi-ehl-1}:         [PASS][9] -> [DMESG-WARN][10] +36 similar
> > issues
> >    [9]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-ehl-1/igt@i915_selftest@live@mman.html
> >    [10]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-ehl-1/igt@i915_selftest@live@mman.html
> > 
> >   * {igt@i915_selftest@live@ring_submission}:
> >     - fi-icl-y:           [PASS][11] -> [DMESG-WARN][12]
> >    [11]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@ring_submission.html
> >    [12]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@ring_submission.html
> >     - fi-icl-u2:          [PASS][13] -> [DMESG-WARN][14]
> >    [13]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@ring_submission.html
> >    [14]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@ring_submission.html
> >     - fi-icl-dsi:         [PASS][15] -> [DMESG-WARN][16]
> >    [15]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@ring_submission.html
> >    [16]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@ring_submission.html
> >     - fi-icl-guc:         [PASS][17] -> [DMESG-WARN][18]
> >    [17]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@ring_submission.html
> >    [18]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@ring_submission.html
> > 
> >   
> > Known issues
> > ------------
> > 
> >   Here are the changes found in Patchwork_16900 that come from known
> > issues:
> > 
> > ### IGT changes ###
> > 
> > #### Issues hit ####
> > 
> >   * igt@gem_exec_suspend@basic-s4-devices:
> >     - fi-tgl-y:           [PASS][19] -> [FAIL][20] ([CI#94])
> >    [19]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
> >    [20]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
> > 
> >   * igt@i915_selftest@live@requests:
> >     - fi-icl-dsi:         [PASS][21] -> [DMESG-WARN][22]
> > ([fdo#109644] / [fdo#110464])
> >    [21]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-dsi/igt@i915_selftest@live@requests.html
> >    [22]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-dsi/igt@i915_selftest@live@requests.html
> >     - fi-icl-u2:          [PASS][23] -> [DMESG-WARN][24]
> > ([fdo#109644] / [fdo#110464])
> >    [23]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@i915_selftest@live@requests.html
> >    [24]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@i915_selftest@live@requests.html
> >     - fi-icl-y:           [PASS][25] -> [DMESG-WARN][26]
> > ([fdo#109644] / [fdo#110464])
> >    [25]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-y/igt@i915_selftest@live@requests.html
> >    [26]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-y/igt@i915_selftest@live@requests.html
> >     - fi-icl-guc:         [PASS][27] -> [DMESG-WARN][28]
> > ([fdo#109644] / [fdo#110464])
> >    [27]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-guc/igt@i915_selftest@live@requests.html
> >    [28]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-guc/igt@i915_selftest@live@requests.html
> > 
> >   * igt@kms_chamelium@common-hpd-after-suspend:
> >     - fi-icl-u2:          [PASS][29] -> [DMESG-WARN][30] ([IGT#4] /
> > [i915#263])
> >    [29]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
> >    [30]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
> > 
> >   * igt@vgem_basic@dmabuf-fence:
> >     - fi-tgl-y:           [PASS][31] -> [DMESG-WARN][32] ([CI#94] /
> > [i915#402]) +1 similar issue
> >    [31]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html
> >    [32]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html
> > 
> >   
> > #### Possible fixes ####
> > 
> >   * igt@gem_flink_basic@bad-open:
> >     - fi-tgl-y:           [DMESG-WARN][33] ([CI#94] / [i915#402]) ->
> > [PASS][34]
> >    [33]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_flink_basic@bad-open.html
> >    [34]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/fi-tgl-y/igt@gem_flink_basic@bad-open.html
> > 
> >   
> >   {name}: This element is suppressed. This means it is ignored when
> > computing
> >           the status of the difference (SUCCESS, WARNING, or
> > FAILURE).
> > 
> >   [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
> >   [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
> >   [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
> >   [fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
> >   [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
> >   [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
> > 
> > 
> > Participating hosts (44 -> 36)
> > ------------------------------
> > 
> >   Additional (3): fi-bdw-5557u fi-cfl-8109u fi-kbl-7500u 
> >   Missing    (11): fi-bsw-n3050 fi-hsw-4200u fi-skl-6770hq fi-hsw-
> > peppy fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper
> > fi-bdw-samus fi-kbl-r 
> > 
> > 
> > Build changes
> > -------------
> > 
> >   * CI: CI-20190529 -> None
> >   * Linux: CI_DRM_8106 -> Patchwork_16900
> > 
> >   CI-20190529: 20190529
> >   CI_DRM_8106: 5b0076e8066ea8218e7857ee1aa28b0670acde94 @
> > git://anongit.freedesktop.org/gfx-ci/linux
> >   IGT_5504: d6788bf0404f76b66170e18eb26c85004b5ccb25 @
> > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> >   Patchwork_16900: a995cd45a7e572470849cf32c088b872f7dd8aa1 @
> > git://anongit.freedesktop.org/gfx-ci/linux
> > 
> > 
> > == Linux commits ==
> > 
> > a995cd45a7e5 drm/i915: Add Wa_1409178092:icl,ehl
> > 4d09f0159ae0 drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and
> > EHL
> > e33fb022adac drm/i915: Apply Wa_1406680159:icl, ehl as an engine
> > workaround
> > 9a81ad532448 drm/i915: Add Wa_1406306137:icl,ehl
> > 682a3994e88f drm/i915: Add Wa_1604278689:icl,ehl
> > c6b5ba431538 drm/i915: Add Wa_1207131216:icl,ehl
> > 76da0301fb50 drm/i915: Handle all MCR ranges
> > 
> > == Logs ==
> > 
> > For more details see: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16900/index.html
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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