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* [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients
@ 2020-03-10 14:18 Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 2/6] tools/intel_scaler_coef: Add support for chv plane " Ville Syrjala
                   ` (6 more replies)
  0 siblings, 7 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-03-10 14:18 UTC (permalink / raw)
  To: igt-dev

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some of our scalers have programmable coefficients. Add support for
the format originally defined for the gen2/3/4 video overlay. The
same format (or slight variants) has been reused in later platforms
for the panel fitter and pipe scaler.

The full list of hardware that supports this stuff:
- gen2/3/4 video overlay
- ilk/snb panel fitters
- ivb panel fitter 0
- cnl+ pipe scalers

The tool can calculate the filter coefficients for a random smattering
of filter and window functions.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/Makefile.sources    |    1 +
 tools/intel_scaler_coef.c | 1021 +++++++++++++++++++++++++++++++++++++
 tools/meson.build         |    1 +
 3 files changed, 1023 insertions(+)
 create mode 100644 tools/intel_scaler_coef.c

diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index b7a43d47e5df..e6937bb5c478 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -28,6 +28,7 @@ tools_prog_lists =		\
 	intel_panel_fitter	\
 	intel_reg_checker	\
 	intel_residency		\
+	intel_scaler_coef	\
 	intel_stepping		\
 	intel_vbt_decode	\
 	intel_watermark		\
diff --git a/tools/intel_scaler_coef.c b/tools/intel_scaler_coef.c
new file mode 100644
index 000000000000..19e247ab266a
--- /dev/null
+++ b/tools/intel_scaler_coef.c
@@ -0,0 +1,1021 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <assert.h>
+#include <getopt.h>
+#include <math.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "igt_aux.h"
+#include "drmtest.h"
+
+struct filter;
+
+/*
+ * x = [0:ntaps-1] with an additional offset of
+ * [-0.5:0.5[ depending on the phase.
+ */
+typedef double (*func)(const struct filter *f, double x);
+
+struct function {
+	const char *name;
+	func func;
+};
+
+struct phase {
+	double *coefs;
+};
+
+enum coef_format {
+	FORMAT_OVL_Y_HORZ,
+	FORMAT_OVL_UV_HORZ,
+	FORMAT_OVL_Y_VERT,
+	FORMAT_OVL_UV_VERT,
+	FORMAT_ILK_PF_HORZ,
+	FORMAT_ILK_PF_VERT_5TAP,
+	FORMAT_ILK_PF_VERT_3TAP,
+	FORMAT_CNL_PS,
+	FORMAT_INVALID,
+};
+
+static const char * const coef_formats[] = {
+	[FORMAT_OVL_Y_HORZ] = "ovl_y_horz",
+	[FORMAT_OVL_UV_HORZ] = "ovl_uv_horz",
+	[FORMAT_OVL_Y_VERT] = "ovl_y_vert",
+	[FORMAT_OVL_UV_VERT] = "ovl_uv_vert",
+	[FORMAT_ILK_PF_HORZ] = "ilk_pf_horz",
+	[FORMAT_ILK_PF_VERT_5TAP] = "ilk_pf_vert_5tap",
+	[FORMAT_ILK_PF_VERT_3TAP] = "ilk_pf_vert_3tap",
+	[FORMAT_CNL_PS] = "cnl_ps",
+};
+
+enum filter_mode {
+	MODE_LOWPASS,
+	MODE_HIGHPASS,
+	MODE_BANDPASS,
+	MODE_BANDSTOP,
+	MODE_INVALID,
+};
+
+static const char * const filter_modes[] = {
+	[MODE_LOWPASS] = "lowpass",
+	[MODE_HIGHPASS] = "highpass",
+	[MODE_BANDPASS] = "bandpass",
+	[MODE_BANDSTOP] = "bandstop",
+};
+
+struct filter_config {
+	int ntaps;
+	int nphases;
+	int center_mantissa_bits;
+	int other_mantissa_bits;
+	enum coef_format format;
+	bool high_prec_taps;
+	int nhwtaps;
+	const int *hwtaps;
+};
+
+struct filter {
+	struct filter_config config;
+	enum filter_mode mode;
+	bool strict;
+	double cutoff, cutoff_high;
+	double phase_offset;
+	const struct function *filter;
+	const struct function *window;
+	struct phase *phases;
+};
+
+static double _sinc(double x)
+{
+	if (x == 0.0)
+		return 1.0;
+	else
+		return sin(x) / x;
+}
+
+/* return the index of the center tap */
+static int center_tap(const struct filter *f)
+{
+	return (f->config.ntaps - 1) / 2;
+}
+
+/* filter functions */
+
+static double nearest(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+	double t = 0.5;
+
+	x -= n;
+
+	if (x >= -t && x < t)
+		return 1.0;
+	else
+		return 0.0;
+}
+
+static double linear(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+	double t = 1.0;
+
+	x -= n;
+
+	if (x >= -t && x < t)
+		return 1.0 - fabs(x) / t;
+	else
+		return 0.0;
+}
+
+static double nearest_box(const struct filter *f, double x)
+{
+	return 1.0;
+}
+
+static double linear_box(const struct filter *f, double x)
+{
+	int i = x + 0.5;
+
+	x -= i;
+
+	if (i == 0)
+		return 0.5 - fabs(x);
+	else if (i == f->config.ntaps - 1)
+		return 0.5 + fabs(x);
+	else
+		return 1.0;
+}
+
+static double tent(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+	double t = f->config.ntaps / 2;
+
+	x -= n;
+
+	if (x >= -t && x < t)
+		return 1.0 - fabs(x) / t;
+	else
+		return 0.0;
+}
+
+static double sinc(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+
+	x = f->cutoff * 2.0 * M_PI * (x - n);
+
+	return _sinc(x);
+}
+
+static double sharp(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+	int i = x + 0.5;
+
+	if (i == n)
+		return 5.0;
+	else if (i == n-1 || i==n+1)
+		return -2.0;
+	else
+		return 0.0;
+}
+
+static double edge(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+	int i = x + 0.5;
+
+	if (i == n)
+		return -3.0;
+	else if (i == n-1 || i==n+1)
+		return 1.0;
+	else if (i == n-2 || i==n+2)
+		return -0.25;
+	else
+		return 0.0;
+}
+
+static const struct function filter_funcs[] = {
+	{ .name = "nearest", .func = nearest, },
+	{ .name = "linear", .func = linear, },
+	{ .name = "nearest_box", .func = nearest_box, },
+	{ .name = "linear_box", .func = linear_box, },
+	{ .name = "tent", .func = tent, },
+	{ .name = "sinc", .func = sinc, },
+	{ .name = "sharp", .func = sharp, },
+	{ .name = "edge", .func = edge, },
+};
+
+/* window functions */
+
+static double rect(const struct filter *f, double x)
+{
+	return 1.0;
+}
+
+static double hann(const struct filter *f, double x)
+{
+	x = 2.0 * M_PI * x / (f->config.ntaps - 1);
+
+	return 0.5 - 0.5 * cos(x);
+}
+
+static double hann_wide(const struct filter *f, double x)
+{
+	x = 2.0 * M_PI * (x + 0.5) / f->config.ntaps;
+
+	return 0.5 - 0.5 * cos(x);
+}
+
+static double hamming(const struct filter *f, double x)
+{
+	x = 2.0 * M_PI * x / (f->config.ntaps - 1);
+
+	return 0.54 - 0.46 * cos(x);
+}
+
+static double blackman(const struct filter *f, double x)
+{
+	x = 2.0 * M_PI * x / (f->config.ntaps - 1);
+
+	return 0.42 - 0.5 * cos(x) + 0.08 * cos(2.0 * x);
+}
+
+static double lanczos2(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+
+	x = M_PI * (x - n) / 2.0;
+
+	return _sinc(x);
+}
+
+static double lanczos3(const struct filter *f, double x)
+{
+	int n = center_tap(f);
+
+	x = M_PI * (x - n) / 3.0;
+
+	return _sinc(x);
+}
+
+static const struct function window_funcs[] = {
+	{ .name = "rect", .func = rect, },
+	{ .name = "bartlett", .func = tent, },
+	{ .name = "hann", .func = hann, },
+	{ .name = "hann_wide", .func = hann_wide, },
+	{ .name = "hamming", .func = hamming, },
+	{ .name = "blackman", .func = blackman, },
+	{ .name = "lanczos2", .func = lanczos2, },
+	{ .name = "lanczos3", .func = lanczos3, },
+};
+
+/* */
+
+static double sum_taps(const struct filter *f, int p)
+{
+	const double *coefs = f->phases[p].coefs;
+	double sum = 0.0;
+
+	for (int t = 0; t < f->config.ntaps; t++)
+		sum += coefs[t];
+
+	return sum;
+}
+
+static double calc_phase(const struct filter *f, int p)
+{
+	/* [-0.5:0.5[ + phase_offset */
+	return (double) p / f->config.nphases - 0.5 + f->phase_offset;
+}
+
+static void create_phase(struct filter *f, int p, double *coefs)
+{
+	double phase = calc_phase(f, p);
+	func filter = f->filter->func;
+
+	for (int t = 0; t < f->config.ntaps; t++)
+		coefs[t] = filter(f, t + phase);
+}
+
+static void invert_phase(struct filter *f, double *coefs)
+{
+	int n = center_tap(f);
+
+	for (int t = 0; t < f->config.ntaps; t++)
+		coefs[t] = -coefs[t];
+
+	coefs[n] += 1.0;
+}
+
+static void add_phase(struct filter *f, int p,
+		      const double *coefs2)
+{
+	double *coefs = f->phases[p].coefs;
+
+	for (int t = 0; t < f->config.ntaps; t++)
+		coefs[t] += coefs2[t];
+}
+
+static void mul_phase(struct filter *f, int p, double mul)
+{
+	double *coefs = f->phases[p].coefs;
+
+	for (int t = 0; t < f->config.ntaps; t++)
+		coefs[t] *= mul;
+}
+
+static void window_phase(struct filter *f, int p)
+{
+	double phase = calc_phase(f, p);
+	double *coefs = f->phases[p].coefs;
+	func window = f->window->func;
+
+	for (int t = 0; t < f->config.ntaps; t++)
+		coefs[t] *= window(f, t + phase);
+}
+
+static void generate_filter_phase(struct filter *f, int p)
+{
+	double *coefs = f->phases[p].coefs;
+
+	/* apply the filter function */
+	create_phase(f, p, coefs);
+
+	if (f->mode == MODE_HIGHPASS)
+		invert_phase(f, coefs);
+
+	if (f->mode == MODE_BANDPASS || f->mode == MODE_BANDSTOP) {
+		double coefs_high[f->config.ntaps];
+
+		igt_swap(f->cutoff, f->cutoff_high);
+
+		create_phase(f, p, coefs_high);
+		invert_phase(f, coefs_high);
+		add_phase(f, p, coefs_high);
+
+		igt_swap(f->cutoff, f->cutoff_high);
+
+		if (f->mode == MODE_BANDPASS)
+			invert_phase(f, coefs);
+	}
+
+	/* apply window function */
+	window_phase(f, p);
+
+	/* normalize */
+	mul_phase(f, p, 1.0 / sum_taps(f, p));
+}
+
+static void generate_filter(struct filter *f)
+{
+	int p;
+
+	f->phases = calloc(f->config.nphases/2+1, sizeof f->phases[0]);
+	assert(f->phases);
+
+	for (p = 0; p < f->config.nphases/2+1; p++) {
+		f->phases[p].coefs = calloc(f->config.ntaps, sizeof f->phases[p].coefs[0]);
+		assert(f->phases[p].coefs);
+
+		generate_filter_phase(f, p);
+	}
+}
+
+static int nhwtaps(const struct filter *f)
+{
+	return f->config.nhwtaps ?: f->config.ntaps;
+}
+
+static int hwtap_to_tap(const struct filter *f, int _t)
+{
+	if (!f->config.hwtaps)
+		return _t;
+
+	for (int t = 0; t < f->config.nhwtaps; t++) {
+		if (f->config.hwtaps[t] == _t)
+			return t;
+	}
+
+	return -1;
+}
+
+#if 0
+static int tap_to_hwtap(const struct filter *f, int t)
+{
+	if (!f->config.hwtaps)
+		return t;
+
+	return f->config.hwtaps[t];
+}
+#endif
+
+static const int ilk_pf_vert_3tap_hwtaps[] = { 0, 2, 4 };
+static const int cnl_ps_hwtaps[] = { 6, 5, 4, 3, 2, 1, 0 };
+
+static const struct filter_config configs[] = {
+	[FORMAT_OVL_Y_HORZ] = {
+		.ntaps = 5, .nphases = 32,
+		.center_mantissa_bits = 9,
+		.other_mantissa_bits = 7,
+		.format = FORMAT_OVL_Y_HORZ,
+	},
+	[FORMAT_OVL_UV_HORZ] = {
+		.ntaps = 3, .nphases = 32,
+		.center_mantissa_bits = 9,
+		.other_mantissa_bits = 7,
+		.format = FORMAT_OVL_UV_HORZ,
+	},
+	[FORMAT_OVL_Y_VERT] = {
+		.ntaps = 3, .nphases = 32,
+		.center_mantissa_bits = 8,
+		.other_mantissa_bits = 6,
+		.format = FORMAT_OVL_Y_VERT,
+	},
+	[FORMAT_OVL_UV_VERT] = {
+		.ntaps = 3, .nphases = 32,
+		.center_mantissa_bits = 6,
+		.other_mantissa_bits = 6,
+		.format = FORMAT_OVL_UV_VERT,
+	},
+	[FORMAT_ILK_PF_HORZ] = {
+		.ntaps = 7, .nphases = 32,
+		.center_mantissa_bits = 9,
+		.other_mantissa_bits = 7,
+		.high_prec_taps = true,
+		.format = FORMAT_ILK_PF_HORZ,
+	},
+	[FORMAT_ILK_PF_VERT_5TAP] = {
+		.ntaps = 5, .nphases = 32,
+		.center_mantissa_bits = 9,
+		.other_mantissa_bits = 7,
+		.high_prec_taps = true,
+		.format = FORMAT_ILK_PF_VERT_5TAP,
+	},
+	[FORMAT_ILK_PF_VERT_3TAP] = {
+		.ntaps = 3, .nphases = 32,
+		.center_mantissa_bits = 9,
+		.other_mantissa_bits = 7,
+		.high_prec_taps = true,
+		.format = FORMAT_ILK_PF_VERT_3TAP,
+		.hwtaps = ilk_pf_vert_3tap_hwtaps, .nhwtaps = 5,
+	},
+	[FORMAT_CNL_PS] = {
+		.ntaps = 7, .nphases = 32,
+		.center_mantissa_bits = 9,
+		.other_mantissa_bits = 9,
+		.format = FORMAT_CNL_PS,
+		.hwtaps = cnl_ps_hwtaps, .nhwtaps = 7,
+	},
+};
+
+/*
+ * Filter coefficient format used by:
+ * - gen2/3/4 video overlay
+ * - ilk/snb/ivb 7x5 panel fitter
+ * - cnl+ pipe scaler
+ */
+union gen2_coef_reg
+{
+	struct {
+		uint16_t mantissa:12;
+		uint16_t exponent:3;
+		uint16_t sign:1;
+	};
+	uint16_t reg;
+};
+
+static int exp_to_hw(const struct filter *f, int t, int exp)
+{
+	/*
+	 * On some hw the non-center taps trade
+	 * away >= 1.0 values for more precision.
+	 */
+	if (f->config.high_prec_taps && t != center_tap(f) && exp == 4)
+		exp = 0;
+
+	assert(exp >= 0 && exp <= 3);
+
+	return exp;
+}
+
+static int exp_from_hw(const struct filter *f, int t, int exp)
+{
+	assert(exp >= 0 && exp <= 3);
+
+	/*
+	 * On some hw the non-center taps trade
+	 * away >= 1.0 values for more precision.
+	 */
+	if (f->config.high_prec_taps && t != center_tap(f) && exp == 0)
+		exp = 4;
+
+	return exp;
+}
+
+static int sign_to_int(bool sign)
+{
+	return sign ? -1 : 1;
+}
+
+static double gen2_reg_to_coef(const struct filter *f, int t,
+			       const union gen2_coef_reg *r)
+{
+	return (sign_to_int(r->sign) * (double) r->mantissa) /
+		(1 << (11 + exp_from_hw(f, t, r->exponent)));
+}
+
+
+static int gen2_mantissa_bits(const struct filter *f, int t)
+{
+	if (t == center_tap(f))
+		return f->config.center_mantissa_bits;
+	else
+		return f->config.other_mantissa_bits;
+}
+
+static void gen2_coef_to_reg(const struct filter *f,
+			     int t, double coef,
+			     union gen2_coef_reg *r)
+{
+	int mantissa_bits = gen2_mantissa_bits(f, t);
+	int max = (1 << mantissa_bits) - 1;
+	int exp, exp_max, exp_min;
+
+	if (f->config.high_prec_taps && t != center_tap(f)) {
+		exp_min = 1;
+		exp_max = 4;
+	} else {
+		exp_min = 0;
+		exp_max = 3;
+	}
+
+	if (coef < 0.0) {
+		coef = -coef;
+		r->sign = 1;
+	} else {
+		r->sign = 0;
+	}
+
+	/* find the exponent that gives the best precision */
+	for (exp = exp_max; exp >= exp_min; exp--) {
+		int c = coef * (1 << (mantissa_bits + exp - 1)) + 0.5;
+
+		if (!f->strict && exp == exp_min)
+			c = min(c, max-1);
+
+		if (c <= max) {
+			r->exponent = exp_to_hw(f, t, exp);
+			r->mantissa = c << (12 - mantissa_bits);
+			return;
+		}
+	}
+
+	fprintf(stderr, "Unable to represent %f in hardware format\n",
+		sign_to_int(r->sign) * coef);
+	assert(0);
+}
+
+/*
+ * Calculate the hardware specific register format for the tap
+ * and translate that back to a floating point value. So afterwards
+ * the floating point value will be limited by the precision of
+ * the hardware.
+ */
+static void gen2_update_tap(struct filter *f, int p, int t)
+{
+	double *coefs = f->phases[p].coefs;
+	union gen2_coef_reg r;
+
+	gen2_coef_to_reg(f, t, coefs[t], &r);
+
+	coefs[t] = gen2_reg_to_coef(f, t, &r);
+}
+
+static void update_tap(struct filter *f, int p, int t)
+{
+	switch (f->config.format) {
+	default:
+		gen2_update_tap(f, p, t);
+		break;
+	}
+}
+
+/*
+ * Convert the coefficients into the hardware format and back
+ */
+static void update_taps(struct filter *f, int p)
+{
+	for (int t = 0; t < f->config.ntaps; t++)
+		update_tap(f, p, t);
+}
+
+/*
+ * Make the taps sum to 1.0 by adding the remaining error
+ * to each tap in turn starting from the center tap.
+ */
+static void fixup_taps(struct filter *f, int p)
+{
+	double *coefs = f->phases[p].coefs;
+	double sum;
+	int i;
+
+	sum = sum_taps(f, p);
+
+	while (sum != 1.0) {
+		for (i = 0; i < f->config.ntaps; i++) {
+			int n = center_tap(f);
+			int t;
+
+			if (i & 1)
+				t = n + (i + 1) / 2;
+			else
+				t = n - i / 2;
+
+			coefs[t] += 1.0 - sum;
+
+			update_tap(f, p, t);
+
+			sum = sum_taps(f, p);
+			if (sum == 1.0)
+				break;
+		}
+	}
+}
+
+/*
+ * Convert the filter coefficients into the hardware specific
+ * format and back.
+ */
+static void update_filter(struct filter *f)
+{
+	for (int p = 0; p < f->config.nphases/2+1; p++)
+		update_taps(f, p);
+}
+
+/*
+ * Make sure the taps for each phase sum up to 1.0 and adjust
+ * if necessary to guarantee that.
+ */
+static void fixup_filter(struct filter *f)
+{
+	for (int p = 0; p < f->config.nphases/2+1; p++)
+		fixup_taps(f, p);
+}
+
+/* */
+
+/*
+ * Print out the filter information in floating point format.
+ */
+static void print_filter(const struct filter *f)
+{
+	int p, t;
+
+	printf(" format = %s\n"
+	       " ntaps = %d\n"
+	       " nphases = %d\n"
+	       " cutoff = %f\n"
+	       " cutoff_high = %f\n"
+	       " filter = %s\n"
+	       " window = %s\n"
+	       " mode = %s\n"
+	       " coefs = {\n",
+	       coef_formats[f->config.format],
+	       f->config.ntaps, f->config.nphases,
+	       f->cutoff, f->cutoff_high,
+	       f->filter->name, f->window->name,
+	       filter_modes[f->mode]);
+
+	for (p = 0; p < f->config.nphases/2+1; p++) {
+		const double *coefs = f->phases[p].coefs;
+		double sum = 0.0;
+
+		printf(" %4d: {", p);
+		for (t = 0; t < f->config.ntaps; t++) {
+			printf(" % f", coefs[t]);
+			sum += coefs[t];
+		}
+		printf(" } sum = %.10f\n", sum);
+	}
+	printf(" }\n");
+}
+
+/*
+ * Print out the filter information in hardware specific format.
+ */
+static void hw_print_filter(const struct filter *f)
+{
+	printf(" format = %s\n"
+	       " ntaps = %d\n"
+	       " nphases = %d\n"
+	       " cutoff = %f\n"
+	       " cutoff_high = %f\n"
+	       " filter = %s\n"
+	       " window = %s\n"
+	       " mode = %s\n"
+	       " coefs = {\n",
+	       coef_formats[f->config.format],
+	       f->config.ntaps, f->config.nphases,
+	       f->cutoff, f->cutoff_high,
+	       f->filter->name, f->window->name,
+	       filter_modes[f->mode]);
+
+	for (int p = 0; p < f->config.nphases/2+1; p++) {
+		const double *coefs = f->phases[p].coefs;
+		int sum = 0;
+
+		printf(" %4d: {", p);
+		for (int t = 0; t < f->config.ntaps; t++) {
+			switch (f->config.format) {
+			default: {
+				union gen2_coef_reg r;
+				int exp;
+
+				gen2_coef_to_reg(f, t, coefs[t], &r);
+
+				exp = exp_from_hw(f, t, r.exponent);
+
+				/* sum in .16 binary fixed point */
+				sum += sign_to_int(r.sign) * r.mantissa << (5 - exp);
+
+				printf(" %04x", r.reg);
+			}
+				break;
+			}
+		}
+		printf(" } sum = 0x%x\n", sum);
+	}
+	printf(" }\n");
+}
+
+/*
+ * Print out the filter coefs as a C structure..
+ */
+static void print_c_filter(const struct filter *f)
+{
+	printf("struct %s = {\n", coef_formats[f->config.format]);
+
+	for (int p = 0; p < f->config.nphases/2+1; p++) {
+		const double *coefs = f->phases[p].coefs;
+
+		printf("\t[%2d] = {", p);
+
+		for (int _t = 0; _t < nhwtaps(f); _t++) {
+			int t = hwtap_to_tap(f, _t);
+			double coef;
+
+			if (t >= 0)
+				coef = coefs[t];
+			else
+				coef = 0.0;
+
+			switch (f->config.format) {
+			default: {
+				union gen2_coef_reg r;
+
+				gen2_coef_to_reg(f, t, coef, &r);
+
+				printf(" 0x%04x,", r.reg);
+			}
+				break;
+			}
+		}
+		printf(" },\n");
+	}
+	printf("};\n");
+}
+
+/* */
+
+static void usage(FILE *stream, const char *name)
+{
+	int i;
+
+	fprintf(stream, "Usage: %s [-h|--help] [-s|--strict]"
+		" [-t|--taps <taps>] [-p|--phases <phases>]"
+		" [-c|--cutoff <cutoff>] [-C|--high-cutoff <cutoff>]"
+		" [-f|--filter <filter>] [-w|--window <window>]"
+		" [-m|--mantissa <bits>] [-F|--format <format>]"
+		" [-M|--mode <mode>]"
+		"\n"
+		" -h|--help: Show this help text\n"
+		" -s|--strict: Fail if any coefficient is out of range for the hardware, otherwise clamp it\n"
+		" -t|--taps <taps>: number of filter taps [1:1024]\n"
+		" -p|--phases <phases>: number of filter phases [1:1024]\n"
+		" -c|--cutoff <cutoff>: cutoff frequency for sinc filter [0.0:0.5]\n"
+		" -C|--high-cutoff <cutoff>: high cutoff frequency for bandpass/bandstop [0.0:0.5]\n"
+		" -f|--filter <filter>: filter function\n"
+		" -w|--window <window>: window function\n"
+		" -m|--mantissa <bits>: number of mantissa bits in the coefficients [1:12]\n"
+		" -F|--format <format>: hardware coefficient format\n"
+		" -M|--mode <mode>: filter mode\n"
+		, name);
+
+	fprintf(stream, "Possible filter functions: ");
+	for (i = 0; i < ARRAY_SIZE(filter_funcs); i++)
+		fprintf(stream, "%s%c", filter_funcs[i].name, i == ARRAY_SIZE(filter_funcs) - 1 ? '\n' : ',');
+
+	fprintf(stream, "Possible window functions: ");
+	for (i = 0; i < ARRAY_SIZE(window_funcs); i++)
+		fprintf(stream, "%s%c", window_funcs[i].name, i == ARRAY_SIZE(window_funcs) - 1 ? '\n' : ',');
+
+	fprintf(stream, "Possible hardware coefficient formats: ");
+	for (i = 0; i < ARRAY_SIZE(coef_formats); i++)
+		fprintf(stream, "%s%c", coef_formats[i], i == FORMAT_INVALID - 1 ? '\n' : ',');
+
+	fprintf(stream, "Possible filter modes: ");
+	for (i = 0; i < ARRAY_SIZE(filter_modes); i++)
+		fprintf(stream, "%s%c", filter_modes[i], i == MODE_INVALID - 1 ? '\n' : ',');
+}
+
+int main(int argc, char *argv[])
+{
+	const struct option opts[] = {
+		{ .name = "help", .val = 'h' },
+		{ .name = "strict", .val = 's' },
+		{ .name = "taps", .has_arg = true, .val = 't' },
+		{ .name = "phases", .has_arg = true, .val = 'p' },
+		{ .name = "cutoff", .has_arg = true, .val = 'c' },
+		{ .name = "high-cutoff", .has_arg = true, .val = 'C' },
+		{ .name = "filter", .has_arg = true, .val = 'f' },
+		{ .name = "window", .has_arg = true, .val = 'w' },
+		{ .name = "mantissa-center", .has_arg = true, .val = 'B' },
+		{ .name = "mantissa-other", .has_arg = true, .val = 'b' },
+		{ .name = "format", .has_arg = true, .val = 'F' },
+		{ .name = "mode", .has_arg = true, .val = 'M' },
+		{}
+	};
+	struct filter f = {
+		.config = configs[FORMAT_CNL_PS],
+		.mode = MODE_LOWPASS,
+		.strict = false,
+		.cutoff = 0.5,
+		.cutoff_high = 0.5,
+		.filter = &filter_funcs[0],
+		.window = &window_funcs[0],
+	};
+	bool error = false, help = false;
+
+	for (;;) {
+		int c = getopt_long(argc, argv, "hst:p:c:C:f:w:F:M:B:b:", opts, NULL);
+
+		if (c == -1)
+			break;
+
+		switch (c) {
+			int i;
+		case 'h':
+			help = true;
+			break;
+		case 's':
+			f.strict = true;
+			break;
+		case 't':
+			f.config.ntaps = atoi(optarg);
+			if (f.config.ntaps < 1 || f.config.ntaps > 1024) {
+				fprintf(stderr, "Invalid number of taps: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'p':
+			f.config.nphases = atoi(optarg);
+			if (f.config.nphases < 1 || f.config.nphases > 1024) {
+				fprintf(stderr, "Invalid number of phases: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'c':
+			f.cutoff = strtod(optarg, NULL);
+			if (f.cutoff < 0.0 || f.cutoff > 0.5) {
+				fprintf(stderr, "Invalid cutoff frequency: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'C':
+			f.cutoff_high = strtod(optarg, NULL);
+			if (f.cutoff_high < 0.0 || f.cutoff_high > 0.5) {
+				fprintf(stderr, "Invalid high cutoff frequency: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'f':
+			f.filter = NULL;
+			for (i = 0; i < ARRAY_SIZE(filter_funcs); i++) {
+				if (!strcmp(optarg, filter_funcs[i].name)) {
+					f.filter = &filter_funcs[i];
+					break;
+				}
+			}
+			if (f.filter == NULL) {
+				fprintf(stderr, "Unknwon filter function: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'w':
+			f.window = NULL;
+			for (i = 0; i < ARRAY_SIZE(window_funcs); i++) {
+				if (!strcmp(optarg, window_funcs[i].name)) {
+					f.window = &window_funcs[i];
+					break;
+				}
+			}
+			if (f.window == NULL) {
+				fprintf(stderr, "Unknwon window function: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'B':
+			f.config.center_mantissa_bits = atoi(optarg);
+			if (f.config.center_mantissa_bits < 1 || f.config.center_mantissa_bits > 12) {
+				fprintf(stderr, "Invalid center tap mantissa bits: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'b':
+			f.config.other_mantissa_bits = atoi(optarg);
+			if (f.config.other_mantissa_bits < 1 || f.config.other_mantissa_bits > 12) {
+				fprintf(stderr, "Invalid other tap mantissa bits: %s\n", optarg);
+				error = true;
+			}
+			break;
+		case 'F':
+			for (f.config.format = 0;
+			     f.config.format < ARRAY_SIZE(coef_formats);
+			     f.config.format++) {
+				if (!strcmp(optarg, coef_formats[f.config.format]))
+					break;
+			}
+			if (f.config.format == FORMAT_INVALID) {
+				fprintf(stderr, "Unknown hardware coefficient format: %s\n", optarg);
+				error = true;
+			}
+			f.config = configs[f.config.format];
+			break;
+		case 'M':
+			for (f.mode = 0; f.mode < ARRAY_SIZE(filter_modes); f.mode++) {
+				if (!strcmp(optarg, filter_modes[f.mode]))
+					break;
+			}
+			if (f.mode == MODE_INVALID) {
+				fprintf(stderr, "Unknown filter mode: %s\n", optarg);
+				error = true;
+			}
+			break;
+		default:
+			error = true;
+		}
+	}
+
+	if (help) {
+		usage(stdout, argv[0]);
+		return 0;
+	} else if (error) {
+		usage(stderr, argv[0]);
+		return 1;
+	}
+
+	generate_filter(&f);
+	print_filter(&f);
+	hw_print_filter(&f);
+
+	update_filter(&f);
+	print_filter(&f);
+	hw_print_filter(&f);
+
+	fixup_filter(&f);
+	print_filter(&f);
+	hw_print_filter(&f);
+
+	print_c_filter(&f);
+
+	return 0;
+}
diff --git a/tools/meson.build b/tools/meson.build
index 59b56d5dedb9..a47badebe1b0 100644
--- a/tools/meson.build
+++ b/tools/meson.build
@@ -30,6 +30,7 @@ tools_progs = [
 	'intel_panel_fitter',
 	'intel_reg_checker',
 	'intel_residency',
+	'intel_scaler_coef',
 	'intel_stepping',
 	'intel_vbt_decode',
 	'intel_watermark',
-- 
2.24.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [igt-dev] [PATCH i-g-t 2/6] tools/intel_scaler_coef: Add support for chv plane scaler coefficients
  2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
@ 2020-03-10 14:18 ` Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 3/6] HACK: tools/intel_scaler_coef: Test ilk/snb/ivb panel fitter programmable coefficients Ville Syrjala
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-03-10 14:18 UTC (permalink / raw)
  To: igt-dev

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV pipe B primary plane has a scaler. It's totally alien hardware
and thus requires its own style of scaler coefficients.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_scaler_coef.c | 92 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/tools/intel_scaler_coef.c b/tools/intel_scaler_coef.c
index 19e247ab266a..a85af924fb6b 100644
--- a/tools/intel_scaler_coef.c
+++ b/tools/intel_scaler_coef.c
@@ -61,6 +61,8 @@ enum coef_format {
 	FORMAT_ILK_PF_VERT_5TAP,
 	FORMAT_ILK_PF_VERT_3TAP,
 	FORMAT_CNL_PS,
+	FORMAT_CHV_HORZ,
+	FORMAT_CHV_VERT,
 	FORMAT_INVALID,
 };
 
@@ -73,6 +75,8 @@ static const char * const coef_formats[] = {
 	[FORMAT_ILK_PF_VERT_5TAP] = "ilk_pf_vert_5tap",
 	[FORMAT_ILK_PF_VERT_3TAP] = "ilk_pf_vert_3tap",
 	[FORMAT_CNL_PS] = "cnl_ps",
+	[FORMAT_CHV_HORZ] = "chv_horz",
+	[FORMAT_CHV_VERT] = "chv_vert",
 };
 
 enum filter_mode {
@@ -441,6 +445,9 @@ static int tap_to_hwtap(const struct filter *f, int t)
 static const int ilk_pf_vert_3tap_hwtaps[] = { 0, 2, 4 };
 static const int cnl_ps_hwtaps[] = { 6, 5, 4, 3, 2, 1, 0 };
 
+static const int chv_horz_hwtaps[] = { 8, 7, 6, 5, 4, 3, 2, 1, 0 };
+static const int chv_vert_hwtaps[] = { 4, 3, 2, 1, 0 };
+
 static const struct filter_config configs[] = {
 	[FORMAT_OVL_Y_HORZ] = {
 		.ntaps = 5, .nphases = 32,
@@ -495,6 +502,16 @@ static const struct filter_config configs[] = {
 		.format = FORMAT_CNL_PS,
 		.hwtaps = cnl_ps_hwtaps, .nhwtaps = 7,
 	},
+	[FORMAT_CHV_HORZ] = {
+		.ntaps = 9, .nphases = 32,
+		.format = FORMAT_CHV_HORZ,
+		.hwtaps = chv_horz_hwtaps, .nhwtaps = 9,
+	},
+	[FORMAT_CHV_VERT] = {
+		.ntaps = 5, .nphases = 32,
+		.format = FORMAT_CHV_VERT,
+		.hwtaps = chv_vert_hwtaps, .nhwtaps = 5,
+	},
 };
 
 /*
@@ -620,9 +637,64 @@ static void gen2_update_tap(struct filter *f, int p, int t)
 	coefs[t] = gen2_reg_to_coef(f, t, &r);
 }
 
+/*
+ * chv plane scaler filter coefficient hardware register layout
+ */
+union chv_coef_reg
+{
+	uint16_t reg; /* s2.10 */
+};
+
+static int sign_extend(int reg, int bits)
+{
+	bits = 32 - bits;
+
+	return (reg << bits) >> bits;
+}
+
+static double chv_reg_to_coef(const union chv_coef_reg *r)
+{
+	double c = sign_extend(r->reg, 12);
+
+	return c / (1 << 10);
+}
+
+static void chv_coef_to_reg(const struct filter *f,
+			    double coef,
+			    union chv_coef_reg *r)
+{
+	int max = 2 << 10;
+	int c = coef * (1 << 10);
+
+	if (!f->strict)
+		c = clamp(c, -max, max-1);
+
+	if (c >= -max && c < max) {
+		r->reg = c & 0xfff;
+		return;
+	}
+
+	fprintf(stderr, "Unable to represent %f in hardware format\n", coef);
+	assert(0);
+}
+
+static void chv_update_tap(struct filter *f, int p, int t)
+{
+	double *coefs = f->phases[p].coefs;
+	union chv_coef_reg r;
+
+	chv_coef_to_reg(f, coefs[t], &r);
+
+	coefs[t] = chv_reg_to_coef(&r);
+}
+
 static void update_tap(struct filter *f, int p, int t)
 {
 	switch (f->config.format) {
+	case FORMAT_CHV_HORZ:
+	case FORMAT_CHV_VERT:
+		chv_update_tap(f, p, t);
+		break;
 	default:
 		gen2_update_tap(f, p, t);
 		break;
@@ -767,6 +839,17 @@ static void hw_print_filter(const struct filter *f)
 				/* sum in .16 binary fixed point */
 				sum += sign_to_int(r.sign) * r.mantissa << (5 - exp);
 
+				printf(" %04x", r.reg);
+			}
+				break;
+			case FORMAT_CHV_HORZ:
+			case FORMAT_CHV_VERT: {
+				union chv_coef_reg r;
+
+				chv_coef_to_reg(f, coefs[t], &r);
+
+				sum += sign_extend(r.reg, 12);
+
 				printf(" %04x", r.reg);
 			}
 				break;
@@ -804,6 +887,15 @@ static void print_c_filter(const struct filter *f)
 
 				gen2_coef_to_reg(f, t, coef, &r);
 
+				printf(" 0x%04x,", r.reg);
+			}
+				break;
+			case FORMAT_CHV_HORZ:
+			case FORMAT_CHV_VERT: {
+				union chv_coef_reg r;
+
+				chv_coef_to_reg(f, coefs[t], &r);
+
 				printf(" 0x%04x,", r.reg);
 			}
 				break;
-- 
2.24.1

_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [igt-dev] [PATCH i-g-t 3/6] HACK: tools/intel_scaler_coef: Test ilk/snb/ivb panel fitter programmable coefficients
  2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 2/6] tools/intel_scaler_coef: Add support for chv plane " Ville Syrjala
@ 2020-03-10 14:18 ` Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 4/6] HACK: tools/intel_scaler_coef: Test cnl+ pipe scaler " Ville Syrjala
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-03-10 14:18 UTC (permalink / raw)
  To: igt-dev

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ilk/snb/ivb panel fitters (only pf0 on ivb) have programmable
coefficients. Add some code to figure out how they work.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_scaler_coef.c | 262 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 260 insertions(+), 2 deletions(-)

diff --git a/tools/intel_scaler_coef.c b/tools/intel_scaler_coef.c
index a85af924fb6b..8565261099d0 100644
--- a/tools/intel_scaler_coef.c
+++ b/tools/intel_scaler_coef.c
@@ -35,6 +35,9 @@
 #include "igt_aux.h"
 #include "drmtest.h"
 
+#include "intel_io.h"
+#include "intel_chipset.h"
+
 struct filter;
 
 /*
@@ -432,7 +435,6 @@ static int hwtap_to_tap(const struct filter *f, int _t)
 	return -1;
 }
 
-#if 0
 static int tap_to_hwtap(const struct filter *f, int t)
 {
 	if (!f->config.hwtaps)
@@ -440,7 +442,6 @@ static int tap_to_hwtap(const struct filter *f, int t)
 
 	return f->config.hwtaps[t];
 }
-#endif
 
 static const int ilk_pf_vert_3tap_hwtaps[] = { 0, 2, 4 };
 static const int cnl_ps_hwtaps[] = { 6, 5, 4, 3, 2, 1, 0 };
@@ -949,6 +950,260 @@ static void usage(FILE *stream, const char *name)
 		fprintf(stream, "%s%c", filter_modes[i], i == MODE_INVALID - 1 ? '\n' : ',');
 }
 
+struct rect {
+	int x, y, w, h;
+};
+
+#define _PIPE_REG(reg_a, pipe) ((reg_a) + (pipe) * 0x1000)
+#define HTOTAL(pipe)	_PIPE_REG(0x60000, (pipe))
+#define VTOTAL(pipe)	_PIPE_REG(0x6000c, (pipe))
+#define PIPECONF(pipe)	_PIPE_REG(0x70008, (pipe))
+#define  PIPECONF_ENABLE	(1 << 31)
+#define PIPESRC(pipe)	_PIPE_REG(0x6001C, (pipe))
+
+#define _PF_REG(reg_0, pf)	((reg_0) + (pf) * 0x800)
+#define PF_CTRL(pf)	_PF_REG(0x68080, (pf)) /* aka. PF_CTRL1 */
+#define  PF_ENABLE		(1 << 31)
+#define  PF_PIPE(pipe)		((pipe) << 29) /* ivb */
+#define  PF_FILTER_PROG		(0 << 23)
+#define  PF_FILTER_MED		(1 << 23)
+#define  PF_FILTER_EDGE_ENH	(2 << 23)
+#define  PF_FILTER_EDGE_SOFT	(3 << 23)
+#define PF_WIN_POS(pf)	_PF_REG(0x68070, (pf))
+#define PF_WIN_SZ(pf)	_PF_REG(0x68074, (pf))
+#define PF_HSCALE(pf)	_PF_REG(0x68084, (pf)) /* aka. PF_CTRL2 */
+#define PF_VSCALE(pf)	_PF_REG(0x68090, (pf)) /* aka. PF_CTRL4 */
+
+/* ilk/snb: both panel fitters */
+#define PF_HFILTL_COEF(pf, i)	(_PF_REG(0x68100, (pf)) + 4 * (i))
+#define PF_HFILTC_COEF(pf, i)	(_PF_REG(0x68200, (pf)) + 4 * (i))
+#define PF_VFILTL_COEF(pf, i)	(_PF_REG(0x68300, (pf)) + 4 * (i))
+#define PF_VFILTC_COEF(pf, i)	(_PF_REG(0x68400, (pf)) + 4 * (i))
+
+/* ivb: only pf0 (7x5 capable) */
+#define PF_HCOEF_INDEX 0x680a0
+#define PF_VCOEF_INDEX 0x680b0
+#define  PF_COEF_AUTO_INCREMENT (1 << 15)
+#define PF_HCOEF_DATA 0x680a4
+#define PF_VCOEF_DATA 0x680b4
+
+static uint32_t I915_READ(uint32_t reg)
+{
+	uint32_t tmp = INREG(reg);
+	printf("0x%x = 0x%x\n", reg, tmp);
+	return tmp;
+}
+
+static void I915_WRITE(uint32_t reg, uint32_t value)
+{
+	OUTREG(reg, value);
+}
+
+static int ilk_coef_index(const struct filter *f, int p, int t)
+{
+	assert(f->config.nphases/2+1 == 17);
+	assert(f->config.ntaps == 7 ||
+	       f->config.ntaps == 5 ||
+	       f->config.ntaps == 3);
+
+	return nhwtaps(f) * p + tap_to_hwtap(f, t);
+}
+
+static void ilk_horz_coefs(struct filter *f, uint16_t hcoef[])
+{
+	f->config = configs[FORMAT_ILK_PF_HORZ];
+
+	generate_filter(f);
+	print_filter(f);
+	hw_print_filter(f);
+	update_filter(f);
+	print_filter(f);
+	hw_print_filter(f);
+	fixup_filter(f);
+	printf("ilk pf horz\n");
+	print_filter(f);
+	hw_print_filter(f);
+	print_c_filter(f);
+
+	for (int p = 0; p < f->config.nphases/2+1; p++) {
+		const double *coefs = f->phases[p].coefs;
+
+		for (int t = 0; t < f->config.ntaps; t++) {
+			union gen2_coef_reg r;
+			int i = ilk_coef_index(f, p, t);
+
+			gen2_coef_to_reg(f, t, coefs[t], &r);
+
+			hcoef[i] = r.reg;
+		}
+	}
+}
+
+static void ilk_vert_coefs(struct filter *f, uint16_t vcoef[], int src_w)
+{
+	/*
+	 * The pfit automagically switches to three
+	 * line mode when the source width is too big.
+	 */
+	if (src_w > 2048)
+		f->config = configs[FORMAT_ILK_PF_VERT_3TAP];
+	else
+		f->config = configs[FORMAT_ILK_PF_VERT_5TAP];
+
+	generate_filter(f);
+	print_filter(f);
+	hw_print_filter(f);
+	update_filter(f);
+	print_filter(f);
+	hw_print_filter(f);
+	fixup_filter(f);
+	printf("ilk pf vert\n");
+	print_filter(f);
+	hw_print_filter(f);
+	print_c_filter(f);
+
+	for (int p = 0; p < f->config.nphases/2+1; p++) {
+		const double *coefs = f->phases[p].coefs;
+
+		for (int t = 0; t < f->config.ntaps; t++) {
+			union gen2_coef_reg r;
+			int i = ilk_coef_index(f, p, t);
+
+			gen2_coef_to_reg(f, t, coefs[t], &r);
+
+			vcoef[i] = r.reg;
+		}
+	}
+}
+
+static void ilk_program_hcoefs(int pf, const uint16_t hcoef[])
+{
+	for (int i = 0; i < 7 * 17; i += 2) {
+		uint32_t tmp = hcoef[i+1] << 16 | hcoef[i];
+
+		I915_WRITE(PF_HFILTL_COEF(pf, i/2), tmp);
+		I915_WRITE(PF_HFILTC_COEF(pf, i/2), tmp);
+	}
+}
+
+static void ilk_program_vcoefs(int pf, const uint16_t vcoef[])
+{
+	for (int i = 0; i < 5 * 17; i += 2) {
+		uint32_t tmp = vcoef[i+1] << 16 | vcoef[i];
+
+		I915_WRITE(PF_VFILTL_COEF(pf, i/2), tmp);
+		I915_WRITE(PF_VFILTC_COEF(pf, i/2), tmp);
+	}
+}
+
+static void ivb_program_hcoefs(const uint16_t hcoef[])
+{
+	I915_WRITE(PF_HCOEF_INDEX, PF_COEF_AUTO_INCREMENT);
+
+	/* twice for luma/R + chroma/G/B */
+	for (int j = 0; j < 2; j++) {
+		for (int i = 0; i < 7 * 17; i += 2) {
+			uint32_t tmp = hcoef[i+1] << 16 | hcoef[i];
+
+			I915_WRITE(PF_HCOEF_DATA, tmp);
+		}
+	}
+
+	I915_WRITE(PF_HCOEF_INDEX, 0);
+}
+
+static void ivb_program_vcoefs(const uint16_t vcoef[])
+{
+	I915_WRITE(PF_VCOEF_INDEX, PF_COEF_AUTO_INCREMENT);
+
+	/* twice for luma/R + chroma/G/B */
+	for (int j = 0; j < 2; j++) {
+		for (int i = 0; i < 5 * 17; i += 2) {
+			uint32_t tmp = vcoef[i+1] << 16 | vcoef[i];
+
+			I915_WRITE(PF_VCOEF_DATA, tmp);
+		}
+	}
+
+	I915_WRITE(PF_VCOEF_INDEX, 0);
+}
+
+static void ilk_program(struct filter *f, int pipe)
+{
+	struct intel_mmio_data mmio_data;
+	struct rect src = {};
+	struct rect dst = {};
+	uint16_t hcoef[7*17+1] = {};
+	uint16_t vcoef[5*17+1] = {};
+	uint32_t devid;
+	bool is_ivb;
+	int pf;
+
+	devid = intel_get_pci_device()->device_id;
+
+	if (!IS_IVYBRIDGE(devid) && !IS_GEN6(devid) && !IS_GEN5(devid))
+		return;
+
+	is_ivb = IS_IVYBRIDGE(devid);
+
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
+
+	if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
+		goto out;
+
+	/* On IVB only PF0 has programmable coefficients */
+	pf = is_ivb ? 0 : pipe;
+
+	dst.w = (I915_READ(HTOTAL(pipe)) & 0xffff) + 1;
+	dst.h = (I915_READ(VTOTAL(pipe)) & 0xffff) + 1;
+
+	dst.x = 64;
+	dst.y = 16;
+	dst.w -= 128;
+	dst.h -= 32;
+
+	src.w = ((I915_READ(PIPESRC(pipe)) >> 16) & 0xffff) + 1;
+	src.h = (I915_READ(PIPESRC(pipe)) & 0xffff) + 1;
+
+	ilk_horz_coefs(f, hcoef);
+	ilk_vert_coefs(f, vcoef, src.w);
+
+	if (is_ivb) {
+		ivb_program_hcoefs(hcoef);
+		ivb_program_vcoefs(vcoef);
+	} else {
+		ilk_program_hcoefs(pf, hcoef);
+		ilk_program_vcoefs(pf, vcoef);
+	}
+
+	I915_WRITE(PF_CTRL(pf),
+		   PF_ENABLE |
+		   (is_ivb ? PF_PIPE(pipe) : 0) |
+		   PF_FILTER_PROG);
+
+	I915_WRITE(PF_WIN_POS(pf), dst.x << 16 | dst.y);
+	I915_WRITE(PF_WIN_SZ(pf), dst.w << 16 | dst.h);
+
+	printf("%dx%d%+d%+d -> %dx%d%+d%+d\n",
+	       src.w, src.h, src.x, src.y,
+	       dst.w, dst.h, dst.x, dst.y);
+	printf("sw: hscale 0x%x, vscale 0x%x\n",
+	       (((src.w << 16) + 1) / dst.w) >> 1,
+	       (((src.h << 16) + 1) / dst.h) >> 1);
+	printf("hw: hscale 0x%x, vscale 0x%x\n",
+	       I915_READ(PF_HSCALE(pf)),
+	       I915_READ(PF_VSCALE(pf)));
+
+	sleep(2);
+
+	I915_WRITE(PF_CTRL(pf), 0);
+	I915_WRITE(PF_WIN_POS(pf), 0);
+	I915_WRITE(PF_WIN_SZ(pf), 0);
+
+ out:
+	intel_register_access_fini(&mmio_data);
+}
+
 int main(int argc, char *argv[])
 {
 	const struct option opts[] = {
@@ -1109,5 +1364,8 @@ int main(int argc, char *argv[])
 
 	print_c_filter(&f);
 
+	if (1)
+		ilk_program(&f, 0);
+
 	return 0;
 }
-- 
2.24.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [igt-dev] [PATCH i-g-t 4/6] HACK: tools/intel_scaler_coef: Test cnl+ pipe scaler programmable coefficients
  2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 2/6] tools/intel_scaler_coef: Add support for chv plane " Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 3/6] HACK: tools/intel_scaler_coef: Test ilk/snb/ivb panel fitter programmable coefficients Ville Syrjala
@ 2020-03-10 14:18 ` Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 5/6] HACK: tools/intel_scaler_coef: Test chv plane " Ville Syrjala
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-03-10 14:18 UTC (permalink / raw)
  To: igt-dev

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

cnl+ (actually glk already has this, but presumably not validated)
have programmable pipe scaler coefficients. Add some code to figure
out how they work.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_scaler_coef.c | 166 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 166 insertions(+)

diff --git a/tools/intel_scaler_coef.c b/tools/intel_scaler_coef.c
index 8565261099d0..de6872a91545 100644
--- a/tools/intel_scaler_coef.c
+++ b/tools/intel_scaler_coef.c
@@ -1204,6 +1204,170 @@ static void ilk_program(struct filter *f, int pipe)
 	intel_register_access_fini(&mmio_data);
 }
 
+#define _PS_REG(reg_a_1, pipe, scaler)	((reg_a_1) + (pipe) * 0x800 + (scaler) * 0x100)
+#define PS_CTRL(pipe, scaler)		_PS_REG(0x68180, (pipe), (scaler))
+#define  PS_ENABLE			(1 << 31)
+#define  PS_CTRL_FILTER_PROG		(1 << 23)
+#define  PS_CTRL_Y_VERT_FILTER_SET(set)		((set) << 4)
+#define  PS_CTRL_Y_HORZ_FILTER_SET(set)		((set) << 3)
+#define  PS_CTRL_UV_VERT_FILTER_SET(set)	((set) << 2)
+#define  PS_CTRL_UV_HORZ_FILTER_SET(set)	((set) << 1)
+#define PS_WIN_POS(pipe, scaler)	_PS_REG(0x68170, (pipe), (scaler))
+#define PS_WIN_SZ(pipe, scaler)		_PS_REG(0x68174, (pipe), (scaler))
+#define PS_VSCALE(pipe, scaler)		_PS_REG(0x68184, (pipe), (scaler))
+#define PS_VPHASE(pipe, scaler)		_PS_REG(0x68188, (pipe), (scaler))
+#define PS_HSCALE(pipe, scaler)		_PS_REG(0x68190, (pipe), (scaler))
+#define PS_HPHASE(pipe, scaler)		_PS_REG(0x68194, (pipe), (scaler))
+#define  PS_Y_PHASE(x)          ((x) << 16)
+#define  PS_UV_RGB_PHASE(x)     ((x) << 0)
+#define  PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
+#define  PS_PHASE_TRIP (1 << 0)
+
+#define _PS_COEF_REG(reg_a_1, pipe, scaler, set)	(_PS_REG((reg_a_1), (pipe), (scaler)) + (set) * 0x8)
+#define PS_COEF_INDEX(pipe, scaler, set)	_PS_COEF_REG(0x68198, (pipe), (scaler), (set))
+#define  PS_COEF_AUTO_INCREMENT	(1 << 10)
+#define PS_COEF_DATA(pipe, scaler, set)		_PS_COEF_REG(0x6819c, (pipe), (scaler), (set))
+
+static uint16_t ps_calc_phase(int scale)
+{
+	bool chroma_cosited = false;
+	int sub = 1;
+	int phase = -0x8000;
+	uint16_t trip = 0;
+
+	if (chroma_cosited)
+		phase += (sub - 1) * 0x8000 / sub;
+
+	phase += scale / (2 * sub);
+
+	if (phase < 0)
+		phase = 0x10000 + phase;
+	else
+		trip = PS_PHASE_TRIP;
+
+	return ((phase >> 2) & PS_PHASE_MASK) | trip;
+}
+
+static void cnl_program_coefs(int pipe, int scaler, int set,
+			      const uint16_t coef[])
+{
+	I915_WRITE(PS_COEF_INDEX(pipe, scaler, set),
+		   PS_COEF_AUTO_INCREMENT);
+
+	for (int i = 0; i < 7 * 17; i += 2) {
+		uint32_t tmp = coef[i+1] << 16 | coef[i];
+
+		I915_WRITE(PS_COEF_DATA(pipe, scaler, set), tmp);
+	}
+
+	I915_WRITE(PS_COEF_INDEX(pipe, scaler, set), 0);
+}
+
+static void cnl_coefs(struct filter *f, uint16_t coef[])
+{
+	f->config = configs[FORMAT_CNL_PS];
+
+	generate_filter(f);
+	print_filter(f);
+	hw_print_filter(f);
+	update_filter(f);
+	print_filter(f);
+	hw_print_filter(f);
+	fixup_filter(f);
+	printf("cnl ps\n");
+	print_filter(f);
+	hw_print_filter(f);
+	print_c_filter(f);
+
+	for (int p = 0; p < f->config.nphases/2+1; p++) {
+		const double *coefs = f->phases[p].coefs;
+
+		for (int t = 0; t < f->config.ntaps; t++) {
+			union gen2_coef_reg r;
+			int i = ilk_coef_index(f, p, t);
+
+			gen2_coef_to_reg(f, t, coefs[t], &r);
+
+			coef[i] = r.reg;
+		}
+	}
+}
+
+static void cnl_program(struct filter *f, int pipe)
+{
+	struct intel_mmio_data mmio_data;
+	struct rect src = {};
+	struct rect dst = {};
+	uint16_t hcoef[7*17+1] = {};
+	uint16_t vcoef[7*17+1] = {};
+	uint32_t devid;
+	int trans = pipe;
+	int scaler = 0;
+
+	devid = intel_get_pci_device()->device_id;
+
+	if (intel_gen(devid) < 10 && !IS_GEMINILAKE(devid))
+		return;
+
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
+
+	if (!(I915_READ(PIPECONF(trans)) & PIPECONF_ENABLE))
+		trans = 0xf; /* assume we are using transcoder EDP */
+	if (!(I915_READ(PIPECONF(trans)) & PIPECONF_ENABLE))
+		goto out;
+
+	dst.w = (I915_READ(HTOTAL(trans)) & 0xffff) + 1;
+	dst.h = (I915_READ(VTOTAL(trans)) & 0xffff) + 1;
+
+	src.w = ((I915_READ(PIPESRC(pipe)) >> 16) & 0xffff) + 1;
+	src.h = (I915_READ(PIPESRC(pipe)) & 0xffff) + 1;
+
+	dst.x = 8;
+	dst.y = 8;
+	dst.w -= 16;
+	dst.h -= 16;
+
+	cnl_coefs(f, hcoef);
+	cnl_coefs(f, vcoef);
+
+	cnl_program_coefs(pipe, scaler, 0, hcoef);
+	cnl_program_coefs(pipe, scaler, 1, vcoef);
+
+	I915_WRITE(PS_VPHASE(pipe, scaler),
+		   ps_calc_phase((src.h << 16) / dst.h));
+	I915_WRITE(PS_HPHASE(pipe, scaler),
+		   ps_calc_phase((src.w << 16) / dst.w));
+
+	I915_WRITE(PS_CTRL(pipe, scaler), PS_ENABLE |
+		   PS_CTRL_FILTER_PROG |
+		   PS_CTRL_Y_VERT_FILTER_SET(0) |
+		   PS_CTRL_Y_HORZ_FILTER_SET(0) |
+		   PS_CTRL_UV_VERT_FILTER_SET(0) |
+		   PS_CTRL_UV_HORZ_FILTER_SET(0));
+
+	I915_WRITE(PS_WIN_POS(pipe, scaler), dst.x << 16 | dst.y);
+	I915_WRITE(PS_WIN_SZ(pipe, scaler), dst.w << 16 | dst.h);
+
+	printf("%dx%d%+d%+d -> %dx%d%+d%+d\n",
+	       src.w, src.h, src.x, src.y,
+	       dst.w, dst.h, dst.x, dst.y);
+	printf("sw: hscale 0x%x, vscale 0x%x\n",
+	       (((src.w << 16) + 1) / dst.w) >> 1,
+	       (((src.h << 16) + 1) / dst.h) >> 1);
+	printf("hw: hscale 0x%x, vscale 0x%x\n",
+	       I915_READ(PS_HSCALE(pipe, scaler)),
+	       I915_READ(PS_VSCALE(pipe, scaler)));
+
+	sleep(2);
+
+	I915_WRITE(PS_CTRL(pipe, scaler), 0);
+	I915_WRITE(PS_WIN_POS(pipe, scaler), 0);
+	I915_WRITE(PS_WIN_SZ(pipe, scaler), 0);
+
+ out:
+	intel_register_access_fini(&mmio_data);
+}
+
 int main(int argc, char *argv[])
 {
 	const struct option opts[] = {
@@ -1364,6 +1528,8 @@ int main(int argc, char *argv[])
 
 	print_c_filter(&f);
 
+	if (1)
+		cnl_program(&f, 0);
 	if (1)
 		ilk_program(&f, 0);
 
-- 
2.24.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [igt-dev] [PATCH i-g-t 5/6] HACK: tools/intel_scaler_coef: Test chv plane scaler programmable coefficients
  2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
                   ` (2 preceding siblings ...)
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 4/6] HACK: tools/intel_scaler_coef: Test cnl+ pipe scaler " Ville Syrjala
@ 2020-03-10 14:18 ` Ville Syrjala
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 6/6] HACK: lib/igt_fb: Paint diagonals Ville Syrjala
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-03-10 14:18 UTC (permalink / raw)
  To: igt-dev

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

chv pipe B primary plane has a scaler that has programmable
coefficients. Add some code to figure out how this stuff works.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_scaler_coef.c | 382 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 382 insertions(+)

diff --git a/tools/intel_scaler_coef.c b/tools/intel_scaler_coef.c
index de6872a91545..fbac5e7a9c3e 100644
--- a/tools/intel_scaler_coef.c
+++ b/tools/intel_scaler_coef.c
@@ -1368,6 +1368,386 @@ static void cnl_program(struct filter *f, int pipe)
 	intel_register_access_fini(&mmio_data);
 }
 
+#define VLV_DISPLAY_BASE 0x180000
+
+#define PCPSXCONFIG(sprite)            (VLV_DISPLAY_BASE + 0x6d000 + (sprite) * 0x1000)
+#define  PCPSX_SCALER_EN               (1 << 0)
+#define PCPSXHS_CNTL(sprite)           (VLV_DISPLAY_BASE + 0x6d100 + (sprite) * 0x1000)
+#define PCPSXHS_H(sprite)              (VLV_DISPLAY_BASE + 0x6d104 + (sprite) * 0x1000)
+#define PCPSXHS_W(sprite)              (VLV_DISPLAY_BASE + 0x6d108 + (sprite) * 0x1000)
+#define PCPSXHS_NBP(sprite)            (VLV_DISPLAY_BASE + 0x6d10c + (sprite) * 0x1000)
+#define PCPSXHS_ISF(sprite)            (VLV_DISPLAY_BASE + 0x6d110 + (sprite) * 0x1000)
+#define PCPSXHS_PC(sprite)             (VLV_DISPLAY_BASE + 0x6d114 + (sprite) * 0x1000)
+#define PCPSXHS_PM(sprite, phase, w)   (VLV_DISPLAY_BASE + 0x6d200 + (sprite) * 0x1000 + (phase) * 16 + (w) * 4)
+#define PCPSXHS_APM(sprite, phase, w)  (VLV_DISPLAY_BASE + 0x6d300 + (sprite) * 0x1000 + (phase) * 16 + (w) * 4)
+#define PCPSXVS_CNTL(sprite)           (VLV_DISPLAY_BASE + 0x6d500 + (sprite) * 0x1000)
+#define PCPSXVS_H(sprite)              (VLV_DISPLAY_BASE + 0x6d504 + (sprite) * 0x1000)
+#define PCPSXVS_W(sprite)              (VLV_DISPLAY_BASE + 0x6d508 + (sprite) * 0x1000)
+#define PCPSXVS_ISF(sprite)            (VLV_DISPLAY_BASE + 0x6d510 + (sprite) * 0x1000)
+#define PCPSXVS_PC(sprite)             (VLV_DISPLAY_BASE + 0x6d514 + (sprite) * 0x1000)
+#define PCPSXVS_PM(sprite, phase, w)   (VLV_DISPLAY_BASE + 0x6d600 + (sprite) * 0x1000 + (phase) * 8 + (w) * 4)
+#define PCPSXVS_APM(sprite, phase, w)  (VLV_DISPLAY_BASE + 0x6d700 + (sprite) * 0x1000 + (phase) * 8 + (w) * 4)
+
+#define SPCTL (VLV_DISPLAY_BASE + 0x72380)
+#define PRIMCTL (VLV_DISPLAY_BASE + 0x71180)
+#define  PLANE_EN               (1u << 31)
+
+#define SPPOS (VLV_DISPLAY_BASE + 0x7238c)
+#define PRIMPOS (VLV_DISPLAY_BASE + 0x61a08)
+
+#define SPSIZE (VLV_DISPLAY_BASE + 0x72390)
+#define PRIMSIZE (VLV_DISPLAY_BASE + 0x61a0c)
+
+static bool chv_plane_enabled(bool sprite)
+{
+	uint32_t tmp;
+
+	if (sprite)
+		tmp = I915_READ(SPCTL);
+	else
+		tmp = I915_READ(PRIMCTL);
+
+	return tmp & PLANE_EN;
+}
+
+static void chv_set_plane_size(const struct rect *r,
+			       bool sprite)
+{
+	if (sprite)
+		I915_WRITE(SPPOS, r->y << 16 | r->x);
+	else
+		I915_WRITE(PRIMPOS, r->y << 16 | r->x);
+
+	if (sprite)
+		I915_WRITE(SPSIZE, (r->h - 1) << 16 | (r->w - 1));
+	else
+		I915_WRITE(PRIMSIZE, (r->h - 1) << 16 | (r->w - 1));
+}
+
+static void chv_get_plane_size(struct rect *r,
+			       bool sprite)
+{
+	uint32_t tmp;
+
+	if (sprite)
+		tmp = I915_READ(SPPOS);
+	else
+		tmp = I915_READ(PRIMPOS);
+
+	r->x = tmp & 0xffff;
+	r->y = tmp >> 16;
+
+	if (sprite)
+		tmp = I915_READ(SPSIZE);
+	else
+		tmp = I915_READ(PRIMSIZE);
+
+	r->w = (tmp & 0xffff) + 1;
+	r->h = (tmp >> 16) + 1;
+}
+
+static int chv_coef_index(const struct filter *f, int p, int t)
+{
+	assert(f->config.nphases/2 == 16);
+	assert(f->config.ntaps == 9 ||
+	       f->config.ntaps == 5);
+
+	return nhwtaps(f) * p + tap_to_hwtap(f, t);
+}
+
+static void chv_coefs(struct filter *f, uint16_t coef[])
+{
+	for (int p = 0; p < f->config.nphases/2; p++) {
+		const double *coefs = f->phases[p].coefs;
+
+		for (int t = 0; t < f->config.ntaps; t++) {
+			union chv_coef_reg r;
+			int i = chv_coef_index(f, p, t);
+
+			chv_coef_to_reg(f, coefs[t], &r);
+
+			coef[i] = r.reg;
+		}
+	}
+}
+
+static void chv_rgb_hcoefs(struct filter *f, uint16_t coef[])
+{
+	f->config = configs[FORMAT_CHV_HORZ];
+
+	f->phase_offset = 0.5 / f->config.nphases;
+
+	generate_filter(f);
+	update_filter(f);
+	fixup_filter(f);
+
+	printf("chv rgb horz\n");
+	print_filter(f);
+	hw_print_filter(f);
+	print_c_filter(f);
+
+	chv_coefs(f, coef);
+}
+
+static void chv_alpha_hcoefs(struct filter *f, uint16_t coef[])
+{
+	f->config = configs[FORMAT_CHV_HORZ];
+	f->filter = &filter_funcs[1];
+	f->window = &window_funcs[0];
+	f->phase_offset = 0.5 / f->config.nphases;
+	f->mode = MODE_LOWPASS;
+
+	generate_filter(f);
+	update_filter(f);
+	fixup_filter(f);
+
+	printf("chv alpha horz\n");
+	print_filter(f);
+	hw_print_filter(f);
+	print_c_filter(f);
+
+	chv_coefs(f, coef);
+}
+
+static void chv_rgb_vcoefs(struct filter *f, uint16_t coef[])
+{
+	f->config = configs[FORMAT_CHV_VERT];
+
+	f->phase_offset = 0.5 / f->config.nphases;
+
+	generate_filter(f);
+	update_filter(f);
+	fixup_filter(f);
+
+	printf("chv rgb vert\n");
+	print_filter(f);
+	hw_print_filter(f);
+	print_c_filter(f);
+
+	chv_coefs(f, coef);
+}
+
+static void chv_alpha_vcoefs(struct filter *f, uint16_t coef[])
+{
+	f->config = configs[FORMAT_CHV_VERT];
+	f->filter = &filter_funcs[1];
+	f->window = &window_funcs[0];
+	f->phase_offset = 0.5 / f->config.nphases;
+	f->mode = MODE_LOWPASS;
+
+	generate_filter(f);
+	update_filter(f);
+	fixup_filter(f);
+
+	printf("chv alpha vert\n");
+	print_filter(f);
+	hw_print_filter(f);
+	print_c_filter(f);
+
+	chv_coefs(f, coef);
+}
+
+static void chv_program_rgb_horz(bool sprite, const uint16_t coef[])
+{
+	for (int p = 0; p < 16; p++) {
+		uint32_t tmp;
+
+		tmp = coef[2] << 24 | coef[1] << 12 | coef[0];
+		I915_WRITE(PCPSXHS_PM(sprite, p, 0), tmp);
+
+		tmp = coef[5] << 28 | coef[4] << 16 | coef[3] << 4 | coef[2] >> 8;
+		I915_WRITE(PCPSXHS_PM(sprite, p, 1), tmp);
+
+		tmp = coef[7] << 20 | coef[6] << 8 | coef[5] >> 4;
+		I915_WRITE(PCPSXHS_PM(sprite, p, 2), tmp);
+
+		tmp = coef[8];
+		I915_WRITE(PCPSXHS_PM(sprite, p, 3), tmp);
+
+		coef += 9;
+	}
+}
+
+static void chv_program_alpha_horz(bool sprite, const uint16_t coef[])
+{
+	for (int p = 0; p < 16; p++) {
+		uint32_t tmp;
+
+		tmp = coef[2] << 24 | coef[1] << 12 | coef[0];
+		I915_WRITE(PCPSXHS_APM(sprite, p, 0), tmp);
+
+		tmp = coef[5] << 28 | coef[4] << 16 | coef[3] << 4 | coef[2] >> 8;
+		I915_WRITE(PCPSXHS_APM(sprite, p, 1), tmp);
+
+		tmp = coef[7] << 20 | coef[6] << 8 | coef[5] >> 4;
+		I915_WRITE(PCPSXHS_APM(sprite, p, 2), tmp);
+
+		tmp = coef[8];
+		I915_WRITE(PCPSXHS_APM(sprite, p, 3), tmp);
+
+		coef += 9;
+	}
+}
+
+static void chv_program_rgb_vert(bool sprite, const uint16_t coef[])
+{
+	for (int p = 0; p < 16; p++) {
+		uint32_t tmp;
+
+		tmp = coef[2] << 24 | coef[1] << 12 | coef[0];
+		I915_WRITE(PCPSXVS_PM(sprite, p, 0), tmp);
+
+		tmp = coef[4] << 16 | coef[3] << 4 | coef[2] >> 8;
+		I915_WRITE(PCPSXVS_PM(sprite, p, 1), tmp);
+
+		coef += 5;
+	}
+}
+
+static void chv_program_alpha_vert(bool sprite, const uint16_t coef[])
+{
+	for (int p = 0; p < 16; p++) {
+		uint32_t tmp;
+
+		tmp = coef[2] << 24 | coef[1] << 12 | coef[0];
+		I915_WRITE(PCPSXVS_APM(sprite, p, 0), tmp);
+
+		tmp = coef[4] << 16 | coef[3] << 4 | coef[2] >> 8;
+		I915_WRITE(PCPSXVS_APM(sprite, p, 1), tmp);
+
+		coef += 5;
+	}
+}
+
+static unsigned int chv_initial_phase(const struct filter *f)
+{
+	return ((f->config.nphases - 1) << 16) / (f->config.nphases * 2);
+}
+
+static unsigned int chv_vert_read_offset(int ntaps)
+{
+	/* 5 taps -> -2 */
+	return 0x10 | (ntaps / 2);
+}
+
+static void chv_program(struct filter *f)
+{
+	struct filter af = {};
+	struct intel_mmio_data mmio_data;
+	uint16_t hcoef[9*16] = {};
+	uint16_t vcoef[5*16] = {};
+	bool sprite = false;
+	uint32_t devid;
+	struct rect orig_dst;
+	struct rect dst;
+	struct rect src;
+
+	devid = intel_get_pci_device()->device_id;
+
+	if (!IS_CHERRYVIEW(devid))
+		return;
+
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
+
+	if (!chv_plane_enabled(sprite))
+		goto out;
+
+	chv_get_plane_size(&src, sprite);
+
+	dst = src;
+	orig_dst = dst;
+
+	dst.x = 16;
+	dst.y = 16;
+	dst.w -= 32;
+	dst.h -= 32;
+
+	chv_rgb_hcoefs(f, hcoef);
+
+	I915_WRITE(PCPSXHS_CNTL(sprite), 0);
+	I915_WRITE(PCPSXHS_H(sprite), src.h);
+	I915_WRITE(PCPSXHS_W(sprite), (dst.w << 16) | src.w);
+	I915_WRITE(PCPSXHS_NBP(sprite), chv_vert_read_offset(5) << 8);
+	I915_WRITE(PCPSXHS_ISF(sprite), (src.w << 16) / dst.w);
+	I915_WRITE(PCPSXHS_PC(sprite), chv_initial_phase(f) << 8 |
+		   f->config.nphases);
+
+	chv_program_rgb_horz(sprite, hcoef);
+	chv_alpha_hcoefs(&af, hcoef);
+	chv_program_alpha_horz(sprite, hcoef);
+
+	chv_rgb_vcoefs(f, vcoef);
+
+	I915_WRITE(PCPSXVS_CNTL(sprite), 0);
+	I915_WRITE(PCPSXVS_H(sprite), (dst.h << 16) | src.h);
+	I915_WRITE(PCPSXVS_W(sprite), dst.w);
+	I915_WRITE(PCPSXVS_ISF(sprite), (src.h << 16) / dst.h);
+	I915_WRITE(PCPSXVS_PC(sprite), chv_initial_phase(f) << 8 |
+		   f->config.nphases);
+
+	chv_program_rgb_vert(sprite, vcoef);
+	chv_alpha_vcoefs(&af, vcoef);
+	chv_program_alpha_vert(sprite, vcoef);
+
+#if 0
+	I915_READ(PCPSXHS_CNTL(sprite));
+	I915_READ(PCPSXHS_H(sprite));
+	I915_READ(PCPSXHS_W(sprite));
+	I915_READ(PCPSXHS_NBP(sprite));
+	I915_READ(PCPSXHS_ISF(sprite));
+	I915_READ(PCPSXHS_PC(sprite));
+
+	for (int p = 0; p < 16; p++) {
+		printf("p = %d\n", p);
+		I915_READ(PCPSXHS_PM(sprite, p, 0));
+		I915_READ(PCPSXHS_PM(sprite, p, 1));
+		I915_READ(PCPSXHS_PM(sprite, p, 2));
+		I915_READ(PCPSXHS_PM(sprite, p, 3));
+	}
+
+	for (int p = 0; p < 16; p++) {
+		printf("p = %d\n", p);
+		I915_READ(PCPSXHS_APM(sprite, p, 0));
+		I915_READ(PCPSXHS_APM(sprite, p, 1));
+		I915_READ(PCPSXHS_APM(sprite, p, 2));
+		I915_READ(PCPSXHS_APM(sprite, p, 3));
+	}
+
+	I915_READ(PCPSXVS_CNTL(sprite));
+	I915_READ(PCPSXVS_H(sprite));
+	I915_READ(PCPSXVS_W(sprite));
+	I915_READ(PCPSXVS_ISF(sprite));
+	I915_READ(PCPSXVS_PC(sprite));
+
+	for (int p = 0; p < 16; p++) {
+		printf("p = %d\n", p);
+		I915_READ(PCPSXVS_PM(sprite, p, 0));
+		I915_READ(PCPSXVS_PM(sprite, p, 1));
+	}
+
+	for (int p = 0; p < 16; p++) {
+		printf("p = %d\n", p);
+		I915_READ(PCPSXVS_APM(sprite, p, 0));
+		I915_READ(PCPSXVS_APM(sprite, p, 1));
+	}
+#endif
+
+	I915_WRITE(PCPSXCONFIG(sprite), PCPSX_SCALER_EN);
+	chv_set_plane_size(&dst, sprite);
+
+	printf("%dx%d%+d%+d -> %dx%d%+d%+d\n",
+	       src.w, src.h, src.x, src.y,
+	       dst.w, dst.h, dst.x, dst.y);
+
+	sleep(2);
+
+	chv_set_plane_size(&orig_dst, sprite);
+	I915_WRITE(PCPSXCONFIG(sprite), 0);
+
+ out:
+	intel_register_access_fini(&mmio_data);
+}
+
 int main(int argc, char *argv[])
 {
 	const struct option opts[] = {
@@ -1532,6 +1912,8 @@ int main(int argc, char *argv[])
 		cnl_program(&f, 0);
 	if (1)
 		ilk_program(&f, 0);
+	if (1)
+		chv_program(&f);
 
 	return 0;
 }
-- 
2.24.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [igt-dev] [PATCH i-g-t 6/6] HACK: lib/igt_fb: Paint diagonals
  2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
                   ` (3 preceding siblings ...)
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 5/6] HACK: tools/intel_scaler_coef: Test chv plane " Ville Syrjala
@ 2020-03-10 14:18 ` Ville Syrjala
  2020-03-10 15:21 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Patchwork
  2020-03-10 19:26 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  6 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-03-10 14:18 UTC (permalink / raw)
  To: igt-dev

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Paint diagonals on the standard test pattern so that scaling
artifacts are more readily visible.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 lib/igt_fb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 0c4fdc5d4889..cc57493e01c5 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1479,6 +1479,18 @@ paint_marker(cairo_t *cr, int x, int y)
 	igt_cairo_printf_line(cr, align, 0, "(%d, %d)", x, y);
 }
 
+static void
+paint_diagonals(cairo_t *cr, int w, int h)
+{
+	cairo_move_to(cr, 0, 0);
+	cairo_line_to(cr, w, h);
+	cairo_move_to(cr, 0, h);
+	cairo_line_to(cr, w, 0);
+	cairo_set_source_rgb(cr, 1, 1, 1);
+	cairo_set_line_width(cr, 1);
+	cairo_stroke(cr);
+}
+
 /**
  * igt_paint_test_pattern:
  * @cr: cairo drawing context
@@ -1499,6 +1511,8 @@ void igt_paint_test_pattern(cairo_t *cr, int width, int height)
 
 	cairo_set_line_cap(cr, CAIRO_LINE_CAP_SQUARE);
 
+	paint_diagonals(cr, width, height);
+
 	/* Paint corner markers */
 	paint_marker(cr, 0, 0);
 	paint_marker(cr, width, 0);
-- 
2.24.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients
  2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
                   ` (4 preceding siblings ...)
  2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 6/6] HACK: lib/igt_fb: Paint diagonals Ville Syrjala
@ 2020-03-10 15:21 ` Patchwork
  2020-03-10 19:26 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  6 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-03-10 15:21 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: igt-dev

== Series Details ==

Series: series starting with [i-g-t,1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients
URL   : https://patchwork.freedesktop.org/series/74521/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8106 -> IGTPW_4285
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/index.html

Known issues
------------

  Here are the changes found in IGTPW_4285 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-tgl-y:           [PASS][1] -> [FAIL][2] ([CI#94])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live@execlists:
    - fi-tgl-y:           [PASS][3] -> [INCOMPLETE][4] ([CI#94] / [i915#647])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/fi-tgl-y/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-cml-s:           [PASS][5] -> [DMESG-FAIL][6] ([i915#877])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/fi-cml-s/igt@i915_selftest@live@gem_contexts.html

  * igt@prime_vgem@basic-read:
    - fi-tgl-y:           [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@prime_vgem@basic-read.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/fi-tgl-y/igt@prime_vgem@basic-read.html

  
#### Possible fixes ####

  * igt@gem_flink_basic@bad-open:
    - fi-tgl-y:           [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/fi-tgl-y/igt@gem_flink_basic@bad-open.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/fi-tgl-y/igt@gem_flink_basic@bad-open.html

  
  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877


Participating hosts (44 -> 42)
------------------------------

  Additional (5): fi-bdw-5557u fi-kbl-7500u fi-cfl-8109u fi-skl-6600u fi-snb-2600 
  Missing    (7): fi-hsw-4200u fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-byt-clapper fi-bdw-samus fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5504 -> IGTPW_4285

  CI-20190529: 20190529
  CI_DRM_8106: 5b0076e8066ea8218e7857ee1aa28b0670acde94 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4285: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/index.html
  IGT_5504: d6788bf0404f76b66170e18eb26c85004b5ccb25 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients
  2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
                   ` (5 preceding siblings ...)
  2020-03-10 15:21 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Patchwork
@ 2020-03-10 19:26 ` Patchwork
  6 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-03-10 19:26 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: igt-dev

== Series Details ==

Series: series starting with [i-g-t,1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients
URL   : https://patchwork.freedesktop.org/series/74521/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8106_full -> IGTPW_4285_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4285_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4285_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4285_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_parallel@bcs0-contexts:
    - shard-tglb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-tglb1/igt@gem_exec_parallel@bcs0-contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-tglb2/igt@gem_exec_parallel@bcs0-contexts.html

  * igt@kms_3d:
    - shard-kbl:          [PASS][3] -> [INCOMPLETE][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-kbl7/igt@kms_3d.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-kbl6/igt@kms_3d.html

  
Known issues
------------

  Here are the changes found in IGTPW_4285_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-kbl2/igt@gem_ctx_isolation@bcs0-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-kbl2/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-iclb:         [PASS][7] -> [INCOMPLETE][8] ([i915#1402])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb5/igt@gem_ctx_persistence@close-replace-race.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb8/igt@gem_ctx_persistence@close-replace-race.html

  * igt@gem_exec_schedule@implicit-write-read-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276] / [i915#677])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb1/igt@gem_exec_schedule@implicit-write-read-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb7/igt@gem_exec_schedule@implicit-write-read-bsd2.html

  * igt@gem_exec_schedule@pi-shared-iova-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([i915#677])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb5/igt@gem_exec_schedule@pi-shared-iova-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb2/igt@gem_exec_schedule@pi-shared-iova-bsd.html

  * igt@gem_exec_schedule@preempt-other-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112146]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb8/igt@gem_exec_schedule@preempt-other-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb4/igt@gem_exec_schedule@preempt-other-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109276]) +13 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [PASS][17] -> [FAIL][18] ([i915#644])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-hsw:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-hsw7/igt@gem_userptr_blits@dmabuf-unsync.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-hsw6/igt@gem_userptr_blits@dmabuf-unsync.html
    - shard-snb:          [PASS][21] -> [DMESG-WARN][22] ([fdo#111870] / [i915#478])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-snb4/igt@gem_userptr_blits@dmabuf-unsync.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-snb2/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-iclb:         [PASS][23] -> [FAIL][24] ([i915#447])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb8/igt@i915_pm_dc@dc5-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html

  * igt@i915_pm_rps@reset:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([i915#413])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb7/igt@i915_pm_rps@reset.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb4/igt@i915_pm_rps@reset.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
    - shard-kbl:          [PASS][27] -> [FAIL][28] ([i915#54])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
    - shard-apl:          [PASS][29] -> [FAIL][30] ([i915#54])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([i915#180])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-apl8/igt@kms_flip@flip-vs-suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-apl6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-apl:          [PASS][33] -> [INCOMPLETE][34] ([fdo#103927])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-apl2/igt@kms_flip@modeset-vs-vblank-race.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-apl6/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-glk:          [PASS][35] -> [FAIL][36] ([i915#899])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([fdo#109642] / [fdo#111068])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb6/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb3/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][41] -> [FAIL][42] ([i915#31])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-apl1/igt@kms_setmode@basic.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-apl8/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-d-ts-continuation-modeset-rpm:
    - shard-tglb:         [PASS][43] -> [SKIP][44] ([fdo#112015])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-tglb1/igt@kms_vblank@pipe-d-ts-continuation-modeset-rpm.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-tglb5/igt@kms_vblank@pipe-d-ts-continuation-modeset-rpm.html

  * igt@perf_pmu@busy-start-vcs1:
    - shard-iclb:         [PASS][45] -> [SKIP][46] ([fdo#112080]) +7 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb4/igt@perf_pmu@busy-start-vcs1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb5/igt@perf_pmu@busy-start-vcs1.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][47] ([i915#180]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_persistence@processes:
    - shard-kbl:          [FAIL][49] ([i915#570] / [i915#679]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-kbl2/igt@gem_ctx_persistence@processes.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-kbl7/igt@gem_ctx_persistence@processes.html

  * igt@gem_exec_balancer@hang:
    - shard-tglb:         [FAIL][51] ([i915#1277]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-tglb1/igt@gem_exec_balancer@hang.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-tglb3/igt@gem_exec_balancer@hang.html

  * igt@gem_exec_schedule@implicit-both-bsd:
    - shard-iclb:         [SKIP][53] ([i915#677]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb6/igt@gem_exec_schedule@implicit-both-bsd.html

  * igt@gem_exec_schedule@implicit-both-bsd2:
    - shard-iclb:         [SKIP][55] ([fdo#109276] / [i915#677]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb7/igt@gem_exec_schedule@implicit-both-bsd2.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][57] ([fdo#112146]) -> [PASS][58] +4 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-glk:          [DMESG-WARN][59] ([i915#118] / [i915#95]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-glk2/igt@gem_exec_whisper@basic-queues-forked.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-glk7/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@i915_suspend@sysfs-reader:
    - shard-snb:          [DMESG-WARN][61] ([i915#42]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-snb4/igt@i915_suspend@sysfs-reader.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-snb6/igt@i915_suspend@sysfs-reader.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          [FAIL][63] ([i915#79]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [DMESG-WARN][65] ([i915#180] / [i915#56]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [INCOMPLETE][67] -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
    - shard-hsw:          [DMESG-WARN][69] ([i915#478]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-hsw7/igt@kms_plane_multiple@atomic-pipe-c-tiling-x.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-hsw4/igt@kms_plane_multiple@atomic-pipe-c-tiling-x.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][71] ([fdo#109441]) -> [PASS][72] +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [FAIL][73] ([i915#31]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-hsw6/igt@kms_setmode@basic.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-hsw6/igt@kms_setmode@basic.html

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         [SKIP][75] ([fdo#112080]) -> [PASS][76] +14 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb5/igt@perf_pmu@busy-no-semaphores-vcs1.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html

  * igt@prime_vgem@basic-gtt:
    - shard-snb:          [DMESG-WARN][77] ([i915#478]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-snb4/igt@prime_vgem@basic-gtt.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-snb6/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][79] ([fdo#109276]) -> [PASS][80] +18 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_linear_blits@normal:
    - shard-apl:          [TIMEOUT][81] ([i915#1322]) -> [TIMEOUT][82] ([fdo#111732] / [i915#1322])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-apl4/igt@gem_linear_blits@normal.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-apl4/igt@gem_linear_blits@normal.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][83] ([fdo#110789] / [fdo#111870] / [i915#478]) -> [DMESG-WARN][84] ([fdo#111870] / [i915#478])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-snb6/igt@gem_userptr_blits@dmabuf-sync.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-snb5/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-hsw:          [DMESG-WARN][85] ([fdo#110789] / [fdo#111870]) -> [DMESG-WARN][86] ([fdo#111870])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-hsw8/igt@gem_userptr_blits@dmabuf-sync.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-hsw1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [FAIL][87] ([i915#454]) -> [SKIP][88] ([i915#468])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-tglb1/igt@i915_pm_dc@dc6-dpms.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-snb:          [SKIP][89] ([fdo#109271]) -> [INCOMPLETE][90] ([i915#82])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-snb5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-snb4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@fences:
    - shard-snb:          [INCOMPLETE][91] ([i915#82]) -> [SKIP][92] ([fdo#109271])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-snb4/igt@i915_pm_rpm@fences.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-snb5/igt@i915_pm_rpm@fences.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][93] ([fdo#109349]) -> [DMESG-WARN][94] ([i915#1226])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8106/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#112015]: https://bugs.freedesktop.org/show_bug.cgi?id=112015
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
  [i915#1322]: https://gitlab.freedesktop.org/drm/intel/issues/1322
  [i915#1402]: https://gitlab.freedesktop.org/drm/intel/issues/1402
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#56]: https://gitlab.freedesktop.org/drm/intel/issues/56
  [i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 8)
------------------------------

  Missing    (2): pig-skl-6260u pig-glk-j5005 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5504 -> IGTPW_4285
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_8106: 5b0076e8066ea8218e7857ee1aa28b0670acde94 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4285: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/index.html
  IGT_5504: d6788bf0404f76b66170e18eb26c85004b5ccb25 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4285/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2020-03-10 19:26 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-10 14:18 [igt-dev] [PATCH i-g-t 1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Ville Syrjala
2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 2/6] tools/intel_scaler_coef: Add support for chv plane " Ville Syrjala
2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 3/6] HACK: tools/intel_scaler_coef: Test ilk/snb/ivb panel fitter programmable coefficients Ville Syrjala
2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 4/6] HACK: tools/intel_scaler_coef: Test cnl+ pipe scaler " Ville Syrjala
2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 5/6] HACK: tools/intel_scaler_coef: Test chv plane " Ville Syrjala
2020-03-10 14:18 ` [igt-dev] [PATCH i-g-t 6/6] HACK: lib/igt_fb: Paint diagonals Ville Syrjala
2020-03-10 15:21 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/6] tools/intel_scaler_coef: Add a tool for calculating scaler coefficients Patchwork
2020-03-10 19:26 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork

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