* [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement
[not found] <db66a177-0ae2-14a2-0ec7-854531a2a62a@gmail.com>
@ 2020-03-11 11:49 ` Akira Yokosawa
2020-03-11 15:31 ` Akira Yokosawa
2020-03-11 16:11 ` [PATCH 1/2] cpu/overheads: Fix typos in large server's overhead table Paul E. McKenney
1 sibling, 1 reply; 4+ messages in thread
From: Akira Yokosawa @ 2020-03-11 11:49 UTC (permalink / raw)
To: Paul E. McKenney; +Cc: perfbook, Akira Yokosawa
From 9256445a646099df48b3f6af7ad232dd228f3039 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Tue, 10 Mar 2020 22:12:45 +0900
Subject: [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement
Also flag suspicious raws in Table E.1 as comments.
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
Hi Paul,
Think of this as a reminder rather than a patch to be applied as is.
Updated Table E.1 looks inconsistent to me.
Thanks, Akira
--
cpu/overheads.tex | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/cpu/overheads.tex b/cpu/overheads.tex
index d1b4f596..e5ea0803 100644
--- a/cpu/overheads.tex
+++ b/cpu/overheads.tex
@@ -189,7 +189,7 @@ atomic operations on the lock data structure, one for acquisition and
the other for release.
In-core operations involving interactions between the hardware threads
-sharing a single core are about the same cost and same-CPU operations.
+sharing a single core are about the same cost as same-CPU operations.
This should not be too surprising, given that these two hardware threads
also share the full cache hierarchy.
CAS stands for an atomic compare-and-swap operation, where the hardware
@@ -198,9 +198,9 @@ compares the contents of the specified memory location to a specified
in which case the CAS operation is said to have succeeded.
If they compare unequal, the memory location keeps its (unexpected) value,
and the CAS operation is said to have failed.
-The operation is atomic is that the hardware guarantees that the memory
+The operation is atomic in that the hardware guarantees that the memory
location will not be changed between the compare and the store.
-CAS functionality is provided by the x86 \co{lock;cmpxchg} instruction.
+CAS functionality is provided by the \co{lock;cmpxchg} instruction on x86.
In the case of the blind CAS, the software specifies the old value
without looking at the memory location.
@@ -317,15 +317,15 @@ thousand clock cycles.
Clock period & 0.4 & 1.0 \\
Same-CPU CAS & 12.2 & 33.8 \\
Same-CPU lock & 25.6 & 71.2 \\
- Blind CAS & 12.9 & 35.8 \\
- CAS & 7.0 & 19.4 \\
+ Blind CAS & 12.9 & 35.8 \\ % CAS?
+ CAS & 7.0 & 19.4 \\ % Blind CAS?
\midrule
Off-Core & & \\
- Blind CAS & 31.2 & 86.6 \\
+ Blind CAS & 31.2 & 86.6 \\ % Realy Blind?
CAS & 31.2 & 86.5 \\
\midrule
Off-Socket & & \\
- Blind CAS & 92.4 & 256.7 \\
+ Blind CAS & 92.4 & 256.7 \\ % Realy Blind?
CAS & 95.9 & 266.4 \\
\midrule
Off-System & & \\
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement
2020-03-11 11:49 ` [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement Akira Yokosawa
@ 2020-03-11 15:31 ` Akira Yokosawa
2020-03-11 16:30 ` Paul E. McKenney
0 siblings, 1 reply; 4+ messages in thread
From: Akira Yokosawa @ 2020-03-11 15:31 UTC (permalink / raw)
To: Paul E. McKenney; +Cc: perfbook, Akira Yokosawa
On Wed, 11 Mar 2020 20:49:10 +0900, Akira Yokosawa wrote:
> From 9256445a646099df48b3f6af7ad232dd228f3039 Mon Sep 17 00:00:00 2001
> From: Akira Yokosawa <akiyks@gmail.com>
> Date: Tue, 10 Mar 2020 22:12:45 +0900
> Subject: [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement
>
> Also flag suspicious raws in Table E.1 as comments.
Obvious typo:
... rows ...
>
> Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
> ---
> Hi Paul,
>
> Think of this as a reminder rather than a patch to be applied as is.
So I'm not submitting v2 of this one.
Thanks, Akira
> Updated Table E.1 looks inconsistent to me.
>
> Thanks, Akira
> --
> cpu/overheads.tex | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/cpu/overheads.tex b/cpu/overheads.tex
> index d1b4f596..e5ea0803 100644
> --- a/cpu/overheads.tex
> +++ b/cpu/overheads.tex
> @@ -189,7 +189,7 @@ atomic operations on the lock data structure, one for acquisition and
> the other for release.
>
> In-core operations involving interactions between the hardware threads
> -sharing a single core are about the same cost and same-CPU operations.
> +sharing a single core are about the same cost as same-CPU operations.
> This should not be too surprising, given that these two hardware threads
> also share the full cache hierarchy.
> CAS stands for an atomic compare-and-swap operation, where the hardware
> @@ -198,9 +198,9 @@ compares the contents of the specified memory location to a specified
> in which case the CAS operation is said to have succeeded.
> If they compare unequal, the memory location keeps its (unexpected) value,
> and the CAS operation is said to have failed.
> -The operation is atomic is that the hardware guarantees that the memory
> +The operation is atomic in that the hardware guarantees that the memory
> location will not be changed between the compare and the store.
> -CAS functionality is provided by the x86 \co{lock;cmpxchg} instruction.
> +CAS functionality is provided by the \co{lock;cmpxchg} instruction on x86.
>
> In the case of the blind CAS, the software specifies the old value
> without looking at the memory location.
> @@ -317,15 +317,15 @@ thousand clock cycles.
> Clock period & 0.4 & 1.0 \\
> Same-CPU CAS & 12.2 & 33.8 \\
> Same-CPU lock & 25.6 & 71.2 \\
> - Blind CAS & 12.9 & 35.8 \\
> - CAS & 7.0 & 19.4 \\
> + Blind CAS & 12.9 & 35.8 \\ % CAS?
> + CAS & 7.0 & 19.4 \\ % Blind CAS?
> \midrule
> Off-Core & & \\
> - Blind CAS & 31.2 & 86.6 \\
> + Blind CAS & 31.2 & 86.6 \\ % Realy Blind?
> CAS & 31.2 & 86.5 \\
> \midrule
> Off-Socket & & \\
> - Blind CAS & 92.4 & 256.7 \\
> + Blind CAS & 92.4 & 256.7 \\ % Realy Blind?
> CAS & 95.9 & 266.4 \\
> \midrule
> Off-System & & \\
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] cpu/overheads: Fix typos in large server's overhead table
[not found] <db66a177-0ae2-14a2-0ec7-854531a2a62a@gmail.com>
2020-03-11 11:49 ` [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement Akira Yokosawa
@ 2020-03-11 16:11 ` Paul E. McKenney
1 sibling, 0 replies; 4+ messages in thread
From: Paul E. McKenney @ 2020-03-11 16:11 UTC (permalink / raw)
To: Akira Yokosawa; +Cc: perfbook
On Wed, Mar 11, 2020 at 08:46:36PM +0900, Akira Yokosawa wrote:
> >From 512ad80cac5977ad331260b4691b172585827e1b Mon Sep 17 00:00:00 2001
> From: Akira Yokosawa <akiyks@gmail.com>
> Date: Tue, 10 Mar 2020 20:48:17 +0900
> Subject: [PATCH 1/2] cpu/overheads: Fix typo in large server's overhead table
>
> CPU 224 is not among Off-core CPUs.
>
> Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Good catch, applied, thank you!!!
Thanx, Paul
> ---
> cpu/overheads.tex | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/cpu/overheads.tex b/cpu/overheads.tex
> index 717a9ea0..d1b4f596 100644
> --- a/cpu/overheads.tex
> +++ b/cpu/overheads.tex
> @@ -149,8 +149,8 @@ optimization.
> Same-CPU lock & 15.4 & 32.3 & 0 \\
> In-core blind CAS & 7.2 & 15.2 & 224 \\
> In-core CAS & 18.0 & 37.7 & 224 \\
> - Off-core blind CAS & 47.5 & 99.8 & 1--27,224--251 \\
> - Off-core CAS & 101.9 & 214.0 & 1--27,224--251 \\
> + Off-core blind CAS & 47.5 & 99.8 & 1--27,225--251 \\
> + Off-core CAS & 101.9 & 214.0 & 1--27,225--251 \\
> Off-socket blind CAS & 148.8 & 312.5 & 28--111,252--335 \\
> Off-socket CAS & 442.9 & 930.1 & 28--111,252--335 \\
> Cross-interconnect blind CAS & 336.6 & 706.8 & 112--223,336--447 \\
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement
2020-03-11 15:31 ` Akira Yokosawa
@ 2020-03-11 16:30 ` Paul E. McKenney
0 siblings, 0 replies; 4+ messages in thread
From: Paul E. McKenney @ 2020-03-11 16:30 UTC (permalink / raw)
To: Akira Yokosawa; +Cc: perfbook
On Thu, Mar 12, 2020 at 12:31:45AM +0900, Akira Yokosawa wrote:
> On Wed, 11 Mar 2020 20:49:10 +0900, Akira Yokosawa wrote:
> > From 9256445a646099df48b3f6af7ad232dd228f3039 Mon Sep 17 00:00:00 2001
> > From: Akira Yokosawa <akiyks@gmail.com>
> > Date: Tue, 10 Mar 2020 22:12:45 +0900
> > Subject: [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement
> >
> > Also flag suspicious raws in Table E.1 as comments.
>
> Obvious typo:
> ... rows ...
> >
> > Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
> > ---
> > Hi Paul,
> >
> > Think of this as a reminder rather than a patch to be applied as is.
>
> So I'm not submitting v2 of this one.
>
> Thanks, Akira
>
> > Updated Table E.1 looks inconsistent to me.
Same numbers as before, and yes, the in-core numbers look strange.
The story I heard was that it was an artifact of instruction scheduling.
My understanding is that the between-cores numbers benefit from
instruction look-ahead, so that the load is aware that the cmpxchg is
on its way.
I applied the other two hunks and removed the "raws" sentence, thank
you very much!
Thanx, Paul
> > Thanks, Akira
> > --
> > cpu/overheads.tex | 14 +++++++-------
> > 1 file changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/cpu/overheads.tex b/cpu/overheads.tex
> > index d1b4f596..e5ea0803 100644
> > --- a/cpu/overheads.tex
> > +++ b/cpu/overheads.tex
> > @@ -189,7 +189,7 @@ atomic operations on the lock data structure, one for acquisition and
> > the other for release.
> >
> > In-core operations involving interactions between the hardware threads
> > -sharing a single core are about the same cost and same-CPU operations.
> > +sharing a single core are about the same cost as same-CPU operations.
> > This should not be too surprising, given that these two hardware threads
> > also share the full cache hierarchy.
> > CAS stands for an atomic compare-and-swap operation, where the hardware
> > @@ -198,9 +198,9 @@ compares the contents of the specified memory location to a specified
> > in which case the CAS operation is said to have succeeded.
> > If they compare unequal, the memory location keeps its (unexpected) value,
> > and the CAS operation is said to have failed.
> > -The operation is atomic is that the hardware guarantees that the memory
> > +The operation is atomic in that the hardware guarantees that the memory
> > location will not be changed between the compare and the store.
> > -CAS functionality is provided by the x86 \co{lock;cmpxchg} instruction.
> > +CAS functionality is provided by the \co{lock;cmpxchg} instruction on x86.
> >
> > In the case of the blind CAS, the software specifies the old value
> > without looking at the memory location.
> > @@ -317,15 +317,15 @@ thousand clock cycles.
> > Clock period & 0.4 & 1.0 \\
> > Same-CPU CAS & 12.2 & 33.8 \\
> > Same-CPU lock & 25.6 & 71.2 \\
> > - Blind CAS & 12.9 & 35.8 \\
> > - CAS & 7.0 & 19.4 \\
> > + Blind CAS & 12.9 & 35.8 \\ % CAS?
> > + CAS & 7.0 & 19.4 \\ % Blind CAS?
> > \midrule
> > Off-Core & & \\
> > - Blind CAS & 31.2 & 86.6 \\
> > + Blind CAS & 31.2 & 86.6 \\ % Realy Blind?
> > CAS & 31.2 & 86.5 \\
> > \midrule
> > Off-Socket & & \\
> > - Blind CAS & 92.4 & 256.7 \\
> > + Blind CAS & 92.4 & 256.7 \\ % Realy Blind?
> > CAS & 95.9 & 266.4 \\
> > \midrule
> > Off-System & & \\
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <db66a177-0ae2-14a2-0ec7-854531a2a62a@gmail.com>
2020-03-11 11:49 ` [PATCH 2/2] cpu/overheads: Typo fixes and wording improvement Akira Yokosawa
2020-03-11 15:31 ` Akira Yokosawa
2020-03-11 16:30 ` Paul E. McKenney
2020-03-11 16:11 ` [PATCH 1/2] cpu/overheads: Fix typos in large server's overhead table Paul E. McKenney
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