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* [PATCH RFC 0/9] Add riscv64 kvm accel support
@ 2020-03-13  3:49 ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Hi,

This series adds riscv64 kvm support, It is based on riscv_kvm_master
branch at https://github.com/kvm-riscv/linux.

This series depends on above pending changes which haven't yet been
accepted, so this QEMU patch series is blocked until that dependency
has been dealt with, but is worth reviewing anyway.

Several steps to use this:

1. Build riscv64 emulation
$ ./configure --target-list=riscv64-softmmu
$ make -j$(nproc)

2. Build kernel
riscv_kvm_master branch at https://github.com/kvm-riscv/linux

3. Build QEMU VM
I cross build in riscv toolchain
$ PKG_CONFIG_LIBDIR=<toolchain pkgconfig path>
$ export PKG_CONFIG_SYSROOT_DIR=<toolchain sysroot path>
$ ./configure --target-list=riscv64-softmmu --enable-kvm \
--cross-prefix=riscv64-linux-gnu- --disable-libiscsi --disable-glusterfs \
--disable-libusb --disable-usb-redir --audio-drv-list= --disable-opengl \
--disable-libxml2

4. Start riscv64 emulation
$ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
        -name guest=riscv-hyp,debug-threads=on \
        -smp 4 \
        -kernel ./fw_jump.elf \
        -device loader,file=./Image,addr=0x80200000 \
        -drive file=./hyp.img,format=raw,id=hd0 \
        -device virtio-blk-device,drive=hd0 \
        -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"

5. Start kvm-acceled QEMU VM in riscv64 emulation
$ ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
        -name guest=riscv-guset \
         -smp 2 \
        -kernel ./Image \
        -drive file=./guest.img,format=raw,id=hd0 \
        -device virtio-blk-device,drive=hd0 \
        -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"

Yifei Jiang (9):
  linux-header: Update linux/kvm.h
  target/riscv: Add target/riscv/kvm.c to place the public kvm interface
  target/riscv: Implement function kvm_arch_init_vcpu
  target/riscv: Implement kvm_arch_get_registers
  target/riscv: Implement kvm_arch_put_registers
  target/riscv: Support start kernel directly by KVM
  hw/riscv: PLIC update external interrupt by KVM when kvm enabled
  target/riscv: Handler KVM_EXIT_RISCV_SBI exit
  target/riscv: add host riscv64 cpu type

 configure                  |   1 +
 hw/riscv/sifive_plic.c     |  31 ++-
 hw/riscv/virt.c            |  15 +-
 linux-headers/linux/kvm.h  |   8 +
 target/riscv/Makefile.objs |   1 +
 target/riscv/cpu.c         |   9 +
 target/riscv/cpu.h         |   4 +
 target/riscv/kvm.c         | 513 +++++++++++++++++++++++++++++++++++++
 target/riscv/kvm_riscv.h   |  25 ++
 9 files changed, 596 insertions(+), 11 deletions(-)
 create mode 100644 target/riscv/kvm.c
 create mode 100644 target/riscv/kvm_riscv.h

-- 
2.19.1




^ permalink raw reply	[flat|nested] 36+ messages in thread
* [PATCH RFC 0/9] Add riscv64 kvm accel support
@ 2020-03-13  3:49 ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Hi,

This series adds riscv64 kvm support, It is based on riscv_kvm_master
branch at https://github.com/kvm-riscv/linux.

This series depends on above pending changes which haven't yet been
accepted, so this QEMU patch series is blocked until that dependency
has been dealt with, but is worth reviewing anyway.

Several steps to use this:

1. Build riscv64 emulation
$ ./configure --target-list=riscv64-softmmu
$ make -j$(nproc)

2. Build kernel
riscv_kvm_master branch at https://github.com/kvm-riscv/linux

3. Build QEMU VM
I cross build in riscv toolchain
$ PKG_CONFIG_LIBDIR=<toolchain pkgconfig path>
$ export PKG_CONFIG_SYSROOT_DIR=<toolchain sysroot path>
$ ./configure --target-list=riscv64-softmmu --enable-kvm \
--cross-prefix=riscv64-linux-gnu- --disable-libiscsi --disable-glusterfs \
--disable-libusb --disable-usb-redir --audio-drv-list= --disable-opengl \
--disable-libxml2

4. Start riscv64 emulation
$ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
        -name guest=riscv-hyp,debug-threads=on \
        -smp 4 \
        -kernel ./fw_jump.elf \
        -device loader,file=./Image,addr=0x80200000 \
        -drive file=./hyp.img,format=raw,id=hd0 \
        -device virtio-blk-device,drive=hd0 \
        -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"

5. Start kvm-acceled QEMU VM in riscv64 emulation
$ ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
        -name guest=riscv-guset \
         -smp 2 \
        -kernel ./Image \
        -drive file=./guest.img,format=raw,id=hd0 \
        -device virtio-blk-device,drive=hd0 \
        -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"

Yifei Jiang (9):
  linux-header: Update linux/kvm.h
  target/riscv: Add target/riscv/kvm.c to place the public kvm interface
  target/riscv: Implement function kvm_arch_init_vcpu
  target/riscv: Implement kvm_arch_get_registers
  target/riscv: Implement kvm_arch_put_registers
  target/riscv: Support start kernel directly by KVM
  hw/riscv: PLIC update external interrupt by KVM when kvm enabled
  target/riscv: Handler KVM_EXIT_RISCV_SBI exit
  target/riscv: add host riscv64 cpu type

 configure                  |   1 +
 hw/riscv/sifive_plic.c     |  31 ++-
 hw/riscv/virt.c            |  15 +-
 linux-headers/linux/kvm.h  |   8 +
 target/riscv/Makefile.objs |   1 +
 target/riscv/cpu.c         |   9 +
 target/riscv/cpu.h         |   4 +
 target/riscv/kvm.c         | 513 +++++++++++++++++++++++++++++++++++++
 target/riscv/kvm_riscv.h   |  25 ++
 9 files changed, 596 insertions(+), 11 deletions(-)
 create mode 100644 target/riscv/kvm.c
 create mode 100644 target/riscv/kvm_riscv.h

-- 
2.19.1




^ permalink raw reply	[flat|nested] 36+ messages in thread
* [PATCH RFC 1/9] linux-header: Update linux/kvm.h
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Update linux/kvm.h to commit b9a6e4cd9 on https://github.com/kvm-riscv/linux.
Only use this header file, so do not update all linux headers.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 linux-headers/linux/kvm.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 265099100e..7cfc111af5 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -236,6 +236,7 @@ struct kvm_hyperv_exit {
 #define KVM_EXIT_IOAPIC_EOI       26
 #define KVM_EXIT_HYPERV           27
 #define KVM_EXIT_ARM_NISV         28
+#define KVM_EXIT_RISCV_SBI        28
 
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
@@ -400,6 +401,13 @@ struct kvm_run {
 			__u64 esr_iss;
 			__u64 fault_ipa;
 		} arm_nisv;
+		/* KVM_EXIT_RISCV_SBI */
+		struct {
+			unsigned long extension_id;
+			unsigned long function_id;
+			unsigned long args[6];
+			unsigned long ret[2];
+		} riscv_sbi;
 		/* Fix the size of the union. */
 		char padding[256];
 	};
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 1/9] linux-header: Update linux/kvm.h
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Update linux/kvm.h to commit b9a6e4cd9 on https://github.com/kvm-riscv/linux.
Only use this header file, so do not update all linux headers.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 linux-headers/linux/kvm.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 265099100e..7cfc111af5 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -236,6 +236,7 @@ struct kvm_hyperv_exit {
 #define KVM_EXIT_IOAPIC_EOI       26
 #define KVM_EXIT_HYPERV           27
 #define KVM_EXIT_ARM_NISV         28
+#define KVM_EXIT_RISCV_SBI        28
 
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
@@ -400,6 +401,13 @@ struct kvm_run {
 			__u64 esr_iss;
 			__u64 fault_ipa;
 		} arm_nisv;
+		/* KVM_EXIT_RISCV_SBI */
+		struct {
+			unsigned long extension_id;
+			unsigned long function_id;
+			unsigned long args[6];
+			unsigned long ret[2];
+		} riscv_sbi;
 		/* Fix the size of the union. */
 		char padding[256];
 	};
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c.
Meanwhile, add riscv64 kvm support to configure.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 configure                  |   1 +
 target/riscv/Makefile.objs |   1 +
 target/riscv/kvm.c         | 128 +++++++++++++++++++++++++++++++++++++
 3 files changed, 130 insertions(+)
 create mode 100644 target/riscv/kvm.c

diff --git a/configure b/configure
index 3c7470096f..30024a8aef 100755
--- a/configure
+++ b/configure
@@ -200,6 +200,7 @@ supported_kvm_target() {
         x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \
         mips:mips | mipsel:mips | \
         ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \
+        riscv64:riscv64 | \
         s390x:s390x)
             return 0
         ;;
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index ff651f69f6..7ea8f4c3da 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1,5 +1,6 @@
 obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o
 obj-$(CONFIG_SOFTMMU) += pmp.o
+obj-$(CONFIG_KVM) += kvm.o
 
 ifeq ($(CONFIG_SOFTMMU),y)
 obj-y += monitor.o
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index 0000000000..8c386d9acf
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -0,0 +1,128 @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+    KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+    return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+    return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+                             uint64_t address, uint32_t data, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+    return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+    abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+                                int vector, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+    return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+    return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+    return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+    return 0;
+}
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c.
Meanwhile, add riscv64 kvm support to configure.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 configure                  |   1 +
 target/riscv/Makefile.objs |   1 +
 target/riscv/kvm.c         | 128 +++++++++++++++++++++++++++++++++++++
 3 files changed, 130 insertions(+)
 create mode 100644 target/riscv/kvm.c

diff --git a/configure b/configure
index 3c7470096f..30024a8aef 100755
--- a/configure
+++ b/configure
@@ -200,6 +200,7 @@ supported_kvm_target() {
         x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \
         mips:mips | mipsel:mips | \
         ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \
+        riscv64:riscv64 | \
         s390x:s390x)
             return 0
         ;;
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index ff651f69f6..7ea8f4c3da 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1,5 +1,6 @@
 obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o
 obj-$(CONFIG_SOFTMMU) += pmp.o
+obj-$(CONFIG_KVM) += kvm.o
 
 ifeq ($(CONFIG_SOFTMMU),y)
 obj-y += monitor.o
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index 0000000000..8c386d9acf
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -0,0 +1,128 @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+    KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+    return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+    return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+                             uint64_t address, uint32_t data, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+    return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+    abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+                                int vector, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+    return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+    return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+    return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+    return 0;
+}
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 3/9] target/riscv: Implement function kvm_arch_init_vcpu
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Get isa info from kvm while kvm init.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 8c386d9acf..3e8f8e7185 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,18 @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 
+static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
+{
+    __u64 id = KVM_REG_RISCV | type | idx;
+
+#if defined(TARGET_RISCV32)
+    id |= KVM_REG_SIZE_U32;
+#elif defined(TARGET_RISCV64)
+    id |= KVM_REG_SIZE_U64;
+#endif
+    return id;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -79,7 +91,19 @@ void kvm_arch_init_irq_routing(KVMState *s)
 
 int kvm_arch_init_vcpu(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+    uint64_t isa;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    __u64 id;
+
+    id = kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
+    ret = kvm_get_one_reg(cs, id, &isa);
+    if (ret) {
+        return ret;
+    }
+    cpu->env.misa = isa;
+
+    return ret;
 }
 
 int kvm_arch_msi_data_to_gsi(uint32_t data)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 3/9] target/riscv: Implement function kvm_arch_init_vcpu
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Get isa info from kvm while kvm init.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 8c386d9acf..3e8f8e7185 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,18 @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 
+static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
+{
+    __u64 id = KVM_REG_RISCV | type | idx;
+
+#if defined(TARGET_RISCV32)
+    id |= KVM_REG_SIZE_U32;
+#elif defined(TARGET_RISCV64)
+    id |= KVM_REG_SIZE_U64;
+#endif
+    return id;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -79,7 +91,19 @@ void kvm_arch_init_irq_routing(KVMState *s)
 
 int kvm_arch_init_vcpu(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+    uint64_t isa;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    __u64 id;
+
+    id = kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
+    ret = kvm_get_one_reg(cs, id, &isa);
+    if (ret) {
+        return ret;
+    }
+    cpu->env.misa = isa;
+
+    return ret;
 }
 
 int kvm_arch_msi_data_to_gsi(uint32_t data)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 4/9] target/riscv: Implement kvm_arch_get_registers
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 144 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 143 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 3e8f8e7185..8d5069b9e9 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -50,13 +50,155 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
     return id;
 }
 
+#define RISCV_CORE_REG(name)  kvm_riscv_reg_id(KVM_REG_RISCV_CORE, \
+                 KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(name)  kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \
+                 KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->pc = reg;
+
+    for (i = 1; i < 32; i++) {
+        __u64 id = kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i);
+        ret = kvm_get_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+        env->gpr[i] = reg;
+    }
+
+    return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->mstatus = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sie), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->mie = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(stvec), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->stvec = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sscratch), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->sscratch = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sepc), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->sepc = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(scause), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->scause = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sip), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->mip = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->satp = reg;
+
+    return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
 
 int kvm_arch_get_registers(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_get_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_put_registers(CPUState *cs, int level)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 4/9] target/riscv: Implement kvm_arch_get_registers
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 144 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 143 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 3e8f8e7185..8d5069b9e9 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -50,13 +50,155 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
     return id;
 }
 
+#define RISCV_CORE_REG(name)  kvm_riscv_reg_id(KVM_REG_RISCV_CORE, \
+                 KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(name)  kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \
+                 KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->pc = reg;
+
+    for (i = 1; i < 32; i++) {
+        __u64 id = kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i);
+        ret = kvm_get_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+        env->gpr[i] = reg;
+    }
+
+    return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->mstatus = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sie), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->mie = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(stvec), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->stvec = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sscratch), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->sscratch = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sepc), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->sepc = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(scause), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->scause = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sip), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->mip = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->satp = reg;
+
+    return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+            env->fpr[i] = reg;
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
 
 int kvm_arch_get_registers(CPUState *cs)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_get_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_get_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_put_registers(CPUState *cs, int level)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 5/9] target/riscv: Implement kvm_arch_put_registers
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Put GPR CSR and FP registers by kvm by KVM_SET_ONE_REG ioctl

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 136 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 135 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 8d5069b9e9..6dffda36bb 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    reg = env->pc;
+    ret = kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    for (i = 1; i < 32; i++) {
+        __u64 id = kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i);
+        reg = env->gpr[i];
+        ret = kvm_set_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    return ret;
+}
+
 static int kvm_riscv_get_regs_csr(CPUState *cs)
 {
     int ret = 0;
@@ -142,6 +167,64 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    reg = env->mstatus;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->mie;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sie), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->stvec;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(stvec), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->sscratch;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sscratch), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->sepc;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sepc), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->scause;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(scause), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->mip;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sip), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->satp;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
+}
+
+
 static int kvm_riscv_get_regs_fp(CPUState *cs)
 {
     int ret = 0;
@@ -175,6 +258,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -203,7 +320,24 @@ int kvm_arch_get_registers(CPUState *cs)
 
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_put_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_release_virq_post(int virq)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 5/9] target/riscv: Implement kvm_arch_put_registers
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Put GPR CSR and FP registers by kvm by KVM_SET_ONE_REG ioctl

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 136 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 135 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 8d5069b9e9..6dffda36bb 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_core(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    reg = env->pc;
+    ret = kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    for (i = 1; i < 32; i++) {
+        __u64 id = kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i);
+        reg = env->gpr[i];
+        ret = kvm_set_one_reg(cs, id, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    return ret;
+}
+
 static int kvm_riscv_get_regs_csr(CPUState *cs)
 {
     int ret = 0;
@@ -142,6 +167,64 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_csr(CPUState *cs)
+{
+    int ret = 0;
+    uint64_t reg;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    reg = env->mstatus;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->mie;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sie), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->stvec;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(stvec), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->sscratch;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sscratch), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->sepc;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sepc), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->scause;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(scause), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->mip;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sip), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->satp;
+    ret = kvm_set_one_reg(cs, RISCV_CSR_REG(sstatus), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
+}
+
+
 static int kvm_riscv_get_regs_fp(CPUState *cs)
 {
     int ret = 0;
@@ -175,6 +258,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
     return ret;
 }
 
+static int kvm_riscv_put_regs_fp(CPUState *cs)
+{
+    int ret = 0;
+    int i;
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+    if (riscv_has_ext(env, RVD)) {
+        uint64_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    if (riscv_has_ext(env, RVF)) {
+        uint32_t reg;
+        for (i = 0; i < 32; i++) {
+            reg = env->fpr[i];
+            ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), &reg);
+            if (ret) {
+                return ret;
+            }
+        }
+        return ret;
+    }
+
+    return ret;
+}
+
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -203,7 +320,24 @@ int kvm_arch_get_registers(CPUState *cs)
 
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
-    return 0;
+    int ret = 0;
+
+    ret = kvm_riscv_put_regs_core(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_csr(cs);
+    if (ret) {
+        return ret;
+    }
+
+    ret = kvm_riscv_put_regs_fp(cs);
+    if (ret) {
+        return ret;
+    }
+
+    return ret;
 }
 
 int kvm_arch_release_virq_post(int virq)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 6/9] target/riscv: Support start kernel directly by KVM
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset.In addition,add kvm_riscv.h to place riscv specific
interface.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 hw/riscv/virt.c          | 15 +++++++++++++--
 target/riscv/cpu.c       |  4 ++++
 target/riscv/cpu.h       |  3 +++
 target/riscv/kvm.c       | 14 ++++++++++++++
 target/riscv/kvm_riscv.h | 24 ++++++++++++++++++++++++
 5 files changed, 58 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/kvm_riscv.h

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 85ec9e22aa..e42c61208d 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -42,6 +42,7 @@
 #include "exec/address-spaces.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "sysemu/kvm.h"
 
 #include <libfdt.h>
 
@@ -480,6 +481,9 @@ static void riscv_virt_board_init(MachineState *machine)
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     int i;
     unsigned int smp_cpus = machine->smp.cpus;
+    uint64_t kernel_entry = 0;
+    hwaddr start_fdt;
+    CPUState *cs;
 
     /* Initialize SOC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
@@ -510,7 +514,7 @@ static void riscv_virt_board_init(MachineState *machine)
                                  memmap[VIRT_DRAM].base);
 
     if (machine->kernel_filename) {
-        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                                   NULL);
 
         if (machine->initrd_filename) {
@@ -564,10 +568,17 @@ static void riscv_virt_board_init(MachineState *machine)
         exit(1);
     }
     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
+    start_fdt = memmap[VIRT_MROM].base + sizeof(reset_vec);
     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
-                          memmap[VIRT_MROM].base + sizeof(reset_vec),
+                          start_fdt,
                           &address_space_memory);
 
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        RISCVCPU *riscv_cpu = RISCV_CPU(cs);
+        riscv_cpu->env.loader_start = kernel_entry;
+        riscv_cpu->env.fdt_start = start_fdt;
+    }
+
     /* create PLIC hart topology configuration string */
     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
     plic_hart_config = g_malloc0(plic_hart_config_len);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c0b7023100..3c3264869f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -28,6 +28,7 @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "fpu/softfloat-helpers.h"
+#include "kvm_riscv.h"
 
 /* RISC-V CPU definitions */
 
@@ -346,6 +347,9 @@ static void riscv_cpu_reset(CPUState *cs)
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+#ifdef CONFIG_KVM
+    kvm_riscv_reset_vcpu(cpu);
+#endif
 }
 
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dcdf92227..2724eca714 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -213,6 +213,9 @@ struct CPURISCVState {
 
     /* Fields from here on are preserved across CPU reset. */
     QEMUTimer *timer; /* Internal timer */
+
+    hwaddr loader_start;
+    hwaddr fdt_start;
 };
 
 #define RISCV_CPU_CLASS(klass) \
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 6dffda36bb..b9aec66b69 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -37,6 +37,7 @@
 #include "hw/irq.h"
 #include "qemu/log.h"
 #include "hw/loader.h"
+#include "kvm_riscv.h"
 
 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
 {
@@ -426,3 +427,16 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     return 0;
 }
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+    CPURISCVState *env = &cpu->env;
+
+    if (!kvm_enabled()) {
+        return;
+    }
+    env->pc = cpu->env.loader_start;
+    env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
+    env->gpr[11] = cpu->env.fdt_start;         /* a1 */
+}
+
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
new file mode 100644
index 0000000000..f38c82bf59
--- /dev/null
+++ b/target/riscv/kvm_riscv.h
@@ -0,0 +1,24 @@
+/*
+ * QEMU KVM support -- RISC-V specific functions.
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_KVM_RISCV_H
+#define QEMU_KVM_RISCV_H
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+
+#endif
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 6/9] target/riscv: Support start kernel directly by KVM
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset.In addition,add kvm_riscv.h to place riscv specific
interface.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 hw/riscv/virt.c          | 15 +++++++++++++--
 target/riscv/cpu.c       |  4 ++++
 target/riscv/cpu.h       |  3 +++
 target/riscv/kvm.c       | 14 ++++++++++++++
 target/riscv/kvm_riscv.h | 24 ++++++++++++++++++++++++
 5 files changed, 58 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/kvm_riscv.h

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 85ec9e22aa..e42c61208d 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -42,6 +42,7 @@
 #include "exec/address-spaces.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "sysemu/kvm.h"
 
 #include <libfdt.h>
 
@@ -480,6 +481,9 @@ static void riscv_virt_board_init(MachineState *machine)
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     int i;
     unsigned int smp_cpus = machine->smp.cpus;
+    uint64_t kernel_entry = 0;
+    hwaddr start_fdt;
+    CPUState *cs;
 
     /* Initialize SOC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
@@ -510,7 +514,7 @@ static void riscv_virt_board_init(MachineState *machine)
                                  memmap[VIRT_DRAM].base);
 
     if (machine->kernel_filename) {
-        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                                   NULL);
 
         if (machine->initrd_filename) {
@@ -564,10 +568,17 @@ static void riscv_virt_board_init(MachineState *machine)
         exit(1);
     }
     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
+    start_fdt = memmap[VIRT_MROM].base + sizeof(reset_vec);
     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
-                          memmap[VIRT_MROM].base + sizeof(reset_vec),
+                          start_fdt,
                           &address_space_memory);
 
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        RISCVCPU *riscv_cpu = RISCV_CPU(cs);
+        riscv_cpu->env.loader_start = kernel_entry;
+        riscv_cpu->env.fdt_start = start_fdt;
+    }
+
     /* create PLIC hart topology configuration string */
     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
     plic_hart_config = g_malloc0(plic_hart_config_len);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c0b7023100..3c3264869f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -28,6 +28,7 @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "fpu/softfloat-helpers.h"
+#include "kvm_riscv.h"
 
 /* RISC-V CPU definitions */
 
@@ -346,6 +347,9 @@ static void riscv_cpu_reset(CPUState *cs)
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+#ifdef CONFIG_KVM
+    kvm_riscv_reset_vcpu(cpu);
+#endif
 }
 
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dcdf92227..2724eca714 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -213,6 +213,9 @@ struct CPURISCVState {
 
     /* Fields from here on are preserved across CPU reset. */
     QEMUTimer *timer; /* Internal timer */
+
+    hwaddr loader_start;
+    hwaddr fdt_start;
 };
 
 #define RISCV_CPU_CLASS(klass) \
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 6dffda36bb..b9aec66b69 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -37,6 +37,7 @@
 #include "hw/irq.h"
 #include "qemu/log.h"
 #include "hw/loader.h"
+#include "kvm_riscv.h"
 
 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
 {
@@ -426,3 +427,16 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     return 0;
 }
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+    CPURISCVState *env = &cpu->env;
+
+    if (!kvm_enabled()) {
+        return;
+    }
+    env->pc = cpu->env.loader_start;
+    env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
+    env->gpr[11] = cpu->env.fdt_start;         /* a1 */
+}
+
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
new file mode 100644
index 0000000000..f38c82bf59
--- /dev/null
+++ b/target/riscv/kvm_riscv.h
@@ -0,0 +1,24 @@
+/*
+ * QEMU KVM support -- RISC-V specific functions.
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_KVM_RISCV_H
+#define QEMU_KVM_RISCV_H
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+
+#endif
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Only support supervisor external interrupt currently.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 hw/riscv/sifive_plic.c   | 31 ++++++++++++++++++++++---------
 target/riscv/kvm.c       | 19 +++++++++++++++++++
 target/riscv/kvm_riscv.h |  1 +
 3 files changed, 42 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index c1e04cbb98..ff5c18ed20 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -29,6 +29,8 @@
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
 #include "hw/riscv/sifive_plic.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
 
 #define RISCV_DEBUG_PLIC 0
 
@@ -145,15 +147,26 @@ static void sifive_plic_update(SiFivePLICState *plic)
             continue;
         }
         int level = sifive_plic_irqs_pending(plic, addrid);
-        switch (mode) {
-        case PLICMode_M:
-            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
-            break;
-        case PLICMode_S:
-            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
-            break;
-        default:
-            break;
+        if (kvm_enabled()) {
+            if (mode == PLICMode_M) {
+                continue;
+            }
+#ifdef CONFIG_KVM
+            kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
+#endif
+        } else {
+            switch (mode) {
+            case PLICMode_M:
+                riscv_cpu_update_mip(RISCV_CPU(cpu),
+                                     MIP_MEIP, BOOL_TO_MASK(level));
+                break;
+            case PLICMode_S:
+                riscv_cpu_update_mip(RISCV_CPU(cpu),
+                                     MIP_SEIP, BOOL_TO_MASK(level));
+                break;
+            default:
+                break;
+            }
         }
     }
 
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index b9aec66b69..0f429fd802 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -440,3 +440,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
     env->gpr[11] = cpu->env.fdt_start;         /* a1 */
 }
 
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+    int ret;
+    unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+    if (irq != IRQ_S_EXT) {
+        return;
+    }
+
+    if (!kvm_enabled()) {
+        return;
+    }
+
+    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+    if (ret < 0) {
+        perror("Set irq failed");
+        abort();
+    }
+}
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index f38c82bf59..ed281bdce0 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -20,5 +20,6 @@
 #define QEMU_KVM_RISCV_H
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 
 #endif
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Only support supervisor external interrupt currently.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 hw/riscv/sifive_plic.c   | 31 ++++++++++++++++++++++---------
 target/riscv/kvm.c       | 19 +++++++++++++++++++
 target/riscv/kvm_riscv.h |  1 +
 3 files changed, 42 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index c1e04cbb98..ff5c18ed20 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -29,6 +29,8 @@
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
 #include "hw/riscv/sifive_plic.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
 
 #define RISCV_DEBUG_PLIC 0
 
@@ -145,15 +147,26 @@ static void sifive_plic_update(SiFivePLICState *plic)
             continue;
         }
         int level = sifive_plic_irqs_pending(plic, addrid);
-        switch (mode) {
-        case PLICMode_M:
-            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
-            break;
-        case PLICMode_S:
-            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
-            break;
-        default:
-            break;
+        if (kvm_enabled()) {
+            if (mode == PLICMode_M) {
+                continue;
+            }
+#ifdef CONFIG_KVM
+            kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
+#endif
+        } else {
+            switch (mode) {
+            case PLICMode_M:
+                riscv_cpu_update_mip(RISCV_CPU(cpu),
+                                     MIP_MEIP, BOOL_TO_MASK(level));
+                break;
+            case PLICMode_S:
+                riscv_cpu_update_mip(RISCV_CPU(cpu),
+                                     MIP_SEIP, BOOL_TO_MASK(level));
+                break;
+            default:
+                break;
+            }
         }
     }
 
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index b9aec66b69..0f429fd802 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -440,3 +440,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
     env->gpr[11] = cpu->env.fdt_start;         /* a1 */
 }
 
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+    int ret;
+    unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+    if (irq != IRQ_S_EXT) {
+        return;
+    }
+
+    if (!kvm_enabled()) {
+        return;
+    }
+
+    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+    if (ret < 0) {
+        perror("Set irq failed");
+        abort();
+    }
+}
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index f38c82bf59..ed281bdce0 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -20,5 +20,6 @@
 #define QEMU_KVM_RISCV_H
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 
 #endif
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Use char-fe handler console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 54 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0f429fd802..1df70fbb29 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,7 @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 #include "kvm_riscv.h"
+#include "chardev/char-fe.h"
 
 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
 {
@@ -61,6 +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
 
 #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
 
+enum sbi_ext_id {
+    SBI_EXT_0_1_SET_TIMER = 0x0,
+    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
+    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
+    SBI_EXT_0_1_CLEAR_IPI = 0x3,
+    SBI_EXT_0_1_SEND_IPI = 0x4,
+    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
+    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
+    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
+    SBI_EXT_0_1_SHUTDOWN = 0x8,
+    SBI_EXT_BASE = 0x10,
+};
+
 static int kvm_riscv_get_regs_core(CPUState *cs)
 {
     int ret = 0;
@@ -423,9 +437,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static int kvm_riscv_handle_sbi(struct kvm_run *run)
+{
+    int ret = 0;
+    unsigned char ch;
+    switch (run->riscv_sbi.extension_id) {
+    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
+        ch = run->riscv_sbi.args[0];
+        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+        break;
+    case SBI_EXT_0_1_CONSOLE_GETCHAR:
+        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
+        if (ret == sizeof(ch)) {
+            run->riscv_sbi.args[0] = ch;
+        } else {
+            run->riscv_sbi.args[0] = -1;
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
+                      __func__, run->riscv_sbi.extension_id);
+        ret = -1;
+        break;
+    }
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
-    return 0;
+    int ret = 0;
+    switch (run->exit_reason) {
+    case KVM_EXIT_RISCV_SBI:
+        ret = kvm_riscv_handle_sbi(run);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+                      __func__, run->exit_reason);
+        ret = -1;
+        break;
+    }
+    return ret;
 }
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Use char-fe handler console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/kvm.c | 54 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0f429fd802..1df70fbb29 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,7 @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 #include "kvm_riscv.h"
+#include "chardev/char-fe.h"
 
 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
 {
@@ -61,6 +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
 
 #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
 
+enum sbi_ext_id {
+    SBI_EXT_0_1_SET_TIMER = 0x0,
+    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
+    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
+    SBI_EXT_0_1_CLEAR_IPI = 0x3,
+    SBI_EXT_0_1_SEND_IPI = 0x4,
+    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
+    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
+    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
+    SBI_EXT_0_1_SHUTDOWN = 0x8,
+    SBI_EXT_BASE = 0x10,
+};
+
 static int kvm_riscv_get_regs_core(CPUState *cs)
 {
     int ret = 0;
@@ -423,9 +437,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static int kvm_riscv_handle_sbi(struct kvm_run *run)
+{
+    int ret = 0;
+    unsigned char ch;
+    switch (run->riscv_sbi.extension_id) {
+    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
+        ch = run->riscv_sbi.args[0];
+        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+        break;
+    case SBI_EXT_0_1_CONSOLE_GETCHAR:
+        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
+        if (ret == sizeof(ch)) {
+            run->riscv_sbi.args[0] = ch;
+        } else {
+            run->riscv_sbi.args[0] = -1;
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
+                      __func__, run->riscv_sbi.extension_id);
+        ret = -1;
+        break;
+    }
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
-    return 0;
+    int ret = 0;
+    switch (run->exit_reason) {
+    case KVM_EXIT_RISCV_SBI:
+        ret = kvm_riscv_handle_sbi(run);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+                      __func__, run->exit_reason);
+        ret = -1;
+        break;
+    }
+    return ret;
 }
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 9/9] target/riscv: add host riscv64 cpu type
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  3:49   ` Yifei Jiang
  -1 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, zhang.zhanghailiang, sagark, kbastian,
	victor.zhangxiaofeng, Alistair.Francis, yinyipeng1, palmer,
	Yifei Jiang, dengkai1

Currently, host cpu is inherited simply.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/cpu.c | 5 +++++
 target/riscv/cpu.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3c3264869f..11557719cf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -203,6 +203,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
     set_feature(env, RISCV_FEATURE_PMP);
 }
 
+static void riscv_host_cpu_init(Object *obj)
+{
+}
+
 #endif
 
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -622,6 +626,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
     /* Deprecated */
     DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2724eca714..10b053a467 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -39,6 +39,7 @@
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 /* Deprecated */
 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH RFC 9/9] target/riscv: add host riscv64 cpu type
@ 2020-03-13  3:49   ` Yifei Jiang
  0 siblings, 0 replies; 36+ messages in thread
From: Yifei Jiang @ 2020-03-13  3:49 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: anup.patel, palmer, Alistair.Francis, sagark, kbastian,
	victor.zhangxiaofeng, zhang.zhanghailiang, dengkai1, yinyipeng1,
	Yifei Jiang

Currently, host cpu is inherited simply.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/cpu.c | 5 +++++
 target/riscv/cpu.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3c3264869f..11557719cf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -203,6 +203,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
     set_feature(env, RISCV_FEATURE_PMP);
 }
 
+static void riscv_host_cpu_init(Object *obj)
+{
+}
+
 #endif
 
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -622,6 +626,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
     /* Deprecated */
     DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2724eca714..10b053a467 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -39,6 +39,7 @@
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 /* Deprecated */
 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-- 
2.19.1




^ permalink raw reply related	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 0/9] Add riscv64 kvm accel support
  2020-03-13  3:49 ` Yifei Jiang
@ 2020-03-13  5:59   ` Anup Patel
  -1 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-13  5:59 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: victor.zhangxiaofeng, open list:RISC-V, zhang.zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Anup Patel,
	QEMU Developers, Alistair Francis, yinyipeng1, Palmer Dabbelt,
	dengkai1

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Hi,
>
> This series adds riscv64 kvm support, It is based on riscv_kvm_master
> branch at https://github.com/kvm-riscv/linux.
>
> This series depends on above pending changes which haven't yet been
> accepted, so this QEMU patch series is blocked until that dependency
> has been dealt with, but is worth reviewing anyway.
>
> Several steps to use this:
>
> 1. Build riscv64 emulation
> $ ./configure --target-list=riscv64-softmmu
> $ make -j$(nproc)
>
> 2. Build kernel
> riscv_kvm_master branch at https://github.com/kvm-riscv/linux
>
> 3. Build QEMU VM
> I cross build in riscv toolchain
> $ PKG_CONFIG_LIBDIR=<toolchain pkgconfig path>
> $ export PKG_CONFIG_SYSROOT_DIR=<toolchain sysroot path>
> $ ./configure --target-list=riscv64-softmmu --enable-kvm \
> --cross-prefix=riscv64-linux-gnu- --disable-libiscsi --disable-glusterfs \
> --disable-libusb --disable-usb-redir --audio-drv-list= --disable-opengl \
> --disable-libxml2
>
> 4. Start riscv64 emulation
> $ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
>         -name guest=riscv-hyp,debug-threads=on \
>         -smp 4 \
>         -kernel ./fw_jump.elf \
>         -device loader,file=./Image,addr=0x80200000 \
>         -drive file=./hyp.img,format=raw,id=hd0 \
>         -device virtio-blk-device,drive=hd0 \
>         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> 5. Start kvm-acceled QEMU VM in riscv64 emulation
> $ ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
>         -name guest=riscv-guset \
>          -smp 2 \
>         -kernel ./Image \
>         -drive file=./guest.img,format=raw,id=hd0 \
>         -device virtio-blk-device,drive=hd0 \
>         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> Yifei Jiang (9):
>   linux-header: Update linux/kvm.h
>   target/riscv: Add target/riscv/kvm.c to place the public kvm interface
>   target/riscv: Implement function kvm_arch_init_vcpu
>   target/riscv: Implement kvm_arch_get_registers
>   target/riscv: Implement kvm_arch_put_registers
>   target/riscv: Support start kernel directly by KVM
>   hw/riscv: PLIC update external interrupt by KVM when kvm enabled
>   target/riscv: Handler KVM_EXIT_RISCV_SBI exit
>   target/riscv: add host riscv64 cpu type
>
>  configure                  |   1 +
>  hw/riscv/sifive_plic.c     |  31 ++-
>  hw/riscv/virt.c            |  15 +-
>  linux-headers/linux/kvm.h  |   8 +
>  target/riscv/Makefile.objs |   1 +
>  target/riscv/cpu.c         |   9 +
>  target/riscv/cpu.h         |   4 +
>  target/riscv/kvm.c         | 513 +++++++++++++++++++++++++++++++++++++
>  target/riscv/kvm_riscv.h   |  25 ++
>  9 files changed, 596 insertions(+), 11 deletions(-)
>  create mode 100644 target/riscv/kvm.c
>  create mode 100644 target/riscv/kvm_riscv.h
>
> --
> 2.19.1
>
>
>

First of all many thanks for doing QEMU KVM support. It wasted
bit of my time because I was already doing it but I am happy to
see the patches on list sooner.

In future, please CC the KVM RISC-V mailing list for all QEMU KVM
RISC-V work. The KVM RISC-V mailing list for related projects
(QEMU, KVMTOOL, libvirt, etc) and not just Linux KVM RISC-V.

Currently, we can only review this patch series and get it in final
shape but it can only be merged in QEMU after Linux KVM RISC-V
patches are merged in Linux kernel.

I will be sending out KVM RISC-V v11 series today. There is
a crucial bug fix related to HIDELEG CSR programing. This
bug fix is required in both QEMU and KVM RISC-V. Palmer has
already accepted QEMU HIDELEG CSR fix. The KVM RISC-V
v11 series will have this fix as well.

Thanks & Regards,
Anup Patel


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 0/9] Add riscv64 kvm accel support
@ 2020-03-13  5:59   ` Anup Patel
  0 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-13  5:59 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: QEMU Developers, open list:RISC-V, Anup Patel,
	zhang.zhanghailiang, Sagar Karandikar, Bastian Koppelmann,
	victor.zhangxiaofeng, Alistair Francis, yinyipeng1,
	Palmer Dabbelt, dengkai1

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Hi,
>
> This series adds riscv64 kvm support, It is based on riscv_kvm_master
> branch at https://github.com/kvm-riscv/linux.
>
> This series depends on above pending changes which haven't yet been
> accepted, so this QEMU patch series is blocked until that dependency
> has been dealt with, but is worth reviewing anyway.
>
> Several steps to use this:
>
> 1. Build riscv64 emulation
> $ ./configure --target-list=riscv64-softmmu
> $ make -j$(nproc)
>
> 2. Build kernel
> riscv_kvm_master branch at https://github.com/kvm-riscv/linux
>
> 3. Build QEMU VM
> I cross build in riscv toolchain
> $ PKG_CONFIG_LIBDIR=<toolchain pkgconfig path>
> $ export PKG_CONFIG_SYSROOT_DIR=<toolchain sysroot path>
> $ ./configure --target-list=riscv64-softmmu --enable-kvm \
> --cross-prefix=riscv64-linux-gnu- --disable-libiscsi --disable-glusterfs \
> --disable-libusb --disable-usb-redir --audio-drv-list= --disable-opengl \
> --disable-libxml2
>
> 4. Start riscv64 emulation
> $ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
>         -name guest=riscv-hyp,debug-threads=on \
>         -smp 4 \
>         -kernel ./fw_jump.elf \
>         -device loader,file=./Image,addr=0x80200000 \
>         -drive file=./hyp.img,format=raw,id=hd0 \
>         -device virtio-blk-device,drive=hd0 \
>         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> 5. Start kvm-acceled QEMU VM in riscv64 emulation
> $ ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
>         -name guest=riscv-guset \
>          -smp 2 \
>         -kernel ./Image \
>         -drive file=./guest.img,format=raw,id=hd0 \
>         -device virtio-blk-device,drive=hd0 \
>         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> Yifei Jiang (9):
>   linux-header: Update linux/kvm.h
>   target/riscv: Add target/riscv/kvm.c to place the public kvm interface
>   target/riscv: Implement function kvm_arch_init_vcpu
>   target/riscv: Implement kvm_arch_get_registers
>   target/riscv: Implement kvm_arch_put_registers
>   target/riscv: Support start kernel directly by KVM
>   hw/riscv: PLIC update external interrupt by KVM when kvm enabled
>   target/riscv: Handler KVM_EXIT_RISCV_SBI exit
>   target/riscv: add host riscv64 cpu type
>
>  configure                  |   1 +
>  hw/riscv/sifive_plic.c     |  31 ++-
>  hw/riscv/virt.c            |  15 +-
>  linux-headers/linux/kvm.h  |   8 +
>  target/riscv/Makefile.objs |   1 +
>  target/riscv/cpu.c         |   9 +
>  target/riscv/cpu.h         |   4 +
>  target/riscv/kvm.c         | 513 +++++++++++++++++++++++++++++++++++++
>  target/riscv/kvm_riscv.h   |  25 ++
>  9 files changed, 596 insertions(+), 11 deletions(-)
>  create mode 100644 target/riscv/kvm.c
>  create mode 100644 target/riscv/kvm_riscv.h
>
> --
> 2.19.1
>
>
>

First of all many thanks for doing QEMU KVM support. It wasted
bit of my time because I was already doing it but I am happy to
see the patches on list sooner.

In future, please CC the KVM RISC-V mailing list for all QEMU KVM
RISC-V work. The KVM RISC-V mailing list for related projects
(QEMU, KVMTOOL, libvirt, etc) and not just Linux KVM RISC-V.

Currently, we can only review this patch series and get it in final
shape but it can only be merged in QEMU after Linux KVM RISC-V
patches are merged in Linux kernel.

I will be sending out KVM RISC-V v11 series today. There is
a crucial bug fix related to HIDELEG CSR programing. This
bug fix is required in both QEMU and KVM RISC-V. Palmer has
already accepted QEMU HIDELEG CSR fix. The KVM RISC-V
v11 series will have this fix as well.

Thanks & Regards,
Anup Patel


^ permalink raw reply	[flat|nested] 36+ messages in thread
* RE: [PATCH RFC 0/9] Add riscv64 kvm accel support
  2020-03-13  5:59   ` Anup Patel
@ 2020-03-13  7:02     ` Jiangyifei
  -1 siblings, 0 replies; 36+ messages in thread
From: Jiangyifei @ 2020-03-13  7:02 UTC (permalink / raw)
  To: Anup Patel
  Cc: Zhangxiaofeng (F),
	open list:RISC-V, Zhanghailiang, Sagar Karandikar,
	Bastian Koppelmann, Anup Patel, QEMU Developers,
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)


> -----Original Message-----
> From: Anup Patel [mailto:anup@brainfault.org]
> Sent: Friday, March 13, 2020 2:00 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V <qemu-
> riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>; Zhanghailiang
> <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-
> paderborn.de>; Zhangxiaofeng (F) <victor.zhangxiaofeng@huawei.com>;
> Alistair Francis <Alistair.Francis@wdc.com>; yinyipeng
> <yinyipeng1@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH RFC 0/9] Add riscv64 kvm accel support
> 
> On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Hi,
> >
> > This series adds riscv64 kvm support, It is based on riscv_kvm_master
> > branch at https://github.com/kvm-riscv/linux.
> >
> > This series depends on above pending changes which haven't yet been
> > accepted, so this QEMU patch series is blocked until that dependency
> > has been dealt with, but is worth reviewing anyway.
> >
> > Several steps to use this:
> >
> > 1. Build riscv64 emulation
> > $ ./configure --target-list=riscv64-softmmu $ make -j$(nproc)
> >
> > 2. Build kernel
> > riscv_kvm_master branch at https://github.com/kvm-riscv/linux
> >
> > 3. Build QEMU VM
> > I cross build in riscv toolchain
> > $ PKG_CONFIG_LIBDIR=<toolchain pkgconfig path> $ export
> > PKG_CONFIG_SYSROOT_DIR=<toolchain sysroot path> $ ./configure
> > --target-list=riscv64-softmmu --enable-kvm \
> > --cross-prefix=riscv64-linux-gnu- --disable-libiscsi
> > --disable-glusterfs \ --disable-libusb --disable-usb-redir
> > --audio-drv-list= --disable-opengl \
> > --disable-libxml2
> >
> > 4. Start riscv64 emulation
> > $ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
> >         -name guest=riscv-hyp,debug-threads=on \
> >         -smp 4 \
> >         -kernel ./fw_jump.elf \
> >         -device loader,file=./Image,addr=0x80200000 \
> >         -drive file=./hyp.img,format=raw,id=hd0 \
> >         -device virtio-blk-device,drive=hd0 \
> >         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
> >
> > 5. Start kvm-acceled QEMU VM in riscv64 emulation $
> > ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
> >         -name guest=riscv-guset \
> >          -smp 2 \
> >         -kernel ./Image \
> >         -drive file=./guest.img,format=raw,id=hd0 \
> >         -device virtio-blk-device,drive=hd0 \
> >         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
> >
> > Yifei Jiang (9):
> >   linux-header: Update linux/kvm.h
> >   target/riscv: Add target/riscv/kvm.c to place the public kvm interface
> >   target/riscv: Implement function kvm_arch_init_vcpu
> >   target/riscv: Implement kvm_arch_get_registers
> >   target/riscv: Implement kvm_arch_put_registers
> >   target/riscv: Support start kernel directly by KVM
> >   hw/riscv: PLIC update external interrupt by KVM when kvm enabled
> >   target/riscv: Handler KVM_EXIT_RISCV_SBI exit
> >   target/riscv: add host riscv64 cpu type
> >
> >  configure                  |   1 +
> >  hw/riscv/sifive_plic.c     |  31 ++-
> >  hw/riscv/virt.c            |  15 +-
> >  linux-headers/linux/kvm.h  |   8 +
> >  target/riscv/Makefile.objs |   1 +
> >  target/riscv/cpu.c         |   9 +
> >  target/riscv/cpu.h         |   4 +
> >  target/riscv/kvm.c         | 513
> +++++++++++++++++++++++++++++++++++++
> >  target/riscv/kvm_riscv.h   |  25 ++
> >  9 files changed, 596 insertions(+), 11 deletions(-)  create mode
> > 100644 target/riscv/kvm.c  create mode 100644 target/riscv/kvm_riscv.h
> >
> > --
> > 2.19.1
> >
> >
> >
> 
> First of all many thanks for doing QEMU KVM support. It wasted bit of my
> time because I was already doing it but I am happy to see the patches on list
> sooner.
> 
> In future, please CC the KVM RISC-V mailing list for all QEMU KVM RISC-V
> work. The KVM RISC-V mailing list for related projects (QEMU, KVMTOOL,
> libvirt, etc) and not just Linux KVM RISC-V.
> 
> Currently, we can only review this patch series and get it in final shape but it
> can only be merged in QEMU after Linux KVM RISC-V patches are merged in
> Linux kernel.
> 
> I will be sending out KVM RISC-V v11 series today. There is a crucial bug fix
> related to HIDELEG CSR programing. This bug fix is required in both QEMU
> and KVM RISC-V. Palmer has already accepted QEMU HIDELEG CSR fix. The
> KVM RISC-V
> v11 series will have this fix as well.
> 
> Thanks & Regards,
> Anup Patel

Thank you for your quick reply and being able to review for us. We will soon be verifying based on the KVM RISC-V v11 series.

Regards,
Yifei Jiang

^ permalink raw reply	[flat|nested] 36+ messages in thread
* RE: [PATCH RFC 0/9] Add riscv64 kvm accel support
@ 2020-03-13  7:02     ` Jiangyifei
  0 siblings, 0 replies; 36+ messages in thread
From: Jiangyifei @ 2020-03-13  7:02 UTC (permalink / raw)
  To: Anup Patel
  Cc: QEMU Developers, open list:RISC-V, Anup Patel, Zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Zhangxiaofeng (F),
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)


> -----Original Message-----
> From: Anup Patel [mailto:anup@brainfault.org]
> Sent: Friday, March 13, 2020 2:00 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V <qemu-
> riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>; Zhanghailiang
> <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-
> paderborn.de>; Zhangxiaofeng (F) <victor.zhangxiaofeng@huawei.com>;
> Alistair Francis <Alistair.Francis@wdc.com>; yinyipeng
> <yinyipeng1@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH RFC 0/9] Add riscv64 kvm accel support
> 
> On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Hi,
> >
> > This series adds riscv64 kvm support, It is based on riscv_kvm_master
> > branch at https://github.com/kvm-riscv/linux.
> >
> > This series depends on above pending changes which haven't yet been
> > accepted, so this QEMU patch series is blocked until that dependency
> > has been dealt with, but is worth reviewing anyway.
> >
> > Several steps to use this:
> >
> > 1. Build riscv64 emulation
> > $ ./configure --target-list=riscv64-softmmu $ make -j$(nproc)
> >
> > 2. Build kernel
> > riscv_kvm_master branch at https://github.com/kvm-riscv/linux
> >
> > 3. Build QEMU VM
> > I cross build in riscv toolchain
> > $ PKG_CONFIG_LIBDIR=<toolchain pkgconfig path> $ export
> > PKG_CONFIG_SYSROOT_DIR=<toolchain sysroot path> $ ./configure
> > --target-list=riscv64-softmmu --enable-kvm \
> > --cross-prefix=riscv64-linux-gnu- --disable-libiscsi
> > --disable-glusterfs \ --disable-libusb --disable-usb-redir
> > --audio-drv-list= --disable-opengl \
> > --disable-libxml2
> >
> > 4. Start riscv64 emulation
> > $ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
> >         -name guest=riscv-hyp,debug-threads=on \
> >         -smp 4 \
> >         -kernel ./fw_jump.elf \
> >         -device loader,file=./Image,addr=0x80200000 \
> >         -drive file=./hyp.img,format=raw,id=hd0 \
> >         -device virtio-blk-device,drive=hd0 \
> >         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
> >
> > 5. Start kvm-acceled QEMU VM in riscv64 emulation $
> > ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \
> >         -name guest=riscv-guset \
> >          -smp 2 \
> >         -kernel ./Image \
> >         -drive file=./guest.img,format=raw,id=hd0 \
> >         -device virtio-blk-device,drive=hd0 \
> >         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
> >
> > Yifei Jiang (9):
> >   linux-header: Update linux/kvm.h
> >   target/riscv: Add target/riscv/kvm.c to place the public kvm interface
> >   target/riscv: Implement function kvm_arch_init_vcpu
> >   target/riscv: Implement kvm_arch_get_registers
> >   target/riscv: Implement kvm_arch_put_registers
> >   target/riscv: Support start kernel directly by KVM
> >   hw/riscv: PLIC update external interrupt by KVM when kvm enabled
> >   target/riscv: Handler KVM_EXIT_RISCV_SBI exit
> >   target/riscv: add host riscv64 cpu type
> >
> >  configure                  |   1 +
> >  hw/riscv/sifive_plic.c     |  31 ++-
> >  hw/riscv/virt.c            |  15 +-
> >  linux-headers/linux/kvm.h  |   8 +
> >  target/riscv/Makefile.objs |   1 +
> >  target/riscv/cpu.c         |   9 +
> >  target/riscv/cpu.h         |   4 +
> >  target/riscv/kvm.c         | 513
> +++++++++++++++++++++++++++++++++++++
> >  target/riscv/kvm_riscv.h   |  25 ++
> >  9 files changed, 596 insertions(+), 11 deletions(-)  create mode
> > 100644 target/riscv/kvm.c  create mode 100644 target/riscv/kvm_riscv.h
> >
> > --
> > 2.19.1
> >
> >
> >
> 
> First of all many thanks for doing QEMU KVM support. It wasted bit of my
> time because I was already doing it but I am happy to see the patches on list
> sooner.
> 
> In future, please CC the KVM RISC-V mailing list for all QEMU KVM RISC-V
> work. The KVM RISC-V mailing list for related projects (QEMU, KVMTOOL,
> libvirt, etc) and not just Linux KVM RISC-V.
> 
> Currently, we can only review this patch series and get it in final shape but it
> can only be merged in QEMU after Linux KVM RISC-V patches are merged in
> Linux kernel.
> 
> I will be sending out KVM RISC-V v11 series today. There is a crucial bug fix
> related to HIDELEG CSR programing. This bug fix is required in both QEMU
> and KVM RISC-V. Palmer has already accepted QEMU HIDELEG CSR fix. The
> KVM RISC-V
> v11 series will have this fix as well.
> 
> Thanks & Regards,
> Anup Patel

Thank you for your quick reply and being able to review for us. We will soon be verifying based on the KVM RISC-V v11 series.

Regards,
Yifei Jiang

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
  2020-03-13  3:49   ` Yifei Jiang
@ 2020-03-31  5:16     ` Anup Patel
  -1 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31  5:16 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: victor.zhangxiaofeng, open list:RISC-V, zhang.zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Anup Patel,
	QEMU Developers, Alistair Francis, yinyipeng1, Palmer Dabbelt,
	dengkai1

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Use char-fe handler console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  target/riscv/kvm.c | 54 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 0f429fd802..1df70fbb29 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -38,6 +38,7 @@
>  #include "qemu/log.h"
>  #include "hw/loader.h"
>  #include "kvm_riscv.h"
> +#include "chardev/char-fe.h"
>
>  static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
>  {
> @@ -61,6 +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
>
>  #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
>
> +enum sbi_ext_id {
> +    SBI_EXT_0_1_SET_TIMER = 0x0,
> +    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> +    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> +    SBI_EXT_0_1_CLEAR_IPI = 0x3,
> +    SBI_EXT_0_1_SEND_IPI = 0x4,
> +    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> +    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> +    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> +    SBI_EXT_0_1_SHUTDOWN = 0x8,
> +    SBI_EXT_BASE = 0x10,
> +};
> +

Please add separate SBI ecall interface header (similar to OpenSBI).
This header will only have SBI spec related defines.

Refer,
https://github.com/riscv/opensbi/blob/master/include/sbi/sbi_ecall_interface.h

>  static int kvm_riscv_get_regs_core(CPUState *cs)
>  {
>      int ret = 0;
> @@ -423,9 +437,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
>      return true;
>  }
>
> +static int kvm_riscv_handle_sbi(struct kvm_run *run)
> +{
> +    int ret = 0;
> +    unsigned char ch;
> +    switch (run->riscv_sbi.extension_id) {
> +    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
> +        ch = run->riscv_sbi.args[0];
> +        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
> +        break;
> +    case SBI_EXT_0_1_CONSOLE_GETCHAR:
> +        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
> +        if (ret == sizeof(ch)) {
> +            run->riscv_sbi.args[0] = ch;
> +        } else {
> +            run->riscv_sbi.args[0] = -1;
> +        }
> +        break;

Please emulate SBI v0.1 Shutdown call as well.

> +    default:
> +        qemu_log_mask(LOG_UNIMP,
> +                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
> +                      __func__, run->riscv_sbi.extension_id);
> +        ret = -1;
> +        break;
> +    }
> +    return ret;
> +}
> +
>  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
>  {
> -    return 0;
> +    int ret = 0;
> +    switch (run->exit_reason) {
> +    case KVM_EXIT_RISCV_SBI:
> +        ret = kvm_riscv_handle_sbi(run);
> +        break;
> +    default:
> +        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
> +                      __func__, run->exit_reason);
> +        ret = -1;
> +        break;
> +    }
> +    return ret;
>  }
>
>  void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> --
> 2.19.1
>
>
>

Regards,
Anup


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
@ 2020-03-31  5:16     ` Anup Patel
  0 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31  5:16 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: QEMU Developers, open list:RISC-V, Anup Patel,
	zhang.zhanghailiang, Sagar Karandikar, Bastian Koppelmann,
	victor.zhangxiaofeng, Alistair Francis, yinyipeng1,
	Palmer Dabbelt, dengkai1

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Use char-fe handler console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  target/riscv/kvm.c | 54 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 0f429fd802..1df70fbb29 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -38,6 +38,7 @@
>  #include "qemu/log.h"
>  #include "hw/loader.h"
>  #include "kvm_riscv.h"
> +#include "chardev/char-fe.h"
>
>  static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
>  {
> @@ -61,6 +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
>
>  #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
>
> +enum sbi_ext_id {
> +    SBI_EXT_0_1_SET_TIMER = 0x0,
> +    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> +    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> +    SBI_EXT_0_1_CLEAR_IPI = 0x3,
> +    SBI_EXT_0_1_SEND_IPI = 0x4,
> +    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> +    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> +    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> +    SBI_EXT_0_1_SHUTDOWN = 0x8,
> +    SBI_EXT_BASE = 0x10,
> +};
> +

Please add separate SBI ecall interface header (similar to OpenSBI).
This header will only have SBI spec related defines.

Refer,
https://github.com/riscv/opensbi/blob/master/include/sbi/sbi_ecall_interface.h

>  static int kvm_riscv_get_regs_core(CPUState *cs)
>  {
>      int ret = 0;
> @@ -423,9 +437,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
>      return true;
>  }
>
> +static int kvm_riscv_handle_sbi(struct kvm_run *run)
> +{
> +    int ret = 0;
> +    unsigned char ch;
> +    switch (run->riscv_sbi.extension_id) {
> +    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
> +        ch = run->riscv_sbi.args[0];
> +        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
> +        break;
> +    case SBI_EXT_0_1_CONSOLE_GETCHAR:
> +        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
> +        if (ret == sizeof(ch)) {
> +            run->riscv_sbi.args[0] = ch;
> +        } else {
> +            run->riscv_sbi.args[0] = -1;
> +        }
> +        break;

Please emulate SBI v0.1 Shutdown call as well.

> +    default:
> +        qemu_log_mask(LOG_UNIMP,
> +                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
> +                      __func__, run->riscv_sbi.extension_id);
> +        ret = -1;
> +        break;
> +    }
> +    return ret;
> +}
> +
>  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
>  {
> -    return 0;
> +    int ret = 0;
> +    switch (run->exit_reason) {
> +    case KVM_EXIT_RISCV_SBI:
> +        ret = kvm_riscv_handle_sbi(run);
> +        break;
> +    default:
> +        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
> +                      __func__, run->exit_reason);
> +        ret = -1;
> +        break;
> +    }
> +    return ret;
>  }
>
>  void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> --
> 2.19.1
>
>
>

Regards,
Anup


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
  2020-03-13  3:49   ` Yifei Jiang
@ 2020-03-31  9:13     ` Anup Patel
  -1 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31  9:13 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: victor.zhangxiaofeng, open list:RISC-V, zhang.zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Anup Patel,
	QEMU Developers, Alistair Francis, yinyipeng1, Palmer Dabbelt,
	dengkai1

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c.
> Meanwhile, add riscv64 kvm support to configure.

This should be for both riscv64 and riscv32. The KVMTOOL compiles perfectly
fine for riscv32 (although not tested much) so there is no harm is supporting
both riscv64 and riscv32 from start itself.

Regards,
Anup


>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  configure                  |   1 +
>  target/riscv/Makefile.objs |   1 +
>  target/riscv/kvm.c         | 128 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 130 insertions(+)
>  create mode 100644 target/riscv/kvm.c
>
> diff --git a/configure b/configure
> index 3c7470096f..30024a8aef 100755
> --- a/configure
> +++ b/configure
> @@ -200,6 +200,7 @@ supported_kvm_target() {
>          x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \
>          mips:mips | mipsel:mips | \
>          ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \
> +        riscv64:riscv64 | \
>          s390x:s390x)
>              return 0
>          ;;
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index ff651f69f6..7ea8f4c3da 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -1,5 +1,6 @@
>  obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o
>  obj-$(CONFIG_SOFTMMU) += pmp.o
> +obj-$(CONFIG_KVM) += kvm.o
>
>  ifeq ($(CONFIG_SOFTMMU),y)
>  obj-y += monitor.o
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> new file mode 100644
> index 0000000000..8c386d9acf
> --- /dev/null
> +++ b/target/riscv/kvm.c
> @@ -0,0 +1,128 @@
> +/*
> + * RISC-V implementation of KVM hooks
> + *
> + * Copyright (c) 2020 Huawei Technologies Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include <sys/ioctl.h>
> +
> +#include <linux/kvm.h>
> +
> +#include "qemu-common.h"
> +#include "qemu/timer.h"
> +#include "qemu/error-report.h"
> +#include "qemu/main-loop.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/kvm.h"
> +#include "sysemu/kvm_int.h"
> +#include "cpu.h"
> +#include "trace.h"
> +#include "hw/pci/pci.h"
> +#include "exec/memattrs.h"
> +#include "exec/address-spaces.h"
> +#include "hw/boards.h"
> +#include "hw/irq.h"
> +#include "qemu/log.h"
> +#include "hw/loader.h"
> +
> +const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> +    KVM_CAP_LAST_INFO
> +};
> +
> +int kvm_arch_get_registers(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_put_registers(CPUState *cs, int level)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_release_virq_post(int virq)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
> +                             uint64_t address, uint32_t data, PCIDevice *dev)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_destroy_vcpu(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +unsigned long kvm_arch_vcpu_id(CPUState *cpu)
> +{
> +    return cpu->cpu_index;
> +}
> +
> +void kvm_arch_init_irq_routing(KVMState *s)
> +{
> +}
> +
> +int kvm_arch_init_vcpu(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_msi_data_to_gsi(uint32_t data)
> +{
> +    abort();
> +}
> +
> +int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
> +                                int vector, PCIDevice *dev)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_init(MachineState *ms, KVMState *s)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_irqchip_create(KVMState *s)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_process_async_events(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
> +{
> +}
> +
> +MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
> +{
> +    return MEMTXATTRS_UNSPECIFIED;
> +}
> +
> +bool kvm_arch_stop_on_emulation_error(CPUState *cs)
> +{
> +    return true;
> +}
> +
> +int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
> +{
> +    return 0;
> +}
> --
> 2.19.1
>
>
>


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
@ 2020-03-31  9:13     ` Anup Patel
  0 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31  9:13 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: QEMU Developers, open list:RISC-V, Anup Patel,
	zhang.zhanghailiang, Sagar Karandikar, Bastian Koppelmann,
	victor.zhangxiaofeng, Alistair Francis, yinyipeng1,
	Palmer Dabbelt, dengkai1

On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c.
> Meanwhile, add riscv64 kvm support to configure.

This should be for both riscv64 and riscv32. The KVMTOOL compiles perfectly
fine for riscv32 (although not tested much) so there is no harm is supporting
both riscv64 and riscv32 from start itself.

Regards,
Anup


>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  configure                  |   1 +
>  target/riscv/Makefile.objs |   1 +
>  target/riscv/kvm.c         | 128 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 130 insertions(+)
>  create mode 100644 target/riscv/kvm.c
>
> diff --git a/configure b/configure
> index 3c7470096f..30024a8aef 100755
> --- a/configure
> +++ b/configure
> @@ -200,6 +200,7 @@ supported_kvm_target() {
>          x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \
>          mips:mips | mipsel:mips | \
>          ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \
> +        riscv64:riscv64 | \
>          s390x:s390x)
>              return 0
>          ;;
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index ff651f69f6..7ea8f4c3da 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -1,5 +1,6 @@
>  obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o
>  obj-$(CONFIG_SOFTMMU) += pmp.o
> +obj-$(CONFIG_KVM) += kvm.o
>
>  ifeq ($(CONFIG_SOFTMMU),y)
>  obj-y += monitor.o
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> new file mode 100644
> index 0000000000..8c386d9acf
> --- /dev/null
> +++ b/target/riscv/kvm.c
> @@ -0,0 +1,128 @@
> +/*
> + * RISC-V implementation of KVM hooks
> + *
> + * Copyright (c) 2020 Huawei Technologies Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include <sys/ioctl.h>
> +
> +#include <linux/kvm.h>
> +
> +#include "qemu-common.h"
> +#include "qemu/timer.h"
> +#include "qemu/error-report.h"
> +#include "qemu/main-loop.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/kvm.h"
> +#include "sysemu/kvm_int.h"
> +#include "cpu.h"
> +#include "trace.h"
> +#include "hw/pci/pci.h"
> +#include "exec/memattrs.h"
> +#include "exec/address-spaces.h"
> +#include "hw/boards.h"
> +#include "hw/irq.h"
> +#include "qemu/log.h"
> +#include "hw/loader.h"
> +
> +const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> +    KVM_CAP_LAST_INFO
> +};
> +
> +int kvm_arch_get_registers(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_put_registers(CPUState *cs, int level)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_release_virq_post(int virq)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
> +                             uint64_t address, uint32_t data, PCIDevice *dev)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_destroy_vcpu(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +unsigned long kvm_arch_vcpu_id(CPUState *cpu)
> +{
> +    return cpu->cpu_index;
> +}
> +
> +void kvm_arch_init_irq_routing(KVMState *s)
> +{
> +}
> +
> +int kvm_arch_init_vcpu(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_msi_data_to_gsi(uint32_t data)
> +{
> +    abort();
> +}
> +
> +int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
> +                                int vector, PCIDevice *dev)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_init(MachineState *ms, KVMState *s)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_irqchip_create(KVMState *s)
> +{
> +    return 0;
> +}
> +
> +int kvm_arch_process_async_events(CPUState *cs)
> +{
> +    return 0;
> +}
> +
> +void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
> +{
> +}
> +
> +MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
> +{
> +    return MEMTXATTRS_UNSPECIFIED;
> +}
> +
> +bool kvm_arch_stop_on_emulation_error(CPUState *cs)
> +{
> +    return true;
> +}
> +
> +int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
> +{
> +    return 0;
> +}
> --
> 2.19.1
>
>
>


^ permalink raw reply	[flat|nested] 36+ messages in thread
* RE: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
  2020-03-31  5:16     ` Anup Patel
@ 2020-03-31  9:26       ` Jiangyifei
  -1 siblings, 0 replies; 36+ messages in thread
From: Jiangyifei @ 2020-03-31  9:26 UTC (permalink / raw)
  To: Anup Patel
  Cc: Zhangxiaofeng (F),
	open list:RISC-V, Zhanghailiang, Sagar Karandikar,
	Bastian Koppelmann, Anup Patel, QEMU Developers,
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)


> -----Original Message-----
> From: Anup Patel [mailto:anup@brainfault.org]
> Sent: Tuesday, March 31, 2020 1:17 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V <qemu-
> riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>; Zhanghailiang
> <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-
> paderborn.de>; Zhangxiaofeng (F) <victor.zhangxiaofeng@huawei.com>;
> Alistair Francis <Alistair.Francis@wdc.com>; yinyipeng
> <yinyipeng1@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
> 
> On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Use char-fe handler console sbi call, which implement early console io
> > while apply 'earlycon=sbi' into kernel parameters.
> >
> > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> > ---
> >  target/riscv/kvm.c | 54
> > +++++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 53 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > 0f429fd802..1df70fbb29 100644
> > --- a/target/riscv/kvm.c
> > +++ b/target/riscv/kvm.c
> > @@ -38,6 +38,7 @@
> >  #include "qemu/log.h"
> >  #include "hw/loader.h"
> >  #include "kvm_riscv.h"
> > +#include "chardev/char-fe.h"
> >
> >  static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)  { @@ -61,6
> > +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
> >
> >  #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D,
> > idx)
> >
> > +enum sbi_ext_id {
> > +    SBI_EXT_0_1_SET_TIMER = 0x0,
> > +    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> > +    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> > +    SBI_EXT_0_1_CLEAR_IPI = 0x3,
> > +    SBI_EXT_0_1_SEND_IPI = 0x4,
> > +    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> > +    SBI_EXT_0_1_SHUTDOWN = 0x8,
> > +    SBI_EXT_BASE = 0x10,
> > +};
> > +
> 
> Please add separate SBI ecall interface header (similar to OpenSBI).
> This header will only have SBI spec related defines.
> 
> Refer,
> https://github.com/riscv/opensbi/blob/master/include/sbi/sbi_ecall_interfa
> ce.h

Yes, thanks for your review. I'll update it at next series after you review this series all.

> 
> >  static int kvm_riscv_get_regs_core(CPUState *cs)  {
> >      int ret = 0;
> > @@ -423,9 +437,47 @@ bool
> kvm_arch_stop_on_emulation_error(CPUState *cs)
> >      return true;
> >  }
> >
> > +static int kvm_riscv_handle_sbi(struct kvm_run *run) {
> > +    int ret = 0;
> > +    unsigned char ch;
> > +    switch (run->riscv_sbi.extension_id) {
> > +    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
> > +        ch = run->riscv_sbi.args[0];
> > +        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
> > +        break;
> > +    case SBI_EXT_0_1_CONSOLE_GETCHAR:
> > +        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
> > +        if (ret == sizeof(ch)) {
> > +            run->riscv_sbi.args[0] = ch;
> > +        } else {
> > +            run->riscv_sbi.args[0] = -1;
> > +        }
> > +        break;
> 
> Please emulate SBI v0.1 Shutdown call as well.

It seems that there is no need for emulating SHUTDOWN call at QEMU.
SBI_EXT_0_1_SHUTDOWN is redirect to KVM_SYSTEM_EVENT_SHUTDOWN in KVM,
which is handled by common kvm-exit handler in QEMU.
And, It is normal to perform `poweroff` in the virtual machine.

> 
> > +    default:
> > +        qemu_log_mask(LOG_UNIMP,
> > +                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
> > +                      __func__, run->riscv_sbi.extension_id);
> > +        ret = -1;
> > +        break;
> > +    }
> > +    return ret;
> > +}
> > +
> >  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)  {
> > -    return 0;
> > +    int ret = 0;
> > +    switch (run->exit_reason) {
> > +    case KVM_EXIT_RISCV_SBI:
> > +        ret = kvm_riscv_handle_sbi(run);
> > +        break;
> > +    default:
> > +        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
> > +                      __func__, run->exit_reason);
> > +        ret = -1;
> > +        break;
> > +    }
> > +    return ret;
> >  }
> >
> >  void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> > --
> > 2.19.1
> >
> >
> >
> 
> Regards,
> Anup

Best regards,
Yifei Jiang

^ permalink raw reply	[flat|nested] 36+ messages in thread
* RE: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
@ 2020-03-31  9:26       ` Jiangyifei
  0 siblings, 0 replies; 36+ messages in thread
From: Jiangyifei @ 2020-03-31  9:26 UTC (permalink / raw)
  To: Anup Patel
  Cc: QEMU Developers, open list:RISC-V, Anup Patel, Zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Zhangxiaofeng (F),
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)


> -----Original Message-----
> From: Anup Patel [mailto:anup@brainfault.org]
> Sent: Tuesday, March 31, 2020 1:17 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V <qemu-
> riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>; Zhanghailiang
> <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-
> paderborn.de>; Zhangxiaofeng (F) <victor.zhangxiaofeng@huawei.com>;
> Alistair Francis <Alistair.Francis@wdc.com>; yinyipeng
> <yinyipeng1@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
> 
> On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Use char-fe handler console sbi call, which implement early console io
> > while apply 'earlycon=sbi' into kernel parameters.
> >
> > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> > ---
> >  target/riscv/kvm.c | 54
> > +++++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 53 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > 0f429fd802..1df70fbb29 100644
> > --- a/target/riscv/kvm.c
> > +++ b/target/riscv/kvm.c
> > @@ -38,6 +38,7 @@
> >  #include "qemu/log.h"
> >  #include "hw/loader.h"
> >  #include "kvm_riscv.h"
> > +#include "chardev/char-fe.h"
> >
> >  static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)  { @@ -61,6
> > +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
> >
> >  #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D,
> > idx)
> >
> > +enum sbi_ext_id {
> > +    SBI_EXT_0_1_SET_TIMER = 0x0,
> > +    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> > +    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> > +    SBI_EXT_0_1_CLEAR_IPI = 0x3,
> > +    SBI_EXT_0_1_SEND_IPI = 0x4,
> > +    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> > +    SBI_EXT_0_1_SHUTDOWN = 0x8,
> > +    SBI_EXT_BASE = 0x10,
> > +};
> > +
> 
> Please add separate SBI ecall interface header (similar to OpenSBI).
> This header will only have SBI spec related defines.
> 
> Refer,
> https://github.com/riscv/opensbi/blob/master/include/sbi/sbi_ecall_interfa
> ce.h

Yes, thanks for your review. I'll update it at next series after you review this series all.

> 
> >  static int kvm_riscv_get_regs_core(CPUState *cs)  {
> >      int ret = 0;
> > @@ -423,9 +437,47 @@ bool
> kvm_arch_stop_on_emulation_error(CPUState *cs)
> >      return true;
> >  }
> >
> > +static int kvm_riscv_handle_sbi(struct kvm_run *run) {
> > +    int ret = 0;
> > +    unsigned char ch;
> > +    switch (run->riscv_sbi.extension_id) {
> > +    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
> > +        ch = run->riscv_sbi.args[0];
> > +        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
> > +        break;
> > +    case SBI_EXT_0_1_CONSOLE_GETCHAR:
> > +        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
> > +        if (ret == sizeof(ch)) {
> > +            run->riscv_sbi.args[0] = ch;
> > +        } else {
> > +            run->riscv_sbi.args[0] = -1;
> > +        }
> > +        break;
> 
> Please emulate SBI v0.1 Shutdown call as well.

It seems that there is no need for emulating SHUTDOWN call at QEMU.
SBI_EXT_0_1_SHUTDOWN is redirect to KVM_SYSTEM_EVENT_SHUTDOWN in KVM,
which is handled by common kvm-exit handler in QEMU.
And, It is normal to perform `poweroff` in the virtual machine.

> 
> > +    default:
> > +        qemu_log_mask(LOG_UNIMP,
> > +                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
> > +                      __func__, run->riscv_sbi.extension_id);
> > +        ret = -1;
> > +        break;
> > +    }
> > +    return ret;
> > +}
> > +
> >  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)  {
> > -    return 0;
> > +    int ret = 0;
> > +    switch (run->exit_reason) {
> > +    case KVM_EXIT_RISCV_SBI:
> > +        ret = kvm_riscv_handle_sbi(run);
> > +        break;
> > +    default:
> > +        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
> > +                      __func__, run->exit_reason);
> > +        ret = -1;
> > +        break;
> > +    }
> > +    return ret;
> >  }
> >
> >  void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> > --
> > 2.19.1
> >
> >
> >
> 
> Regards,
> Anup

Best regards,
Yifei Jiang

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
  2020-03-31  9:26       ` Jiangyifei
@ 2020-03-31  9:51         ` Anup Patel
  -1 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31  9:51 UTC (permalink / raw)
  To: Jiangyifei
  Cc: Zhangxiaofeng (F),
	open list:RISC-V, Zhanghailiang, Sagar Karandikar,
	Bastian Koppelmann, Anup Patel, QEMU Developers,
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)

On Tue, Mar 31, 2020 at 2:56 PM Jiangyifei <jiangyifei@huawei.com> wrote:
>
>
> > -----Original Message-----
> > From: Anup Patel [mailto:anup@brainfault.org]
> > Sent: Tuesday, March 31, 2020 1:17 PM
> > To: Jiangyifei <jiangyifei@huawei.com>
> > Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V <qemu-
> > riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>; Zhanghailiang
> > <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> > <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-
> > paderborn.de>; Zhangxiaofeng (F) <victor.zhangxiaofeng@huawei.com>;
> > Alistair Francis <Alistair.Francis@wdc.com>; yinyipeng
> > <yinyipeng1@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> > dengkai (A) <dengkai1@huawei.com>
> > Subject: Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
> >
> > On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> > >
> > > Use char-fe handler console sbi call, which implement early console io
> > > while apply 'earlycon=sbi' into kernel parameters.
> > >
> > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> > > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> > > ---
> > >  target/riscv/kvm.c | 54
> > > +++++++++++++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 53 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > > 0f429fd802..1df70fbb29 100644
> > > --- a/target/riscv/kvm.c
> > > +++ b/target/riscv/kvm.c
> > > @@ -38,6 +38,7 @@
> > >  #include "qemu/log.h"
> > >  #include "hw/loader.h"
> > >  #include "kvm_riscv.h"
> > > +#include "chardev/char-fe.h"
> > >
> > >  static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)  { @@ -61,6
> > > +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
> > >
> > >  #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D,
> > > idx)
> > >
> > > +enum sbi_ext_id {
> > > +    SBI_EXT_0_1_SET_TIMER = 0x0,
> > > +    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> > > +    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> > > +    SBI_EXT_0_1_CLEAR_IPI = 0x3,
> > > +    SBI_EXT_0_1_SEND_IPI = 0x4,
> > > +    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> > > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> > > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> > > +    SBI_EXT_0_1_SHUTDOWN = 0x8,
> > > +    SBI_EXT_BASE = 0x10,
> > > +};
> > > +
> >
> > Please add separate SBI ecall interface header (similar to OpenSBI).
> > This header will only have SBI spec related defines.
> >
> > Refer,
> > https://github.com/riscv/opensbi/blob/master/include/sbi/sbi_ecall_interfa
> > ce.h
>
> Yes, thanks for your review. I'll update it at next series after you review this series all.
>
> >
> > >  static int kvm_riscv_get_regs_core(CPUState *cs)  {
> > >      int ret = 0;
> > > @@ -423,9 +437,47 @@ bool
> > kvm_arch_stop_on_emulation_error(CPUState *cs)
> > >      return true;
> > >  }
> > >
> > > +static int kvm_riscv_handle_sbi(struct kvm_run *run) {
> > > +    int ret = 0;
> > > +    unsigned char ch;
> > > +    switch (run->riscv_sbi.extension_id) {
> > > +    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
> > > +        ch = run->riscv_sbi.args[0];
> > > +        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
> > > +        break;
> > > +    case SBI_EXT_0_1_CONSOLE_GETCHAR:
> > > +        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
> > > +        if (ret == sizeof(ch)) {
> > > +            run->riscv_sbi.args[0] = ch;
> > > +        } else {
> > > +            run->riscv_sbi.args[0] = -1;
> > > +        }
> > > +        break;
> >
> > Please emulate SBI v0.1 Shutdown call as well.
>
> It seems that there is no need for emulating SHUTDOWN call at QEMU.
> SBI_EXT_0_1_SHUTDOWN is redirect to KVM_SYSTEM_EVENT_SHUTDOWN in KVM,
> which is handled by common kvm-exit handler in QEMU.
> And, It is normal to perform `poweroff` in the virtual machine.

Ahh, yes I forgot about KVM_SYSTEM_EVENT_SHUTDOWN

No need to handle SBI_EXT_0_1_SHUTDOWN here.

Regards,
Anup

>
> >
> > > +    default:
> > > +        qemu_log_mask(LOG_UNIMP,
> > > +                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
> > > +                      __func__, run->riscv_sbi.extension_id);
> > > +        ret = -1;
> > > +        break;
> > > +    }
> > > +    return ret;
> > > +}
> > > +
> > >  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)  {
> > > -    return 0;
> > > +    int ret = 0;
> > > +    switch (run->exit_reason) {
> > > +    case KVM_EXIT_RISCV_SBI:
> > > +        ret = kvm_riscv_handle_sbi(run);
> > > +        break;
> > > +    default:
> > > +        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
> > > +                      __func__, run->exit_reason);
> > > +        ret = -1;
> > > +        break;
> > > +    }
> > > +    return ret;
> > >  }
> > >
> > >  void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> > > --
> > > 2.19.1
> > >
> > >
> > >
> >
> > Regards,
> > Anup
>
> Best regards,
> Yifei Jiang


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
@ 2020-03-31  9:51         ` Anup Patel
  0 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31  9:51 UTC (permalink / raw)
  To: Jiangyifei
  Cc: QEMU Developers, open list:RISC-V, Anup Patel, Zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Zhangxiaofeng (F),
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)

On Tue, Mar 31, 2020 at 2:56 PM Jiangyifei <jiangyifei@huawei.com> wrote:
>
>
> > -----Original Message-----
> > From: Anup Patel [mailto:anup@brainfault.org]
> > Sent: Tuesday, March 31, 2020 1:17 PM
> > To: Jiangyifei <jiangyifei@huawei.com>
> > Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V <qemu-
> > riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>; Zhanghailiang
> > <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> > <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-
> > paderborn.de>; Zhangxiaofeng (F) <victor.zhangxiaofeng@huawei.com>;
> > Alistair Francis <Alistair.Francis@wdc.com>; yinyipeng
> > <yinyipeng1@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> > dengkai (A) <dengkai1@huawei.com>
> > Subject: Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
> >
> > On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> > >
> > > Use char-fe handler console sbi call, which implement early console io
> > > while apply 'earlycon=sbi' into kernel parameters.
> > >
> > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> > > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> > > ---
> > >  target/riscv/kvm.c | 54
> > > +++++++++++++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 53 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > > 0f429fd802..1df70fbb29 100644
> > > --- a/target/riscv/kvm.c
> > > +++ b/target/riscv/kvm.c
> > > @@ -38,6 +38,7 @@
> > >  #include "qemu/log.h"
> > >  #include "hw/loader.h"
> > >  #include "kvm_riscv.h"
> > > +#include "chardev/char-fe.h"
> > >
> > >  static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)  { @@ -61,6
> > > +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
> > >
> > >  #define RISCV_FP_D_REG(idx)  kvm_riscv_reg_id(KVM_REG_RISCV_FP_D,
> > > idx)
> > >
> > > +enum sbi_ext_id {
> > > +    SBI_EXT_0_1_SET_TIMER = 0x0,
> > > +    SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> > > +    SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> > > +    SBI_EXT_0_1_CLEAR_IPI = 0x3,
> > > +    SBI_EXT_0_1_SEND_IPI = 0x4,
> > > +    SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> > > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> > > +    SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> > > +    SBI_EXT_0_1_SHUTDOWN = 0x8,
> > > +    SBI_EXT_BASE = 0x10,
> > > +};
> > > +
> >
> > Please add separate SBI ecall interface header (similar to OpenSBI).
> > This header will only have SBI spec related defines.
> >
> > Refer,
> > https://github.com/riscv/opensbi/blob/master/include/sbi/sbi_ecall_interfa
> > ce.h
>
> Yes, thanks for your review. I'll update it at next series after you review this series all.
>
> >
> > >  static int kvm_riscv_get_regs_core(CPUState *cs)  {
> > >      int ret = 0;
> > > @@ -423,9 +437,47 @@ bool
> > kvm_arch_stop_on_emulation_error(CPUState *cs)
> > >      return true;
> > >  }
> > >
> > > +static int kvm_riscv_handle_sbi(struct kvm_run *run) {
> > > +    int ret = 0;
> > > +    unsigned char ch;
> > > +    switch (run->riscv_sbi.extension_id) {
> > > +    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
> > > +        ch = run->riscv_sbi.args[0];
> > > +        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
> > > +        break;
> > > +    case SBI_EXT_0_1_CONSOLE_GETCHAR:
> > > +        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
> > > +        if (ret == sizeof(ch)) {
> > > +            run->riscv_sbi.args[0] = ch;
> > > +        } else {
> > > +            run->riscv_sbi.args[0] = -1;
> > > +        }
> > > +        break;
> >
> > Please emulate SBI v0.1 Shutdown call as well.
>
> It seems that there is no need for emulating SHUTDOWN call at QEMU.
> SBI_EXT_0_1_SHUTDOWN is redirect to KVM_SYSTEM_EVENT_SHUTDOWN in KVM,
> which is handled by common kvm-exit handler in QEMU.
> And, It is normal to perform `poweroff` in the virtual machine.

Ahh, yes I forgot about KVM_SYSTEM_EVENT_SHUTDOWN

No need to handle SBI_EXT_0_1_SHUTDOWN here.

Regards,
Anup

>
> >
> > > +    default:
> > > +        qemu_log_mask(LOG_UNIMP,
> > > +                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
> > > +                      __func__, run->riscv_sbi.extension_id);
> > > +        ret = -1;
> > > +        break;
> > > +    }
> > > +    return ret;
> > > +}
> > > +
> > >  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)  {
> > > -    return 0;
> > > +    int ret = 0;
> > > +    switch (run->exit_reason) {
> > > +    case KVM_EXIT_RISCV_SBI:
> > > +        ret = kvm_riscv_handle_sbi(run);
> > > +        break;
> > > +    default:
> > > +        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
> > > +                      __func__, run->exit_reason);
> > > +        ret = -1;
> > > +        break;
> > > +    }
> > > +    return ret;
> > >  }
> > >
> > >  void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> > > --
> > > 2.19.1
> > >
> > >
> > >
> >
> > Regards,
> > Anup
>
> Best regards,
> Yifei Jiang


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
  2020-03-31  9:13     ` Anup Patel
@ 2020-03-31 11:19       ` Anup Patel
  -1 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31 11:19 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: Zhangxiaofeng (F),
	open list:RISC-V, Zhanghailiang, Sagar Karandikar,
	Bastian Koppelmann, Anup Patel, QEMU Developers,
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)

On Tue, Mar 31, 2020 at 2:43 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c.
> > Meanwhile, add riscv64 kvm support to configure.
>
> This should be for both riscv64 and riscv32. The KVMTOOL compiles perfectly
> fine for riscv32 (although not tested much) so there is no harm is supporting
> both riscv64 and riscv32 from start itself.

For your reference, I have updated KVM RISC-V and KVMTOOL RISC-V repos
at:
https://github.com/kvm-riscv/linux.git (riscv_kvm_master branch)
https://github.com/kvm-riscv/kvmtool.git (riscv_master branch)

Above repos work for both RV32 and RV64 systems.

Regards,
Anup


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
@ 2020-03-31 11:19       ` Anup Patel
  0 siblings, 0 replies; 36+ messages in thread
From: Anup Patel @ 2020-03-31 11:19 UTC (permalink / raw)
  To: Yifei Jiang
  Cc: QEMU Developers, open list:RISC-V, Anup Patel, Zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Zhangxiaofeng (F),
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)

On Tue, Mar 31, 2020 at 2:43 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c.
> > Meanwhile, add riscv64 kvm support to configure.
>
> This should be for both riscv64 and riscv32. The KVMTOOL compiles perfectly
> fine for riscv32 (although not tested much) so there is no harm is supporting
> both riscv64 and riscv32 from start itself.

For your reference, I have updated KVM RISC-V and KVMTOOL RISC-V repos
at:
https://github.com/kvm-riscv/linux.git (riscv_kvm_master branch)
https://github.com/kvm-riscv/kvmtool.git (riscv_master branch)

Above repos work for both RV32 and RV64 systems.

Regards,
Anup


^ permalink raw reply	[flat|nested] 36+ messages in thread
* RE: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
  2020-03-31 11:19       ` Anup Patel
@ 2020-04-11  4:11         ` Jiangyifei
  -1 siblings, 0 replies; 36+ messages in thread
From: Jiangyifei @ 2020-04-11  4:11 UTC (permalink / raw)
  To: Anup Patel
  Cc: Zhangxiaofeng (F),
	open list:RISC-V, Zhanghailiang, Sagar Karandikar,
	Bastian Koppelmann, Anup Patel, QEMU Developers,
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)


> -----Original Message-----
> From: Anup Patel [mailto:anup@brainfault.org]
> Sent: Tuesday, March 31, 2020 7:19 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V
> <qemu-riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>;
> Zhanghailiang <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> <sagark@eecs.berkeley.edu>; Bastian Koppelmann
> <kbastian@mail.uni-paderborn.de>; Zhangxiaofeng (F)
> <victor.zhangxiaofeng@huawei.com>; Alistair Francis
> <Alistair.Francis@wdc.com>; yinyipeng <yinyipeng1@huawei.com>; Palmer
> Dabbelt <palmer@dabbelt.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the
> public kvm interface
> 
> On Tue, Mar 31, 2020 at 2:43 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> > >
> > > Add target/riscv/kvm.c to place kvm_arch_* function needed by
> kvm/kvm-all.c.
> > > Meanwhile, add riscv64 kvm support to configure.
> >
> > This should be for both riscv64 and riscv32. The KVMTOOL compiles
> > perfectly fine for riscv32 (although not tested much) so there is no
> > harm is supporting both riscv64 and riscv32 from start itself.
> 
> For your reference, I have updated KVM RISC-V and KVMTOOL RISC-V repos
> at:
> https://github.com/kvm-riscv/linux.git (riscv_kvm_master branch)
> https://github.com/kvm-riscv/kvmtool.git (riscv_master branch)
> 
> Above repos work for both RV32 and RV64 systems.
> 
> Regards,
> Anup

Hi,

I will add riscv32 support and send v2 series. But I don't test completely, because it need time to build riscv32 QEMU and its dependent libraries.
Anyway, I will continue to build and test riscv32 QEMU.

By the way, I had a problem with start riscv64 vm at latest kvm-riscv version.
lastest version:
tcg qemu: https://github.com/qemu/qemu
linux: https://github.com/kvm-riscv/linux
opensbi: https://github.com/riscv/opensbi
kvmtool: https://github.com/kvm-riscv/kvmtool
when start vm with kvmtools or this qemu series, I received kernel panic.
Do you have this problem ?

[    3.583963] Run /sbin/init as init process
[    3.972264] rcS[44]: unhandled signal 11 code 0x1 at 0x0000003fc8d67170
[    3.997398] CPU: 0 PID: 44 Comm: rcS Not tainted 5.6.0-rc5-14036-g6e1e9fcf5f30 #2
[    4.025143] epc: 0000003fc8d67170 ra : 0000000000018c1c sp : 0000003fffb84e00
[    4.051611]  gp : 0000000000136648 tp : 0000003fd6086710 t0 : 0000000000000003
[    4.078223]  t1 : 000000000001792c t2 : 000000000000000b s0 : 0000000000018bf0
[    4.105082]  s1 : 0000003fffa2fa70 a0 : 0000000000019868 a1 : 0000000000000002
[    4.131824]  a2 : 0000003fffb84e08 a3 : 0000000000104984 a4 : 00000000001049dc
[    4.158209]  a5 : 0000003fd628e710 a6 : 0000003fffb84e00 a7 : 0000000000000000
[    4.184756]  s2 : 0000003fffa2fa10 s3 : 0000000000137010 s4 : 0000000000000001
[    4.211448]  s5 : 0000003fc8d65918 s6 : 0000000000000001 s7 : 0000000000112000
[    4.238238]  s8 : 0000000000136140 s9 : 0000000000000000 s10: 0000000000000000
[    4.264880]  s11: 0000000000000000 t3 : 0000003fc8d67170 t4 : 0000000000000002
[    4.291543]  t5 : 0000003fd6282180 t6 : 0000000000000000
[    4.311196] status: 0000000000004020 badaddr: 0000003fc8d67170 cause: 000000000000000c
[    4.348835] init[1]: unhandled signal 11 code 0x1 at 0x0000003fd6292468
[    4.373718] CPU: 0 PID: 1 Comm: init Not tainted 5.6.0-rc5-14036-g6e1e9fcf5f30 #2
[    4.401344] epc: 0000003fd6292468 ra : 0000000000102f88 sp : 0000003fffa2f960
[    4.427814]  gp : 0000000000136648 tp : 0000003fc8b50710 t0 : 0000003fd629d170
[    4.454199]  t1 : 0000000000000238 t2 : 00000000001353f0 s0 : 0000000000124000
[    4.480699]  s1 : 0000000000000008 a0 : 0000000000123aa8 a1 : 0000000000000006
[    4.507352]  a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
[    4.533818]  a5 : fffffffffffff000 a6 : 0000003fc8d65918 a7 : 0000000000000104
[    4.560408]  s2 : 0000000000000000 s3 : 0000000000000000 s4 : 0000000000000000
[    4.586966]  s5 : 000000000000002c s6 : 0000000000000003 s7 : 0000000000000000
[    4.613331]  s8 : 0000000000136140 s9 : 0000000000000000 s10: 0000000000000000
[    4.640006]  s11: 0000000000000000 t3 : 0000003fd6292468 t4 : 0000000000000002
[    4.666372]  t5 : 0000003fc8b53dc8 t6 : 0000000000000000
[    4.686124] status: 0000000000004020 badaddr: 0000003fd6292468 cause: 000000000000000c
[    4.715612] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

Best Regards,
Yifei Jiang

^ permalink raw reply	[flat|nested] 36+ messages in thread
* RE: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
@ 2020-04-11  4:11         ` Jiangyifei
  0 siblings, 0 replies; 36+ messages in thread
From: Jiangyifei @ 2020-04-11  4:11 UTC (permalink / raw)
  To: Anup Patel
  Cc: QEMU Developers, open list:RISC-V, Anup Patel, Zhanghailiang,
	Sagar Karandikar, Bastian Koppelmann, Zhangxiaofeng (F),
	Alistair Francis, yinyipeng, Palmer Dabbelt, dengkai (A)


> -----Original Message-----
> From: Anup Patel [mailto:anup@brainfault.org]
> Sent: Tuesday, March 31, 2020 7:19 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V
> <qemu-riscv@nongnu.org>; Anup Patel <anup.patel@wdc.com>;
> Zhanghailiang <zhang.zhanghailiang@huawei.com>; Sagar Karandikar
> <sagark@eecs.berkeley.edu>; Bastian Koppelmann
> <kbastian@mail.uni-paderborn.de>; Zhangxiaofeng (F)
> <victor.zhangxiaofeng@huawei.com>; Alistair Francis
> <Alistair.Francis@wdc.com>; yinyipeng <yinyipeng1@huawei.com>; Palmer
> Dabbelt <palmer@dabbelt.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the
> public kvm interface
> 
> On Tue, Mar 31, 2020 at 2:43 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Fri, Mar 13, 2020 at 9:23 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
> > >
> > > Add target/riscv/kvm.c to place kvm_arch_* function needed by
> kvm/kvm-all.c.
> > > Meanwhile, add riscv64 kvm support to configure.
> >
> > This should be for both riscv64 and riscv32. The KVMTOOL compiles
> > perfectly fine for riscv32 (although not tested much) so there is no
> > harm is supporting both riscv64 and riscv32 from start itself.
> 
> For your reference, I have updated KVM RISC-V and KVMTOOL RISC-V repos
> at:
> https://github.com/kvm-riscv/linux.git (riscv_kvm_master branch)
> https://github.com/kvm-riscv/kvmtool.git (riscv_master branch)
> 
> Above repos work for both RV32 and RV64 systems.
> 
> Regards,
> Anup

Hi,

I will add riscv32 support and send v2 series. But I don't test completely, because it need time to build riscv32 QEMU and its dependent libraries.
Anyway, I will continue to build and test riscv32 QEMU.

By the way, I had a problem with start riscv64 vm at latest kvm-riscv version.
lastest version:
tcg qemu: https://github.com/qemu/qemu
linux: https://github.com/kvm-riscv/linux
opensbi: https://github.com/riscv/opensbi
kvmtool: https://github.com/kvm-riscv/kvmtool
when start vm with kvmtools or this qemu series, I received kernel panic.
Do you have this problem ?

[    3.583963] Run /sbin/init as init process
[    3.972264] rcS[44]: unhandled signal 11 code 0x1 at 0x0000003fc8d67170
[    3.997398] CPU: 0 PID: 44 Comm: rcS Not tainted 5.6.0-rc5-14036-g6e1e9fcf5f30 #2
[    4.025143] epc: 0000003fc8d67170 ra : 0000000000018c1c sp : 0000003fffb84e00
[    4.051611]  gp : 0000000000136648 tp : 0000003fd6086710 t0 : 0000000000000003
[    4.078223]  t1 : 000000000001792c t2 : 000000000000000b s0 : 0000000000018bf0
[    4.105082]  s1 : 0000003fffa2fa70 a0 : 0000000000019868 a1 : 0000000000000002
[    4.131824]  a2 : 0000003fffb84e08 a3 : 0000000000104984 a4 : 00000000001049dc
[    4.158209]  a5 : 0000003fd628e710 a6 : 0000003fffb84e00 a7 : 0000000000000000
[    4.184756]  s2 : 0000003fffa2fa10 s3 : 0000000000137010 s4 : 0000000000000001
[    4.211448]  s5 : 0000003fc8d65918 s6 : 0000000000000001 s7 : 0000000000112000
[    4.238238]  s8 : 0000000000136140 s9 : 0000000000000000 s10: 0000000000000000
[    4.264880]  s11: 0000000000000000 t3 : 0000003fc8d67170 t4 : 0000000000000002
[    4.291543]  t5 : 0000003fd6282180 t6 : 0000000000000000
[    4.311196] status: 0000000000004020 badaddr: 0000003fc8d67170 cause: 000000000000000c
[    4.348835] init[1]: unhandled signal 11 code 0x1 at 0x0000003fd6292468
[    4.373718] CPU: 0 PID: 1 Comm: init Not tainted 5.6.0-rc5-14036-g6e1e9fcf5f30 #2
[    4.401344] epc: 0000003fd6292468 ra : 0000000000102f88 sp : 0000003fffa2f960
[    4.427814]  gp : 0000000000136648 tp : 0000003fc8b50710 t0 : 0000003fd629d170
[    4.454199]  t1 : 0000000000000238 t2 : 00000000001353f0 s0 : 0000000000124000
[    4.480699]  s1 : 0000000000000008 a0 : 0000000000123aa8 a1 : 0000000000000006
[    4.507352]  a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
[    4.533818]  a5 : fffffffffffff000 a6 : 0000003fc8d65918 a7 : 0000000000000104
[    4.560408]  s2 : 0000000000000000 s3 : 0000000000000000 s4 : 0000000000000000
[    4.586966]  s5 : 000000000000002c s6 : 0000000000000003 s7 : 0000000000000000
[    4.613331]  s8 : 0000000000136140 s9 : 0000000000000000 s10: 0000000000000000
[    4.640006]  s11: 0000000000000000 t3 : 0000003fd6292468 t4 : 0000000000000002
[    4.666372]  t5 : 0000003fc8b53dc8 t6 : 0000000000000000
[    4.686124] status: 0000000000004020 badaddr: 0000003fd6292468 cause: 000000000000000c
[    4.715612] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

Best Regards,
Yifei Jiang

^ permalink raw reply	[flat|nested] 36+ messages in thread
end of thread, other threads:[~2020-04-11  4:12 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-13  3:49 [PATCH RFC 0/9] Add riscv64 kvm accel support Yifei Jiang
2020-03-13  3:49 ` Yifei Jiang
2020-03-13  3:49 ` [PATCH RFC 1/9] linux-header: Update linux/kvm.h Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-13  3:49 ` [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-31  9:13   ` Anup Patel
2020-03-31  9:13     ` Anup Patel
2020-03-31 11:19     ` Anup Patel
2020-03-31 11:19       ` Anup Patel
2020-04-11  4:11       ` Jiangyifei
2020-04-11  4:11         ` Jiangyifei
2020-03-13  3:49 ` [PATCH RFC 3/9] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-13  3:49 ` [PATCH RFC 4/9] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-13  3:49 ` [PATCH RFC 5/9] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-13  3:49 ` [PATCH RFC 6/9] target/riscv: Support start kernel directly by KVM Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-13  3:49 ` [PATCH RFC 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-13  3:49 ` [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-31  5:16   ` Anup Patel
2020-03-31  5:16     ` Anup Patel
2020-03-31  9:26     ` Jiangyifei
2020-03-31  9:26       ` Jiangyifei
2020-03-31  9:51       ` Anup Patel
2020-03-31  9:51         ` Anup Patel
2020-03-13  3:49 ` [PATCH RFC 9/9] target/riscv: add host riscv64 cpu type Yifei Jiang
2020-03-13  3:49   ` Yifei Jiang
2020-03-13  5:59 ` [PATCH RFC 0/9] Add riscv64 kvm accel support Anup Patel
2020-03-13  5:59   ` Anup Patel
2020-03-13  7:02   ` Jiangyifei
2020-03-13  7:02     ` Jiangyifei

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