From: Marc Zyngier <maz@kernel.org> To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: John Garry <john.garry@huawei.com>, chenxiang <chenxiang66@hisilicon.com>, Zhou Wang <wangzhou1@hisilicon.com>, Ming Lei <ming.lei@redhat.com>, Jason Cooper <jason@lakedaemon.net>, Thomas Gleixner <tglx@linutronix.de> Subject: [PATCH v3 0/2] irqchip/gic-v3-its: Balance LPI affinity across CPUs Date: Mon, 16 Mar 2020 11:54:31 +0000 [thread overview] Message-ID: <20200316115433.9017-1-maz@kernel.org> (raw) When mapping a LPI, the ITS driver picks the first possible affinity, which is in most cases CPU0, assuming that if that's not suitable, someone will come and set the affinity to something more interesting. It apparently isn't the case, and people complain of poor performance when many interrupts are glued to the same CPU. So let's place the interrupts by finding the "least loaded" CPU (that is, the one that has the fewer LPIs mapped to it). So called 'managed' interrupts are an interesting case where the affinity is actually dictated by the kernel itself, and we should honor this. * From v2: - Split accounting from CPU selection - Track managed and unmanaged interrupts separately Marc Zyngier (2): irqchip/gic-v3-its: Track LPI distribution on a per CPU basis irqchip/gic-v3-its: Balance initial LPI affinity across CPUs drivers/irqchip/irq-gic-v3-its.c | 153 +++++++++++++++++++++++++------ 1 file changed, 127 insertions(+), 26 deletions(-) -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Jason Cooper <jason@lakedaemon.net>, chenxiang <chenxiang66@hisilicon.com>, John Garry <john.garry@huawei.com>, Ming Lei <ming.lei@redhat.com>, Zhou Wang <wangzhou1@hisilicon.com>, Thomas Gleixner <tglx@linutronix.de> Subject: [PATCH v3 0/2] irqchip/gic-v3-its: Balance LPI affinity across CPUs Date: Mon, 16 Mar 2020 11:54:31 +0000 [thread overview] Message-ID: <20200316115433.9017-1-maz@kernel.org> (raw) When mapping a LPI, the ITS driver picks the first possible affinity, which is in most cases CPU0, assuming that if that's not suitable, someone will come and set the affinity to something more interesting. It apparently isn't the case, and people complain of poor performance when many interrupts are glued to the same CPU. So let's place the interrupts by finding the "least loaded" CPU (that is, the one that has the fewer LPIs mapped to it). So called 'managed' interrupts are an interesting case where the affinity is actually dictated by the kernel itself, and we should honor this. * From v2: - Split accounting from CPU selection - Track managed and unmanaged interrupts separately Marc Zyngier (2): irqchip/gic-v3-its: Track LPI distribution on a per CPU basis irqchip/gic-v3-its: Balance initial LPI affinity across CPUs drivers/irqchip/irq-gic-v3-its.c | 153 +++++++++++++++++++++++++------ 1 file changed, 127 insertions(+), 26 deletions(-) -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2020-03-16 11:54 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-16 11:54 Marc Zyngier [this message] 2020-03-16 11:54 ` [PATCH v3 0/2] irqchip/gic-v3-its: Balance LPI affinity across CPUs Marc Zyngier 2020-03-16 11:54 ` [PATCH v3 1/2] irqchip/gic-v3-its: Track LPI distribution on a per CPU basis Marc Zyngier 2020-03-16 11:54 ` Marc Zyngier 2020-03-16 11:54 ` [PATCH v3 2/2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs Marc Zyngier 2020-03-16 11:54 ` Marc Zyngier 2020-03-16 13:02 ` John Garry 2020-03-16 13:02 ` John Garry 2020-03-16 13:14 ` Marc Zyngier 2020-03-16 13:14 ` Marc Zyngier 2020-03-17 18:43 ` John Garry 2020-03-17 18:43 ` John Garry 2020-03-18 14:16 ` Marc Zyngier 2020-03-18 14:16 ` Marc Zyngier 2020-03-18 14:25 ` John Garry 2020-03-18 14:25 ` John Garry 2020-03-18 12:22 ` John Garry 2020-03-18 12:22 ` John Garry 2020-03-18 14:04 ` Marc Zyngier 2020-03-18 14:04 ` Marc Zyngier 2020-03-18 15:34 ` John Garry 2020-03-18 15:34 ` John Garry 2020-03-18 17:30 ` Marc Zyngier 2020-03-18 17:30 ` Marc Zyngier 2020-03-18 19:00 ` John Garry 2020-03-18 19:00 ` John Garry 2020-03-27 17:52 ` John Garry 2020-03-27 17:52 ` John Garry 2020-03-19 12:31 ` [PATCH v3 0/2] irqchip/gic-v3-its: Balance " John Garry 2020-03-19 12:31 ` John Garry 2020-03-27 17:47 ` John Garry 2020-03-27 17:47 ` John Garry 2020-04-01 11:33 ` John Garry 2020-04-01 11:33 ` John Garry 2020-05-14 12:05 ` John Garry 2020-05-14 12:05 ` John Garry 2020-05-15 10:14 ` Marc Zyngier 2020-05-15 10:14 ` Marc Zyngier 2020-05-15 11:50 ` John Garry 2020-05-15 11:50 ` John Garry 2020-05-15 15:37 ` Marc Zyngier 2020-05-15 15:37 ` Marc Zyngier 2020-05-15 16:15 ` John Garry 2020-05-15 16:15 ` John Garry
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200316115433.9017-1-maz@kernel.org \ --to=maz@kernel.org \ --cc=chenxiang66@hisilicon.com \ --cc=jason@lakedaemon.net \ --cc=john.garry@huawei.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=ming.lei@redhat.com \ --cc=tglx@linutronix.de \ --cc=wangzhou1@hisilicon.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.