[PATCH v6 0/4] Add initial i.MX8MQ support

[PATCH v6 0/4] Add initial i.MX8MQ support

[Philipp Zabel]

With the i.MX8MQ decoders in active use and the i.MX8MM power domain
support still up in the air, I think it makes sense to merge i.MX8MQ
Hantro support now and accept that i.MX8MM may or may not require
different bindings.

Patch 4 depends on [2] for the MAINTAINERS change.

Changes since v5 [1]:
 - Drop merged patches
 - Drop i.MX8MM bindings
 - Change example node name to video-codec
 - Convert i.MX8MQ bindings to YAML
 - Drop i.MX8MM support
 - Rebase onto media/master
 - Enable h.264 and VP8 decoding
 - Enable post-processing

[1] https://lore.kernel.org/linux-media/20190612093915.18973-1-p.zabel@pengutronix.de
[2] https://lore.kernel.org/linux-media/20200318132108.21873-9-ezequiel@collabora.com

regards
Philipp

Philipp Zabel (4):
  media: dt-bindings: Document i.MX8MQ VPU bindings
  media: hantro: add initial i.MX8MQ support
  arm64: dts: imx8mq: enable Hantro G1/G2 VPU
  media: MAINTAINERS: add myself to co-maintain Hantro G1/G2 for i.MX8MQ

 .../bindings/media/nxp,imx8mq-vpu.yaml        |  77 ++++++
 MAINTAINERS                                   |   2 +
 arch/arm64/boot/dts/freescale/imx8mq.dtsi     |  27 +++
 drivers/staging/media/hantro/Kconfig          |  16 +-
 drivers/staging/media/hantro/Makefile         |   3 +
 drivers/staging/media/hantro/hantro_drv.c     |   3 +
 drivers/staging/media/hantro/hantro_hw.h      |   1 +
 drivers/staging/media/hantro/imx8m_vpu_hw.c   | 220 ++++++++++++++++++
 8 files changed, 345 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
 create mode 100644 drivers/staging/media/hantro/imx8m_vpu_hw.c

-- 
2.20.1

[PATCH v6 1/4] media: dt-bindings: Document i.MX8MQ VPU bindings

[Philipp Zabel]

Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
Changes since v5:
 - Drop i.MX8MM bindings
 - Change example node name to video-codec
 - Convert to YAML
---
 .../bindings/media/nxp,imx8mq-vpu.yaml        | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml

diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
new file mode 100644
index 000000000000..a2d1cd77c1e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs
+
+maintainers:
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+  Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.
+
+properties:
+  compatible:
+    const: nxp,imx8mq-vpu
+
+  reg:
+    maxItems: 3
+
+  reg-names:
+    items:
+      - const: g1
+      - const: g2
+      - const: ctrl
+
+  interrupts:
+    maxItems: 2
+
+  interrupt-names:
+    items:
+      - const: g1
+      - const: g2
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: g1
+      - const: g2
+      - const: bus
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+
+examples:
+  - |
+        #include <dt-bindings/clock/imx8mq-clock.h>
+        #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+        vpu: video-codec@38300000 {
+                compatible = "nxp,imx8mq-vpu";
+                reg = <0x38300000 0x10000>,
+                      <0x38310000 0x10000>,
+                      <0x38320000 0x10000>;
+                reg-names = "g1", "g2", "ctrl";
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "g1", "g2";
+                clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+                         <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+                         <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+                clock-names = "g1", "g2", "bus";
+                power-domains = <&pgc_vpu>;
+        };
-- 
2.20.1

[PATCH v6 2/4] media: hantro: add initial i.MX8MQ support

[Philipp Zabel]

This enables h.264, MPEG-2, and VP8 decoding on the Hantro G1 on
i.MX8MQ, with post-processing support.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
Changes since v5:
 - Rebase onto media/master
 - Enable h.264 and VP8 decoding
 - Enable post-processing
---
 drivers/staging/media/hantro/Kconfig        |  16 +-
 drivers/staging/media/hantro/Makefile       |   3 +
 drivers/staging/media/hantro/hantro_drv.c   |   3 +
 drivers/staging/media/hantro/hantro_hw.h    |   1 +
 drivers/staging/media/hantro/imx8m_vpu_hw.c | 220 ++++++++++++++++++++
 5 files changed, 239 insertions(+), 4 deletions(-)
 create mode 100644 drivers/staging/media/hantro/imx8m_vpu_hw.c

diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig
index de77fe6554e7..99aed9a5b0b9 100644
--- a/drivers/staging/media/hantro/Kconfig
+++ b/drivers/staging/media/hantro/Kconfig
@@ -1,19 +1,27 @@
 # SPDX-License-Identifier: GPL-2.0
 config VIDEO_HANTRO
 	tristate "Hantro VPU driver"
-	depends on ARCH_ROCKCHIP || COMPILE_TEST
+	depends on ARCH_MXC || ARCH_ROCKCHIP || COMPILE_TEST
 	depends on VIDEO_DEV && VIDEO_V4L2 && MEDIA_CONTROLLER
 	depends on MEDIA_CONTROLLER_REQUEST_API
 	select VIDEOBUF2_DMA_CONTIG
 	select VIDEOBUF2_VMALLOC
 	select V4L2_MEM2MEM_DEV
 	help
-	  Support for the Hantro IP based Video Processing Unit present on
-	  Rockchip SoC, which accelerates video and image encoding and
-	  decoding.
+	  Support for the Hantro IP based Video Processing Units present on
+	  Rockchip and NXP i.MX8M SoCs, which accelerate video and image
+	  encoding and decoding.
 	  To compile this driver as a module, choose M here: the module
 	  will be called hantro-vpu.
 
+config VIDEO_HANTRO_IMX8M
+	bool "Hantro VPU i.MX8M support"
+	depends on VIDEO_HANTRO
+	depends on ARCH_MXC || COMPILE_TEST
+	default y
+	help
+	  Enable support for i.MX8M SoCs.
+
 config VIDEO_HANTRO_ROCKCHIP
 	bool "Hantro VPU Rockchip support"
 	depends on VIDEO_HANTRO
diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile
index 496b30c3c396..68c29a9c4946 100644
--- a/drivers/staging/media/hantro/Makefile
+++ b/drivers/staging/media/hantro/Makefile
@@ -16,6 +16,9 @@ hantro-vpu-y += \
 		hantro_mpeg2.o \
 		hantro_vp8.o
 
+hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \
+		imx8m_vpu_hw.o
+
 hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
 		rk3288_vpu_hw.o \
 		rk3399_vpu_hw.o
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index bd204da6c669..c990accc0777 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -479,6 +479,9 @@ static const struct of_device_id of_hantro_match[] = {
 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
 	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
 	{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
+#endif
+#ifdef CONFIG_VIDEO_HANTRO_IMX8M
+	{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index 435f30ae89fd..4053d8710e04 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -155,6 +155,7 @@ enum hantro_enc_fmt {
 extern const struct hantro_variant rk3399_vpu_variant;
 extern const struct hantro_variant rk3328_vpu_variant;
 extern const struct hantro_variant rk3288_vpu_variant;
+extern const struct hantro_variant imx8mq_vpu_variant;
 
 extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
 
diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
new file mode 100644
index 000000000000..cb2420c5526e
--- /dev/null
+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Hantro VPU codec driver
+ *
+ * Copyright (C) 2019 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include "hantro.h"
+#include "hantro_jpeg.h"
+#include "hantro_g1_regs.h"
+
+#define CTRL_SOFT_RESET		0x00
+#define RESET_G1		BIT(1)
+#define RESET_G2		BIT(0)
+
+#define CTRL_CLOCK_ENABLE	0x04
+#define CLOCK_G1		BIT(1)
+#define CLOCK_G2		BIT(0)
+
+#define CTRL_G1_DEC_FUSE	0x08
+#define CTRL_G1_PP_FUSE		0x0c
+#define CTRL_G2_DEC_FUSE	0x10
+
+static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits)
+{
+	u32 val;
+
+	/* Assert */
+	val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
+	val &= ~reset_bits;
+	writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
+
+	udelay(2);
+
+	/* Release */
+	val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
+	val |= reset_bits;
+	writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
+}
+
+static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits)
+{
+	u32 val;
+
+	val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE);
+	val |= clock_bits;
+	writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);
+}
+
+static int imx8mq_runtime_resume(struct hantro_dev *vpu)
+{
+	int ret;
+
+	ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);
+	if (ret) {
+		dev_err(vpu->dev, "Failed to enable clocks\n");
+		return ret;
+	}
+
+	imx8m_soft_reset(vpu, RESET_G1 | RESET_G2);
+	imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2);
+
+	/* Set values of the fuse registers */
+	writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE);
+	writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE);
+	writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE);
+
+	clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);
+
+	return 0;
+}
+
+/*
+ * Supported formats.
+ */
+
+static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = {
+	{
+		.fourcc = V4L2_PIX_FMT_YUYV,
+		.codec_mode = HANTRO_MODE_NONE,
+	},
+};
+
+static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
+	{
+		.fourcc = V4L2_PIX_FMT_NV12,
+		.codec_mode = HANTRO_MODE_NONE,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
+		.codec_mode = HANTRO_MODE_MPEG2_DEC,
+		.max_depth = 2,
+		.frmsize = {
+			.min_width = 48,
+			.max_width = 1920,
+			.step_width = MB_DIM,
+			.min_height = 48,
+			.max_height = 1088,
+			.step_height = MB_DIM,
+		},
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
+		.codec_mode = HANTRO_MODE_VP8_DEC,
+		.max_depth = 2,
+		.frmsize = {
+			.min_width = 48,
+			.max_width = 3840,
+			.step_width = 16,
+			.min_height = 48,
+			.max_height = 2160,
+			.step_height = 16,
+		},
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_H264_SLICE,
+		.codec_mode = HANTRO_MODE_H264_DEC,
+		.max_depth = 2,
+		.frmsize = {
+			.min_width = 48,
+			.max_width = 3840,
+			.step_width = MB_DIM,
+			.min_height = 48,
+			.max_height = 2160,
+			.step_height = MB_DIM,
+		},
+	},
+};
+
+static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
+{
+	struct hantro_dev *vpu = dev_id;
+	enum vb2_buffer_state state;
+	u32 status;
+
+	status = vdpu_read(vpu, G1_REG_INTERRUPT);
+	state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?
+		 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
+
+	vdpu_write(vpu, 0, G1_REG_INTERRUPT);
+	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
+
+	hantro_irq_done(vpu, 0, state);
+
+	return IRQ_HANDLED;
+}
+
+static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
+{
+	vpu->dec_base = vpu->reg_bases[0];
+	vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];
+
+	return 0;
+}
+
+static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx)
+{
+	struct hantro_dev *vpu = ctx->dev;
+
+	imx8m_soft_reset(vpu, RESET_G1);
+}
+
+/*
+ * Supported codec ops.
+ */
+
+static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = {
+	[HANTRO_MODE_MPEG2_DEC] = {
+		.run = hantro_g1_mpeg2_dec_run,
+		.reset = imx8m_vpu_g1_reset,
+		.init = hantro_mpeg2_dec_init,
+		.exit = hantro_mpeg2_dec_exit,
+	},
+	[HANTRO_MODE_VP8_DEC] = {
+		.run = hantro_g1_vp8_dec_run,
+		.reset = imx8m_vpu_g1_reset,
+		.init = hantro_vp8_dec_init,
+		.exit = hantro_vp8_dec_exit,
+	},
+	[HANTRO_MODE_H264_DEC] = {
+		.run = hantro_g1_h264_dec_run,
+		.reset = imx8m_vpu_g1_reset,
+		.init = hantro_h264_dec_init,
+		.exit = hantro_h264_dec_exit,
+	},
+};
+
+/*
+ * VPU variants.
+ */
+
+static const struct hantro_irq imx8mq_irqs[] = {
+	{ "g1", imx8m_vpu_g1_irq },
+	{ "g2", NULL /* TODO: imx8m_vpu_g2_irq */ },
+};
+
+static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
+static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" };
+
+const struct hantro_variant imx8mq_vpu_variant = {
+	.dec_fmts = imx8m_vpu_dec_fmts,
+	.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
+	.postproc_fmts = imx8m_vpu_postproc_fmts,
+	.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
+	.postproc_regs = &hantro_g1_postproc_regs,
+	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
+		 HANTRO_H264_DECODER,
+	.codec_ops = imx8mq_vpu_codec_ops,
+	.init = imx8mq_vpu_hw_init,
+	.runtime_resume = imx8mq_runtime_resume,
+	.irqs = imx8mq_irqs,
+	.num_irqs = ARRAY_SIZE(imx8mq_irqs),
+	.clk_names = imx8mq_clk_names,
+	.num_clocks = ARRAY_SIZE(imx8mq_clk_names),
+	.reg_names = imx8mq_reg_names,
+	.num_regs = ARRAY_SIZE(imx8mq_reg_names)
+};
-- 
2.20.1

[PATCH v6 3/4] arm64: dts: imx8mq: enable Hantro G1/G2 VPU

[Philipp Zabel]

Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
decoder cores and a reset/control block.

Hook up the bus clock to the VPU power domain to enable handshakes, and
configure the core clocks to 600 MHz and the bus clock to 800 MHz by
default.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
New in v6.
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a1e83922c71..98e464ecb68a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -666,6 +666,7 @@
 					pgc_vpu: power-domain@6 {
 						#power-domain-cells = <0>;
 						reg = <IMX8M_POWER_DOMAIN_VPU>;
+						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
 					};
 
 					pgc_disp: power-domain@7 {
@@ -1130,6 +1131,32 @@
 			status = "disabled";
 		};
 
+		vpu: video-codec@38300000 {
+			compatible = "nxp,imx8mq-vpu";
+			reg = <0x38300000 0x10000>,
+			      <0x38310000 0x10000>,
+			      <0x38320000 0x10000>;
+			reg-names = "g1", "g2", "ctrl";
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "g1", "g2";
+			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+			clock-names = "g1", "g2", "bus";
+			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+					  <&clk IMX8MQ_CLK_VPU_G2>,
+					  <&clk IMX8MQ_CLK_VPU_BUS>,
+					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
+			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+						 <&clk IMX8MQ_VPU_PLL_OUT>,
+						 <&clk IMX8MQ_SYS1_PLL_800M>,
+						 <&clk IMX8MQ_VPU_PLL>;
+			assigned-clock-rates = <600000000>, <600000000>,
+					       <800000000>, <0>;
+			power-domains = <&pgc_vpu>;
+		};
+
 		pcie0: pcie@33800000 {
 			compatible = "fsl,imx8mq-pcie";
 			reg = <0x33800000 0x400000>,
-- 
2.20.1

[PATCH v6 4/4] media: MAINTAINERS: add myself to co-maintain Hantro G1/G2 for i.MX8MQ

[Philipp Zabel]

Add path and co-maintainer entry for i.MX8MQ device tree bindings.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
New in v6.
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 46c95dc8ab5f..2b8b3e7f3df3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14314,10 +14314,12 @@ F:	Documentation/devicetree/bindings/media/rockchip-rga.txt
 
 HANTRO VPU CODEC DRIVER
 M:	Ezequiel Garcia <ezequiel@collabora.com>
+M:	Philipp Zabel <p.zabel@pengutronix.de>
 L:	linux-media@vger.kernel.org
 L:	linux-rockchip@lists.infradead.org
 S:	Maintained
 F:	drivers/staging/media/hantro/
+F:	Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
 F:	Documentation/devicetree/bindings/media/rockchip-vpu.yaml
 
 ROCKER DRIVER
-- 
2.20.1

Re: [PATCH v6 1/4] media: dt-bindings: Document i.MX8MQ VPU bindings

[Rob Herring]

On Fri, 20 Mar 2020 14:12:53 +0100, Philipp Zabel wrote:
> Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
> Changes since v5:
>  - Drop i.MX8MM bindings
>  - Change example node name to video-codec
>  - Convert to YAML
> ---
>  .../bindings/media/nxp,imx8mq-vpu.yaml        | 77 +++++++++++++++++++
>  1 file changed, 77 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v6 0/4] Add initial i.MX8MQ support

[Ezequiel Garcia]

Hi Philipp,

Tested on the EVK, looks great.

On Fri, 2020-03-20 at 14:12 +0100, Philipp Zabel wrote:
> With the i.MX8MQ decoders in active use and the i.MX8MM power domain
> support still up in the air, I think it makes sense to merge i.MX8MQ
> Hantro support now and accept that i.MX8MM may or may not require
> different bindings.
> 
> Patch 4 depends on [2] for the MAINTAINERS change.
> 

Thanks a lot for stepping up and helping to maintain
the driver!

For all patches:

Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>

> Changes since v5 [1]:
>  - Drop merged patches
>  - Drop i.MX8MM bindings
>  - Change example node name to video-codec
>  - Convert i.MX8MQ bindings to YAML
>  - Drop i.MX8MM support
>  - Rebase onto media/master
>  - Enable h.264 and VP8 decoding
>  - Enable post-processing
> 
> [1] https://lore.kernel.org/linux-media/20190612093915.18973-1-p.zabel@pengutronix.de
> [2] https://lore.kernel.org/linux-media/20200318132108.21873-9-ezequiel@collabora.com
> 
> regards
> Philipp
> 
> Philipp Zabel (4):
>   media: dt-bindings: Document i.MX8MQ VPU bindings
>   media: hantro: add initial i.MX8MQ support
>   arm64: dts: imx8mq: enable Hantro G1/G2 VPU
>   media: MAINTAINERS: add myself to co-maintain Hantro G1/G2 for i.MX8MQ
> 
>  .../bindings/media/nxp,imx8mq-vpu.yaml        |  77 ++++++
>  MAINTAINERS                                   |   2 +
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi     |  27 +++
>  drivers/staging/media/hantro/Kconfig          |  16 +-
>  drivers/staging/media/hantro/Makefile         |   3 +
>  drivers/staging/media/hantro/hantro_drv.c     |   3 +
>  drivers/staging/media/hantro/hantro_hw.h      |   1 +
>  drivers/staging/media/hantro/imx8m_vpu_hw.c   | 220 ++++++++++++++++++
>  8 files changed, 345 insertions(+), 4 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
>  create mode 100644 drivers/staging/media/hantro/imx8m_vpu_hw.c
> 

Re: [PATCH v6 3/4] arm64: dts: imx8mq: enable Hantro G1/G2 VPU

[Philipp Zabel]

Hi Shawn,

On Fri, 2020-03-20 at 14:12 +0100, Philipp Zabel wrote:
> Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
> decoder cores and a reset/control block.
> 
> Hook up the bus clock to the VPU power domain to enable handshakes, and
> configure the core clocks to 600 MHz and the bus clock to 800 MHz by
> default.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

could you pick up this patch? The driver and binding parts have been
merged in media/master.

regards
Philipp

> ---
> New in v6.
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 6a1e83922c71..98e464ecb68a 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -666,6 +666,7 @@
>  					pgc_vpu: power-domain@6 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8M_POWER_DOMAIN_VPU>;
> +						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
>  					};
>  
>  					pgc_disp: power-domain@7 {
> @@ -1130,6 +1131,32 @@
>  			status = "disabled";
>  		};
>  
> +		vpu: video-codec@38300000 {
> +			compatible = "nxp,imx8mq-vpu";
> +			reg = <0x38300000 0x10000>,
> +			      <0x38310000 0x10000>,
> +			      <0x38320000 0x10000>;
> +			reg-names = "g1", "g2", "ctrl";
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "g1", "g2";
> +			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> +				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +			clock-names = "g1", "g2", "bus";
> +			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> +					  <&clk IMX8MQ_CLK_VPU_G2>,
> +					  <&clk IMX8MQ_CLK_VPU_BUS>,
> +					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
> +			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> +						 <&clk IMX8MQ_VPU_PLL_OUT>,
> +						 <&clk IMX8MQ_SYS1_PLL_800M>,
> +						 <&clk IMX8MQ_VPU_PLL>;
> +			assigned-clock-rates = <600000000>, <600000000>,
> +					       <800000000>, <0>;
> +			power-domains = <&pgc_vpu>;
> +		};
> +
>  		pcie0: pcie@33800000 {
>  			compatible = "fsl,imx8mq-pcie";
>  			reg = <0x33800000 0x400000>,

Re: [PATCH v6 3/4] arm64: dts: imx8mq: enable Hantro G1/G2 VPU

[Ezequiel Garcia]

On Wed, 2020-05-27 at 18:19 +0200, Philipp Zabel wrote:
> Hi Shawn,
> 
> On Fri, 2020-03-20 at 14:12 +0100, Philipp Zabel wrote:
> > Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
> > decoder cores and a reset/control block.
> > 
> > Hook up the bus clock to the VPU power domain to enable handshakes, and
> > configure the core clocks to 600 MHz and the bus clock to 800 MHz by
> > default.
> > 
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> 
> could you pick up this patch? The driver and binding parts have been
> merged in media/master.
> 

Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>

It looks good and it matches the downstream device tree.

Thanks,
Ezequiel

> regards
> Philipp
> 
> > ---
> > New in v6.
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 6a1e83922c71..98e464ecb68a 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -666,6 +666,7 @@
> >  					pgc_vpu: power-domain@6 {
> >  						#power-domain-cells = <0>;
> >  						reg = <IMX8M_POWER_DOMAIN_VPU>;
> > +						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> >  					};
> >  
> >  					pgc_disp: power-domain@7 {
> > @@ -1130,6 +1131,32 @@
> >  			status = "disabled";
> >  		};
> >  
> > +		vpu: video-codec@38300000 {
> > +			compatible = "nxp,imx8mq-vpu";
> > +			reg = <0x38300000 0x10000>,
> > +			      <0x38310000 0x10000>,
> > +			      <0x38320000 0x10000>;
> > +			reg-names = "g1", "g2", "ctrl";
> > +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "g1", "g2";
> > +			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > +				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > +				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > +			clock-names = "g1", "g2", "bus";
> > +			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > +					  <&clk IMX8MQ_CLK_VPU_G2>,
> > +					  <&clk IMX8MQ_CLK_VPU_BUS>,
> > +					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > +			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > +						 <&clk IMX8MQ_VPU_PLL_OUT>,
> > +						 <&clk IMX8MQ_SYS1_PLL_800M>,
> > +						 <&clk IMX8MQ_VPU_PLL>;
> > +			assigned-clock-rates = <600000000>, <600000000>,
> > +					       <800000000>, <0>;
> > +			power-domains = <&pgc_vpu>;
> > +		};
> > +
> >  		pcie0: pcie@33800000 {
> >  			compatible = "fsl,imx8mq-pcie";
> >  			reg = <0x33800000 0x400000>,

Re: [PATCH v6 3/4] arm64: dts: imx8mq: enable Hantro G1/G2 VPU

[Ezequiel Garcia]

Hello Shawn,

Gentle ping.

Thanks a lot!
Ezequiel

On Wed, 27 May 2020 at 22:02, Ezequiel Garcia <ezequiel@collabora.com> wrote:
>
> On Wed, 2020-05-27 at 18:19 +0200, Philipp Zabel wrote:
> > Hi Shawn,
> >
> > On Fri, 2020-03-20 at 14:12 +0100, Philipp Zabel wrote:
> > > Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
> > > decoder cores and a reset/control block.
> > >
> > > Hook up the bus clock to the VPU power domain to enable handshakes, and
> > > configure the core clocks to 600 MHz and the bus clock to 800 MHz by
> > > default.
> > >
> > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> >
> > could you pick up this patch? The driver and binding parts have been
> > merged in media/master.
> >
>
> Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
> Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
>
> It looks good and it matches the downstream device tree.
>
> Thanks,
> Ezequiel
>
> > regards
> > Philipp
> >
> > > ---
> > > New in v6.
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++
> > >  1 file changed, 27 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > index 6a1e83922c71..98e464ecb68a 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > @@ -666,6 +666,7 @@
> > >                                     pgc_vpu: power-domain@6 {
> > >                                             #power-domain-cells = <0>;
> > >                                             reg = <IMX8M_POWER_DOMAIN_VPU>;
> > > +                                           clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > >                                     };
> > >
> > >                                     pgc_disp: power-domain@7 {
> > > @@ -1130,6 +1131,32 @@
> > >                     status = "disabled";
> > >             };
> > >
> > > +           vpu: video-codec@38300000 {
> > > +                   compatible = "nxp,imx8mq-vpu";
> > > +                   reg = <0x38300000 0x10000>,
> > > +                         <0x38310000 0x10000>,
> > > +                         <0x38320000 0x10000>;
> > > +                   reg-names = "g1", "g2", "ctrl";
> > > +                   interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > > +                   interrupt-names = "g1", "g2";
> > > +                   clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > +                            <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > +                            <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > +                   clock-names = "g1", "g2", "bus";
> > > +                   assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > > +                                     <&clk IMX8MQ_CLK_VPU_G2>,
> > > +                                     <&clk IMX8MQ_CLK_VPU_BUS>,
> > > +                                     <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > +                   assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +                                            <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +                                            <&clk IMX8MQ_SYS1_PLL_800M>,
> > > +                                            <&clk IMX8MQ_VPU_PLL>;
> > > +                   assigned-clock-rates = <600000000>, <600000000>,
> > > +                                          <800000000>, <0>;
> > > +                   power-domains = <&pgc_vpu>;
> > > +           };
> > > +
> > >             pcie0: pcie@33800000 {
> > >                     compatible = "fsl,imx8mq-pcie";
> > >                     reg = <0x33800000 0x400000>,
>
>

Re: [PATCH v6 3/4] arm64: dts: imx8mq: enable Hantro G1/G2 VPU

[Shawn Guo]

On Fri, Mar 20, 2020 at 02:12:55PM +0100, Philipp Zabel wrote:
> Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
> decoder cores and a reset/control block.
> 
> Hook up the bus clock to the VPU power domain to enable handshakes, and
> configure the core clocks to 600 MHz and the bus clock to 800 MHz by
> default.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Applied, thanks.