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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
	Julien Grall <julien@xen.org>, Wei Liu <wl@xen.org>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	Ian Jackson <ian.jackson@eu.citrix.com>,
	George Dunlap <george.dunlap@citrix.com>,
	Tim Deegan <tim@xen.org>,
	xen-devel@lists.xenproject.org
Subject: Re: [Xen-devel] [PATCH v7 1/3] x86/tlb: introduce a flush HVM ASIDs flag
Date: Fri, 20 Mar 2020 16:05:37 +0100	[thread overview]
Message-ID: <20200320150537.GA24458@Air-de-Roger.citrite.net> (raw)
In-Reply-To: <b5766ee3-90d3-7da8-c01a-eb538790c896@suse.com>

On Fri, Mar 20, 2020 at 03:59:35PM +0100, Jan Beulich wrote:
> On 20.03.2020 15:49, Roger Pau Monné wrote:
> > On Fri, Mar 20, 2020 at 02:27:36PM +0000, Julien Grall wrote:
> >>
> >>
> >> On 20/03/2020 14:22, Roger Pau Monné wrote:
> >>> static inline void filtered_flush_tlb_mask(uint32_t tlbflush_timestamp)
> >>> {
> >>>      cpumask_t mask;
> >>>
> >>>      cpumask_copy(&mask, &cpu_online_map);
> >>>      tlbflush_filter(&mask, tlbflush_timestamp);
> >>>      if ( !cpumask_empty(&mask) )
> >>>      {
> >>>          perfc_incr(need_flush_tlb_flush);
> >>> #if CONFIG_X86
> >>>          /*
> >>>           * filtered_flush_tlb_mask is used after modifying the p2m in
> >>>           * populate_physmap, Xen needs to trigger an ASID tickle as this is a
> >>>           * requirement on AMD hardware.
> >>>           */
> >>
> >> I don't think this comment is correct. populate_physmap() is only going to
> >> add entry in the P2M and therefore flush should not be needed.
> > 
> > Since this is strictly only adding entries I think you are right and
> > the ASID tickle could be avoided, as long as we can assert the gfn was
> > empty (or didn't have the valid bit set) previous to being populated.
> 
> While this may be true for x86, it's not guaranteed in general
> that non-present translations may not also be put into TLBs.
> So from common code there shouldn't be assumptions like this.

But as pointed out by Julien filtered_flush_tlb_mask is exclusively
used in combination with accumulate_tlbflush, which only cares about
the need_tlbflush in the page struct, and hence if pages added to the
physmap didn't had an owner you won't end up calling
filtered_flush_tlb_mask at all.

So the ASID tickle must be performed somewhere else, because gating
the ASID flush on whether the page had a previous owner is not
correct.

Thanks, Roger.

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  reply	other threads:[~2020-03-20 15:06 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-19 15:47 [Xen-devel] [PATCH v7 0/3] x86/guest: use assisted TLB flush in guest mode Roger Pau Monne
2020-03-19 15:47 ` [Xen-devel] [PATCH v7 1/3] x86/tlb: introduce a flush HVM ASIDs flag Roger Pau Monne
2020-03-19 16:21   ` Julien Grall
2020-03-19 17:38     ` Roger Pau Monné
2020-03-19 18:07       ` Julien Grall
2020-03-19 18:43         ` Roger Pau Monné
2020-03-19 19:07           ` Julien Grall
2020-03-20  7:21             ` Jan Beulich
2020-03-20  9:01               ` Roger Pau Monné
2020-03-20  9:12                 ` Julien Grall
2020-03-20  9:42                   ` Roger Pau Monné
2020-03-20 10:00                     ` Roger Pau Monné
2020-03-20 10:08                       ` Julien Grall
2020-03-20 10:24                         ` Roger Pau Monné
2020-03-20 10:36                           ` Julien Grall
2020-03-20 11:18                             ` Roger Pau Monné
2020-03-20 13:19                   ` Jan Beulich
2020-03-20 14:17                     ` Julien Grall
2020-03-20 14:56                       ` Jan Beulich
2020-03-20 13:16                 ` Jan Beulich
2020-03-20 14:22                   ` Roger Pau Monné
2020-03-20 14:27                     ` Julien Grall
2020-03-20 14:43                       ` Julien Grall
2020-03-20 14:52                         ` Roger Pau Monné
2020-03-20 14:49                       ` Roger Pau Monné
2020-03-20 14:59                         ` Jan Beulich
2020-03-20 15:05                           ` Roger Pau Monné [this message]
2020-03-19 15:47 ` [Xen-devel] [PATCH v7 2/3] x86/tlb: allow disabling the TLB clock Roger Pau Monne
2020-03-19 15:47 ` [Xen-devel] [PATCH v7 3/3] x86/tlb: use Xen L0 assisted TLB flush when available Roger Pau Monne

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