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* [PATCH] riscv: mm: synchronize MMU after page table update
@ 2020-03-24  5:49 ` Nick Hu
  0 siblings, 0 replies; 6+ messages in thread
From: Nick Hu @ 2020-03-24  5:49 UTC (permalink / raw)
  To: paul.walmsley, palmer, aou, guoren, akpm, rppt, nickhu,
	mark.rutland, nylon7, alankao, alexios.zavras, tglx, npiggin,
	anup, zong.li, linux-riscv, linux-kernel

Similar to commit bf587caae305 ("riscv: mm: synchronize MMU after pte change")

For those riscv implementations whose TLB cannot synchronize with dcache,
an SFENCE.VMA is necessary after page table update.
This patch fixed two functions:

1. pgd_alloc
During fork, a parent process prepares pgd for its child and updates satp
later, but they may not run on the same core. Adding a remote SFENCE.VMA to
invalidate TLB in other cores is needed. Thus use flush_tlb_all() instead
of local_flush_tlb_all() here.
Similar approaches can be found in arm and csky.

2. __set_fixmap
Add a SFENCE.VMA after fixmap pte update.
Similar approaches can be found in arm and sh.

Signed-off-by: Nick Hu <nickhu@andestech.com>
Signed-off-by: Nylon Chen <nylon7@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
---
 arch/riscv/include/asm/pgalloc.h | 1 +
 arch/riscv/mm/init.c             | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
index 3f601ee8233f..071468fa14b7 100644
--- a/arch/riscv/include/asm/pgalloc.h
+++ b/arch/riscv/include/asm/pgalloc.h
@@ -51,6 +51,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 		memcpy(pgd + USER_PTRS_PER_PGD,
 			init_mm.pgd + USER_PTRS_PER_PGD,
 			(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+		flush_tlb_all();
 	}
 	return pgd;
 }
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index fab855963c73..a7f329503ed0 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -203,8 +203,8 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
 		set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
 	} else {
 		pte_clear(&init_mm, addr, ptep);
-		local_flush_tlb_page(addr);
 	}
+	local_flush_tlb_page(addr);
 }
 
 static pte_t *__init get_pte_virt(phys_addr_t pa)
-- 
2.17.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] riscv: mm: synchronize MMU after page table update
@ 2020-03-24  5:49 ` Nick Hu
  0 siblings, 0 replies; 6+ messages in thread
From: Nick Hu @ 2020-03-24  5:49 UTC (permalink / raw)
  To: paul.walmsley, palmer, aou, guoren, akpm, rppt, nickhu,
	mark.rutland, nylon7, alankao, alexios.zavras, tglx, npiggin,
	anup, zong.li, linux-riscv, linux-kernel

Similar to commit bf587caae305 ("riscv: mm: synchronize MMU after pte change")

For those riscv implementations whose TLB cannot synchronize with dcache,
an SFENCE.VMA is necessary after page table update.
This patch fixed two functions:

1. pgd_alloc
During fork, a parent process prepares pgd for its child and updates satp
later, but they may not run on the same core. Adding a remote SFENCE.VMA to
invalidate TLB in other cores is needed. Thus use flush_tlb_all() instead
of local_flush_tlb_all() here.
Similar approaches can be found in arm and csky.

2. __set_fixmap
Add a SFENCE.VMA after fixmap pte update.
Similar approaches can be found in arm and sh.

Signed-off-by: Nick Hu <nickhu@andestech.com>
Signed-off-by: Nylon Chen <nylon7@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
---
 arch/riscv/include/asm/pgalloc.h | 1 +
 arch/riscv/mm/init.c             | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
index 3f601ee8233f..071468fa14b7 100644
--- a/arch/riscv/include/asm/pgalloc.h
+++ b/arch/riscv/include/asm/pgalloc.h
@@ -51,6 +51,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 		memcpy(pgd + USER_PTRS_PER_PGD,
 			init_mm.pgd + USER_PTRS_PER_PGD,
 			(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+		flush_tlb_all();
 	}
 	return pgd;
 }
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index fab855963c73..a7f329503ed0 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -203,8 +203,8 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
 		set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
 	} else {
 		pte_clear(&init_mm, addr, ptep);
-		local_flush_tlb_page(addr);
 	}
+	local_flush_tlb_page(addr);
 }
 
 static pte_t *__init get_pte_virt(phys_addr_t pa)
-- 
2.17.0



^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: mm: synchronize MMU after page table update
  2020-03-24  5:49 ` Nick Hu
@ 2020-03-24  6:38   ` Guo Ren
  -1 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2020-03-24  6:38 UTC (permalink / raw)
  To: Nick Hu
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton,
	Mike Rapoport, Mark Rutland, nylon7, Alan Kao, alexios.zavras,
	Thomas Gleixner, npiggin, Anup Patel, Zong Li, linux-riscv,
	Linux Kernel Mailing List

On Tue, Mar 24, 2020 at 1:50 PM Nick Hu <nickhu@andestech.com> wrote:
>
> Similar to commit bf587caae305 ("riscv: mm: synchronize MMU after pte change")
>
> For those riscv implementations whose TLB cannot synchronize with dcache,
> an SFENCE.VMA is necessary after page table update.
> This patch fixed two functions:
>
> 1. pgd_alloc
> During fork, a parent process prepares pgd for its child and updates satp
> later, but they may not run on the same core. Adding a remote SFENCE.VMA to
> invalidate TLB in other cores is needed. Thus use flush_tlb_all() instead
> of local_flush_tlb_all() here.
> Similar approaches can be found in arm and csky.
>
> 2. __set_fixmap
> Add a SFENCE.VMA after fixmap pte update.
> Similar approaches can be found in arm and sh.
>
> Signed-off-by: Nick Hu <nickhu@andestech.com>
> Signed-off-by: Nylon Chen <nylon7@andestech.com>
> Cc: Alan Kao <alankao@andestech.com>
> ---
>  arch/riscv/include/asm/pgalloc.h | 1 +
>  arch/riscv/mm/init.c             | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
> index 3f601ee8233f..071468fa14b7 100644
> --- a/arch/riscv/include/asm/pgalloc.h
> +++ b/arch/riscv/include/asm/pgalloc.h
> @@ -51,6 +51,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
>                 memcpy(pgd + USER_PTRS_PER_PGD,
>                         init_mm.pgd + USER_PTRS_PER_PGD,
>                         (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
> +               flush_tlb_all();
Are you sure to put a tlb flush operation here ? I think it should be
a dcache flush ops (but there is no solution for riscv ISA :P)

Ref to csky's implementation, just some old cores need sync dcache
with tlb by a simple dcache flush range ops and tlb ops should be put
in another place due to Linux infrastructure.

static inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
        pgd_t *ret;
        pgd_t *init;

        ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
        if (ret) {
                init = pgd_offset(&init_mm, 0UL);
                pgd_init((unsigned long *)ret);
                memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
                        (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
                /* prevent out of order excute */
                smp_mb();
#ifdef CONFIG_CPU_NEED_TLBSYNC
                dcache_wb_range((unsigned int)ret,
                                (unsigned int)(ret + PTRS_PER_PGD));
#endif
        }

        return ret;
}


>         }
>         return pgd;
>  }
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index fab855963c73..a7f329503ed0 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -203,8 +203,8 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
>                 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
>         } else {
>                 pte_clear(&init_mm, addr, ptep);
> -               local_flush_tlb_page(addr);
>         }
> +       local_flush_tlb_page(addr);
>  }
>
>  static pte_t *__init get_pte_virt(phys_addr_t pa)
> --
> 2.17.0
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: mm: synchronize MMU after page table update
@ 2020-03-24  6:38   ` Guo Ren
  0 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2020-03-24  6:38 UTC (permalink / raw)
  To: Nick Hu
  Cc: Mark Rutland, Albert Ou, Alan Kao, Anup Patel,
	Linux Kernel Mailing List, npiggin, Mike Rapoport,
	alexios.zavras, linux-riscv, Palmer Dabbelt, Zong Li,
	Paul Walmsley, Andrew Morton, nylon7, Thomas Gleixner

On Tue, Mar 24, 2020 at 1:50 PM Nick Hu <nickhu@andestech.com> wrote:
>
> Similar to commit bf587caae305 ("riscv: mm: synchronize MMU after pte change")
>
> For those riscv implementations whose TLB cannot synchronize with dcache,
> an SFENCE.VMA is necessary after page table update.
> This patch fixed two functions:
>
> 1. pgd_alloc
> During fork, a parent process prepares pgd for its child and updates satp
> later, but they may not run on the same core. Adding a remote SFENCE.VMA to
> invalidate TLB in other cores is needed. Thus use flush_tlb_all() instead
> of local_flush_tlb_all() here.
> Similar approaches can be found in arm and csky.
>
> 2. __set_fixmap
> Add a SFENCE.VMA after fixmap pte update.
> Similar approaches can be found in arm and sh.
>
> Signed-off-by: Nick Hu <nickhu@andestech.com>
> Signed-off-by: Nylon Chen <nylon7@andestech.com>
> Cc: Alan Kao <alankao@andestech.com>
> ---
>  arch/riscv/include/asm/pgalloc.h | 1 +
>  arch/riscv/mm/init.c             | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
> index 3f601ee8233f..071468fa14b7 100644
> --- a/arch/riscv/include/asm/pgalloc.h
> +++ b/arch/riscv/include/asm/pgalloc.h
> @@ -51,6 +51,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
>                 memcpy(pgd + USER_PTRS_PER_PGD,
>                         init_mm.pgd + USER_PTRS_PER_PGD,
>                         (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
> +               flush_tlb_all();
Are you sure to put a tlb flush operation here ? I think it should be
a dcache flush ops (but there is no solution for riscv ISA :P)

Ref to csky's implementation, just some old cores need sync dcache
with tlb by a simple dcache flush range ops and tlb ops should be put
in another place due to Linux infrastructure.

static inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
        pgd_t *ret;
        pgd_t *init;

        ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
        if (ret) {
                init = pgd_offset(&init_mm, 0UL);
                pgd_init((unsigned long *)ret);
                memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
                        (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
                /* prevent out of order excute */
                smp_mb();
#ifdef CONFIG_CPU_NEED_TLBSYNC
                dcache_wb_range((unsigned int)ret,
                                (unsigned int)(ret + PTRS_PER_PGD));
#endif
        }

        return ret;
}


>         }
>         return pgd;
>  }
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index fab855963c73..a7f329503ed0 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -203,8 +203,8 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
>                 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
>         } else {
>                 pte_clear(&init_mm, addr, ptep);
> -               local_flush_tlb_page(addr);
>         }
> +       local_flush_tlb_page(addr);
>  }
>
>  static pte_t *__init get_pte_virt(phys_addr_t pa)
> --
> 2.17.0
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: mm: synchronize MMU after page table update
  2020-03-24  5:49 ` Nick Hu
@ 2020-04-03 16:03   ` Palmer Dabbelt
  -1 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2020-04-03 16:03 UTC (permalink / raw)
  To: nickhu
  Cc: Paul Walmsley, aou, guoren, akpm, rppt, nickhu, mark.rutland,
	nylon7, alankao, alexios.zavras, tglx, npiggin, anup, zong.li,
	linux-riscv, linux-kernel

On Mon, 23 Mar 2020 22:49:45 PDT (-0700), nickhu@andestech.com wrote:
> Similar to commit bf587caae305 ("riscv: mm: synchronize MMU after pte change")
>
> For those riscv implementations whose TLB cannot synchronize with dcache,
> an SFENCE.VMA is necessary after page table update.
> This patch fixed two functions:
>
> 1. pgd_alloc
> During fork, a parent process prepares pgd for its child and updates satp
> later, but they may not run on the same core. Adding a remote SFENCE.VMA to
> invalidate TLB in other cores is needed. Thus use flush_tlb_all() instead
> of local_flush_tlb_all() here.
> Similar approaches can be found in arm and csky.
>
> 2. __set_fixmap
> Add a SFENCE.VMA after fixmap pte update.
> Similar approaches can be found in arm and sh.
>
> Signed-off-by: Nick Hu <nickhu@andestech.com>
> Signed-off-by: Nylon Chen <nylon7@andestech.com>
> Cc: Alan Kao <alankao@andestech.com>
> ---
>  arch/riscv/include/asm/pgalloc.h | 1 +
>  arch/riscv/mm/init.c             | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
> index 3f601ee8233f..071468fa14b7 100644
> --- a/arch/riscv/include/asm/pgalloc.h
> +++ b/arch/riscv/include/asm/pgalloc.h
> @@ -51,6 +51,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
>  		memcpy(pgd + USER_PTRS_PER_PGD,
>  			init_mm.pgd + USER_PTRS_PER_PGD,
>  			(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
> +		flush_tlb_all();
>  	}
>  	return pgd;
>  }
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index fab855963c73..a7f329503ed0 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -203,8 +203,8 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
>  		set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
>  	} else {
>  		pte_clear(&init_mm, addr, ptep);
> -		local_flush_tlb_page(addr);
>  	}
> +	local_flush_tlb_page(addr);
>  }
>
>  static pte_t *__init get_pte_virt(phys_addr_t pa)

As a general rule, any fences are supposed to have a comment describing why
they're there.  The generic fences will be caught by checkpatch, but I don't
remember if these are.

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: mm: synchronize MMU after page table update
@ 2020-04-03 16:03   ` Palmer Dabbelt
  0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2020-04-03 16:03 UTC (permalink / raw)
  To: nickhu
  Cc: mark.rutland, aou, alankao, nickhu, anup, linux-kernel, npiggin,
	rppt, alexios.zavras, linux-riscv, guoren, zong.li,
	Paul Walmsley, akpm, nylon7, tglx

On Mon, 23 Mar 2020 22:49:45 PDT (-0700), nickhu@andestech.com wrote:
> Similar to commit bf587caae305 ("riscv: mm: synchronize MMU after pte change")
>
> For those riscv implementations whose TLB cannot synchronize with dcache,
> an SFENCE.VMA is necessary after page table update.
> This patch fixed two functions:
>
> 1. pgd_alloc
> During fork, a parent process prepares pgd for its child and updates satp
> later, but they may not run on the same core. Adding a remote SFENCE.VMA to
> invalidate TLB in other cores is needed. Thus use flush_tlb_all() instead
> of local_flush_tlb_all() here.
> Similar approaches can be found in arm and csky.
>
> 2. __set_fixmap
> Add a SFENCE.VMA after fixmap pte update.
> Similar approaches can be found in arm and sh.
>
> Signed-off-by: Nick Hu <nickhu@andestech.com>
> Signed-off-by: Nylon Chen <nylon7@andestech.com>
> Cc: Alan Kao <alankao@andestech.com>
> ---
>  arch/riscv/include/asm/pgalloc.h | 1 +
>  arch/riscv/mm/init.c             | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
> index 3f601ee8233f..071468fa14b7 100644
> --- a/arch/riscv/include/asm/pgalloc.h
> +++ b/arch/riscv/include/asm/pgalloc.h
> @@ -51,6 +51,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
>  		memcpy(pgd + USER_PTRS_PER_PGD,
>  			init_mm.pgd + USER_PTRS_PER_PGD,
>  			(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
> +		flush_tlb_all();
>  	}
>  	return pgd;
>  }
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index fab855963c73..a7f329503ed0 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -203,8 +203,8 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
>  		set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
>  	} else {
>  		pte_clear(&init_mm, addr, ptep);
> -		local_flush_tlb_page(addr);
>  	}
> +	local_flush_tlb_page(addr);
>  }
>
>  static pte_t *__init get_pte_virt(phys_addr_t pa)

As a general rule, any fences are supposed to have a comment describing why
they're there.  The generic fences will be caught by checkpatch, but I don't
remember if these are.


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-04-03 16:03 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-24  5:49 [PATCH] riscv: mm: synchronize MMU after page table update Nick Hu
2020-03-24  5:49 ` Nick Hu
2020-03-24  6:38 ` Guo Ren
2020-03-24  6:38   ` Guo Ren
2020-04-03 16:03 ` Palmer Dabbelt
2020-04-03 16:03   ` Palmer Dabbelt

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