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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Cooper Chiou <cooper.chiou@intel.com>,
	Kai-Heng Feng <kai.heng.feng@canonical.com>
Subject: [Intel-gfx] [PATCH v3 2/6] drm/i915/display: Add intel_display_power_get_without_ack()
Date: Tue, 24 Mar 2020 13:14:25 -0700	[thread overview]
Message-ID: <20200324201429.29153-2-jose.souza@intel.com> (raw)
In-Reply-To: <20200324201429.29153-1-jose.souza@intel.com>

To implement ICL TC static sequences is required to get the port aux
powerwell without wait for hardware ack.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 71 +++++++++++++++----
 .../drm/i915/display/intel_display_power.h    | 12 ++++
 2 files changed, 71 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 246e406bb385..9035b220dfa0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -157,14 +157,24 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 	}
 }
 
-static void intel_power_well_enable(struct drm_i915_private *dev_priv,
-				    struct i915_power_well *power_well)
+static void _intel_power_well_enable(struct drm_i915_private *dev_priv,
+				     struct i915_power_well *power_well,
+				     bool wait_ack)
 {
 	drm_dbg_kms(&dev_priv->drm, "enabling %s\n", power_well->desc->name);
-	power_well->desc->ops->enable(dev_priv, power_well);
+	if (wait_ack || !power_well->desc->ops->enable_without_ack)
+		power_well->desc->ops->enable(dev_priv, power_well);
+	else
+		power_well->desc->ops->enable_without_ack(dev_priv, power_well);
 	power_well->hw_enabled = true;
 }
 
+static void intel_power_well_enable(struct drm_i915_private *dev_priv,
+				    struct i915_power_well *power_well)
+{
+	_intel_power_well_enable(dev_priv, power_well, true);
+}
+
 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 				     struct i915_power_well *power_well)
 {
@@ -174,10 +184,11 @@ static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 }
 
 static void intel_power_well_get(struct drm_i915_private *dev_priv,
-				 struct i915_power_well *power_well)
+				 struct i915_power_well *power_well,
+				 bool wait_ack)
 {
 	if (!power_well->count++)
-		intel_power_well_enable(dev_priv, power_well);
+		_intel_power_well_enable(dev_priv, power_well, wait_ack);
 }
 
 static void intel_power_well_put(struct drm_i915_private *dev_priv,
@@ -353,8 +364,9 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
 					  SKL_FUSE_PG_DIST_STATUS(pg), 1));
 }
 
-static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
-				  struct i915_power_well *power_well)
+static void _hsw_power_well_enable(struct drm_i915_private *dev_priv,
+				   struct i915_power_well *power_well,
+				   bool wait_ack)
 {
 	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 	int pw_idx = power_well->desc->hsw.idx;
@@ -379,7 +391,8 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 	val = intel_de_read(dev_priv, regs->driver);
 	intel_de_write(dev_priv, regs->driver,
 		       val | HSW_PWR_WELL_CTL_REQ(pw_idx));
-	hsw_wait_for_power_well_enable(dev_priv, power_well);
+	if (wait_ack)
+		hsw_wait_for_power_well_enable(dev_priv, power_well);
 
 	/* Display WA #1178: cnl */
 	if (IS_CANNONLAKE(dev_priv) &&
@@ -398,6 +411,12 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 				   power_well->desc->hsw.has_vga);
 }
 
+static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
+				  struct i915_power_well *power_well)
+{
+	_hsw_power_well_enable(dev_priv, power_well, true);
+}
+
 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 				   struct i915_power_well *power_well)
 {
@@ -1960,7 +1979,8 @@ intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
 
 static void
 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
-				 enum intel_display_power_domain domain)
+				 enum intel_display_power_domain domain,
+				 bool wait_ack)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
@@ -1969,7 +1989,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 		return;
 
 	for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
-		intel_power_well_get(dev_priv, power_well);
+		intel_power_well_get(dev_priv, power_well, wait_ack);
 
 	power_domains->domain_use_count[domain]++;
 }
@@ -1993,7 +2013,34 @@ intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 	intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
 	mutex_lock(&power_domains->lock);
-	__intel_display_power_get_domain(dev_priv, domain);
+	__intel_display_power_get_domain(dev_priv, domain, true);
+	mutex_unlock(&power_domains->lock);
+
+	return wakeref;
+}
+
+/**
+ * intel_display_power_get_without_ack - grab a power domain reference without
+ * wait for HW ack
+ * @dev_priv: i915 device instance
+ * @domain: power domain to reference
+ *
+ * This function grabs a power domain reference for @domain and ensures that the
+ * power domain and all its parents are powered up but it don't wait for
+ * hardware ack if supported by each powerwell. Users should only grab a
+ * reference to the innermost power domain they need.
+ *
+ * Any power domain reference obtained by this function must have a symmetric
+ * call to intel_display_power_put() to release the reference again.
+ */
+intel_wakeref_t intel_display_power_get_without_ack(struct drm_i915_private *dev_priv,
+						    enum intel_display_power_domain domain)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+
+	mutex_lock(&power_domains->lock);
+	__intel_display_power_get_domain(dev_priv, domain, false);
 	mutex_unlock(&power_domains->lock);
 
 	return wakeref;
@@ -2026,7 +2073,7 @@ intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 	mutex_lock(&power_domains->lock);
 
 	if (__intel_display_power_is_enabled(dev_priv, domain)) {
-		__intel_display_power_get_domain(dev_priv, domain);
+		__intel_display_power_get_domain(dev_priv, domain, true);
 		is_enabled = true;
 	} else {
 		is_enabled = false;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..5db86cc862c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -129,6 +129,16 @@ struct i915_power_well_ops {
 	 */
 	void (*enable)(struct drm_i915_private *dev_priv,
 		       struct i915_power_well *power_well);
+
+	/*
+	 * Enable the well and resources that depend on it (for example
+	 * interrupts located on the well) without reading HW ack. Called after
+	 * the 0->1 refcount transition.
+	 * This will be used by TC subsystem and it is a optional hook.
+	 */
+	void (*enable_without_ack)(struct drm_i915_private *dev_priv,
+				   struct i915_power_well *power_well);
+
 	/*
 	 * Disable the well and resources that depend on it. Called after
 	 * the 1->0 refcount transition.
@@ -270,6 +280,8 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 				      enum intel_display_power_domain domain);
 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 					enum intel_display_power_domain domain);
+intel_wakeref_t intel_display_power_get_without_ack(struct drm_i915_private *dev_priv,
+						    enum intel_display_power_domain domain);
 intel_wakeref_t
 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 				   enum intel_display_power_domain domain);
-- 
2.26.0

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  reply	other threads:[~2020-03-24 20:13 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-24 20:14 [Intel-gfx] [PATCH v3 1/6] drm/i915/tc/tgl: Implement TCCOLD sequences José Roberto de Souza
2020-03-24 20:14 ` José Roberto de Souza [this message]
2020-03-28 10:01   ` [Intel-gfx] [PATCH v3 2/6] drm/i915/display: Add intel_display_power_get_without_ack() Imre Deak
2020-03-24 20:14 ` [Intel-gfx] [PATCH v3 3/6] drm/i915/display: Implement intel_display_power_wait_enable_ack() José Roberto de Souza
2020-03-24 20:14 ` [Intel-gfx] [PATCH v3 4/6] drm/i915/display: Add intel_aux_ch_to_power_domain() José Roberto de Souza
2020-03-24 20:14 ` [Intel-gfx] [PATCH v3 5/6] drm/i915/tc/icl: Implement the TC cold exit sequence José Roberto de Souza
2020-03-28 10:20   ` Imre Deak
2020-03-24 20:14 ` [Intel-gfx] [PATCH v3 6/6] drm/i915/dp: Get TC link reference during DP detection José Roberto de Souza
2020-03-28 10:26   ` Imre Deak
2020-03-30 20:27     ` Souza, Jose
2020-03-31 16:01       ` Imre Deak
2020-03-24 20:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/6] drm/i915/tc/tgl: Implement TCCOLD sequences Patchwork
2020-03-24 20:43   ` Souza, Jose
2020-03-24 20:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-24 22:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-25  5:59 ` [Intel-gfx] [PATCH v3 1/6] " You-Sheng Yang
2020-03-28  9:57 ` Imre Deak
2020-03-30 20:23   ` Souza, Jose
2020-03-31 15:47     ` Imre Deak

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