* [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables
@ 2020-03-27 21:34 José Roberto de Souza
2020-03-27 21:34 ` [Intel-gfx] [PATCH 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR José Roberto de Souza
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: José Roberto de Souza @ 2020-03-27 21:34 UTC (permalink / raw)
To: intel-gfx
DDI ports have its encoders initialized with INTEL_OUTPUT_DDI type and
later eDP ports that have the type changed to INTEL_OUTPUT_EDP.
But for all other DDI ports it can drive HDMI or DP depending on what
user connects to the ports.
ehl_get_combo_buf_trans() and tgl_get_combo_buf_trans() was checking
for INTEL_OUTPUT_DP that was never true, causing eDP vswing tables
being used.
So here changing the check to INTEL_OUTPUT_DDI, HDMI cases will be
correctly handled as it do not use encoder->type, instead it calls the
functions with INTEL_OUTPUT_HDMI as type parameter and HDMI don't have
retraining.
Fixes: bd3cf6f7ce20 ("drm/i915/dp/tgl+: Update combo phy vswing tables")
Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 916a802af788..7af1572d4f1d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -947,7 +947,7 @@ static const struct cnl_ddi_buf_trans *
ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
int *n_entries)
{
- if (type == INTEL_OUTPUT_DP && rate > 270000) {
+ if (type == INTEL_OUTPUT_DDI && rate > 270000) {
*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
return ehl_combo_phy_ddi_translations_hbr2_hbr3;
}
@@ -959,7 +959,7 @@ static const struct cnl_ddi_buf_trans *
tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
int *n_entries)
{
- if (type != INTEL_OUTPUT_DP) {
+ if (type != INTEL_OUTPUT_DDI) {
return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
} else if (rate > 270000) {
*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
--
2.26.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR
2020-03-27 21:34 [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
@ 2020-03-27 21:34 ` José Roberto de Souza
2020-03-27 21:34 ` [Intel-gfx] [PATCH 3/3] drm/i915/tc/icl: Update TC vswing tables José Roberto de Souza
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: José Roberto de Souza @ 2020-03-27 21:34 UTC (permalink / raw)
To: intel-gfx
EHL has now only one table for all DP transmission modes.
BSpec: 21257
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7af1572d4f1d..e1a9e14f46e8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -568,7 +568,7 @@ static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
{ 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
};
-static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_hbr2_hbr3[] = {
+static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
/* NT mV Trans mV db */
{ 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
{ 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
@@ -947,9 +947,9 @@ static const struct cnl_ddi_buf_trans *
ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
int *n_entries)
{
- if (type == INTEL_OUTPUT_DDI && rate > 270000) {
- *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
- return ehl_combo_phy_ddi_translations_hbr2_hbr3;
+ if (type == INTEL_OUTPUT_DDI) {
+ *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
+ return ehl_combo_phy_ddi_translations_dp;
}
return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
--
2.26.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/tc/icl: Update TC vswing tables
2020-03-27 21:34 [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
2020-03-27 21:34 ` [Intel-gfx] [PATCH 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR José Roberto de Souza
@ 2020-03-27 21:34 ` José Roberto de Souza
2020-03-27 22:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/dp: Return the right " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: José Roberto de Souza @ 2020-03-27 21:34 UTC (permalink / raw)
To: intel-gfx
Specification was updated with vswing tables for different
configurations.
Also reordering icl_mg_phy_ddi_buf_trans struct to match table order.
BSpec: 21735
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 93 +++++++++++++++++++-----
1 file changed, 73 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e1a9e14f46e8..ad1109f9a298 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -583,23 +583,51 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
};
struct icl_mg_phy_ddi_buf_trans {
- u32 cri_txdeemph_override_5_0;
u32 cri_txdeemph_override_11_6;
+ u32 cri_txdeemph_override_5_0;
u32 cri_txdeemph_override_17_12;
};
-static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
+static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
+ /* Voltage swing pre-emphasis */
+ { 0x18, 0x00, 0x00 }, /* 0 0 */
+ { 0x1D, 0x00, 0x05 }, /* 0 1 */
+ { 0x24, 0x00, 0x0C }, /* 0 2 */
+ { 0x2B, 0x00, 0x14 }, /* 0 3 */
+ { 0x21, 0x00, 0x00 }, /* 1 0 */
+ { 0x2B, 0x00, 0x08 }, /* 1 1 */
+ { 0x30, 0x00, 0x0F }, /* 1 2 */
+ { 0x31, 0x00, 0x03 }, /* 2 0 */
+ { 0x34, 0x00, 0x0B }, /* 2 1 */
+ { 0x3F, 0x00, 0x00 }, /* 3 0 */
+};
+
+static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
/* Voltage swing pre-emphasis */
- { 0x0, 0x1B, 0x00 }, /* 0 0 */
- { 0x0, 0x23, 0x08 }, /* 0 1 */
- { 0x0, 0x2D, 0x12 }, /* 0 2 */
- { 0x0, 0x00, 0x00 }, /* 0 3 */
- { 0x0, 0x23, 0x00 }, /* 1 0 */
- { 0x0, 0x2B, 0x09 }, /* 1 1 */
- { 0x0, 0x2E, 0x11 }, /* 1 2 */
- { 0x0, 0x2F, 0x00 }, /* 2 0 */
- { 0x0, 0x33, 0x0C }, /* 2 1 */
- { 0x0, 0x00, 0x00 }, /* 3 0 */
+ { 0x18, 0x00, 0x00 }, /* 0 0 */
+ { 0x1D, 0x00, 0x05 }, /* 0 1 */
+ { 0x24, 0x00, 0x0C }, /* 0 2 */
+ { 0x2B, 0x00, 0x14 }, /* 0 3 */
+ { 0x26, 0x00, 0x00 }, /* 1 0 */
+ { 0x2C, 0x00, 0x07 }, /* 1 1 */
+ { 0x33, 0x00, 0x0C }, /* 1 2 */
+ { 0x2E, 0x00, 0x00 }, /* 2 0 */
+ { 0x36, 0x00, 0x09 }, /* 2 1 */
+ { 0x3F, 0x00, 0x00 }, /* 3 0 */
+};
+
+static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
+ /* HDMI Preset VS Pre-emph */
+ { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */
+ { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */
+ { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */
+ { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */
+ { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */
+ { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */
+ { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */
+ { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */
+ { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */
+ { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */
};
struct tgl_dkl_phy_ddi_buf_trans {
@@ -943,6 +971,22 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
return icl_combo_phy_ddi_translations_dp_hbr2;
}
+static const struct icl_mg_phy_ddi_buf_trans *
+icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+ int *n_entries)
+{
+ if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
+ return icl_mg_phy_ddi_translations_hdmi;
+ } else if (rate > 270000) {
+ *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
+ return icl_mg_phy_ddi_translations_hbr2_hbr3;
+ }
+
+ *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
+ return icl_mg_phy_ddi_translations_rbr_hbr;
+}
+
static const struct cnl_ddi_buf_trans *
ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
int *n_entries)
@@ -988,7 +1032,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
0, &n_entries);
else
- n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+ icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
+ &n_entries);
default_entry = n_entries - 1;
} else if (IS_CANNONLAKE(dev_priv)) {
cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
@@ -2062,7 +2107,8 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
icl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate, &n_entries);
else
- n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
+ icl_get_mg_buf_trans(dev_priv, encoder->type,
+ intel_dp->link_rate, &n_entries);
} else if (IS_CANNONLAKE(dev_priv)) {
if (encoder->type == INTEL_OUTPUT_EDP)
cnl_get_buf_trans_edp(dev_priv, &n_entries);
@@ -2377,17 +2423,23 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
}
static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
- int link_clock,
- u32 level)
+ int link_clock, u32 level,
+ enum intel_output_type type)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
u32 n_entries, val;
- int ln;
+ int ln, rate = 0;
+
+ if (type == INTEL_OUTPUT_DDI) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ rate = intel_dp->link_rate;
+ }
- n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
- ddi_translations = icl_mg_phy_ddi_translations;
+ ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate,
+ &n_entries);
/* The table does not have values for level 3 and level 9. */
if (level >= n_entries || level == 3 || level == 9) {
drm_dbg_kms(&dev_priv->drm,
@@ -2511,7 +2563,8 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
if (intel_phy_is_combo(dev_priv, phy))
icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
else
- icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
+ icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
+ type);
}
static void
--
2.26.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/dp: Return the right vswing tables
2020-03-27 21:34 [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
2020-03-27 21:34 ` [Intel-gfx] [PATCH 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR José Roberto de Souza
2020-03-27 21:34 ` [Intel-gfx] [PATCH 3/3] drm/i915/tc/icl: Update TC vswing tables José Roberto de Souza
@ 2020-03-27 22:24 ` Patchwork
2020-03-28 17:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-30 14:50 ` [Intel-gfx] [PATCH 1/3] " Ville Syrjälä
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-03-27 22:24 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/dp: Return the right vswing tables
URL : https://patchwork.freedesktop.org/series/75183/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8206 -> Patchwork_17120
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/index.html
Known issues
------------
Here are the changes found in Patchwork_17120 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][1] -> [DMESG-FAIL][2] ([fdo#108569])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/fi-icl-y/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/fi-icl-y/igt@i915_selftest@live@execlists.html
- fi-kbl-soraka: [PASS][3] -> [INCOMPLETE][4] ([fdo#112259] / [i915#656])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-icl-u2: [DMESG-WARN][5] ([i915#289]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/fi-icl-u2/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/fi-icl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_parallel@contexts:
- fi-icl-dsi: [INCOMPLETE][7] -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/fi-icl-dsi/igt@gem_exec_parallel@contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/fi-icl-dsi/igt@gem_exec_parallel@contexts.html
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (49 -> 35)
------------------------------
Missing (14): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-gdg-551 fi-skl-lmem fi-blb-e6850 fi-byt-clapper fi-bsw-nick fi-skl-6700k2
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8206 -> Patchwork_17120
CI-20190529: 20190529
CI_DRM_8206: 584fcbd287863a6ba897f1b671acd7115d611362 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5543: 779d43cda49c230afd32c37730ad853f02e9d749 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17120: 74823ea17853c6c0a0af0e717ede201b293cccab @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
74823ea17853 drm/i915/tc/icl: Update TC vswing tables
593784ef4b5c drm/i915/dp/ehl: Update vswing table for HBR and RBR
86b6374af310 drm/i915/dp: Return the right vswing tables
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/dp: Return the right vswing tables
2020-03-27 21:34 [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
` (2 preceding siblings ...)
2020-03-27 22:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/dp: Return the right " Patchwork
@ 2020-03-28 17:39 ` Patchwork
2020-03-30 14:50 ` [Intel-gfx] [PATCH 1/3] " Ville Syrjälä
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-03-28 17:39 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/dp: Return the right vswing tables
URL : https://patchwork.freedesktop.org/series/75183/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8206_full -> Patchwork_17120_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17120_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_shared@q-independent@vcs0}:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb8/igt@gem_ctx_shared@q-independent@vcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb1/igt@gem_ctx_shared@q-independent@vcs0.html
* {igt@gem_ctx_shared@q-independent@vcs1}:
- shard-iclb: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb1/igt@gem_ctx_shared@q-independent@vcs1.html
* {igt@perf@blocking-parameterized}:
- shard-hsw: [PASS][4] -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-hsw2/igt@perf@blocking-parameterized.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-hsw6/igt@perf@blocking-parameterized.html
Known issues
------------
Here are the changes found in Patchwork_17120_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@implicit-both-bsd:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#677]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd.html
* igt@gem_exec_schedule@implicit-read-write-bsd2:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276] / [i915#677])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb4/igt@gem_exec_schedule@implicit-read-write-bsd2.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb8/igt@gem_exec_schedule@implicit-read-write-bsd2.html
* igt@gem_exec_schedule@pi-shared-iova-bsd:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#1193])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-skl6/igt@gem_exec_schedule@pi-shared-iova-bsd.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-skl3/igt@gem_exec_schedule@pi-shared-iova-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276]) +17 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112146]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [PASS][16] -> [TIMEOUT][17] ([i915#1526])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-hsw7/igt@i915_pm_rc6_residency@rc6-idle.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-hsw4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@requests:
- shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#1531])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-tglb2/igt@i915_selftest@live@requests.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-tglb7/igt@i915_selftest@live@requests.html
- shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([fdo#109644] / [fdo#110464])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb1/igt@i915_selftest@live@requests.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb8/igt@i915_selftest@live@requests.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([i915#180]) +4 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-apl4/igt@i915_suspend@sysfs-reader.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-apl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +6 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [PASS][26] -> [INCOMPLETE][27] ([i915#61])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-hsw4/igt@kms_flip@flip-vs-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@plain-flip-ts-check:
- shard-skl: [PASS][28] -> [FAIL][29] ([i915#34])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-skl1/igt@kms_flip@plain-flip-ts-check.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-skl2/igt@kms_flip@plain-flip-ts-check.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][30] -> [FAIL][31] ([i915#899])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-glk5/igt@kms_plane_lowres@pipe-a-tiling-x.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-glk2/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#109441])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#112080]) +9 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb1/igt@perf_pmu@init-busy-vcs1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb3/igt@perf_pmu@init-busy-vcs1.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][36] ([fdo#112080]) -> [PASS][37] +8 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb3/igt@gem_busy@busy-vcs1.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb1/igt@gem_busy@busy-vcs1.html
* {igt@gem_ctx_isolation@preservation-s3@rcs0}:
- shard-apl: [DMESG-WARN][38] ([i915#180]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-apl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-apl2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* {igt@gem_ctx_shared@q-independent@vecs0}:
- shard-iclb: [FAIL][40] -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb8/igt@gem_ctx_shared@q-independent@vecs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb1/igt@gem_ctx_shared@q-independent@vecs0.html
* igt@gem_exec_schedule@implicit-write-read-bsd1:
- shard-iclb: [SKIP][42] ([fdo#109276] / [i915#677]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb4/igt@gem_exec_schedule@implicit-write-read-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][44] ([fdo#112146]) -> [PASS][45] +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][46] ([i915#716]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-glk8/igt@gen9_exec_parse@allowed-all.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-glk4/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-glk: [FAIL][48] ([i915#39]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-glk9/igt@i915_pm_rps@min-max-config-loaded.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-glk5/igt@i915_pm_rps@min-max-config-loaded.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][50] ([i915#79]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [DMESG-WARN][52] ([i915#180]) -> [PASS][53] +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [FAIL][54] ([i915#34]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-tglb: [SKIP][56] ([i915#668]) -> [PASS][57] +8 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-iclb: [INCOMPLETE][58] ([i915#1185]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][60] ([fdo#108145]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][62] ([fdo#109441]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb4/igt@kms_psr@psr2_primary_blt.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][64] ([fdo#109276]) -> [PASS][65] +12 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][66] ([i915#454]) -> [SKIP][67] ([i915#468])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-tglb7/igt@i915_pm_dc@dc6-psr.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: [FAIL][68] ([fdo#108145]) -> [FAIL][69] ([fdo#108145] / [i915#95])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8206/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1193]: https://gitlab.freedesktop.org/drm/intel/issues/1193
[i915#1526]: https://gitlab.freedesktop.org/drm/intel/issues/1526
[i915#1531]: https://gitlab.freedesktop.org/drm/intel/issues/1531
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8206 -> Patchwork_17120
CI-20190529: 20190529
CI_DRM_8206: 584fcbd287863a6ba897f1b671acd7115d611362 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5543: 779d43cda49c230afd32c37730ad853f02e9d749 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17120: 74823ea17853c6c0a0af0e717ede201b293cccab @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17120/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables
2020-03-27 21:34 [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
` (3 preceding siblings ...)
2020-03-28 17:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-03-30 14:50 ` Ville Syrjälä
2020-03-30 19:24 ` Souza, Jose
4 siblings, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2020-03-30 14:50 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Mar 27, 2020 at 02:34:11PM -0700, José Roberto de Souza wrote:
> DDI ports have its encoders initialized with INTEL_OUTPUT_DDI type and
> later eDP ports that have the type changed to INTEL_OUTPUT_EDP.
> But for all other DDI ports it can drive HDMI or DP depending on what
> user connects to the ports.
>
> ehl_get_combo_buf_trans() and tgl_get_combo_buf_trans() was checking
> for INTEL_OUTPUT_DP that was never true, causing eDP vswing tables
> being used.
>
> So here changing the check to INTEL_OUTPUT_DDI, HDMI cases will be
> correctly handled as it do not use encoder->type, instead it calls the
> functions with INTEL_OUTPUT_HDMI as type parameter and HDMI don't have
> retraining.
>
> Fixes: bd3cf6f7ce20 ("drm/i915/dp/tgl+: Update combo phy vswing tables")
> Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 916a802af788..7af1572d4f1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -947,7 +947,7 @@ static const struct cnl_ddi_buf_trans *
> ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> int *n_entries)
> {
> - if (type == INTEL_OUTPUT_DP && rate > 270000) {
> + if (type == INTEL_OUTPUT_DDI && rate > 270000) {
Please no. I'd rather not see "DDI" here. We want to check which mode
we're driving the output in, and "DDI" isn't one of the valid choices.
The fact that we sometimes pass in encoder->type is a bit of shortcut
to make the DP vs. EDP distinction. And so far every function knew to
only compare the value against EDP/HDMI and neve against DP. Looks like
someone broke that (admittedly crappy) convention.
We should probably fix this a bit higher up and make sure we only ever
pass in EDP/DP/HDMI, never DDI.
> *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
> return ehl_combo_phy_ddi_translations_hbr2_hbr3;
> }
> @@ -959,7 +959,7 @@ static const struct cnl_ddi_buf_trans *
> tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> int *n_entries)
> {
> - if (type != INTEL_OUTPUT_DP) {
> + if (type != INTEL_OUTPUT_DDI) {
> return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
> } else if (rate > 270000) {
> *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> --
> 2.26.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables
2020-03-30 14:50 ` [Intel-gfx] [PATCH 1/3] " Ville Syrjälä
@ 2020-03-30 19:24 ` Souza, Jose
2020-03-31 14:42 ` Ville Syrjälä
0 siblings, 1 reply; 8+ messages in thread
From: Souza, Jose @ 2020-03-30 19:24 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, 2020-03-30 at 17:50 +0300, Ville Syrjälä wrote:
> On Fri, Mar 27, 2020 at 02:34:11PM -0700, José Roberto de Souza
> wrote:
> > DDI ports have its encoders initialized with INTEL_OUTPUT_DDI type
> > and
> > later eDP ports that have the type changed to INTEL_OUTPUT_EDP.
> > But for all other DDI ports it can drive HDMI or DP depending on
> > what
> > user connects to the ports.
> >
> > ehl_get_combo_buf_trans() and tgl_get_combo_buf_trans() was
> > checking
> > for INTEL_OUTPUT_DP that was never true, causing eDP vswing tables
> > being used.
> >
> > So here changing the check to INTEL_OUTPUT_DDI, HDMI cases will be
> > correctly handled as it do not use encoder->type, instead it calls
> > the
> > functions with INTEL_OUTPUT_HDMI as type parameter and HDMI don't
> > have
> > retraining.
> >
> > Fixes: bd3cf6f7ce20 ("drm/i915/dp/tgl+: Update combo phy vswing
> > tables")
> > Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 916a802af788..7af1572d4f1d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -947,7 +947,7 @@ static const struct cnl_ddi_buf_trans *
> > ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int
> > type, int rate,
> > int *n_entries)
> > {
> > - if (type == INTEL_OUTPUT_DP && rate > 270000) {
> > + if (type == INTEL_OUTPUT_DDI && rate > 270000) {
>
> Please no. I'd rather not see "DDI" here. We want to check which mode
> we're driving the output in, and "DDI" isn't one of the valid
> choices.
>
> The fact that we sometimes pass in encoder->type is a bit of shortcut
> to make the DP vs. EDP distinction. And so far every function knew to
> only compare the value against EDP/HDMI and neve against DP. Looks
> like
> someone broke that (admittedly crappy) convention.
>
> We should probably fix this a bit higher up and make sure we only
> ever
> pass in EDP/DP/HDMI, never DDI.
Okay so for now I will just do the bellow:
if (type != INTEL_OUTPUT_EDP && type != INTEL_OUTPUT_HDMI && rate >
270000) {
Good enough for now?
>
> > *n_entries =
> > ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
> > return ehl_combo_phy_ddi_translations_hbr2_hbr3;
> > }
> > @@ -959,7 +959,7 @@ static const struct cnl_ddi_buf_trans *
> > tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int
> > type, int rate,
> > int *n_entries)
> > {
> > - if (type != INTEL_OUTPUT_DP) {
> > + if (type != INTEL_OUTPUT_DDI) {
> > return icl_get_combo_buf_trans(dev_priv, type, rate,
> > n_entries);
> > } else if (rate > 270000) {
> > *n_entries =
> > ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> > --
> > 2.26.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables
2020-03-30 19:24 ` Souza, Jose
@ 2020-03-31 14:42 ` Ville Syrjälä
0 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2020-03-31 14:42 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Mon, Mar 30, 2020 at 07:24:55PM +0000, Souza, Jose wrote:
> On Mon, 2020-03-30 at 17:50 +0300, Ville Syrjälä wrote:
> > On Fri, Mar 27, 2020 at 02:34:11PM -0700, José Roberto de Souza
> > wrote:
> > > DDI ports have its encoders initialized with INTEL_OUTPUT_DDI type
> > > and
> > > later eDP ports that have the type changed to INTEL_OUTPUT_EDP.
> > > But for all other DDI ports it can drive HDMI or DP depending on
> > > what
> > > user connects to the ports.
> > >
> > > ehl_get_combo_buf_trans() and tgl_get_combo_buf_trans() was
> > > checking
> > > for INTEL_OUTPUT_DP that was never true, causing eDP vswing tables
> > > being used.
> > >
> > > So here changing the check to INTEL_OUTPUT_DDI, HDMI cases will be
> > > correctly handled as it do not use encoder->type, instead it calls
> > > the
> > > functions with INTEL_OUTPUT_HDMI as type parameter and HDMI don't
> > > have
> > > retraining.
> > >
> > > Fixes: bd3cf6f7ce20 ("drm/i915/dp/tgl+: Update combo phy vswing
> > > tables")
> > > Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 916a802af788..7af1572d4f1d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -947,7 +947,7 @@ static const struct cnl_ddi_buf_trans *
> > > ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int
> > > type, int rate,
> > > int *n_entries)
> > > {
> > > - if (type == INTEL_OUTPUT_DP && rate > 270000) {
> > > + if (type == INTEL_OUTPUT_DDI && rate > 270000) {
> >
> > Please no. I'd rather not see "DDI" here. We want to check which mode
> > we're driving the output in, and "DDI" isn't one of the valid
> > choices.
> >
> > The fact that we sometimes pass in encoder->type is a bit of shortcut
> > to make the DP vs. EDP distinction. And so far every function knew to
> > only compare the value against EDP/HDMI and neve against DP. Looks
> > like
> > someone broke that (admittedly crappy) convention.
> >
> > We should probably fix this a bit higher up and make sure we only
> > ever
> > pass in EDP/DP/HDMI, never DDI.
>
> Okay so for now I will just do the bellow:
>
> if (type != INTEL_OUTPUT_EDP && type != INTEL_OUTPUT_HDMI && rate >
> 270000) {
>
> Good enough for now?
Works for me.
> >
> > > *n_entries =
> > > ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
> > > return ehl_combo_phy_ddi_translations_hbr2_hbr3;
> > > }
> > > @@ -959,7 +959,7 @@ static const struct cnl_ddi_buf_trans *
> > > tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int
> > > type, int rate,
> > > int *n_entries)
> > > {
> > > - if (type != INTEL_OUTPUT_DP) {
> > > + if (type != INTEL_OUTPUT_DDI) {
> > > return icl_get_combo_buf_trans(dev_priv, type, rate,
> > > n_entries);
> > > } else if (rate > 270000) {
> > > *n_entries =
> > > ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> > > --
> > > 2.26.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-03-31 14:42 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-27 21:34 [Intel-gfx] [PATCH 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
2020-03-27 21:34 ` [Intel-gfx] [PATCH 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR José Roberto de Souza
2020-03-27 21:34 ` [Intel-gfx] [PATCH 3/3] drm/i915/tc/icl: Update TC vswing tables José Roberto de Souza
2020-03-27 22:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/dp: Return the right " Patchwork
2020-03-28 17:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-30 14:50 ` [Intel-gfx] [PATCH 1/3] " Ville Syrjälä
2020-03-30 19:24 ` Souza, Jose
2020-03-31 14:42 ` Ville Syrjälä
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