From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v6 05/17] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
Date: Sun, 29 Mar 2020 22:35:26 +0530 [thread overview]
Message-ID: <20200329170538.25449-6-pragnesh.patel@sifive.com> (raw)
In-Reply-To: <20200329170538.25449-1-pragnesh.patel@sifive.com>
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 54 +++++++++++++++++++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 16 ++++++
2 files changed, 70 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index db55773bd2..387b13bdfb 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,11 +4,65 @@
*/
/ {
+ cpus {
+ u-boot,dm-spl;
+ cpu0: cpu at 0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu at 1 {
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu2: cpu at 2 {
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu3: cpu at 3 {
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu4: cpu at 4 {
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
soc {
+ u-boot,dm-spl;
otp: otp at 10070000 {
compatible = "sifive,fu540-c000-otp";
reg = <0x0 0x10070000 0x0 0x0FFF>;
fuse-count = <0x1000>;
};
+ clint at 2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ u-boot,dm-spl;
+ };
};
};
+
+&prci {
+ u-boot,dm-spl;
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&qspi2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index f1735c1385..efa7cbb75d 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,3 +4,19 @@
*/
#include "fu540-c000-u-boot.dtsi"
+
+/ {
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+};
+
+&qspi2 {
+ mmc at 0 {
+ u-boot,dm-spl;
+ };
+};
--
2.17.1
next prev parent reply other threads:[~2020-03-29 17:05 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-29 17:05 [PATCH v6 00/17] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 01/17] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-04-02 9:15 ` Jagan Teki
2020-04-02 10:54 ` Pragnesh Patel
2020-04-20 8:05 ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-04-02 9:19 ` Jagan Teki
2020-04-02 9:24 ` Pragnesh Patel
2020-04-02 9:29 ` Jagan Teki
2020-04-02 10:17 ` Pragnesh Patel
2020-04-07 8:02 ` Jagan Teki
2020-04-07 8:10 ` Pragnesh Patel
2020-04-07 9:21 ` Jagan Teki
2020-04-08 4:44 ` Pragnesh Patel
2020-04-20 6:30 ` Bin Meng
2020-04-20 7:54 ` Bin Meng
2020-04-20 8:15 ` Jagan Teki
2020-04-20 8:18 ` Bin Meng
2020-04-20 8:05 ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 03/17] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-04-20 8:05 ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 04/17] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-04-02 9:20 ` Jagan Teki
2020-04-20 8:05 ` Bin Meng
2020-03-29 17:05 ` Pragnesh Patel [this message]
2020-04-02 9:24 ` [PATCH v6 05/17] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Jagan Teki
2020-03-29 17:05 ` [PATCH v6 06/17] sifive: fu540: add ddr driver Pragnesh Patel
2020-04-06 19:27 ` Jagan Teki
2020-04-08 7:41 ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 07/17] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-04-06 19:30 ` Jagan Teki
2020-04-08 4:54 ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 08/17] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-04-20 9:02 ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 09/17] clk: sifive: fu540-prci: Add clock initialization for SPL Pragnesh Patel
2020-04-06 19:35 ` Jagan Teki
2020-04-20 9:00 ` Bin Meng
2020-04-24 10:08 ` Pragnesh Patel
2020-04-24 13:00 ` Bin Meng
2020-04-24 13:34 ` Pragnesh Patel
2020-04-24 13:55 ` Bin Meng
2020-04-24 16:27 ` Pragnesh Patel
2020-04-25 1:32 ` Bin Meng
2020-04-26 10:00 ` Pragnesh Patel
2020-04-27 1:24 ` Bin Meng
2020-04-28 13:56 ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 10/17] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
2020-04-06 19:37 ` Jagan Teki
2020-04-08 6:52 ` Pragnesh Patel
2020-04-20 9:02 ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 11/17] sifive: dts: fu540: Enable gpio in U-Boot SPL Pragnesh Patel
2020-04-20 9:34 ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 12/17] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-04-20 9:35 ` Bin Meng
2020-04-24 13:57 ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 13/17] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
2020-04-20 9:35 ` Bin Meng
2020-04-24 14:06 ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 14/17] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
2020-04-20 9:35 ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 15/17] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
2020-04-20 9:35 ` Bin Meng
2020-04-24 14:08 ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 16/17] sifive: fix palmer's email address Pragnesh Patel
2020-04-06 19:43 ` Jagan Teki
2020-04-08 4:45 ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 17/17] doc: update FU540 RISC-V documentation Pragnesh Patel
2020-04-20 9:46 ` Bin Meng
2020-04-24 14:10 ` Pragnesh Patel
2020-04-02 9:12 ` [PATCH v6 00/17] RISC-V SiFive FU540 support SPL Jagan Teki
2020-04-02 9:42 ` Pragnesh Patel
2020-04-02 9:49 ` Jagan Teki
2020-04-07 9:32 ` Jagan Teki
2020-04-08 4:42 ` Pragnesh Patel
2020-04-20 14:42 ` Bin Meng
2020-04-21 4:29 ` Pragnesh Patel
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