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From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Date: Wed, 8 Apr 2020 04:44:35 +0000	[thread overview]
Message-ID: <MWHPR13MB09446F2FC07517703B064F19E5C00@MWHPR13MB0944.namprd13.prod.outlook.com> (raw)
In-Reply-To: <CAMty3ZB1L7Z1ZpTjvdS=YkmZZGZnKd_zE8465Mq=RnkXry577g@mail.gmail.com>

Hi Jagan,

>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 07 April 2020 14:51
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
><bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>; Troy
>Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen
><rick@andestech.com>; Palmer Dabbelt <palmer@dabbelt.com>
>Subject: Re: [PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM driver for serial
>environment variable
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Tue, Apr 7, 2020 at 1:40 PM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> Hi Jagan,
>>
>> >-----Original Message-----
>> >From: Jagan Teki <jagan@amarulasolutions.com>
>> >Sent: 07 April 2020 13:32
>> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
>> ><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
>> ><bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Troy
>> >Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
>> ><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick
>Chen
>> ><rick@andestech.com>; Palmer Dabbelt <palmer@dabbelt.com>
>> >Subject: Re: [PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM driver
>> >for serial environment variable
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >On Thu, Apr 2, 2020 at 3:47 PM Pragnesh Patel
>> ><pragnesh.patel@sifive.com>
>> >wrote:
>> >>
>> >> Hi Jagan,
>> >>
>> >> >-----Original Message-----
>> >> >From: Jagan Teki <jagan@amarulasolutions.com>
>> >> >Sent: 02 April 2020 14:59
>> >> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
>> >> ><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
>> >> ><bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>> >Troy
>> >> >Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
>> >> ><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick
>> >Chen
>> >> ><rick@andestech.com>; Palmer Dabbelt <palmer@dabbelt.com>
>> >> >Subject: Re: [PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM
>> >> >driver for serial environment variable
>> >> >
>> >> >[External Email] Do not click links or attachments unless you
>> >> >recognize the sender and know the content is safe
>> >> >
>> >> >On Thu, Apr 2, 2020 at 2:54 PM Pragnesh Patel
>> >> ><pragnesh.patel@sifive.com>
>> >> >wrote:
>> >> >>
>> >> >>
>> >> >> Hi Jagan,
>> >> >>
>> >> >> >-----Original Message-----
>> >> >> >From: Jagan Teki <jagan@amarulasolutions.com>
>> >> >> >Sent: 02 April 2020 14:49
>> >> >> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >> >> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
>> >> >> ><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
>> >> >> ><bmeng.cn@gmail.com>; Paul Walmsley
><paul.walmsley@sifive.com>;
>> >> >Troy
>> >> >> >Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
>> >> >> ><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>;
>> >> >> >Rick
>> >> >Chen
>> >> >> ><rick@andestech.com>; Palmer Dabbelt <palmer@dabbelt.com>
>> >> >> >Subject: Re: [PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM
>> >> >> >driver for serial environment variable
>> >> >> >
>> >> >> >[External Email] Do not click links or attachments unless you
>> >> >> >recognize the sender and know the content is safe
>> >> >> >
>> >> >> >On Sun, Mar 29, 2020 at 10:36 PM Pragnesh Patel
>> >> >> ><pragnesh.patel@sifive.com> wrote:
>> >> >> >>
>> >> >> >> Use the OTP DM driver to set the serial environment variable.
>> >> >> >>
>> >> >> >> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >> >> >> ---
>> >> >> >>  arch/riscv/dts/fu540-c000-u-boot.dtsi         |  14 +++
>> >> >> >>  .../dts/hifive-unleashed-a00-u-boot.dtsi      |   6 +
>> >> >> >>  board/sifive/fu540/Kconfig                    |   2 +
>> >> >> >>  board/sifive/fu540/fu540.c                    | 111 ++++++------------
>> >> >> >>  4 files changed, 61 insertions(+), 72 deletions(-)  create
>> >> >> >> mode
>> >> >> >> 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
>> >> >> >>  create mode 100644
>> >> >> >> arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> >> >> >>
>> >> >> >> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> >> >> >> b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> >> >> >> new file mode 100644
>> >> >> >> index 0000000000..db55773bd2
>> >> >> >> --- /dev/null
>> >> >> >> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> >> >> >> @@ -0,0 +1,14 @@
>> >> >> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> >> >> >> +/*
>> >> >> >> + * (C) Copyright 2019 SiFive, Inc  */
>> >> >> >> +
>> >> >> >> +/ {
>> >> >> >> +       soc {
>> >> >> >> +               otp: otp at 10070000 {
>> >> >> >> +                       compatible = "sifive,fu540-c000-otp";
>> >> >> >> +                       reg = <0x0 0x10070000 0x0 0x0FFF>;
>> >> >> >> +                       fuse-count = <0x1000>;
>> >> >> >> +               };
>> >> >> >> +       };
>> >> >> >> +};
>> >> >> >> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> >> >> >> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> >> >> >> new file mode 100644
>> >> >> >> index 0000000000..f1735c1385
>> >> >> >> --- /dev/null
>> >> >> >> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> >> >> >> @@ -0,0 +1,6 @@
>> >> >> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> >> >> >> +/*
>> >> >> >> + * Copyright (C) 2019 SiFive, Inc  */
>> >> >> >> +
>> >> >> >> +#include "fu540-c000-u-boot.dtsi"
>> >> >> >> diff --git a/board/sifive/fu540/Kconfig
>> >> >> >> b/board/sifive/fu540/Kconfig index 5ca21474de..900197bbb2
>> >> >> >> 100644
>> >> >> >> --- a/board/sifive/fu540/Kconfig
>> >> >> >> +++ b/board/sifive/fu540/Kconfig
>> >> >> >> @@ -48,5 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>> >> >> >>         imply SIFIVE_GPIO
>> >> >> >>         imply CMD_GPIO
>> >> >> >>         imply SMP
>> >> >> >> +       imply MISC
>> >> >> >> +       imply SIFIVE_OTP
>> >> >> >
>> >> >> >Mark this default y if it is SIFIVE.
>> >> >>
>> >> >> All other SiFive drivers (SPI_SIFIVE, SIFIVE_GPIO) are enabled
>> >> >> by "imply", so I
>> >> >am following the same. I think "imply" will make it default y.
>> >> >
>> >> >Just mark 'default y' on SIFIVE_OTP area of drivers/misc/Kconfig
>> >> >depends on SIFIVE SoC would select this driver so-that you no need
>> >> >to add impy SIFIVE_OTP here.
>> >>
>> >> I am not sure if all SiFive SoC will contain SiFive OTP controller,
>> >> so it's better
>> >not to make it default y.
>> >>
>> >> If all Sifive SoCs contain OTP controller then I need to add
>> >> another Kconfig option like "RISCV_SIFIVE" as shown below, config
>SIFIVE_OTP
>> >>         default y if RISCV_SIFIVE
>> >
>> >Yes, use this TARGET_SIFIVE_FU540
>>
>> I am okay with this but if other future SiFive SoCs support this OTP then it
>would be a long chain.
>> What's your opinion on this ?
>
>That is fine, these are at least SoC not boards. boards will increment a lot but
>SoC may not. Having SoC dependency or select would be meaningful.

Will update this in v7.

>
>Jagan.

  reply	other threads:[~2020-04-08  4:44 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-29 17:05 [PATCH v6 00/17] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 01/17] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-04-02  9:15   ` Jagan Teki
2020-04-02 10:54     ` Pragnesh Patel
2020-04-20  8:05   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 02/17] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-04-02  9:19   ` Jagan Teki
2020-04-02  9:24     ` Pragnesh Patel
2020-04-02  9:29       ` Jagan Teki
2020-04-02 10:17         ` Pragnesh Patel
2020-04-07  8:02           ` Jagan Teki
2020-04-07  8:10             ` Pragnesh Patel
2020-04-07  9:21               ` Jagan Teki
2020-04-08  4:44                 ` Pragnesh Patel [this message]
2020-04-20  6:30                   ` Bin Meng
2020-04-20  7:54                 ` Bin Meng
2020-04-20  8:15                   ` Jagan Teki
2020-04-20  8:18                     ` Bin Meng
2020-04-20  8:05   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 03/17] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-04-20  8:05   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 04/17] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-04-02  9:20   ` Jagan Teki
2020-04-20  8:05   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 05/17] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-04-02  9:24   ` Jagan Teki
2020-03-29 17:05 ` [PATCH v6 06/17] sifive: fu540: add ddr driver Pragnesh Patel
2020-04-06 19:27   ` Jagan Teki
2020-04-08  7:41     ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 07/17] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-04-06 19:30   ` Jagan Teki
2020-04-08  4:54     ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 08/17] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-04-20  9:02   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 09/17] clk: sifive: fu540-prci: Add clock initialization for SPL Pragnesh Patel
2020-04-06 19:35   ` Jagan Teki
2020-04-20  9:00     ` Bin Meng
2020-04-24 10:08       ` Pragnesh Patel
2020-04-24 13:00         ` Bin Meng
2020-04-24 13:34           ` Pragnesh Patel
2020-04-24 13:55             ` Bin Meng
2020-04-24 16:27               ` Pragnesh Patel
2020-04-25  1:32                 ` Bin Meng
2020-04-26 10:00     ` Pragnesh Patel
2020-04-27  1:24       ` Bin Meng
2020-04-28 13:56         ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 10/17] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
2020-04-06 19:37   ` Jagan Teki
2020-04-08  6:52     ` Pragnesh Patel
2020-04-20  9:02   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 11/17] sifive: dts: fu540: Enable gpio in U-Boot SPL Pragnesh Patel
2020-04-20  9:34   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 12/17] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-04-20  9:35   ` Bin Meng
2020-04-24 13:57     ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 13/17] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
2020-04-20  9:35   ` Bin Meng
2020-04-24 14:06     ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 14/17] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
2020-04-20  9:35   ` Bin Meng
2020-03-29 17:05 ` [PATCH v6 15/17] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
2020-04-20  9:35   ` Bin Meng
2020-04-24 14:08     ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 16/17] sifive: fix palmer's email address Pragnesh Patel
2020-04-06 19:43   ` Jagan Teki
2020-04-08  4:45     ` Pragnesh Patel
2020-03-29 17:05 ` [PATCH v6 17/17] doc: update FU540 RISC-V documentation Pragnesh Patel
2020-04-20  9:46   ` Bin Meng
2020-04-24 14:10     ` Pragnesh Patel
2020-04-02  9:12 ` [PATCH v6 00/17] RISC-V SiFive FU540 support SPL Jagan Teki
2020-04-02  9:42   ` Pragnesh Patel
2020-04-02  9:49     ` Jagan Teki
2020-04-07  9:32 ` Jagan Teki
2020-04-08  4:42   ` Pragnesh Patel
2020-04-20 14:42     ` Bin Meng
2020-04-21  4:29       ` Pragnesh Patel

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