From: Andrew Lunn <andrew@lunn.ch>
To: Daniel Mack <daniel@zonque.org>
Cc: vivien.didelot@gmail.com, f.fainelli@gmail.com,
davem@davemloft.net, netdev@vger.kernel.org
Subject: Re: [PATCH] net: dsa: mv88e6xxx: don't force settings on CPU port
Date: Mon, 30 Mar 2020 20:23:07 +0200 [thread overview]
Message-ID: <20200330182307.GG23477@lunn.ch> (raw)
In-Reply-To: <7a777bc3-9109-153a-a735-e36718c06db5@zonque.org>
On Mon, Mar 30, 2020 at 08:04:08PM +0200, Daniel Mack wrote:
> Hi Andrew,
>
> Thanks for all your input.
>
> On 3/30/20 3:40 PM, Andrew Lunn wrote:
> > On Mon, Mar 30, 2020 at 11:29:27AM +0200, Daniel Mack wrote:
> >> On 3/28/20 12:52 AM, Andrew Lunn wrote:
>
> >>> By explicitly saying there is a PHY for the CPU node, phylink might
> >>> drive it.
> >
> > You want to debug this. Although what you have is unusual, yours is
> > not the only board. It is something we want to work. And ideally,
> > there should be something controlling the PHY.
>
> I agree, but what I believe is happening here is this. The PHY inside
> the switch negotiates a link to the 'external' PHY which is forced to
> 100M maximum speed. That link seems to work fine; the LEDs connected to
> that external PHY indicate that there is link. However, the internal PHY
> in the switch does not receive any packets as the MAC connected to it
> only wants to communicate with 1G.
Which is what phylink is all about. phylink will talk to the PHY,
figure out what it has negotiated, and then configure the MAC to
fit. So you need to debug why this is not happening.
Andrew
next prev parent reply other threads:[~2020-03-30 18:23 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-27 19:51 [PATCH] net: dsa: mv88e6xxx: don't force settings on CPU port Daniel Mack
2020-03-27 20:01 ` Andrew Lunn
2020-03-27 20:48 ` Daniel Mack
2020-03-27 21:18 ` Andrew Lunn
2020-03-27 21:26 ` Daniel Mack
2020-03-27 23:52 ` Andrew Lunn
2020-03-30 9:29 ` Daniel Mack
2020-03-30 13:40 ` Andrew Lunn
2020-03-30 18:04 ` Daniel Mack
2020-03-30 18:23 ` Andrew Lunn [this message]
2020-03-30 18:37 ` Daniel Mack
2020-03-30 18:45 ` Andrew Lunn
2020-06-22 18:43 ` Daniel Mack
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