* [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
@ 2020-04-01 6:48 Yuxian Dai
0 siblings, 0 replies; 11+ messages in thread
From: Yuxian Dai @ 2020-04-01 6:48 UTC (permalink / raw)
To: amd-gfx; +Cc: yuxiadai, Yuxian Dai
From: "yuxiadai@amd.com" <yuxiadai@amd.com>
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..30240fdff840 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value)
+ cur_value_match_level = true;
}
+
+ if(!cur_value_match_level)
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
+
return size;
}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
2020-04-02 6:04 ` Huang Rui
@ 2020-04-02 6:09 ` Dai, Yuxian (David)
0 siblings, 0 replies; 11+ messages in thread
From: Dai, Yuxian (David) @ 2020-04-02 6:09 UTC (permalink / raw)
To: Huang, Ray; +Cc: amd-gfx
[AMD Official Use Only - Internal Distribution Only]
On Wed, Apr 01, 2020 at 07:41:12PM +0800, Yuxian Dai wrote:
> 1.Using the FCLK DPM table to set the MCLK for DPM states consist of
> three entities:
> FCLK
> UCLK
> MEMCLK
> All these three clk change together, MEMCLK from FCLK, so use the fclk
> frequency.
> 2.we should show the current working clock freqency from clock table
> metric
>
> Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
> ---
Next time, if you submit the V2 patch, you can generate it as below
command:
git format-patch --subject-prefix="PATCH v2"
And describe the changes from v1 -> v2 in the commit message. This will help everyone to understand your change.
> I got it.
Reviewed-by: Huang Rui <ray.huang@amd.com>
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++++++
> drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 7bf52ecba01d..c6b39a7026a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
> uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_t metrics;
> + bool cur_value_match_level = false;
>
> if (!clk_table || clk_type >= SMU_CLK_COUNT)
> return -EINVAL;
> @@ -297,8 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
> GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
> size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
> cur_value == value ? "*" : "");
> + if (cur_value == value)
> + cur_value_match_level = true;
> }
>
> + if (!cur_value_match_level)
> + size += sprintf(buf + size, " %uMhz *\n", cur_value);
> +
> return size;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
> index 2a390ddd37dd..89cd6da118a3 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
> @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
> freq = table->SocClocks[dpm_level].Freq; \
> break; \
> case SMU_MCLK: \
> - freq = table->MemClocks[dpm_level].Freq; \
> + freq = table->FClocks[dpm_level].Freq; \
> break; \
> case SMU_DCEFCLK: \
> freq = table->DcfClocks[dpm_level].Freq; \
> --
> 2.17.1
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
2020-04-01 11:41 Yuxian Dai
@ 2020-04-02 6:04 ` Huang Rui
2020-04-02 6:09 ` Dai, Yuxian (David)
0 siblings, 1 reply; 11+ messages in thread
From: Huang Rui @ 2020-04-02 6:04 UTC (permalink / raw)
To: Yuxian Dai; +Cc: amd-gfx
On Wed, Apr 01, 2020 at 07:41:12PM +0800, Yuxian Dai wrote:
> 1.Using the FCLK DPM table to set the MCLK for DPM states consist of
> three entities:
> FCLK
> UCLK
> MEMCLK
> All these three clk change together, MEMCLK from FCLK, so use the fclk
> frequency.
> 2.we should show the current working clock freqency from clock table metric
>
> Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
> ---
Next time, if you submit the V2 patch, you can generate it as below
command:
git format-patch --subject-prefix="PATCH v2"
And describe the changes from v1 -> v2 in the commit message. This will
help everyone to understand your change.
Reviewed-by: Huang Rui <ray.huang@amd.com>
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++++++
> drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 7bf52ecba01d..c6b39a7026a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
> uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_t metrics;
> + bool cur_value_match_level = false;
>
> if (!clk_table || clk_type >= SMU_CLK_COUNT)
> return -EINVAL;
> @@ -297,8 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
> GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
> size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
> cur_value == value ? "*" : "");
> + if (cur_value == value)
> + cur_value_match_level = true;
> }
>
> + if (!cur_value_match_level)
> + size += sprintf(buf + size, " %uMhz *\n", cur_value);
> +
> return size;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
> index 2a390ddd37dd..89cd6da118a3 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
> @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
> freq = table->SocClocks[dpm_level].Freq; \
> break; \
> case SMU_MCLK: \
> - freq = table->MemClocks[dpm_level].Freq; \
> + freq = table->FClocks[dpm_level].Freq; \
> break; \
> case SMU_DCEFCLK: \
> freq = table->DcfClocks[dpm_level].Freq; \
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cray.huang%40amd.com%7Cfa81baf94d2c409e4f0308d7d6319a8f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637213381443101089&sdata=LF2pLZj%2Fq0CwiMSfvDiofXFKuGVfgje7o4Iti%2FtoNj0%3D&reserved=0
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
@ 2020-04-01 11:41 Yuxian Dai
2020-04-02 6:04 ` Huang Rui
0 siblings, 1 reply; 11+ messages in thread
From: Yuxian Dai @ 2020-04-01 11:41 UTC (permalink / raw)
To: amd-gfx; +Cc: Yuxian Dai
1.Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2.we should show the current working clock freqency from clock table metric
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..c6b39a7026a8 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,8 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if (cur_value == value)
+ cur_value_match_level = true;
}
+ if (!cur_value_match_level)
+ size += sprintf(buf + size, " %uMhz *\n", cur_value);
+
return size;
}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
@ 2020-04-01 8:31 Yuxian Dai
0 siblings, 0 replies; 11+ messages in thread
From: Yuxian Dai @ 2020-04-01 8:31 UTC (permalink / raw)
To: amd-gfx; +Cc: yuxiadai, Yuxian Dai
From: "yuxiadai@amd.com" <yuxiadai@amd.com>
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5adc25c8f6f4 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,7 +298,12 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if (cur_value == value)
+ cur_value_match_level = true;
}
+
+ if (!cur_value_match_level)
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
return size;
}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
2020-04-01 7:14 Yuxian Dai
@ 2020-04-01 8:27 ` Wang, Kevin(Yang)
0 siblings, 0 replies; 11+ messages in thread
From: Wang, Kevin(Yang) @ 2020-04-01 8:27 UTC (permalink / raw)
To: Dai, Yuxian (David), amd-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3698 bytes --]
[AMD Official Use Only - Internal Distribution Only]
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Yuxian Dai <Yuxian.Dai@amd.com>
Sent: Wednesday, April 1, 2020 3:14 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Dai, Yuxian (David) <Yuxian.Dai@amd.com>; Dai, Yuxian (David) <Yuxian.Dai@amd.com>
Subject: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxiadai@amd.com" <yuxiadai@amd.com>
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..3901b20196d7 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if (cur_value == value)
+ cur_value_match_level = true;
}
+
+ if (!cur_value_match_level)
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
+
[kevin]:
after remove this unnecessary blank line,
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
return size;
}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
@ 2020-04-01 7:14 Yuxian Dai
2020-04-01 8:27 ` Wang, Kevin(Yang)
0 siblings, 1 reply; 11+ messages in thread
From: Yuxian Dai @ 2020-04-01 7:14 UTC (permalink / raw)
To: amd-gfx; +Cc: yuxiadai, Yuxian Dai
From: "yuxiadai@amd.com" <yuxiadai@amd.com>
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..3901b20196d7 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if (cur_value == value)
+ cur_value_match_level = true;
}
+
+ if (!cur_value_match_level)
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
+
return size;
}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* RE: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
2020-04-01 6:40 ` Wang, Kevin(Yang)
@ 2020-04-01 6:51 ` Dai, Yuxian (David)
0 siblings, 0 replies; 11+ messages in thread
From: Dai, Yuxian (David) @ 2020-04-01 6:51 UTC (permalink / raw)
To: Wang, Kevin(Yang), amd-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3998 bytes --]
[AMD Official Use Only - Internal Distribution Only]
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com<mailto:Yuxian.Dai@amd.com>>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5c5d3f974532 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
[kevin]:
I have a little suggestion about coding style.
"Do not unnecessarily use braces where a single statement will do."
we'd better fix it.
thanks.
* Ok, I will remove it.
https://www.kernel.org/doc/html/latest/process/coding-style.html
Linux kernel coding style - The Linux Kernel documentation<https://www.kernel.org/doc/html/latest/process/coding-style.html>
Linux kernel coding style¶. This is a short document describing the preferred coding style for the linux kernel. Coding style is very personal, and I won't force my views on anybody, but this is what goes for anything that I have to be able to maintain, and I'd prefer it for most other things too. Please at least consider the points made here.
www.kernel.org<http://www.kernel.org>
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
2020-04-01 6:02 Yuxian Dai
@ 2020-04-01 6:40 ` Wang, Kevin(Yang)
2020-04-01 6:51 ` Dai, Yuxian (David)
0 siblings, 1 reply; 11+ messages in thread
From: Wang, Kevin(Yang) @ 2020-04-01 6:40 UTC (permalink / raw)
To: Dai, Yuxian (David), amd-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4342 bytes --]
[AMD Official Use Only - Internal Distribution Only]
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Yuxian Dai <Yuxian.Dai@amd.com>
Sent: Wednesday, April 1, 2020 2:02 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Dai, Yuxian (David) <Yuxian.Dai@amd.com>; Dai, Yuxian (David) <Yuxian.Dai@amd.com>
Subject: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxiadai@amd.com" <yuxiadai@amd.com>
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5c5d3f974532 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
[kevin]:
I have a little suggestion about coding style.
"Do not unnecessarily use braces where a single statement will do."
we'd better fix it.
thanks.
https://www.kernel.org/doc/html/latest/process/coding-style.html
Linux kernel coding style — The Linux Kernel documentation<https://www.kernel.org/doc/html/latest/process/coding-style.html>
Linux kernel coding style¶. This is a short document describing the preferred coding style for the linux kernel. Coding style is very personal, and I won’t force my views on anybody, but this is what goes for anything that I have to be able to maintain, and I’d prefer it for most other things too. Please at least consider the points made here.
www.kernel.org
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
@ 2020-04-01 6:02 Yuxian Dai
2020-04-01 6:40 ` Wang, Kevin(Yang)
0 siblings, 1 reply; 11+ messages in thread
From: Yuxian Dai @ 2020-04-01 6:02 UTC (permalink / raw)
To: amd-gfx; +Cc: yuxiadai, Yuxian Dai
From: "yuxiadai@amd.com" <yuxiadai@amd.com>
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5c5d3f974532 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
@ 2020-04-01 5:53 Yuxian Dai
0 siblings, 0 replies; 11+ messages in thread
From: Yuxian Dai @ 2020-04-01 5:53 UTC (permalink / raw)
To: amd-gfx; +Cc: yuxiadai, Yuxian Dai
From: "yuxiadai@amd.com" <yuxiadai@amd.com>
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 9 ++++++++-
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..32e7a3c05cd4 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,7 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
-
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +297,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq; \
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq; \
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq; \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-04-02 6:09 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-01 6:48 [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK Yuxian Dai
-- strict thread matches above, loose matches on Subject: below --
2020-04-01 11:41 Yuxian Dai
2020-04-02 6:04 ` Huang Rui
2020-04-02 6:09 ` Dai, Yuxian (David)
2020-04-01 8:31 Yuxian Dai
2020-04-01 7:14 Yuxian Dai
2020-04-01 8:27 ` Wang, Kevin(Yang)
2020-04-01 6:02 Yuxian Dai
2020-04-01 6:40 ` Wang, Kevin(Yang)
2020-04-01 6:51 ` Dai, Yuxian (David)
2020-04-01 5:53 Yuxian Dai
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