* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 11:07 Harry Pan
2020-04-22 19:54 ` [tip: perf/urgent] " tip-bot2 for Harry Pan
0 siblings, 1 reply; 5+ messages in thread
From: Harry Pan @ 2020-04-02 11:07 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [tip: perf/urgent] perf/x86/cstate: Add Jasper Lake CPU support
2020-04-02 11:07 [PATCH] perf/x86/cstate: Add Jasper Lake CPU support Harry Pan
@ 2020-04-22 19:54 ` tip-bot2 for Harry Pan
0 siblings, 0 replies; 5+ messages in thread
From: tip-bot2 for Harry Pan @ 2020-04-22 19:54 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Harry Pan, Borislav Petkov, x86, LKML
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 5b16ef2e43ffa1be596652d992235b1cbb244935
Gitweb: https://git.kernel.org/tip/5b16ef2e43ffa1be596652d992235b1cbb244935
Author: Harry Pan <harry.pan@intel.com>
AuthorDate: Thu, 02 Apr 2020 19:07:09 +08:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Wed, 22 Apr 2020 21:43:12 +02:00
perf/x86/cstate: Add Jasper Lake CPU support
The Jasper Lake processor is Tremont microarchitecture, reuse the
glm_cstates table of Goldmont and Goldmont Plus to enable the C-states
residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200402190658.1.Ic02e891daac41303aed1f2fc6c64f6110edd27bd@changeid
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c..442e1ed 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 14:49 Harry Pan
0 siblings, 0 replies; 5+ messages in thread
From: Harry Pan @ 2020-04-02 14:49 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 14:48 Harry Pan
0 siblings, 0 replies; 5+ messages in thread
From: Harry Pan @ 2020-04-02 14:48 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 13:42 Harry Pan
0 siblings, 0 replies; 5+ messages in thread
From: Harry Pan @ 2020-04-02 13:42 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-22 19:54 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-04-02 11:07 [PATCH] perf/x86/cstate: Add Jasper Lake CPU support Harry Pan
2020-04-22 19:54 ` [tip: perf/urgent] " tip-bot2 for Harry Pan
2020-04-02 13:42 [PATCH] " Harry Pan
2020-04-02 14:48 Harry Pan
2020-04-02 14:49 Harry Pan
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