From: Peter Zijlstra <peterz@infradead.org> To: Masami Hiramatsu <mhiramat@kernel.org> Cc: "Christian König" <christian.koenig@amd.com>, "Jann Horn" <jannh@google.com>, "Harry Wentland" <harry.wentland@amd.com>, "Leo Li" <sunpeng.li@amd.com>, amd-gfx@lists.freedesktop.org, "Alex Deucher" <alexander.deucher@amd.com>, "David (ChunMing) Zhou" <David1.Zhou@amd.com>, "Thomas Gleixner" <tglx@linutronix.de>, "Ingo Molnar" <mingo@redhat.com>, "Borislav Petkov" <bp@alien8.de>, "H. Peter Anvin" <hpa@zytor.com>, "the arch/x86 maintainers" <x86@kernel.org>, "kernel list" <linux-kernel@vger.kernel.org>, "Josh Poimboeuf" <jpoimboe@redhat.com>, "Andy Lutomirski" <luto@kernel.org>, "Arnaldo Carvalho de Melo" <acme@kernel.org> Subject: Re: AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Date: Tue, 7 Apr 2020 17:54:49 +0200 [thread overview] Message-ID: <20200407155449.GF20730@hirez.programming.kicks-ass.net> (raw) In-Reply-To: <20200408004111.3dd597f2a7c6172b4c71a9ba@kernel.org> On Wed, Apr 08, 2020 at 12:41:11AM +0900, Masami Hiramatsu wrote: > On Tue, 7 Apr 2020 13:15:35 +0200 > Peter Zijlstra <peterz@infradead.org> wrote: > > > > Also, all the VMX bits seems to qualify as FPU (I can't remember seeing > > > > that previously): > > > > > > Oops, let me check it. > > > > I just send you another patch that could do with insn_is_vmx() > > (sorry!!!) > > Hmm, it is hard to find out the vmx insns. Maybe we need to clarify it by > opcode pattern. (like "VM.*") Yeah, I know. Maybe I should just keep it as I have for now. One thing I thought of is we could perhaps add manual markers in x86-opcode-map.txt. The '{','}' characters appear unused so far, we perhaps we can use them to classify things. That could maybe replace "mmx_expr" as well. That is, something like so: --- diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index ec31f5b60323..e01b76e0a294 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -462,9 +462,9 @@ AVXcode: 1 75: pcmpeqw Pq,Qq | vpcmpeqw Vx,Hx,Wx (66),(v1) 76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1) # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. -77: emms | vzeroupper | vzeroall -78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) -79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) +77: emms {FPU} | vzeroupper | vzeroall +78: VMREAD Ey,Gy {VMX} | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) +79: VMWRITE Gy,Ey {VMX} | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) 7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev) 7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev) 7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2) @@ -965,9 +965,9 @@ GrpTable: Grp6 EndTable GrpTable: Grp7 -0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) +0: SGDT Ms | VMCALL (001),(11B) {VMX} | VMLAUNCH (010),(11B) {VMX} | VMRESUME (011),(11B) {VMX} | VMXOFF (100),(11B) {VMX} | PCONFIG (101),(11B) | ENCLV (000),(11B) 1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) -2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) +2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) {VMX} | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) 3: LIDT Ms 4: SMSW Mw/Rv 5: rdpkru (110),(11B) | wrpkru (111),(11B) | SAVEPREVSSP (F3),(010),(11B) | RSTORSSP Mq (F3) | SETSSBSY (F3),(000),(11B) @@ -987,8 +987,8 @@ GrpTable: Grp9 3: xrstors 4: xsavec 5: xsaves -6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B) -7: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B) +6: VMPTRLD Mq {VMX} | VMCLEAR Mq (66) {VMX} | VMXON Mq (F3) {VMX} | RDRAND Rv (11B) +7: VMPTRST Mq {VMX} | VMPTRST Mq (F3) {VMX} | RDSEED Rv (11B) EndTable GrpTable: Grp10 @@ -1036,10 +1036,10 @@ GrpTable: Grp14 EndTable GrpTable: Grp15 -0: fxsave | RDFSBASE Ry (F3),(11B) -1: fxstor | RDGSBASE Ry (F3),(11B) -2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) -3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) +0: fxsave {FPU} | RDFSBASE Ry (F3),(11B) +1: fxrstor {FPU} | RDGSBASE Ry (F3),(11B) +2: ldmxcsr {FPU} | vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) +3: stmxcsr {FPU} | vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) 4: XSAVE | ptwrite Ey (F3),(11B) 5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B) 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3)
WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org> To: Masami Hiramatsu <mhiramat@kernel.org> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>, "Josh Poimboeuf" <jpoimboe@redhat.com>, "Jann Horn" <jannh@google.com>, "Leo Li" <sunpeng.li@amd.com>, "the arch/x86 maintainers" <x86@kernel.org>, "kernel list" <linux-kernel@vger.kernel.org>, amd-gfx@lists.freedesktop.org, "Ingo Molnar" <mingo@redhat.com>, "Borislav Petkov" <bp@alien8.de>, "Arnaldo Carvalho de Melo" <acme@kernel.org>, "Andy Lutomirski" <luto@kernel.org>, "H. Peter Anvin" <hpa@zytor.com>, "Alex Deucher" <alexander.deucher@amd.com>, "Thomas Gleixner" <tglx@linutronix.de>, "Harry Wentland" <harry.wentland@amd.com>, "Christian König" <christian.koenig@amd.com> Subject: Re: AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Date: Tue, 7 Apr 2020 17:54:49 +0200 [thread overview] Message-ID: <20200407155449.GF20730@hirez.programming.kicks-ass.net> (raw) In-Reply-To: <20200408004111.3dd597f2a7c6172b4c71a9ba@kernel.org> On Wed, Apr 08, 2020 at 12:41:11AM +0900, Masami Hiramatsu wrote: > On Tue, 7 Apr 2020 13:15:35 +0200 > Peter Zijlstra <peterz@infradead.org> wrote: > > > > Also, all the VMX bits seems to qualify as FPU (I can't remember seeing > > > > that previously): > > > > > > Oops, let me check it. > > > > I just send you another patch that could do with insn_is_vmx() > > (sorry!!!) > > Hmm, it is hard to find out the vmx insns. Maybe we need to clarify it by > opcode pattern. (like "VM.*") Yeah, I know. Maybe I should just keep it as I have for now. One thing I thought of is we could perhaps add manual markers in x86-opcode-map.txt. The '{','}' characters appear unused so far, we perhaps we can use them to classify things. That could maybe replace "mmx_expr" as well. That is, something like so: --- diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index ec31f5b60323..e01b76e0a294 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -462,9 +462,9 @@ AVXcode: 1 75: pcmpeqw Pq,Qq | vpcmpeqw Vx,Hx,Wx (66),(v1) 76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1) # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. -77: emms | vzeroupper | vzeroall -78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) -79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) +77: emms {FPU} | vzeroupper | vzeroall +78: VMREAD Ey,Gy {VMX} | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) +79: VMWRITE Gy,Ey {VMX} | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) 7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev) 7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev) 7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2) @@ -965,9 +965,9 @@ GrpTable: Grp6 EndTable GrpTable: Grp7 -0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) +0: SGDT Ms | VMCALL (001),(11B) {VMX} | VMLAUNCH (010),(11B) {VMX} | VMRESUME (011),(11B) {VMX} | VMXOFF (100),(11B) {VMX} | PCONFIG (101),(11B) | ENCLV (000),(11B) 1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) -2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) +2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) {VMX} | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) 3: LIDT Ms 4: SMSW Mw/Rv 5: rdpkru (110),(11B) | wrpkru (111),(11B) | SAVEPREVSSP (F3),(010),(11B) | RSTORSSP Mq (F3) | SETSSBSY (F3),(000),(11B) @@ -987,8 +987,8 @@ GrpTable: Grp9 3: xrstors 4: xsavec 5: xsaves -6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B) -7: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B) +6: VMPTRLD Mq {VMX} | VMCLEAR Mq (66) {VMX} | VMXON Mq (F3) {VMX} | RDRAND Rv (11B) +7: VMPTRST Mq {VMX} | VMPTRST Mq (F3) {VMX} | RDSEED Rv (11B) EndTable GrpTable: Grp10 @@ -1036,10 +1036,10 @@ GrpTable: Grp14 EndTable GrpTable: Grp15 -0: fxsave | RDFSBASE Ry (F3),(11B) -1: fxstor | RDGSBASE Ry (F3),(11B) -2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) -3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) +0: fxsave {FPU} | RDFSBASE Ry (F3),(11B) +1: fxrstor {FPU} | RDGSBASE Ry (F3),(11B) +2: ldmxcsr {FPU} | vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) +3: stmxcsr {FPU} | vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) 4: XSAVE | ptwrite Ey (F3),(11B) 5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B) 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3) _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2020-04-07 15:55 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-02 2:34 AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Jann Horn 2020-04-02 2:34 ` Jann Horn 2020-04-02 7:33 ` Christian König 2020-04-02 7:33 ` Christian König 2020-04-02 7:56 ` Jann Horn 2020-04-02 7:56 ` Jann Horn 2020-04-02 9:36 ` Thomas Gleixner 2020-04-02 9:36 ` Thomas Gleixner 2020-04-02 14:50 ` Jann Horn 2020-04-02 14:50 ` Jann Horn 2020-04-02 14:13 ` Peter Zijlstra 2020-04-02 14:13 ` Peter Zijlstra 2020-04-03 5:28 ` Masami Hiramatsu 2020-04-03 5:28 ` Masami Hiramatsu 2020-04-03 11:21 ` Peter Zijlstra 2020-04-03 11:21 ` Peter Zijlstra 2020-04-04 3:08 ` Masami Hiramatsu 2020-04-04 3:08 ` Masami Hiramatsu 2020-04-04 3:15 ` Randy Dunlap 2020-04-04 3:15 ` Randy Dunlap 2020-04-04 8:32 ` Masami Hiramatsu 2020-04-04 8:32 ` Masami Hiramatsu 2020-04-04 14:32 ` Peter Zijlstra 2020-04-04 14:32 ` Peter Zijlstra 2020-04-05 3:19 ` Masami Hiramatsu 2020-04-05 3:19 ` Masami Hiramatsu 2020-04-06 10:21 ` Peter Zijlstra 2020-04-06 10:21 ` Peter Zijlstra 2020-04-07 9:50 ` Masami Hiramatsu 2020-04-07 9:50 ` Masami Hiramatsu 2020-04-07 11:15 ` Peter Zijlstra 2020-04-07 11:15 ` Peter Zijlstra 2020-04-07 15:41 ` Masami Hiramatsu 2020-04-07 15:41 ` Masami Hiramatsu 2020-04-07 15:43 ` [PATCH] x86: insn: Add insn_is_fpu() Masami Hiramatsu 2020-04-07 15:43 ` Masami Hiramatsu 2020-04-07 15:54 ` Peter Zijlstra [this message] 2020-04-07 15:54 ` AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Peter Zijlstra 2020-04-08 0:31 ` Masami Hiramatsu 2020-04-08 0:31 ` Masami Hiramatsu 2020-04-08 16:09 ` [PATCH v2] x86: insn: Add insn_is_fpu() Masami Hiramatsu 2020-04-08 16:09 ` Masami Hiramatsu 2020-04-09 14:32 ` Peter Zijlstra 2020-04-09 14:32 ` Peter Zijlstra 2020-04-09 14:45 ` Peter Zijlstra 2020-04-09 14:45 ` Peter Zijlstra 2020-04-10 0:47 ` Masami Hiramatsu 2020-04-10 0:47 ` Masami Hiramatsu 2020-04-10 1:22 ` [PATCH v3] " Masami Hiramatsu 2020-04-10 1:22 ` Masami Hiramatsu 2020-04-15 8:23 ` Masami Hiramatsu 2020-04-15 8:23 ` Masami Hiramatsu 2020-04-15 8:49 ` [PATCH v4] " Masami Hiramatsu 2020-04-15 8:49 ` Masami Hiramatsu 2020-04-04 14:36 ` AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Peter Zijlstra 2020-04-04 14:36 ` Peter Zijlstra 2020-04-05 3:37 ` Masami Hiramatsu 2020-04-05 3:37 ` Masami Hiramatsu 2020-04-09 15:59 ` Peter Zijlstra 2020-04-09 15:59 ` Peter Zijlstra 2020-04-09 17:09 ` Peter Zijlstra 2020-04-09 17:09 ` Peter Zijlstra 2020-04-09 18:15 ` Christian König 2020-04-09 18:15 ` Christian König 2020-04-09 20:01 ` Peter Zijlstra 2020-04-09 20:01 ` Peter Zijlstra 2020-04-10 14:31 ` Christian König 2020-04-10 14:31 ` Christian König 2020-04-15 9:16 ` Peter Zijlstra 2020-04-15 9:16 ` Peter Zijlstra 2020-04-17 20:27 ` Rodrigo Siqueira 2020-04-17 20:27 ` Rodrigo Siqueira 2020-04-17 21:56 ` Peter Zijlstra 2020-04-17 21:56 ` Peter Zijlstra
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