* [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
@ 2020-04-13 6:34 Animesh Manna
2020-04-14 15:49 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3) Patchwork
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Animesh Manna @ 2020-04-13 6:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Daniel Vetter
Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
function which also includes pinning and map in cpu domain.
No change is dsb write/commit functions.
Now dsb get/put function is refactored and currently used only for
reference counting. Below dsb api added to do respective job
mentioned below.
intel_dsb_prepare - Allocate, pin and map the buffer.
intel_dsb_cleanup - Unpin and release the gem object.
RFC: Initial patch for design review.
v2: included _init() part in _prepare(). [Daniel, Ville]
v3: dsb_cleanup called after cleanup_planes. [Daniel]
v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten]
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 47 ++++-
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 169 ++++++++++++------
drivers/gpu/drm/i915/display/intel_dsb.h | 6 +-
5 files changed, 170 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 98ece9cd7cdd..fb2caee90734 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -717,7 +717,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
@@ -900,7 +900,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
/* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
@@ -916,7 +916,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
const struct drm_color_lut *lut = blob->data;
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
int i;
@@ -949,7 +949,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
const struct drm_color_lut *lut = blob->data;
const struct drm_color_lut *entry;
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
int i;
@@ -1003,7 +1003,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
{
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
+
+ /*
+ * TODO: Currently dsb buffer filling is done in load_lut() which
+ * can be done much earlier, like initial stage of atomic_commit().
+ * As currently replacing the mmio-write with dsb-write so the same
+ * load_lut() api is used for dsb buffer creation which may not
+ * fit in initial stage. Need to create a separate interface and
+ * a different path in color framework while dealing with dsb.
+ */
if (crtc_state->hw.degamma_lut)
glk_load_degamma_lut(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..42c4d6c7f334 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14844,8 +14844,28 @@ static int intel_atomic_check(struct drm_device *dev,
static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
{
- return drm_atomic_helper_prepare_planes(state->base.dev,
- &state->base);
+ struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i, ret;
+
+ ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Failure in DSB buffer creation enable fallback mmio for register
+ * programming and erroneous path will be handled by dsp-write api.
+ */
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ bool mode_changed = needs_modeset(crtc_state);
+
+ if (mode_changed || crtc_state->update_pipe ||
+ crtc_state->uapi.color_mgmt_changed) {
+ intel_dsb_prepare(crtc_state);
+ }
+ }
+
+ return 0;
}
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
@@ -15298,15 +15318,26 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat
&wait_reset);
}
+static void intel_cleanup_dsbs(struct intel_atomic_state *state)
+{
+ struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
+ intel_dsb_cleanup(crtc_state);
+}
+
static void intel_atomic_cleanup_work(struct work_struct *work)
{
- struct drm_atomic_state *state =
- container_of(work, struct drm_atomic_state, commit_work);
- struct drm_i915_private *i915 = to_i915(state->dev);
+ struct intel_atomic_state *state =
+ container_of(work, struct intel_atomic_state, base.commit_work);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
- drm_atomic_helper_cleanup_planes(&i915->drm, state);
- drm_atomic_helper_commit_cleanup_done(state);
- drm_atomic_state_put(state);
+ drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
+ intel_cleanup_dsbs(state);
+ drm_atomic_helper_commit_cleanup_done(&state->base);
+ drm_atomic_state_put(&state->base);
intel_atomic_helper_free_state(i915);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ba8c08145c88..8b21bab088ea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1079,6 +1079,9 @@ struct intel_crtc_state {
/* Only valid on TGL+ */
enum transcoder mst_master_transcoder;
+
+ /* For DSB related info */
+ struct intel_dsb dsb;
};
enum intel_pipe_crc_source {
@@ -1148,9 +1151,6 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
- /* per pipe DSB related info */
- struct intel_dsb dsb;
-
#ifdef CONFIG_DEBUG_FS
struct intel_pipe_crc pipe_crc;
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index d7a6bf2277df..2c5840240ddc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -34,9 +34,92 @@
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK 0xfffff
+/**
+ * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function prepare the command buffer which is used to store dsb
+ * instructions with data.
+ */
+
+void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = &crtc_state->dsb;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *buf;
+ intel_wakeref_t wakeref;
+
+ if (!HAS_DSB(i915) || dsb->cmd_buf)
+ return;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Gem object creation failed\n");
+ goto out;
+ }
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("Vma creation failed\n");
+ i915_gem_object_put(obj);
+ goto out;
+ }
+
+ buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(buf)) {
+ DRM_ERROR("Command buffer creation failed\n");
+ goto out;
+ }
+
+ dsb->id = DSB1;
+ dsb->vma = vma;
+ dsb->cmd_buf = buf;
+
+out:
+ /*
+ * On error dsb->cmd_buf will continue to be NULL, making the writes
+ * pass-through. Leave the dangling ref to be removed later by the
+ * corresponding intel_dsb_put(): the important error message will
+ * already be logged above.
+ */
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+}
+
+/**
+ * intel_dsb_cleanup() - To cleanup DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function cleanup the DSB context by unpinning and releasing
+ * the VMA object associated with it.
+ */
+
+void intel_dsb_cleanup(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = &crtc_state->dsb;
+
+ if (!HAS_DSB(i915))
+ return;
+
+ if (dsb->vma) {
+ i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
+ dsb->vma = NULL;
+ dsb->cmd_buf = NULL;
+ }
+}
+
static inline bool is_dsb_busy(struct intel_dsb *dsb)
{
- struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct intel_crtc_state *crtc_state =
+ container_of(dsb, typeof(*crtc_state), dsb);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -45,7 +128,9 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
{
- struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct intel_crtc_state *crtc_state =
+ container_of(dsb, typeof(*crtc_state), dsb);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 dsb_ctrl;
@@ -65,7 +150,9 @@ static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
{
- struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct intel_crtc_state *crtc_state =
+ container_of(dsb, typeof(*crtc_state), dsb);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 dsb_ctrl;
@@ -84,68 +171,26 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
}
/**
- * intel_dsb_get() - Allocate DSB context and return a DSB instance.
+ * intel_dsb_get() - Return a DSB instance and increase reference count.
* @crtc: intel_crtc structure to get pipe info.
*
* This function provides handle of a DSB instance, for the further DSB
* operations.
*
* Returns: address of Intel_dsb instance requested for.
- * Failure: Returns the same DSB instance, but without a command buffer.
*/
struct intel_dsb *
-intel_dsb_get(struct intel_crtc *crtc)
+intel_dsb_get(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *i915 = to_i915(dev);
- struct intel_dsb *dsb = &crtc->dsb;
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- u32 *buf;
- intel_wakeref_t wakeref;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = &crtc_state->dsb;
if (!HAS_DSB(i915))
return dsb;
- if (dsb->refcount++ != 0)
- return dsb;
-
- wakeref = intel_runtime_pm_get(&i915->runtime_pm);
-
- obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
- if (IS_ERR(obj)) {
- drm_err(&i915->drm, "Gem object creation failed\n");
- goto out;
- }
-
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
- if (IS_ERR(vma)) {
- drm_err(&i915->drm, "Vma creation failed\n");
- i915_gem_object_put(obj);
- goto out;
- }
-
- buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
- if (IS_ERR(buf)) {
- drm_err(&i915->drm, "Command buffer creation failed\n");
- goto out;
- }
-
- dsb->id = DSB1;
- dsb->vma = vma;
- dsb->cmd_buf = buf;
-
-out:
- /*
- * On error dsb->cmd_buf will continue to be NULL, making the writes
- * pass-through. Leave the dangling ref to be removed later by the
- * corresponding intel_dsb_put(): the important error message will
- * already be logged above.
- */
-
- intel_runtime_pm_put(&i915->runtime_pm, wakeref);
-
+ dsb->refcount++;
return dsb;
}
@@ -153,13 +198,15 @@ intel_dsb_get(struct intel_crtc *crtc)
* intel_dsb_put() - To destroy DSB context.
* @dsb: intel_dsb structure.
*
- * This function destroys the DSB context allocated by a dsb_get(), by
- * unpinning and releasing the VMA object associated with it.
+ * This function decrease the reference count and reset the command
+ * buffer position.
*/
void intel_dsb_put(struct intel_dsb *dsb)
{
- struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct intel_crtc_state *crtc_state =
+ container_of(dsb, typeof(*crtc_state), dsb);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
if (!HAS_DSB(i915))
@@ -169,8 +216,6 @@ void intel_dsb_put(struct intel_dsb *dsb)
return;
if (--dsb->refcount == 0) {
- i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
- dsb->cmd_buf = NULL;
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
}
@@ -192,7 +237,9 @@ void intel_dsb_put(struct intel_dsb *dsb)
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
{
- struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct intel_crtc_state *crtc_state =
+ container_of(dsb, typeof(*crtc_state), dsb);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 *buf = dsb->cmd_buf;
u32 reg_val;
@@ -267,7 +314,9 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
*/
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
- struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct intel_crtc_state *crtc_state =
+ container_of(dsb, typeof(*crtc_state), dsb);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 *buf = dsb->cmd_buf;
@@ -297,7 +346,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
*/
void intel_dsb_commit(struct intel_dsb *dsb)
{
- struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct intel_crtc_state *crtc_state =
+ container_of(dsb, typeof(*crtc_state), dsb);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum pipe pipe = crtc->pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 395ef9ce558e..65e2d0d1c71e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -10,7 +10,7 @@
#include "i915_reg.h"
-struct intel_crtc;
+struct intel_crtc_state;
struct i915_vma;
enum dsb_id {
@@ -41,8 +41,10 @@ struct intel_dsb {
u32 ins_start_offset;
};
+void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
+void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
struct intel_dsb *
-intel_dsb_get(struct intel_crtc *crtc);
+intel_dsb_get(struct intel_crtc_state *crtc_state);
void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
--
2.26.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3)
2020-04-13 6:34 [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna
@ 2020-04-14 15:49 ` Patchwork
2020-04-14 15:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-14 15:49 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3)
URL : https://patchwork.freedesktop.org/series/73036/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_dsb.c:46: warning: Excess function parameter 'crtc' description in 'intel_dsb_prepare'
./drivers/gpu/drm/i915/display/intel_dsb.c:103: warning: Excess function parameter 'dsb' description in 'intel_dsb_cleanup'
./drivers/gpu/drm/i915/display/intel_dsb.c:185: warning: Excess function parameter 'crtc' description in 'intel_dsb_get'
./drivers/gpu/drm/i915/display/intel_dsb.c:47: warning: Function parameter or member 'crtc_state' not described in 'intel_dsb_prepare'
./drivers/gpu/drm/i915/display/intel_dsb.c:47: warning: Excess function parameter 'crtc' description in 'intel_dsb_prepare'
./drivers/gpu/drm/i915/display/intel_dsb.c:104: warning: Function parameter or member 'crtc_state' not described in 'intel_dsb_cleanup'
./drivers/gpu/drm/i915/display/intel_dsb.c:104: warning: Excess function parameter 'dsb' description in 'intel_dsb_cleanup'
./drivers/gpu/drm/i915/display/intel_dsb.c:186: warning: Function parameter or member 'crtc_state' not described in 'intel_dsb_get'
./drivers/gpu/drm/i915/display/intel_dsb.c:186: warning: Excess function parameter 'crtc' description in 'intel_dsb_get'
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3)
2020-04-13 6:34 [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna
2020-04-14 15:49 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3) Patchwork
@ 2020-04-14 15:55 ` Patchwork
2020-04-15 10:31 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-16 9:49 ` [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Maarten Lankhorst
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-14 15:55 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3)
URL : https://patchwork.freedesktop.org/series/73036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8295 -> Patchwork_17284
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/index.html
Known issues
------------
Here are the changes found in Patchwork_17284 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@active:
- fi-bxt-dsi: [PASS][1] -> [DMESG-FAIL][2] ([i915#666])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/fi-bxt-dsi/igt@i915_selftest@live@active.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/fi-bxt-dsi/igt@i915_selftest@live@active.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bsw-n3050: [PASS][3] -> [FAIL][4] ([i915#34])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [INCOMPLETE][5] ([i915#69]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
Participating hosts (49 -> 44)
------------------------------
Missing (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8295 -> Patchwork_17284
CI-20190529: 20190529
CI_DRM_8295: 4cb6dbe0a641129fd07ad1fbfcd6e7b4f03ec5c1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5589: 31962324ac86f029e2841e56e97c42cf9d572956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17284: 5cb8627a887d840870f43c69355eea329635b677 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5cb8627a887d drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3)
2020-04-13 6:34 [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna
2020-04-14 15:49 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3) Patchwork
2020-04-14 15:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-15 10:31 ` Patchwork
2020-04-16 9:49 ` [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Maarten Lankhorst
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-15 10:31 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3)
URL : https://patchwork.freedesktop.org/series/73036/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8295_full -> Patchwork_17284_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17284_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17284_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17284_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@all-pipes-torture-bo:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2] +10 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-kbl7/igt@kms_cursor_legacy@all-pipes-torture-bo.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-kbl6/igt@kms_cursor_legacy@all-pipes-torture-bo.html
* igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] +9 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-apl4/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl3/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] +13 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-tglb6/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb1/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-b-torture-bo:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] +10 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-iclb8/igt@kms_cursor_legacy@pipe-b-torture-bo.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb4/igt@kms_cursor_legacy@pipe-b-torture-bo.html
* igt@kms_cursor_legacy@pipe-c-forked-move:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] +10 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-skl3/igt@kms_cursor_legacy@pipe-c-forked-move.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-skl6/igt@kms_cursor_legacy@pipe-c-forked-move.html
* igt@runner@aborted:
- shard-iclb: NOTRUN -> ([FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb2/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb2/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb7/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb4/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb6/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb3/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb4/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb3/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb5/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb7/igt@runner@aborted.html
- shard-tglb: NOTRUN -> ([FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33]) ([k.org#205379])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb6/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb7/igt@runner@aborted.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb8/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb2/igt@runner@aborted.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb1/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb5/igt@runner@aborted.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb8/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb2/igt@runner@aborted.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb2/igt@runner@aborted.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb8/igt@runner@aborted.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb5/igt@runner@aborted.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb6/igt@runner@aborted.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-tglb5/igt@runner@aborted.html
#### Warnings ####
* igt@runner@aborted:
- shard-apl: ([FAIL][34], [FAIL][35]) ([i915#1423] / [i915#716]) -> ([FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44]) ([i915#1423])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-apl6/igt@runner@aborted.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-apl6/igt@runner@aborted.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl3/igt@runner@aborted.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl4/igt@runner@aborted.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl1/igt@runner@aborted.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl3/igt@runner@aborted.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl2/igt@runner@aborted.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl6/igt@runner@aborted.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl6/igt@runner@aborted.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl3/igt@runner@aborted.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl2/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_17284_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_params@invalid-bsd-ring:
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109276])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-iclb4/igt@gem_exec_params@invalid-bsd-ring.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb8/igt@gem_exec_params@invalid-bsd-ring.html
* igt@kms_cursor_legacy@all-pipes-forked-bo:
- shard-glk: [PASS][47] -> [INCOMPLETE][48] ([i915#58] / [k.org#198133]) +7 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-glk4/igt@kms_cursor_legacy@all-pipes-forked-bo.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-glk1/igt@kms_cursor_legacy@all-pipes-forked-bo.html
* igt@kms_cursor_legacy@pipe-b-torture-move:
- shard-snb: [PASS][49] -> [INCOMPLETE][50] ([i915#82]) +9 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-snb6/igt@kms_cursor_legacy@pipe-b-torture-move.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-snb6/igt@kms_cursor_legacy@pipe-b-torture-move.html
- shard-skl: [PASS][51] -> [INCOMPLETE][52] ([i915#69]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-skl3/igt@kms_cursor_legacy@pipe-b-torture-move.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-skl2/igt@kms_cursor_legacy@pipe-b-torture-move.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#1188])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-kbl: [PASS][55] -> [DMESG-WARN][56] ([i915#180])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][57] -> [SKIP][58] ([fdo#109441])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][59] -> [FAIL][60] ([i915#31])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-glk8/igt@kms_setmode@basic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-glk8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-apl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-apl4/igt@gem_softpin@noreloc-s3.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl4/igt@gem_softpin@noreloc-s3.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][65] ([i915#221]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][67] ([i915#1188]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-skl7/igt@kms_hdr@bpc-switch.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][69] ([i915#180]) -> [PASS][70] +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* {igt@sysfs_heartbeat_interval@mixed@vecs0}:
- shard-skl: [FAIL][71] ([i915#1459]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vecs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-skl2/igt@sysfs_heartbeat_interval@mixed@vecs0.html
#### Warnings ####
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [FAIL][73] ([i915#93] / [i915#95]) -> [DMESG-FAIL][74] ([i915#180] / [i915#95])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: [FAIL][75] ([fdo#108145] / [i915#265]) -> [FAIL][76] ([fdo#108145] / [i915#265] / [i915#95])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: [FAIL][77] ([fdo#108145] / [i915#265] / [i915#93] / [i915#95]) -> [FAIL][78] ([fdo#108145] / [i915#265])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
- shard-apl: [FAIL][79] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][80] ([fdo#108145] / [i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8295/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1423]: https://gitlab.freedesktop.org/drm/intel/issues/1423
[i915#1459]: https://gitlab.freedesktop.org/drm/intel/issues/1459
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8295 -> Patchwork_17284
CI-20190529: 20190529
CI_DRM_8295: 4cb6dbe0a641129fd07ad1fbfcd6e7b4f03ec5c1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5589: 31962324ac86f029e2841e56e97c42cf9d572956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17284: 5cb8627a887d840870f43c69355eea329635b677 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17284/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
2020-04-13 6:34 [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna
` (2 preceding siblings ...)
2020-04-15 10:31 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-04-16 9:49 ` Maarten Lankhorst
2020-04-16 10:00 ` Manna, Animesh
3 siblings, 1 reply; 6+ messages in thread
From: Maarten Lankhorst @ 2020-04-16 9:49 UTC (permalink / raw)
To: Animesh Manna, intel-gfx; +Cc: Jani Nikula, Daniel Vetter
Hey,
Seems we're lacking error handling still when get fails?
~Maarten
Op 13-04-2020 om 08:34 schreef Animesh Manna:
> Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
> function which also includes pinning and map in cpu domain.
>
> No change is dsb write/commit functions.
>
> Now dsb get/put function is refactored and currently used only for
> reference counting. Below dsb api added to do respective job
> mentioned below.
>
> intel_dsb_prepare - Allocate, pin and map the buffer.
> intel_dsb_cleanup - Unpin and release the gem object.
>
> RFC: Initial patch for design review.
> v2: included _init() part in _prepare(). [Daniel, Ville]
> v3: dsb_cleanup called after cleanup_planes. [Daniel]
> v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten]
>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 19 +-
> drivers/gpu/drm/i915/display/intel_display.c | 47 ++++-
> .../drm/i915/display/intel_display_types.h | 6 +-
> drivers/gpu/drm/i915/display/intel_dsb.c | 169 ++++++++++++------
> drivers/gpu/drm/i915/display/intel_dsb.h | 6 +-
> 5 files changed, 170 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 98ece9cd7cdd..fb2caee90734 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -717,7 +717,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
>
> /* Program the max register to clamp values > 1.0. */
> @@ -900,7 +900,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> const struct drm_color_lut *color)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
>
> /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
> @@ -916,7 +916,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
> int i;
>
> @@ -949,7 +949,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
> const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> const struct drm_color_lut *entry;
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
> int i;
>
> @@ -1003,7 +1003,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> {
> const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> +
> + /*
> + * TODO: Currently dsb buffer filling is done in load_lut() which
> + * can be done much earlier, like initial stage of atomic_commit().
> + * As currently replacing the mmio-write with dsb-write so the same
> + * load_lut() api is used for dsb buffer creation which may not
> + * fit in initial stage. Need to create a separate interface and
> + * a different path in color framework while dealing with dsb.
> + */
>
> if (crtc_state->hw.degamma_lut)
> glk_load_degamma_lut(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ec301fe6e3..42c4d6c7f334 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14844,8 +14844,28 @@ static int intel_atomic_check(struct drm_device *dev,
>
> static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
> {
> - return drm_atomic_helper_prepare_planes(state->base.dev,
> - &state->base);
> + struct intel_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> + int i, ret;
> +
> + ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
> + if (ret < 0)
> + return ret;
> +
> + /*
> + * Failure in DSB buffer creation enable fallback mmio for register
> + * programming and erroneous path will be handled by dsp-write api.
> + */
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + bool mode_changed = needs_modeset(crtc_state);
> +
> + if (mode_changed || crtc_state->update_pipe ||
> + crtc_state->uapi.color_mgmt_changed) {
> + intel_dsb_prepare(crtc_state);
> + }
> + }
> +
> + return 0;
> }
>
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> @@ -15298,15 +15318,26 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat
> &wait_reset);
> }
>
> +static void intel_cleanup_dsbs(struct intel_atomic_state *state)
> +{
> + struct intel_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> + int i;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
> + intel_dsb_cleanup(crtc_state);
> +}
> +
> static void intel_atomic_cleanup_work(struct work_struct *work)
> {
> - struct drm_atomic_state *state =
> - container_of(work, struct drm_atomic_state, commit_work);
> - struct drm_i915_private *i915 = to_i915(state->dev);
> + struct intel_atomic_state *state =
> + container_of(work, struct intel_atomic_state, base.commit_work);
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> - drm_atomic_helper_cleanup_planes(&i915->drm, state);
> - drm_atomic_helper_commit_cleanup_done(state);
> - drm_atomic_state_put(state);
> + drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
> + intel_cleanup_dsbs(state);
> + drm_atomic_helper_commit_cleanup_done(&state->base);
> + drm_atomic_state_put(&state->base);
>
> intel_atomic_helper_free_state(i915);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ba8c08145c88..8b21bab088ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1079,6 +1079,9 @@ struct intel_crtc_state {
>
> /* Only valid on TGL+ */
> enum transcoder mst_master_transcoder;
> +
> + /* For DSB related info */
> + struct intel_dsb dsb;
> };
>
> enum intel_pipe_crc_source {
> @@ -1148,9 +1151,6 @@ struct intel_crtc {
> /* scalers available on this crtc */
> int num_scalers;
>
> - /* per pipe DSB related info */
> - struct intel_dsb dsb;
> -
> #ifdef CONFIG_DEBUG_FS
> struct intel_pipe_crc pipe_crc;
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index d7a6bf2277df..2c5840240ddc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -34,9 +34,92 @@
> #define DSB_BYTE_EN_SHIFT 20
> #define DSB_REG_VALUE_MASK 0xfffff
>
> +/**
> + * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
> + * @crtc: intel_crtc structure to get pipe info.
> + *
> + * This function prepare the command buffer which is used to store dsb
> + * instructions with data.
> + */
> +
> +void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_dsb *dsb = &crtc_state->dsb;
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + u32 *buf;
> + intel_wakeref_t wakeref;
> +
> + if (!HAS_DSB(i915) || dsb->cmd_buf)
> + return;
> +
> + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> +
> + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> + if (IS_ERR(obj)) {
> + DRM_ERROR("Gem object creation failed\n");
> + goto out;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_ERROR("Vma creation failed\n");
> + i915_gem_object_put(obj);
> + goto out;
> + }
> +
> + buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> + if (IS_ERR(buf)) {
> + DRM_ERROR("Command buffer creation failed\n");
> + goto out;
> + }
> +
> + dsb->id = DSB1;
> + dsb->vma = vma;
> + dsb->cmd_buf = buf;
> +
> +out:
> + /*
> + * On error dsb->cmd_buf will continue to be NULL, making the writes
> + * pass-through. Leave the dangling ref to be removed later by the
> + * corresponding intel_dsb_put(): the important error message will
> + * already be logged above.
> + */
> +
> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> +}
> +
> +/**
> + * intel_dsb_cleanup() - To cleanup DSB context.
> + * @dsb: intel_dsb structure.
> + *
> + * This function cleanup the DSB context by unpinning and releasing
> + * the VMA object associated with it.
> + */
> +
> +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_dsb *dsb = &crtc_state->dsb;
> +
> + if (!HAS_DSB(i915))
> + return;
> +
> + if (dsb->vma) {
> + i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
> + dsb->vma = NULL;
> + dsb->cmd_buf = NULL;
> + }
> +}
> +
> static inline bool is_dsb_busy(struct intel_dsb *dsb)
> {
> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct intel_crtc_state *crtc_state =
> + container_of(dsb, typeof(*crtc_state), dsb);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -45,7 +128,9 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
>
> static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
> {
> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct intel_crtc_state *crtc_state =
> + container_of(dsb, typeof(*crtc_state), dsb);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 dsb_ctrl;
> @@ -65,7 +150,9 @@ static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
>
> static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
> {
> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct intel_crtc_state *crtc_state =
> + container_of(dsb, typeof(*crtc_state), dsb);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 dsb_ctrl;
> @@ -84,68 +171,26 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
> }
>
> /**
> - * intel_dsb_get() - Allocate DSB context and return a DSB instance.
> + * intel_dsb_get() - Return a DSB instance and increase reference count.
> * @crtc: intel_crtc structure to get pipe info.
> *
> * This function provides handle of a DSB instance, for the further DSB
> * operations.
> *
> * Returns: address of Intel_dsb instance requested for.
> - * Failure: Returns the same DSB instance, but without a command buffer.
> */
>
> struct intel_dsb *
> -intel_dsb_get(struct intel_crtc *crtc)
> +intel_dsb_get(struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *i915 = to_i915(dev);
> - struct intel_dsb *dsb = &crtc->dsb;
> - struct drm_i915_gem_object *obj;
> - struct i915_vma *vma;
> - u32 *buf;
> - intel_wakeref_t wakeref;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_dsb *dsb = &crtc_state->dsb;
>
> if (!HAS_DSB(i915))
> return dsb;
>
> - if (dsb->refcount++ != 0)
> - return dsb;
> -
> - wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> -
> - obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> - if (IS_ERR(obj)) {
> - drm_err(&i915->drm, "Gem object creation failed\n");
> - goto out;
> - }
> -
> - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> - if (IS_ERR(vma)) {
> - drm_err(&i915->drm, "Vma creation failed\n");
> - i915_gem_object_put(obj);
> - goto out;
> - }
> -
> - buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> - if (IS_ERR(buf)) {
> - drm_err(&i915->drm, "Command buffer creation failed\n");
> - goto out;
> - }
> -
> - dsb->id = DSB1;
> - dsb->vma = vma;
> - dsb->cmd_buf = buf;
> -
> -out:
> - /*
> - * On error dsb->cmd_buf will continue to be NULL, making the writes
> - * pass-through. Leave the dangling ref to be removed later by the
> - * corresponding intel_dsb_put(): the important error message will
> - * already be logged above.
> - */
> -
> - intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> -
> + dsb->refcount++;
> return dsb;
> }
>
> @@ -153,13 +198,15 @@ intel_dsb_get(struct intel_crtc *crtc)
> * intel_dsb_put() - To destroy DSB context.
> * @dsb: intel_dsb structure.
> *
> - * This function destroys the DSB context allocated by a dsb_get(), by
> - * unpinning and releasing the VMA object associated with it.
> + * This function decrease the reference count and reset the command
> + * buffer position.
> */
>
> void intel_dsb_put(struct intel_dsb *dsb)
> {
> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct intel_crtc_state *crtc_state =
> + container_of(dsb, typeof(*crtc_state), dsb);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> if (!HAS_DSB(i915))
> @@ -169,8 +216,6 @@ void intel_dsb_put(struct intel_dsb *dsb)
> return;
>
> if (--dsb->refcount == 0) {
> - i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
> - dsb->cmd_buf = NULL;
> dsb->free_pos = 0;
> dsb->ins_start_offset = 0;
> }
> @@ -192,7 +237,9 @@ void intel_dsb_put(struct intel_dsb *dsb)
> void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> u32 val)
> {
> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct intel_crtc_state *crtc_state =
> + container_of(dsb, typeof(*crtc_state), dsb);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 *buf = dsb->cmd_buf;
> u32 reg_val;
> @@ -267,7 +314,9 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> */
> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> {
> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct intel_crtc_state *crtc_state =
> + container_of(dsb, typeof(*crtc_state), dsb);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 *buf = dsb->cmd_buf;
>
> @@ -297,7 +346,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> */
> void intel_dsb_commit(struct intel_dsb *dsb)
> {
> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct intel_crtc_state *crtc_state =
> + container_of(dsb, typeof(*crtc_state), dsb);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum pipe pipe = crtc->pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 395ef9ce558e..65e2d0d1c71e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -10,7 +10,7 @@
>
> #include "i915_reg.h"
>
> -struct intel_crtc;
> +struct intel_crtc_state;
> struct i915_vma;
>
> enum dsb_id {
> @@ -41,8 +41,10 @@ struct intel_dsb {
> u32 ins_start_offset;
> };
>
> +void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
> +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
> struct intel_dsb *
> -intel_dsb_get(struct intel_crtc *crtc);
> +intel_dsb_get(struct intel_crtc_state *crtc_state);
> void intel_dsb_put(struct intel_dsb *dsb);
> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
> void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
2020-04-16 9:49 ` [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Maarten Lankhorst
@ 2020-04-16 10:00 ` Manna, Animesh
0 siblings, 0 replies; 6+ messages in thread
From: Manna, Animesh @ 2020-04-16 10:00 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx; +Cc: Jani Nikula, Daniel Vetter
[-- Attachment #1.1: Type: text/plain, Size: 18166 bytes --]
On 16-04-2020 15:19, Maarten Lankhorst wrote:
> Hey,
>
> Seems we're lacking error handling still when get fails?
Hi Maarten,
Error handling is taken care by dsb-framework, if _prepare() is failed then dsb->cmd_buf will be null and during dsb-write() mmio-write will be used to program registers.
As we have mmio fallback so do not want to fail the commit. Added a code-comment in intel_atomic_prepare_commit(). Maybe if needed I can elaborate a bit more. Please let me know your view on this.
Regards,
Animesh
>
> ~Maarten
>
> Op 13-04-2020 om 08:34 schreef Animesh Manna:
>> Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
>> function which also includes pinning and map in cpu domain.
>>
>> No change is dsb write/commit functions.
>>
>> Now dsb get/put function is refactored and currently used only for
>> reference counting. Below dsb api added to do respective job
>> mentioned below.
>>
>> intel_dsb_prepare - Allocate, pin and map the buffer.
>> intel_dsb_cleanup - Unpin and release the gem object.
>>
>> RFC: Initial patch for design review.
>> v2: included _init() part in _prepare(). [Daniel, Ville]
>> v3: dsb_cleanup called after cleanup_planes. [Daniel]
>> v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten]
>>
>> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_color.c | 19 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 47 ++++-
>> .../drm/i915/display/intel_display_types.h | 6 +-
>> drivers/gpu/drm/i915/display/intel_dsb.c | 169 ++++++++++++------
>> drivers/gpu/drm/i915/display/intel_dsb.h | 6 +-
>> 5 files changed, 170 insertions(+), 77 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>> index 98ece9cd7cdd..fb2caee90734 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -717,7 +717,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
>> static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
>> {
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> - struct intel_dsb *dsb = intel_dsb_get(crtc);
>> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
>> enum pipe pipe = crtc->pipe;
>>
>> /* Program the max register to clamp values > 1.0. */
>> @@ -900,7 +900,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
>> const struct drm_color_lut *color)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> - struct intel_dsb *dsb = intel_dsb_get(crtc);
>> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
>> enum pipe pipe = crtc->pipe;
>>
>> /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
>> @@ -916,7 +916,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
>> const struct drm_color_lut *lut = blob->data;
>> - struct intel_dsb *dsb = intel_dsb_get(crtc);
>> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
>> enum pipe pipe = crtc->pipe;
>> int i;
>>
>> @@ -949,7 +949,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>> const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
>> const struct drm_color_lut *lut = blob->data;
>> const struct drm_color_lut *entry;
>> - struct intel_dsb *dsb = intel_dsb_get(crtc);
>> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
>> enum pipe pipe = crtc->pipe;
>> int i;
>>
>> @@ -1003,7 +1003,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>> {
>> const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> - struct intel_dsb *dsb = intel_dsb_get(crtc);
>> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
>> +
>> + /*
>> + * TODO: Currently dsb buffer filling is done in load_lut() which
>> + * can be done much earlier, like initial stage of atomic_commit().
>> + * As currently replacing the mmio-write with dsb-write so the same
>> + * load_lut() api is used for dsb buffer creation which may not
>> + * fit in initial stage. Need to create a separate interface and
>> + * a different path in color framework while dealing with dsb.
>> + */
>>
>> if (crtc_state->hw.degamma_lut)
>> glk_load_degamma_lut(crtc_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 70ec301fe6e3..42c4d6c7f334 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -14844,8 +14844,28 @@ static int intel_atomic_check(struct drm_device *dev,
>>
>> static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
>> {
>> - return drm_atomic_helper_prepare_planes(state->base.dev,
>> - &state->base);
>> + struct intel_crtc_state *crtc_state;
>> + struct intel_crtc *crtc;
>> + int i, ret;
>> +
>> + ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
>> + if (ret < 0)
>> + return ret;
>> +
>> + /*
>> + * Failure in DSB buffer creation enable fallback mmio for register
>> + * programming and erroneous path will be handled by dsp-write api.
>> + */
>> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
>> + bool mode_changed = needs_modeset(crtc_state);
>> +
>> + if (mode_changed || crtc_state->update_pipe ||
>> + crtc_state->uapi.color_mgmt_changed) {
>> + intel_dsb_prepare(crtc_state);
>> + }
>> + }
>> +
>> + return 0;
>> }
>>
>> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
>> @@ -15298,15 +15318,26 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat
>> &wait_reset);
>> }
>>
>> +static void intel_cleanup_dsbs(struct intel_atomic_state *state)
>> +{
>> + struct intel_crtc_state *crtc_state;
>> + struct intel_crtc *crtc;
>> + int i;
>> +
>> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
>> + intel_dsb_cleanup(crtc_state);
>> +}
>> +
>> static void intel_atomic_cleanup_work(struct work_struct *work)
>> {
>> - struct drm_atomic_state *state =
>> - container_of(work, struct drm_atomic_state, commit_work);
>> - struct drm_i915_private *i915 = to_i915(state->dev);
>> + struct intel_atomic_state *state =
>> + container_of(work, struct intel_atomic_state, base.commit_work);
>> + struct drm_i915_private *i915 = to_i915(state->base.dev);
>>
>> - drm_atomic_helper_cleanup_planes(&i915->drm, state);
>> - drm_atomic_helper_commit_cleanup_done(state);
>> - drm_atomic_state_put(state);
>> + drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
>> + intel_cleanup_dsbs(state);
>> + drm_atomic_helper_commit_cleanup_done(&state->base);
>> + drm_atomic_state_put(&state->base);
>>
>> intel_atomic_helper_free_state(i915);
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index ba8c08145c88..8b21bab088ea 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1079,6 +1079,9 @@ struct intel_crtc_state {
>>
>> /* Only valid on TGL+ */
>> enum transcoder mst_master_transcoder;
>> +
>> + /* For DSB related info */
>> + struct intel_dsb dsb;
>> };
>>
>> enum intel_pipe_crc_source {
>> @@ -1148,9 +1151,6 @@ struct intel_crtc {
>> /* scalers available on this crtc */
>> int num_scalers;
>>
>> - /* per pipe DSB related info */
>> - struct intel_dsb dsb;
>> -
>> #ifdef CONFIG_DEBUG_FS
>> struct intel_pipe_crc pipe_crc;
>> #endif
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index d7a6bf2277df..2c5840240ddc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -34,9 +34,92 @@
>> #define DSB_BYTE_EN_SHIFT 20
>> #define DSB_REG_VALUE_MASK 0xfffff
>>
>> +/**
>> + * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
>> + * @crtc: intel_crtc structure to get pipe info.
>> + *
>> + * This function prepare the command buffer which is used to store dsb
>> + * instructions with data.
>> + */
>> +
>> +void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + struct intel_dsb *dsb = &crtc_state->dsb;
>> + struct drm_i915_gem_object *obj;
>> + struct i915_vma *vma;
>> + u32 *buf;
>> + intel_wakeref_t wakeref;
>> +
>> + if (!HAS_DSB(i915) || dsb->cmd_buf)
>> + return;
>> +
>> + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>> +
>> + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
>> + if (IS_ERR(obj)) {
>> + DRM_ERROR("Gem object creation failed\n");
>> + goto out;
>> + }
>> +
>> + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
>> + if (IS_ERR(vma)) {
>> + DRM_ERROR("Vma creation failed\n");
>> + i915_gem_object_put(obj);
>> + goto out;
>> + }
>> +
>> + buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
>> + if (IS_ERR(buf)) {
>> + DRM_ERROR("Command buffer creation failed\n");
>> + goto out;
>> + }
>> +
>> + dsb->id = DSB1;
>> + dsb->vma = vma;
>> + dsb->cmd_buf = buf;
>> +
>> +out:
>> + /*
>> + * On error dsb->cmd_buf will continue to be NULL, making the writes
>> + * pass-through. Leave the dangling ref to be removed later by the
>> + * corresponding intel_dsb_put(): the important error message will
>> + * already be logged above.
>> + */
>> +
>> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>> +}
>> +
>> +/**
>> + * intel_dsb_cleanup() - To cleanup DSB context.
>> + * @dsb: intel_dsb structure.
>> + *
>> + * This function cleanup the DSB context by unpinning and releasing
>> + * the VMA object associated with it.
>> + */
>> +
>> +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + struct intel_dsb *dsb = &crtc_state->dsb;
>> +
>> + if (!HAS_DSB(i915))
>> + return;
>> +
>> + if (dsb->vma) {
>> + i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
>> + dsb->vma = NULL;
>> + dsb->cmd_buf = NULL;
>> + }
>> +}
>> +
>> static inline bool is_dsb_busy(struct intel_dsb *dsb)
>> {
>> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct intel_crtc_state *crtc_state =
>> + container_of(dsb, typeof(*crtc_state), dsb);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> enum pipe pipe = crtc->pipe;
>>
>> @@ -45,7 +128,9 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
>>
>> static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
>> {
>> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct intel_crtc_state *crtc_state =
>> + container_of(dsb, typeof(*crtc_state), dsb);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> enum pipe pipe = crtc->pipe;
>> u32 dsb_ctrl;
>> @@ -65,7 +150,9 @@ static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
>>
>> static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
>> {
>> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct intel_crtc_state *crtc_state =
>> + container_of(dsb, typeof(*crtc_state), dsb);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> enum pipe pipe = crtc->pipe;
>> u32 dsb_ctrl;
>> @@ -84,68 +171,26 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
>> }
>>
>> /**
>> - * intel_dsb_get() - Allocate DSB context and return a DSB instance.
>> + * intel_dsb_get() - Return a DSB instance and increase reference count.
>> * @crtc: intel_crtc structure to get pipe info.
>> *
>> * This function provides handle of a DSB instance, for the further DSB
>> * operations.
>> *
>> * Returns: address of Intel_dsb instance requested for.
>> - * Failure: Returns the same DSB instance, but without a command buffer.
>> */
>>
>> struct intel_dsb *
>> -intel_dsb_get(struct intel_crtc *crtc)
>> +intel_dsb_get(struct intel_crtc_state *crtc_state)
>> {
>> - struct drm_device *dev = crtc->base.dev;
>> - struct drm_i915_private *i915 = to_i915(dev);
>> - struct intel_dsb *dsb = &crtc->dsb;
>> - struct drm_i915_gem_object *obj;
>> - struct i915_vma *vma;
>> - u32 *buf;
>> - intel_wakeref_t wakeref;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + struct intel_dsb *dsb = &crtc_state->dsb;
>>
>> if (!HAS_DSB(i915))
>> return dsb;
>>
>> - if (dsb->refcount++ != 0)
>> - return dsb;
>> -
>> - wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>> -
>> - obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
>> - if (IS_ERR(obj)) {
>> - drm_err(&i915->drm, "Gem object creation failed\n");
>> - goto out;
>> - }
>> -
>> - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
>> - if (IS_ERR(vma)) {
>> - drm_err(&i915->drm, "Vma creation failed\n");
>> - i915_gem_object_put(obj);
>> - goto out;
>> - }
>> -
>> - buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
>> - if (IS_ERR(buf)) {
>> - drm_err(&i915->drm, "Command buffer creation failed\n");
>> - goto out;
>> - }
>> -
>> - dsb->id = DSB1;
>> - dsb->vma = vma;
>> - dsb->cmd_buf = buf;
>> -
>> -out:
>> - /*
>> - * On error dsb->cmd_buf will continue to be NULL, making the writes
>> - * pass-through. Leave the dangling ref to be removed later by the
>> - * corresponding intel_dsb_put(): the important error message will
>> - * already be logged above.
>> - */
>> -
>> - intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>> -
>> + dsb->refcount++;
>> return dsb;
>> }
>>
>> @@ -153,13 +198,15 @@ intel_dsb_get(struct intel_crtc *crtc)
>> * intel_dsb_put() - To destroy DSB context.
>> * @dsb: intel_dsb structure.
>> *
>> - * This function destroys the DSB context allocated by a dsb_get(), by
>> - * unpinning and releasing the VMA object associated with it.
>> + * This function decrease the reference count and reset the command
>> + * buffer position.
>> */
>>
>> void intel_dsb_put(struct intel_dsb *dsb)
>> {
>> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct intel_crtc_state *crtc_state =
>> + container_of(dsb, typeof(*crtc_state), dsb);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>>
>> if (!HAS_DSB(i915))
>> @@ -169,8 +216,6 @@ void intel_dsb_put(struct intel_dsb *dsb)
>> return;
>>
>> if (--dsb->refcount == 0) {
>> - i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
>> - dsb->cmd_buf = NULL;
>> dsb->free_pos = 0;
>> dsb->ins_start_offset = 0;
>> }
>> @@ -192,7 +237,9 @@ void intel_dsb_put(struct intel_dsb *dsb)
>> void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>> u32 val)
>> {
>> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct intel_crtc_state *crtc_state =
>> + container_of(dsb, typeof(*crtc_state), dsb);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> u32 *buf = dsb->cmd_buf;
>> u32 reg_val;
>> @@ -267,7 +314,9 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>> */
>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>> {
>> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct intel_crtc_state *crtc_state =
>> + container_of(dsb, typeof(*crtc_state), dsb);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> u32 *buf = dsb->cmd_buf;
>>
>> @@ -297,7 +346,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>> */
>> void intel_dsb_commit(struct intel_dsb *dsb)
>> {
>> - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct intel_crtc_state *crtc_state =
>> + container_of(dsb, typeof(*crtc_state), dsb);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_device *dev = crtc->base.dev;
>> struct drm_i915_private *dev_priv = to_i915(dev);
>> enum pipe pipe = crtc->pipe;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
>> index 395ef9ce558e..65e2d0d1c71e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -10,7 +10,7 @@
>>
>> #include "i915_reg.h"
>>
>> -struct intel_crtc;
>> +struct intel_crtc_state;
>> struct i915_vma;
>>
>> enum dsb_id {
>> @@ -41,8 +41,10 @@ struct intel_dsb {
>> u32 ins_start_offset;
>> };
>>
>> +void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
>> +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
>> struct intel_dsb *
>> -intel_dsb_get(struct intel_crtc *crtc);
>> +intel_dsb_get(struct intel_crtc_state *crtc_state);
>> void intel_dsb_put(struct intel_dsb *dsb);
>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
>> void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>
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Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-13 6:34 [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna
2020-04-14 15:49 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev3) Patchwork
2020-04-14 15:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-15 10:31 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-16 9:49 ` [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Maarten Lankhorst
2020-04-16 10:00 ` Manna, Animesh
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