* [Patch v2 1/9] spi: bcm-qspi: Handle clock probe deferral
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:23 ` [Patch v2 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Kamal Dasu
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown
Cc: Florian Fainelli, linux-spi, linux-kernel
From: Florian Fainelli <f.fainelli@gmail.com>
The clock provider may not be ready by the time spi-bcm-qspi gets
probed, handle probe deferral using devm_clk_get_optional().
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 23d295f36c80..74f4579c3f6a 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -1222,6 +1222,11 @@ int bcm_qspi_probe(struct platform_device *pdev,
}
qspi = spi_master_get_devdata(master);
+
+ qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
+ if (IS_ERR(qspi->clk))
+ return PTR_ERR(qspi->clk);
+
qspi->pdev = pdev;
qspi->trans_pos.trans = NULL;
qspi->trans_pos.byte = 0;
@@ -1335,13 +1340,6 @@ int bcm_qspi_probe(struct platform_device *pdev,
qspi->soc_intc = NULL;
}
- qspi->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(qspi->clk)) {
- dev_warn(dev, "unable to get clock\n");
- ret = PTR_ERR(qspi->clk);
- goto qspi_probe_err;
- }
-
ret = clk_prepare_enable(qspi->clk);
if (ret) {
dev_err(dev, "failed to prepare clock\n");
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
2020-04-19 19:23 ` [Patch v2 1/9] spi: bcm-qspi: Handle clock probe deferral Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:23 ` [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown, Rob Herring
Cc: linux-spi, devicetree, linux-kernel
Added documentation for compatibility for brcmstb SoCs :
7425, 7429, 7435, 7216, 7278
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
.../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
index ad7ac80a3841..f5e518d099f2 100644
--- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
+++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
@@ -26,6 +26,16 @@ Required properties:
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
BRCMSTB SoCs
+ "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
+ "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+ BRCMSTB SoCs
"brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP
"brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
2020-04-19 19:23 ` [Patch v2 1/9] spi: bcm-qspi: Handle clock probe deferral Kamal Dasu
2020-04-19 19:23 ` [Patch v2 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:44 ` Florian Fainelli
2020-04-19 19:23 ` [Patch v2 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Kamal Dasu
` (5 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown
Cc: Florian Fainelli, linux-spi, linux-kernel
Older MIPS chips have a QSPI/MSPI controller that does not have the
MSPI_REV offset, reading from that offset will cause a bus error. Match
their compatible string and do not perform a read from that register in
that case.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 50 ++++++++++++++++++++++++++++++++++++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 74f4579c3f6a..d901dcb10d06 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -91,6 +91,7 @@
#define MSPI_MSPI_STATUS 0x020
#define MSPI_CPTQP 0x024
#define MSPI_SPCR3 0x028
+#define MSPI_REV 0x02c
#define MSPI_TXRAM 0x040
#define MSPI_RXRAM 0x0c0
#define MSPI_CDRAM 0x140
@@ -217,6 +218,8 @@ struct bcm_qspi {
struct bcm_qspi_dev_id *dev_ids;
struct completion mspi_done;
struct completion bspi_done;
+ u8 mspi_maj_rev;
+ u8 mspi_min_rev;
};
static inline bool has_bspi(struct bcm_qspi *qspi)
@@ -1190,8 +1193,35 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
.exec_op = bcm_qspi_exec_mem_op,
};
+struct bcm_qspi_data {
+ bool has_mspi_rev;
+};
+
+static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
+ .has_mspi_rev = false,
+};
+
+static const struct bcm_qspi_data bcm_qspi_rev_data = {
+ .has_mspi_rev = true,
+};
+
static const struct of_device_id bcm_qspi_of_match[] = {
- { .compatible = "brcm,spi-bcm-qspi" },
+ {
+ .compatible = "brcm,spi-bcm7425-qspi",
+ .data = &bcm_qspi_no_rev_data,
+ },
+ {
+ .compatible = "brcm,spi-bcm7429-qspi",
+ .data = &bcm_qspi_no_rev_data,
+ },
+ {
+ .compatible = "brcm,spi-bcm7435-qspi",
+ .data = &bcm_qspi_no_rev_data,
+ },
+ {
+ .compatible = "brcm,spi-bcm-qspi",
+ .data = &bcm_qspi_rev_data,
+ },
{},
};
MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
@@ -1199,12 +1229,15 @@ MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
int bcm_qspi_probe(struct platform_device *pdev,
struct bcm_qspi_soc_intc *soc_intc)
{
+ const struct of_device_id *of_id = NULL;
+ const struct bcm_qspi_data *data;
struct device *dev = &pdev->dev;
struct bcm_qspi *qspi;
struct spi_master *master;
struct resource *res;
int irq, ret = 0, num_ints = 0;
u32 val;
+ u32 rev = 0;
const char *name = NULL;
int num_irqs = ARRAY_SIZE(qspi_irq_tab);
@@ -1212,9 +1245,12 @@ int bcm_qspi_probe(struct platform_device *pdev,
if (!dev->of_node)
return -ENODEV;
- if (!of_match_node(bcm_qspi_of_match, dev->of_node))
+ of_id = of_match_node(bcm_qspi_of_match, dev->of_node);
+ if (!of_id)
return -ENODEV;
+ data = of_id->data;
+
master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
if (!master) {
dev_err(dev, "error allocating spi_master\n");
@@ -1349,6 +1385,16 @@ int bcm_qspi_probe(struct platform_device *pdev,
qspi->base_clk = clk_get_rate(qspi->clk);
qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
+ if (data->has_mspi_rev) {
+ rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
+ /* some older revs do not have a MSPI_REV register */
+ if ((rev & 0xff) == 0xff)
+ rev = 0;
+ }
+
+ qspi->mspi_maj_rev = (rev >> 4) & 0xf;
+ qspi->mspi_min_rev = rev & 0xf;
+
bcm_qspi_hw_init(qspi);
init_completion(&qspi->mspi_done);
init_completion(&qspi->bspi_done);
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
` (2 preceding siblings ...)
2020-04-19 19:23 ` [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:23 ` [Patch v2 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Kamal Dasu
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown; +Cc: linux-spi, linux-kernel
As per the spi core implementation for MSPI devices when the transfer is
the last one in the message, the chip may stay selected until the next
transfer. On multi-device SPI busses with nothing blocking messages going
to other devices, this is just a performance hint; starting a message to
another device deselects this one. But in other cases, this can be used
to ensure correctness. Some devices need protocol transactions to be built
from a series of spi_message submissions, where the content of one message
is determined by the results of previous messages and where the whole
transaction ends when the chipselect goes intactive.
On CS change after completing the last serial transfer, the MSPI driver
drives SSb pin CDRAM register correctly according comments in core spi.h
as shown below:
case 1) EOM =1, cs_change =0: SSb inactive
case 2) EOM =1, cs_change =1: SSb active
case 3) EOM =0, cs_change =0: SSb active
case 4) EOM =0, cs_change =1: SSb inactive
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index d901dcb10d06..c48c399dce53 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -615,19 +615,15 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
if (qt->trans->cs_change &&
(flags & TRANS_STATUS_BREAK_CS_CHANGE))
ret |= TRANS_STATUS_BREAK_CS_CHANGE;
- if (ret)
- goto done;
- dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
- ret = TRANS_STATUS_BREAK_EOM;
+ ret |= TRANS_STATUS_BREAK_EOM;
else
- ret = TRANS_STATUS_BREAK_NO_BYTES;
+ ret |= TRANS_STATUS_BREAK_NO_BYTES;
qt->trans = NULL;
}
-done:
dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
return ret;
@@ -774,7 +770,16 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
- if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
+ /*
+ * case 1) EOM =1, cs_change =0: SSb inactive
+ * case 2) EOM =1, cs_change =1: SSb stay active
+ * case 3) EOM =0, cs_change =0: SSb stay active
+ * case 4) EOM =0, cs_change =1: SSb inactive
+ */
+ if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
+ == TRANS_STATUS_BREAK_CS_CHANGE) ||
+ ((tstatus & TRANS_STATUS_BREAK_DESELECT)
+ == TRANS_STATUS_BREAK_EOM)) {
mspi_cdram = read_cdram_slot(qspi, slot - 1) &
~MSPI_CDRAM_CONT_BIT;
write_cdram_slot(qspi, slot - 1, mspi_cdram);
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
` (3 preceding siblings ...)
2020-04-19 19:23 ` [Patch v2 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:23 ` [Patch v2 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Kamal Dasu
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown
Cc: Justin Chen, linux-spi, linux-kernel
From: Justin Chen <justinpopo6@gmail.com>
Currently we set the tx/rx buffer to 0xff when NULL. This causes
problems with some spi slaves where 0xff is a valid command. Looking
at other drivers, the tx/rx buffer is usually set to 0x00 when NULL.
Following this convention solves the issue.
Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index c48c399dce53..e00208801c8b 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -669,7 +669,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
if (buf)
buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
dev_dbg(&qspi->pdev->dev, "RD %02x\n",
- buf ? buf[tp.byte] : 0xff);
+ buf ? buf[tp.byte] : 0x0);
} else {
u16 *buf = tp.trans->rx_buf;
@@ -677,7 +677,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
slot);
dev_dbg(&qspi->pdev->dev, "RD %04x\n",
- buf ? buf[tp.byte] : 0xffff);
+ buf ? buf[tp.byte / 2] : 0x0);
}
update_qspi_trans_byte_count(qspi, &tp,
@@ -732,13 +732,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
while (!tstatus && slot < MSPI_NUM_CDRAM) {
if (tp.trans->bits_per_word <= 8) {
const u8 *buf = tp.trans->tx_buf;
- u8 val = buf ? buf[tp.byte] : 0xff;
+ u8 val = buf ? buf[tp.byte] : 0x00;
write_txram_slot_u8(qspi, slot, val);
dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
} else {
const u16 *buf = tp.trans->tx_buf;
- u16 val = buf ? buf[tp.byte / 2] : 0xffff;
+ u16 val = buf ? buf[tp.byte / 2] : 0x0000;
write_txram_slot_u16(qspi, slot, val);
dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
` (4 preceding siblings ...)
2020-04-19 19:23 ` [Patch v2 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:23 ` [Patch v2 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Kamal Dasu
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown; +Cc: linux-spi, linux-kernel
SCMI only passes clk_prepare_enable() and clk_disable_unprepare(), made
changes to suspend/resume ops to use the appropriate calls so that PM
works for ARM and ARM64 platforms.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index e00208801c8b..a3936ae5a860 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -1455,7 +1455,7 @@ static int __maybe_unused bcm_qspi_suspend(struct device *dev)
bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
spi_master_suspend(qspi->master);
- clk_disable(qspi->clk);
+ clk_disable_unprepare(qspi->clk);
bcm_qspi_hw_uninit(qspi);
return 0;
@@ -1473,7 +1473,7 @@ static int __maybe_unused bcm_qspi_resume(struct device *dev)
qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
true);
- ret = clk_enable(qspi->clk);
+ ret = clk_prepare_enable(qspi->clk);
if (!ret)
spi_master_resume(qspi->master);
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
` (5 preceding siblings ...)
2020-04-19 19:23 ` [Patch v2 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:23 ` [Patch v2 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Kamal Dasu
2020-04-19 19:23 ` [Patch v2 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Kamal Dasu
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown; +Cc: linux-spi, linux-kernel
Setting MSPI_SPCR3.fastbr=1 allows using clock divider (SPBR) values of
1-7, while the default value prohibits these values and requires a minimum
clock divider value of 8.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index a3936ae5a860..edc601dbf221 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -107,13 +107,15 @@
#define MSPI_SPCR2_SPE BIT(6)
#define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
+#define MSPI_SPCR3_FASTBR BIT(0)
+#define MSPI_SPCR3_FASTDT BIT(1)
+
#define MSPI_MSPI_STATUS_SPIF BIT(0)
#define INTR_BASE_BIT_SHIFT 0x02
#define INTR_COUNT 0x07
#define NUM_CHIPSELECT 4
-#define QSPI_SPBR_MIN 8U
#define QSPI_SPBR_MAX 255U
#define OPCODE_DIOR 0xBB
@@ -227,6 +229,25 @@ static inline bool has_bspi(struct bcm_qspi *qspi)
return qspi->bspi_mode;
}
+/* hardware supports spcr3 and fast baud-rate */
+static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
+{
+ if (!has_bspi(qspi) &&
+ ((qspi->mspi_maj_rev >= 1) &&
+ (qspi->mspi_min_rev >= 5)))
+ return true;
+
+ return false;
+}
+
+static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
+{
+ if (bcm_qspi_has_fastbr(qspi))
+ return 1;
+ else
+ return 8;
+}
+
/* Read qspi controller register*/
static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
unsigned int offset)
@@ -534,7 +555,7 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
if (xp->speed_hz)
spbr = qspi->base_clk / (2 * xp->speed_hz);
- spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
+ spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
spcr = MSPI_MASTER_BIT;
@@ -544,6 +565,14 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
spcr |= xp->mode & 3;
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
+ if (bcm_qspi_has_fastbr(qspi)) {
+ spcr = 0;
+
+ /* enable fastbr */
+ spcr |= MSPI_SPCR3_FASTBR;
+ bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
+ }
+
qspi->last_parms = *xp;
}
@@ -1388,7 +1417,6 @@ int bcm_qspi_probe(struct platform_device *pdev,
}
qspi->base_clk = clk_get_rate(qspi->clk);
- qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
if (data->has_mspi_rev) {
rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
@@ -1400,6 +1428,8 @@ int bcm_qspi_probe(struct platform_device *pdev,
qspi->mspi_maj_rev = (rev >> 4) & 0xf;
qspi->mspi_min_rev = rev & 0xf;
+ qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
+
bcm_qspi_hw_init(qspi);
init_completion(&qspi->mspi_done);
init_completion(&qspi->bspi_done);
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
` (6 preceding siblings ...)
2020-04-19 19:23 ` [Patch v2 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
2020-04-19 19:23 ` [Patch v2 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Kamal Dasu
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown; +Cc: linux-spi, linux-kernel
Adding support for MSPI sys clk 108Mhz available on 7216
and 7278 BRCMSTB SoCs.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 44 ++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index edc601dbf221..99f2cfcbb50c 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -109,6 +109,11 @@
#define MSPI_SPCR3_FASTBR BIT(0)
#define MSPI_SPCR3_FASTDT BIT(1)
+#define MSPI_SPCR3_SYSCLKSEL_MASK GENMASK(11, 10)
+#define MSPI_SPCR3_SYSCLKSEL_27 (MSPI_SPCR3_SYSCLKSEL_MASK & \
+ ~(BIT(10) | BIT(11)))
+#define MSPI_SPCR3_SYSCLKSEL_108 (MSPI_SPCR3_SYSCLKSEL_MASK & \
+ BIT(11))
#define MSPI_MSPI_STATUS_SPIF BIT(0)
@@ -117,6 +122,7 @@
#define NUM_CHIPSELECT 4
#define QSPI_SPBR_MAX 255U
+#define MSPI_BASE_FREQ 27000000UL
#define OPCODE_DIOR 0xBB
#define OPCODE_QIOR 0xEB
@@ -222,6 +228,7 @@ struct bcm_qspi {
struct completion bspi_done;
u8 mspi_maj_rev;
u8 mspi_min_rev;
+ bool mspi_spcr3_sysclk;
};
static inline bool has_bspi(struct bcm_qspi *qspi)
@@ -240,6 +247,17 @@ static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
return false;
}
+/* hardware supports sys clk 108Mhz */
+static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
+{
+ if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
+ ((qspi->mspi_maj_rev >= 1) &&
+ (qspi->mspi_min_rev >= 6))))
+ return true;
+
+ return false;
+}
+
static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
{
if (bcm_qspi_has_fastbr(qspi))
@@ -570,6 +588,15 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
/* enable fastbr */
spcr |= MSPI_SPCR3_FASTBR;
+
+ if (bcm_qspi_has_sysclk_108(qspi)) {
+ /* SYSCLK_108 */
+ spcr |= MSPI_SPCR3_SYSCLKSEL_108;
+ qspi->base_clk = MSPI_BASE_FREQ * 4;
+ /* Change spbr as we changed sysclk */
+ bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
+ }
+
bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
}
@@ -1229,14 +1256,22 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
struct bcm_qspi_data {
bool has_mspi_rev;
+ bool has_spcr3_sysclk;
};
static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
.has_mspi_rev = false,
+ .has_spcr3_sysclk = false,
};
static const struct bcm_qspi_data bcm_qspi_rev_data = {
.has_mspi_rev = true,
+ .has_spcr3_sysclk = false,
+};
+
+static const struct bcm_qspi_data bcm_qspi_spcr3_data = {
+ .has_mspi_rev = true,
+ .has_spcr3_sysclk = true,
};
static const struct of_device_id bcm_qspi_of_match[] = {
@@ -1256,6 +1291,14 @@ static const struct of_device_id bcm_qspi_of_match[] = {
.compatible = "brcm,spi-bcm-qspi",
.data = &bcm_qspi_rev_data,
},
+ {
+ .compatible = "brcm,spi-bcm7216-qspi",
+ .data = &bcm_qspi_spcr3_data,
+ },
+ {
+ .compatible = "brcm,spi-bcm7278-qspi",
+ .data = &bcm_qspi_spcr3_data,
+ },
{},
};
MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
@@ -1427,6 +1470,7 @@ int bcm_qspi_probe(struct platform_device *pdev,
qspi->mspi_maj_rev = (rev >> 4) & 0xf;
qspi->mspi_min_rev = rev & 0xf;
+ qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Patch v2 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
` (7 preceding siblings ...)
2020-04-19 19:23 ` [Patch v2 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Kamal Dasu
@ 2020-04-19 19:23 ` Kamal Dasu
8 siblings, 0 replies; 12+ messages in thread
From: Kamal Dasu @ 2020-04-19 19:23 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown; +Cc: linux-spi, linux-kernel
Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI
controllers.
Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 99f2cfcbb50c..681d09085175 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -576,11 +576,17 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
- spcr = MSPI_MASTER_BIT;
+ if (!qspi->mspi_maj_rev)
+ /* legacy controller */
+ spcr = MSPI_MASTER_BIT;
+ else
+ spcr = 0;
+
/* for 16 bit the data should be zero */
if (xp->bits_per_word != 16)
spcr |= xp->bits_per_word << 2;
spcr |= xp->mode & 3;
+
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
if (bcm_qspi_has_fastbr(qspi)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
2020-04-19 19:23 ` [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
@ 2020-04-19 19:44 ` Florian Fainelli
2020-04-20 15:12 ` Kamal Dasu
0 siblings, 1 reply; 12+ messages in thread
From: Florian Fainelli @ 2020-04-19 19:44 UTC (permalink / raw)
To: Kamal Dasu, bcm-kernel-feedback-list, Mark Brown
Cc: Florian Fainelli, linux-spi, linux-kernel
Hi Kamal,
On 4/19/2020 12:23 PM, Kamal Dasu wrote:
> Older MIPS chips have a QSPI/MSPI controller that does not have the
> MSPI_REV offset, reading from that offset will cause a bus error. Match
> their compatible string and do not perform a read from that register in
> that case.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
This patch should also have a From: that is from me.
--
Florian
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
2020-04-19 19:44 ` Florian Fainelli
@ 2020-04-20 15:12 ` Kamal Dasu
2020-04-20 15:17 ` Mark Brown
0 siblings, 1 reply; 12+ messages in thread
From: Kamal Dasu @ 2020-04-20 15:12 UTC (permalink / raw)
To: Florian Fainelli
Cc: bcm-kernel-feedback-list, Mark Brown, linux-spi,
Linux Kernel Mailing List
Yes missed this one.
Should I send a v3 of the entire set.
Kamal
On Sun, Apr 19, 2020 at 3:44 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> Hi Kamal,
>
> On 4/19/2020 12:23 PM, Kamal Dasu wrote:
> > Older MIPS chips have a QSPI/MSPI controller that does not have the
> > MSPI_REV offset, reading from that offset will cause a bus error. Match
> > their compatible string and do not perform a read from that register in
> > that case.
> >
> > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> > Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
>
> This patch should also have a From: that is from me.
> --
> Florian
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
2020-04-20 15:12 ` Kamal Dasu
@ 2020-04-20 15:17 ` Mark Brown
0 siblings, 0 replies; 12+ messages in thread
From: Mark Brown @ 2020-04-20 15:17 UTC (permalink / raw)
To: Kamal Dasu
Cc: Florian Fainelli, bcm-kernel-feedback-list, linux-spi,
Linux Kernel Mailing List
[-- Attachment #1: Type: text/plain, Size: 370 bytes --]
On Mon, Apr 20, 2020 at 11:12:21AM -0400, Kamal Dasu wrote:
> Yes missed this one.
> Should I send a v3 of the entire set.
Yes.
Please don't top post, reply in line with needed context. This allows
readers to readily follow the flow of conversation and understand what
you are talking about and also helps ensure that everything in the
discussion is being addressed.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-04-20 15:17 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
2020-04-19 19:23 ` [Patch v2 1/9] spi: bcm-qspi: Handle clock probe deferral Kamal Dasu
2020-04-19 19:23 ` [Patch v2 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Kamal Dasu
2020-04-19 19:23 ` [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
2020-04-19 19:44 ` Florian Fainelli
2020-04-20 15:12 ` Kamal Dasu
2020-04-20 15:17 ` Mark Brown
2020-04-19 19:23 ` [Patch v2 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Kamal Dasu
2020-04-19 19:23 ` [Patch v2 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Kamal Dasu
2020-04-19 19:23 ` [Patch v2 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Kamal Dasu
2020-04-19 19:23 ` [Patch v2 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Kamal Dasu
2020-04-19 19:23 ` [Patch v2 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Kamal Dasu
2020-04-19 19:23 ` [Patch v2 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Kamal Dasu
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