* [PATCH] arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
@ 2020-04-20 8:17 Ley Foon Tan
2020-04-27 7:07 ` Tan, Ley Foon
0 siblings, 1 reply; 3+ messages in thread
From: Ley Foon Tan @ 2020-04-20 8:17 UTC (permalink / raw)
To: u-boot
Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.
Reported-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index e710aa2f94f0..9d2b3bababe2 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg);
#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
/* Periphpll group */
#define CLKMGR_S10_PERPLL_EN 0xa4
-#define CLKMGR_S10_PERPLL_BYPASS 0xac
+#define CLKMGR_S10_PERPLL_BYPASS 0xb0
#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
--
2.19.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
2020-04-20 8:17 [PATCH] arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset Ley Foon Tan
@ 2020-04-27 7:07 ` Tan, Ley Foon
2020-04-27 7:14 ` Marek Vasut
0 siblings, 1 reply; 3+ messages in thread
From: Tan, Ley Foon @ 2020-04-27 7:07 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Tan, Ley Foon <ley.foon.tan@intel.com>
> Sent: Monday, April 20, 2020 4:17 PM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Ley Foon Tan <lftan.linux@gmail.com>;
> See, Chin Liang <chin.liang.see@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Ang, Chee Hong
> <chee.hong.ang@intel.com>; Tan, Ley Foon <ley.foon.tan@intel.com>
> Subject: [PATCH] arm: socfpga: stratix10: Fix incorrect
> CLKMGR_S10_PERPLL_BYPASS offset
>
> Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.
>
> Reported-by: Chee Hong Ang <chee.hong.ang@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> index e710aa2f94f0..9d2b3bababe2 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg);
> #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
> /* Periphpll group */
> #define CLKMGR_S10_PERPLL_EN 0xa4
> -#define CLKMGR_S10_PERPLL_BYPASS 0xac
> +#define CLKMGR_S10_PERPLL_BYPASS 0xb0
> #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
> #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
> #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
> --
Any comment on this patch?
Thanks.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
2020-04-27 7:07 ` Tan, Ley Foon
@ 2020-04-27 7:14 ` Marek Vasut
0 siblings, 0 replies; 3+ messages in thread
From: Marek Vasut @ 2020-04-27 7:14 UTC (permalink / raw)
To: u-boot
On 4/27/20 9:07 AM, Tan, Ley Foon wrote:
>
>
>> -----Original Message-----
>> From: Tan, Ley Foon <ley.foon.tan@intel.com>
>> Sent: Monday, April 20, 2020 4:17 PM
>> To: u-boot at lists.denx.de
>> Cc: Marek Vasut <marex@denx.de>; Ley Foon Tan <lftan.linux@gmail.com>;
>> See, Chin Liang <chin.liang.see@intel.com>; Simon Goldschmidt
>> <simon.k.r.goldschmidt@gmail.com>; Ang, Chee Hong
>> <chee.hong.ang@intel.com>; Tan, Ley Foon <ley.foon.tan@intel.com>
>> Subject: [PATCH] arm: socfpga: stratix10: Fix incorrect
>> CLKMGR_S10_PERPLL_BYPASS offset
>>
>> Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.
>>
>> Reported-by: Chee Hong Ang <chee.hong.ang@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>> b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>> index e710aa2f94f0..9d2b3bababe2 100644
>> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>> @@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg);
>> #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
>> /* Periphpll group */
>> #define CLKMGR_S10_PERPLL_EN 0xa4
>> -#define CLKMGR_S10_PERPLL_BYPASS 0xac
>> +#define CLKMGR_S10_PERPLL_BYPASS 0xb0
>> #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
>> #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
>> #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
>> --
> Any comment on this patch?
Applied, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-04-27 7:14 UTC | newest]
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2020-04-20 8:17 [PATCH] arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset Ley Foon Tan
2020-04-27 7:07 ` Tan, Ley Foon
2020-04-27 7:14 ` Marek Vasut
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