* [Intel-gfx] [PATCH v26 1/9] drm/i915: Introduce skl_plane_wm_level accessor.
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
@ 2020-04-23 7:58 ` Stanislav Lisovskiy
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
` (13 subsequent siblings)
14 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:58 UTC (permalink / raw)
To: intel-gfx
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
(Ville Syrjälä)
- Moved crtc_state param so that it is first now
(Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
skl_write_plane_wm(Ville Syrjälä)
v4: - Started to use enum values for color plane
- Do sizeof for a type what we are memset'ing
- Zero out wm_uv as well(Ville Syrjälä)
v5: - Fixed rebase conflict caused by COLOR_PLANE_*
enum removal
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 85 ++++++++++++++++++++++++++-------
1 file changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6f40bfee7304..338a82577b76 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4574,6 +4574,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
+ int level,
+ int color_plane)
+{
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4633,22 +4645,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+ if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
drm_WARN_ON(&dev_priv->drm,
- wm->wm[level].min_ddb_alloc != U16_MAX);
+ wm_level->min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4671,11 +4689,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* proportional to its relative data rate.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
+
if (plane_id == PLANE_CURSOR)
continue;
@@ -4690,7 +4713,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+ total[plane_id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -4701,7 +4724,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+ uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
@@ -4744,9 +4767,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
+
/*
* We only disable the watermarks for each plane if
* they exceed the ddb allocation of said plane. This
@@ -4759,9 +4789,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* planes must be enabled before the level will be used."
* So this is actually safe to do.
*/
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+ if (wm_level->min_ddb_alloc > total[plane_id] ||
+ wm_uv_level->min_ddb_alloc > uv_total[plane_id]) {
+ memset(&wm->wm[level], 0,
+ sizeof(wm->wm[level]));
+ memset(&wm->uv_wm[level], 0,
+ sizeof(wm->uv_wm[level]));
+ }
/*
* Wa_1408961008:icl, ehl
@@ -4769,9 +4803,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
- wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
- wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
- wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ 0, 0);
+ wm->wm[level].plane_res_b =
+ wm_level->plane_res_b;
+ wm->wm[level].plane_res_l =
+ wm_level->plane_res_l;
+ wm->wm[level].ignore_lines =
+ wm_level->ignore_lines;
}
}
}
@@ -5385,8 +5424,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
@@ -5419,8 +5463,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_y[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
--
2.24.1.485.gad05a3d8e5
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 1/9] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
@ 2020-04-23 7:58 ` Stanislav Lisovskiy
2020-04-30 9:09 ` Ville Syrjälä
2020-04-30 19:17 ` Stanislav Lisovskiy
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state Stanislav Lisovskiy
` (12 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:58 UTC (permalink / raw)
To: intel-gfx
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of atomic state
v3: - Fixed rebase conflict, now using
intel_atomic_crtc_state_for_each_plane_state in
order to call it from atomic check
v4: - Use fb modifier from plane state
v5: - Make intel_has_sagv static again(Ville)
- Removed unnecessary NULL assignments(Ville)
- Removed unnecessary SAGV debug(Ville)
- Call intel_compute_sagv_mask only for modesets(Ville)
- Serialize global state only if sagv results change, but
not mask itself(Ville)
v6: - use lock global state instead of serialize(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
drivers/gpu/drm/i915/intel_pm.h | 3 +-
3 files changed, 93 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..d6df91058223 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_reject;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 338a82577b76..7e15cf3368ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
- if (!intel_can_enable_sagv(state))
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(new_bw_state))
intel_disable_sagv(dev_priv);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
- if (intel_can_enable_sagv(state))
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(new_bw_state))
intel_enable_sagv(dev_priv);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc_state->uapi.crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
int level, latency;
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
if (!crtc_state->hw.active)
return true;
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
@@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
latency = dev_priv->wm.skl_latency[level];
if (skl_needs_memory_bw_wa(dev_priv) &&
- plane->base.state->fb->modifier ==
+ plane_state->uapi.fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
@@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return bw_state->pipe_sagv_reject == 0;
+}
+
+static int intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *crtc_state;
- enum pipe pipe;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_bw_state *new_bw_state = NULL;
+ const struct intel_bw_state *old_bw_state = NULL;
+ int i;
- if (!intel_has_sagv(dev_priv))
- return false;
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
+ old_bw_state = intel_atomic_get_old_bw_state(state);
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
+ if (intel_crtc_can_enable_sagv(new_crtc_state))
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ if (!new_bw_state)
+ return 0;
- return intel_crtc_can_enable_sagv(crtc_state);
+ if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
/*
@@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
+ if (state->modeset) {
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
+ }
+
/*
* skl_compute_ddb() will have adjusted the final watermarks
* based on how much ddb is available. Now we can actually
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 9a6036ab0f90..fd1dc422e6c5 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -9,6 +9,7 @@
#include <linux/types.h>
#include "i915_reg.h"
+#include "display/intel_bw.h"
struct drm_device;
struct drm_i915_private;
@@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
@ 2020-04-30 9:09 ` Ville Syrjälä
2020-04-30 9:13 ` Lisovskiy, Stanislav
2020-04-30 19:17 ` Stanislav Lisovskiy
1 sibling, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 9:09 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> Future platforms require per-crtc SAGV evaluation
> and serializing global state when those are changed
> from different commits.
>
> v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> so that it sets bit in reject mask.
> - Use bw_state in intel_pre/post_plane_enable_sagv
> instead of atomic state
>
> v3: - Fixed rebase conflict, now using
> intel_atomic_crtc_state_for_each_plane_state in
> order to call it from atomic check
> v4: - Use fb modifier from plane state
>
> v5: - Make intel_has_sagv static again(Ville)
> - Removed unnecessary NULL assignments(Ville)
> - Removed unnecessary SAGV debug(Ville)
> - Call intel_compute_sagv_mask only for modesets(Ville)
> - Serialize global state only if sagv results change, but
> not mask itself(Ville)
>
> v6: - use lock global state instead of serialize(Ville)
What I meant is that we need both. Serialize if sagv state is going to
change, otherwise lock if the mask changes.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> drivers/gpu/drm/i915/intel_pm.h | 3 +-
> 3 files changed, 93 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index ac004d6f4276..d6df91058223 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -18,6 +18,12 @@ struct intel_crtc_state;
> struct intel_bw_state {
> struct intel_global_state base;
>
> + /*
> + * Contains a bit mask, used to determine, whether correspondent
> + * pipe allows SAGV or not.
> + */
> + u8 pipe_sagv_reject;
> +
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 338a82577b76..7e15cf3368ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -43,6 +43,7 @@
> #include "i915_fixed.h"
> #include "i915_irq.h"
> #include "i915_trace.h"
> +#include "display/intel_bw.h"
> #include "intel_pm.h"
> #include "intel_sideband.h"
> #include "../../../platform/x86/intel_ips.h"
> @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_bw_state *new_bw_state;
>
> - if (!intel_can_enable_sagv(state))
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + * This is different from situation when we have SAGV but just can't
> + * afford it due to DBuf limitation - in case if SAGV is completely
> + * disabled in a BIOS, we are not even allowed to send a PCode request,
> + * as it will throw an error. So have to check it here.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + new_bw_state = intel_atomic_get_new_bw_state(state);
> + if (!new_bw_state)
> + return;
> +
> + if (!intel_can_enable_sagv(new_bw_state))
> intel_disable_sagv(dev_priv);
> }
>
> void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_bw_state *new_bw_state;
>
> - if (intel_can_enable_sagv(state))
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + * This is different from situation when we have SAGV but just can't
> + * afford it due to DBuf limitation - in case if SAGV is completely
> + * disabled in a BIOS, we are not even allowed to send a PCode request,
> + * as it will throw an error. So have to check it here.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + new_bw_state = intel_atomic_get_new_bw_state(state);
> + if (!new_bw_state)
> + return;
> +
> + if (intel_can_enable_sagv(new_bw_state))
> intel_enable_sagv(dev_priv);
> }
>
> static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> int level, latency;
>
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> if (!crtc_state->hw.active)
> return true;
>
> + /*
> + * SKL+ workaround: bspec recommends we disable SAGV when we have
> + * more then one pipe enabled
> + */
> + if (hweight8(state->active_pipes) > 1)
> + return false;
> +
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> return false;
>
> - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane->id];
>
> @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> latency = dev_priv->wm.skl_latency[level];
>
> if (skl_needs_memory_bw_wa(dev_priv) &&
> - plane->base.state->fb->modifier ==
> + plane_state->uapi.fb->modifier ==
> I915_FORMAT_MOD_X_TILED)
> latency += 15;
>
> @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> return true;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + return bw_state->pipe_sagv_reject == 0;
> +}
> +
> +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> +{
> + int ret;
> struct intel_crtc *crtc;
> - const struct intel_crtc_state *crtc_state;
> - enum pipe pipe;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_bw_state *new_bw_state = NULL;
> + const struct intel_bw_state *old_bw_state = NULL;
> + int i;
>
> - if (!intel_has_sagv(dev_priv))
> - return false;
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + new_bw_state = intel_atomic_get_bw_state(state);
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
>
> - /*
> - * If there are no active CRTCs, no additional checks need be performed
> - */
> - if (hweight8(state->active_pipes) == 0)
> - return true;
> + old_bw_state = intel_atomic_get_old_bw_state(state);
>
> - /*
> - * SKL+ workaround: bspec recommends we disable SAGV when we have
> - * more then one pipe enabled
> - */
> - if (hweight8(state->active_pipes) > 1)
> - return false;
> + if (intel_crtc_can_enable_sagv(new_crtc_state))
> + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> + else
> + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> + }
>
> - /* Since we're now guaranteed to only have one active CRTC... */
> - pipe = ffs(state->active_pipes) - 1;
> - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> + if (!new_bw_state)
> + return 0;
>
> - return intel_crtc_can_enable_sagv(crtc_state);
> + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> }
>
> /*
> @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> + if (state->modeset) {
> + ret = intel_compute_sagv_mask(state);
> + if (ret)
> + return ret;
> + }
> +
> /*
> * skl_compute_ddb() will have adjusted the final watermarks
> * based on how much ddb is available. Now we can actually
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 9a6036ab0f90..fd1dc422e6c5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -9,6 +9,7 @@
> #include <linux/types.h>
>
> #include "i915_reg.h"
> +#include "display/intel_bw.h"
>
> struct drm_device;
> struct drm_i915_private;
> @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *out);
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-30 9:09 ` Ville Syrjälä
@ 2020-04-30 9:13 ` Lisovskiy, Stanislav
2020-04-30 9:25 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 9:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > Future platforms require per-crtc SAGV evaluation
> > and serializing global state when those are changed
> > from different commits.
> >
> > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > so that it sets bit in reject mask.
> > - Use bw_state in intel_pre/post_plane_enable_sagv
> > instead of atomic state
> >
> > v3: - Fixed rebase conflict, now using
> > intel_atomic_crtc_state_for_each_plane_state in
> > order to call it from atomic check
> > v4: - Use fb modifier from plane state
> >
> > v5: - Make intel_has_sagv static again(Ville)
> > - Removed unnecessary NULL assignments(Ville)
> > - Removed unnecessary SAGV debug(Ville)
> > - Call intel_compute_sagv_mask only for modesets(Ville)
> > - Serialize global state only if sagv results change, but
> > not mask itself(Ville)
> >
> > v6: - use lock global state instead of serialize(Ville)
>
> What I meant is that we need both. Serialize if sagv state is going to
> change, otherwise lock if the mask changes.
As I understand whenever we modify global state but not a real hw, we do
only global state locking - pipe sagv mask is not actually a hw, but just
a virtual thing. It affects the QGV points we enable and if it happens to
affect those in a way that those change - we'll any way have serialize
called from intel_bw.c. Thus shouldn't be an issue.
I can change it anyway of course.
Stan
>
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > 3 files changed, 93 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > index ac004d6f4276..d6df91058223 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > struct intel_bw_state {
> > struct intel_global_state base;
> >
> > + /*
> > + * Contains a bit mask, used to determine, whether correspondent
> > + * pipe allows SAGV or not.
> > + */
> > + u8 pipe_sagv_reject;
> > +
> > unsigned int data_rate[I915_MAX_PIPES];
> > u8 num_active_planes[I915_MAX_PIPES];
> > };
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 338a82577b76..7e15cf3368ad 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -43,6 +43,7 @@
> > #include "i915_fixed.h"
> > #include "i915_irq.h"
> > #include "i915_trace.h"
> > +#include "display/intel_bw.h"
> > #include "intel_pm.h"
> > #include "intel_sideband.h"
> > #include "../../../platform/x86/intel_ips.h"
> > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + const struct intel_bw_state *new_bw_state;
> >
> > - if (!intel_can_enable_sagv(state))
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + * This is different from situation when we have SAGV but just can't
> > + * afford it due to DBuf limitation - in case if SAGV is completely
> > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > + * as it will throw an error. So have to check it here.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > + if (!new_bw_state)
> > + return;
> > +
> > + if (!intel_can_enable_sagv(new_bw_state))
> > intel_disable_sagv(dev_priv);
> > }
> >
> > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + const struct intel_bw_state *new_bw_state;
> >
> > - if (intel_can_enable_sagv(state))
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + * This is different from situation when we have SAGV but just can't
> > + * afford it due to DBuf limitation - in case if SAGV is completely
> > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > + * as it will throw an error. So have to check it here.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > + if (!new_bw_state)
> > + return;
> > +
> > + if (intel_can_enable_sagv(new_bw_state))
> > intel_enable_sagv(dev_priv);
> > }
> >
> > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > {
> > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > - struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > struct intel_plane *plane;
> > + const struct intel_plane_state *plane_state;
> > int level, latency;
> >
> > + if (!intel_has_sagv(dev_priv))
> > + return false;
> > +
> > if (!crtc_state->hw.active)
> > return true;
> >
> > + /*
> > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > + * more then one pipe enabled
> > + */
> > + if (hweight8(state->active_pipes) > 1)
> > + return false;
> > +
> > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > return false;
> >
> > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > const struct skl_plane_wm *wm =
> > &crtc_state->wm.skl.optimal.planes[plane->id];
> >
> > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > latency = dev_priv->wm.skl_latency[level];
> >
> > if (skl_needs_memory_bw_wa(dev_priv) &&
> > - plane->base.state->fb->modifier ==
> > + plane_state->uapi.fb->modifier ==
> > I915_FORMAT_MOD_X_TILED)
> > latency += 15;
> >
> > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > return true;
> > }
> >
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + return bw_state->pipe_sagv_reject == 0;
> > +}
> > +
> > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > +{
> > + int ret;
> > struct intel_crtc *crtc;
> > - const struct intel_crtc_state *crtc_state;
> > - enum pipe pipe;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_bw_state *new_bw_state = NULL;
> > + const struct intel_bw_state *old_bw_state = NULL;
> > + int i;
> >
> > - if (!intel_has_sagv(dev_priv))
> > - return false;
> > + for_each_new_intel_crtc_in_state(state, crtc,
> > + new_crtc_state, i) {
> > + new_bw_state = intel_atomic_get_bw_state(state);
> > + if (IS_ERR(new_bw_state))
> > + return PTR_ERR(new_bw_state);
> >
> > - /*
> > - * If there are no active CRTCs, no additional checks need be performed
> > - */
> > - if (hweight8(state->active_pipes) == 0)
> > - return true;
> > + old_bw_state = intel_atomic_get_old_bw_state(state);
> >
> > - /*
> > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > - * more then one pipe enabled
> > - */
> > - if (hweight8(state->active_pipes) > 1)
> > - return false;
> > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > + else
> > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > + }
> >
> > - /* Since we're now guaranteed to only have one active CRTC... */
> > - pipe = ffs(state->active_pipes) - 1;
> > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > + if (!new_bw_state)
> > + return 0;
> >
> > - return intel_crtc_can_enable_sagv(crtc_state);
> > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > }
> >
> > /*
> > @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > + if (state->modeset) {
> > + ret = intel_compute_sagv_mask(state);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > /*
> > * skl_compute_ddb() will have adjusted the final watermarks
> > * based on how much ddb is available. Now we can actually
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > index 9a6036ab0f90..fd1dc422e6c5 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -9,6 +9,7 @@
> > #include <linux/types.h>
> >
> > #include "i915_reg.h"
> > +#include "display/intel_bw.h"
> >
> > struct drm_device;
> > struct drm_i915_private;
> > @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > struct skl_pipe_wm *out);
> > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-30 9:13 ` Lisovskiy, Stanislav
@ 2020-04-30 9:25 ` Ville Syrjälä
2020-04-30 9:52 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 9:25 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > > Future platforms require per-crtc SAGV evaluation
> > > and serializing global state when those are changed
> > > from different commits.
> > >
> > > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > > so that it sets bit in reject mask.
> > > - Use bw_state in intel_pre/post_plane_enable_sagv
> > > instead of atomic state
> > >
> > > v3: - Fixed rebase conflict, now using
> > > intel_atomic_crtc_state_for_each_plane_state in
> > > order to call it from atomic check
> > > v4: - Use fb modifier from plane state
> > >
> > > v5: - Make intel_has_sagv static again(Ville)
> > > - Removed unnecessary NULL assignments(Ville)
> > > - Removed unnecessary SAGV debug(Ville)
> > > - Call intel_compute_sagv_mask only for modesets(Ville)
> > > - Serialize global state only if sagv results change, but
> > > not mask itself(Ville)
> > >
> > > v6: - use lock global state instead of serialize(Ville)
> >
> > What I meant is that we need both. Serialize if sagv state is going to
> > change, otherwise lock if the mask changes.
>
> As I understand whenever we modify global state but not a real hw, we do
> only global state locking - pipe sagv mask is not actually a hw, but just
> a virtual thing. It affects the QGV points we enable and if it happens to
> affect those in a way that those change - we'll any way have serialize
> called from intel_bw.c. Thus shouldn't be an issue.
I don't like the code to rely on magic happening elsewhere. IMO
it just makes it hard to reason about the logic when you have
constantly remind youself what may or may not happen some other
piece of code. Also we don't even have qgv points on all the
platforms, so presumably we may not even excute that other
piece of code always?
>
> I can change it anyway of course.
>
> Stan
>
> >
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > > 3 files changed, 93 insertions(+), 29 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > index ac004d6f4276..d6df91058223 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > > struct intel_bw_state {
> > > struct intel_global_state base;
> > >
> > > + /*
> > > + * Contains a bit mask, used to determine, whether correspondent
> > > + * pipe allows SAGV or not.
> > > + */
> > > + u8 pipe_sagv_reject;
> > > +
> > > unsigned int data_rate[I915_MAX_PIPES];
> > > u8 num_active_planes[I915_MAX_PIPES];
> > > };
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 338a82577b76..7e15cf3368ad 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -43,6 +43,7 @@
> > > #include "i915_fixed.h"
> > > #include "i915_irq.h"
> > > #include "i915_trace.h"
> > > +#include "display/intel_bw.h"
> > > #include "intel_pm.h"
> > > #include "intel_sideband.h"
> > > #include "../../../platform/x86/intel_ips.h"
> > > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + const struct intel_bw_state *new_bw_state;
> > >
> > > - if (!intel_can_enable_sagv(state))
> > > + /*
> > > + * Just return if we can't control SAGV or don't have it.
> > > + * This is different from situation when we have SAGV but just can't
> > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > + * as it will throw an error. So have to check it here.
> > > + */
> > > + if (!intel_has_sagv(dev_priv))
> > > + return;
> > > +
> > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > + if (!new_bw_state)
> > > + return;
> > > +
> > > + if (!intel_can_enable_sagv(new_bw_state))
> > > intel_disable_sagv(dev_priv);
> > > }
> > >
> > > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + const struct intel_bw_state *new_bw_state;
> > >
> > > - if (intel_can_enable_sagv(state))
> > > + /*
> > > + * Just return if we can't control SAGV or don't have it.
> > > + * This is different from situation when we have SAGV but just can't
> > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > + * as it will throw an error. So have to check it here.
> > > + */
> > > + if (!intel_has_sagv(dev_priv))
> > > + return;
> > > +
> > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > + if (!new_bw_state)
> > > + return;
> > > +
> > > + if (intel_can_enable_sagv(new_bw_state))
> > > intel_enable_sagv(dev_priv);
> > > }
> > >
> > > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > {
> > > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > struct intel_plane *plane;
> > > + const struct intel_plane_state *plane_state;
> > > int level, latency;
> > >
> > > + if (!intel_has_sagv(dev_priv))
> > > + return false;
> > > +
> > > if (!crtc_state->hw.active)
> > > return true;
> > >
> > > + /*
> > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > + * more then one pipe enabled
> > > + */
> > > + if (hweight8(state->active_pipes) > 1)
> > > + return false;
> > > +
> > > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > return false;
> > >
> > > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > const struct skl_plane_wm *wm =
> > > &crtc_state->wm.skl.optimal.planes[plane->id];
> > >
> > > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > latency = dev_priv->wm.skl_latency[level];
> > >
> > > if (skl_needs_memory_bw_wa(dev_priv) &&
> > > - plane->base.state->fb->modifier ==
> > > + plane_state->uapi.fb->modifier ==
> > > I915_FORMAT_MOD_X_TILED)
> > > latency += 15;
> > >
> > > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > return true;
> > > }
> > >
> > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > {
> > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + return bw_state->pipe_sagv_reject == 0;
> > > +}
> > > +
> > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > +{
> > > + int ret;
> > > struct intel_crtc *crtc;
> > > - const struct intel_crtc_state *crtc_state;
> > > - enum pipe pipe;
> > > + struct intel_crtc_state *new_crtc_state;
> > > + struct intel_bw_state *new_bw_state = NULL;
> > > + const struct intel_bw_state *old_bw_state = NULL;
> > > + int i;
> > >
> > > - if (!intel_has_sagv(dev_priv))
> > > - return false;
> > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > + new_crtc_state, i) {
> > > + new_bw_state = intel_atomic_get_bw_state(state);
> > > + if (IS_ERR(new_bw_state))
> > > + return PTR_ERR(new_bw_state);
> > >
> > > - /*
> > > - * If there are no active CRTCs, no additional checks need be performed
> > > - */
> > > - if (hweight8(state->active_pipes) == 0)
> > > - return true;
> > > + old_bw_state = intel_atomic_get_old_bw_state(state);
> > >
> > > - /*
> > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > - * more then one pipe enabled
> > > - */
> > > - if (hweight8(state->active_pipes) > 1)
> > > - return false;
> > > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > + else
> > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > + }
> > >
> > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > - pipe = ffs(state->active_pipes) - 1;
> > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > + if (!new_bw_state)
> > > + return 0;
> > >
> > > - return intel_crtc_can_enable_sagv(crtc_state);
> > > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > + return 0;
> > > }
> > >
> > > /*
> > > @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > if (ret)
> > > return ret;
> > >
> > > + if (state->modeset) {
> > > + ret = intel_compute_sagv_mask(state);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > /*
> > > * skl_compute_ddb() will have adjusted the final watermarks
> > > * based on how much ddb is available. Now we can actually
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > index 9a6036ab0f90..fd1dc422e6c5 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > @@ -9,6 +9,7 @@
> > > #include <linux/types.h>
> > >
> > > #include "i915_reg.h"
> > > +#include "display/intel_bw.h"
> > >
> > > struct drm_device;
> > > struct drm_i915_private;
> > > @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > struct skl_pipe_wm *out);
> > > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > --
> > > 2.24.1.485.gad05a3d8e5
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-30 9:25 ` Ville Syrjälä
@ 2020-04-30 9:52 ` Lisovskiy, Stanislav
2020-04-30 10:08 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 9:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > > > Future platforms require per-crtc SAGV evaluation
> > > > and serializing global state when those are changed
> > > > from different commits.
> > > >
> > > > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > > > so that it sets bit in reject mask.
> > > > - Use bw_state in intel_pre/post_plane_enable_sagv
> > > > instead of atomic state
> > > >
> > > > v3: - Fixed rebase conflict, now using
> > > > intel_atomic_crtc_state_for_each_plane_state in
> > > > order to call it from atomic check
> > > > v4: - Use fb modifier from plane state
> > > >
> > > > v5: - Make intel_has_sagv static again(Ville)
> > > > - Removed unnecessary NULL assignments(Ville)
> > > > - Removed unnecessary SAGV debug(Ville)
> > > > - Call intel_compute_sagv_mask only for modesets(Ville)
> > > > - Serialize global state only if sagv results change, but
> > > > not mask itself(Ville)
> > > >
> > > > v6: - use lock global state instead of serialize(Ville)
> > >
> > > What I meant is that we need both. Serialize if sagv state is going to
> > > change, otherwise lock if the mask changes.
> >
> > As I understand whenever we modify global state but not a real hw, we do
> > only global state locking - pipe sagv mask is not actually a hw, but just
> > a virtual thing. It affects the QGV points we enable and if it happens to
> > affect those in a way that those change - we'll any way have serialize
> > called from intel_bw.c. Thus shouldn't be an issue.
>
> I don't like the code to rely on magic happening elsewhere. IMO
> it just makes it hard to reason about the logic when you have
> constantly remind youself what may or may not happen some other
> piece of code. Also we don't even have qgv points on all the
> platforms, so presumably we may not even excute that other
> piece of code always?
Agree, sounds reasonable. Would be cool may be to unite both serialize
and global state locking, under some helper function, so that same
code snippet is not copy-paste all over the place.
like intel_lock_or_serialize_state(state, bool global_state_changed, bool hw_state_changed)
Stan
>
> >
> > I can change it anyway of course.
> >
> > Stan
> >
> > >
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > > > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > > > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > > > 3 files changed, 93 insertions(+), 29 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > index ac004d6f4276..d6df91058223 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > > > struct intel_bw_state {
> > > > struct intel_global_state base;
> > > >
> > > > + /*
> > > > + * Contains a bit mask, used to determine, whether correspondent
> > > > + * pipe allows SAGV or not.
> > > > + */
> > > > + u8 pipe_sagv_reject;
> > > > +
> > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > };
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 338a82577b76..7e15cf3368ad 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -43,6 +43,7 @@
> > > > #include "i915_fixed.h"
> > > > #include "i915_irq.h"
> > > > #include "i915_trace.h"
> > > > +#include "display/intel_bw.h"
> > > > #include "intel_pm.h"
> > > > #include "intel_sideband.h"
> > > > #include "../../../platform/x86/intel_ips.h"
> > > > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > > {
> > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > + const struct intel_bw_state *new_bw_state;
> > > >
> > > > - if (!intel_can_enable_sagv(state))
> > > > + /*
> > > > + * Just return if we can't control SAGV or don't have it.
> > > > + * This is different from situation when we have SAGV but just can't
> > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > + * as it will throw an error. So have to check it here.
> > > > + */
> > > > + if (!intel_has_sagv(dev_priv))
> > > > + return;
> > > > +
> > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > + if (!new_bw_state)
> > > > + return;
> > > > +
> > > > + if (!intel_can_enable_sagv(new_bw_state))
> > > > intel_disable_sagv(dev_priv);
> > > > }
> > > >
> > > > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > > {
> > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > + const struct intel_bw_state *new_bw_state;
> > > >
> > > > - if (intel_can_enable_sagv(state))
> > > > + /*
> > > > + * Just return if we can't control SAGV or don't have it.
> > > > + * This is different from situation when we have SAGV but just can't
> > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > + * as it will throw an error. So have to check it here.
> > > > + */
> > > > + if (!intel_has_sagv(dev_priv))
> > > > + return;
> > > > +
> > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > + if (!new_bw_state)
> > > > + return;
> > > > +
> > > > + if (intel_can_enable_sagv(new_bw_state))
> > > > intel_enable_sagv(dev_priv);
> > > > }
> > > >
> > > > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > {
> > > > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > struct intel_plane *plane;
> > > > + const struct intel_plane_state *plane_state;
> > > > int level, latency;
> > > >
> > > > + if (!intel_has_sagv(dev_priv))
> > > > + return false;
> > > > +
> > > > if (!crtc_state->hw.active)
> > > > return true;
> > > >
> > > > + /*
> > > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > + * more then one pipe enabled
> > > > + */
> > > > + if (hweight8(state->active_pipes) > 1)
> > > > + return false;
> > > > +
> > > > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > return false;
> > > >
> > > > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > > const struct skl_plane_wm *wm =
> > > > &crtc_state->wm.skl.optimal.planes[plane->id];
> > > >
> > > > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > latency = dev_priv->wm.skl_latency[level];
> > > >
> > > > if (skl_needs_memory_bw_wa(dev_priv) &&
> > > > - plane->base.state->fb->modifier ==
> > > > + plane_state->uapi.fb->modifier ==
> > > > I915_FORMAT_MOD_X_TILED)
> > > > latency += 15;
> > > >
> > > > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > return true;
> > > > }
> > > >
> > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > {
> > > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > + return bw_state->pipe_sagv_reject == 0;
> > > > +}
> > > > +
> > > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > +{
> > > > + int ret;
> > > > struct intel_crtc *crtc;
> > > > - const struct intel_crtc_state *crtc_state;
> > > > - enum pipe pipe;
> > > > + struct intel_crtc_state *new_crtc_state;
> > > > + struct intel_bw_state *new_bw_state = NULL;
> > > > + const struct intel_bw_state *old_bw_state = NULL;
> > > > + int i;
> > > >
> > > > - if (!intel_has_sagv(dev_priv))
> > > > - return false;
> > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > + new_crtc_state, i) {
> > > > + new_bw_state = intel_atomic_get_bw_state(state);
> > > > + if (IS_ERR(new_bw_state))
> > > > + return PTR_ERR(new_bw_state);
> > > >
> > > > - /*
> > > > - * If there are no active CRTCs, no additional checks need be performed
> > > > - */
> > > > - if (hweight8(state->active_pipes) == 0)
> > > > - return true;
> > > > + old_bw_state = intel_atomic_get_old_bw_state(state);
> > > >
> > > > - /*
> > > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > - * more then one pipe enabled
> > > > - */
> > > > - if (hweight8(state->active_pipes) > 1)
> > > > - return false;
> > > > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > + else
> > > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > + }
> > > >
> > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > - pipe = ffs(state->active_pipes) - 1;
> > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > + if (!new_bw_state)
> > > > + return 0;
> > > >
> > > > - return intel_crtc_can_enable_sagv(crtc_state);
> > > > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > > > +
> > > > + return 0;
> > > > }
> > > >
> > > > /*
> > > > @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > if (ret)
> > > > return ret;
> > > >
> > > > + if (state->modeset) {
> > > > + ret = intel_compute_sagv_mask(state);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > > > +
> > > > /*
> > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > * based on how much ddb is available. Now we can actually
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > > index 9a6036ab0f90..fd1dc422e6c5 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > > @@ -9,6 +9,7 @@
> > > > #include <linux/types.h>
> > > >
> > > > #include "i915_reg.h"
> > > > +#include "display/intel_bw.h"
> > > >
> > > > struct drm_device;
> > > > struct drm_i915_private;
> > > > @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > > struct skl_pipe_wm *out);
> > > > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > > > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > > --
> > > > 2.24.1.485.gad05a3d8e5
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-30 9:52 ` Lisovskiy, Stanislav
@ 2020-04-30 10:08 ` Ville Syrjälä
2020-04-30 10:14 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 10:08 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 12:52:42PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > > > > Future platforms require per-crtc SAGV evaluation
> > > > > and serializing global state when those are changed
> > > > > from different commits.
> > > > >
> > > > > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > > > > so that it sets bit in reject mask.
> > > > > - Use bw_state in intel_pre/post_plane_enable_sagv
> > > > > instead of atomic state
> > > > >
> > > > > v3: - Fixed rebase conflict, now using
> > > > > intel_atomic_crtc_state_for_each_plane_state in
> > > > > order to call it from atomic check
> > > > > v4: - Use fb modifier from plane state
> > > > >
> > > > > v5: - Make intel_has_sagv static again(Ville)
> > > > > - Removed unnecessary NULL assignments(Ville)
> > > > > - Removed unnecessary SAGV debug(Ville)
> > > > > - Call intel_compute_sagv_mask only for modesets(Ville)
> > > > > - Serialize global state only if sagv results change, but
> > > > > not mask itself(Ville)
> > > > >
> > > > > v6: - use lock global state instead of serialize(Ville)
> > > >
> > > > What I meant is that we need both. Serialize if sagv state is going to
> > > > change, otherwise lock if the mask changes.
> > >
> > > As I understand whenever we modify global state but not a real hw, we do
> > > only global state locking - pipe sagv mask is not actually a hw, but just
> > > a virtual thing. It affects the QGV points we enable and if it happens to
> > > affect those in a way that those change - we'll any way have serialize
> > > called from intel_bw.c. Thus shouldn't be an issue.
> >
> > I don't like the code to rely on magic happening elsewhere. IMO
> > it just makes it hard to reason about the logic when you have
> > constantly remind youself what may or may not happen some other
> > piece of code. Also we don't even have qgv points on all the
> > platforms, so presumably we may not even excute that other
> > piece of code always?
>
> Agree, sounds reasonable. Would be cool may be to unite both serialize
> and global state locking, under some helper function, so that same
> code snippet is not copy-paste all over the place.
>
> like intel_lock_or_serialize_state(state, bool global_state_changed, bool hw_state_changed)
intel_lock_or_serialize_state(state,
a != b,
x != y);
doesn't really make the intent clear at all. So not really in favor of a
function that takes two booleans.
>
> Stan
>
> >
> > >
> > > I can change it anyway of course.
> > >
> > > Stan
> > >
> > > >
> > > > >
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > > > > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > > > > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > > > > 3 files changed, 93 insertions(+), 29 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > index ac004d6f4276..d6df91058223 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > > > > struct intel_bw_state {
> > > > > struct intel_global_state base;
> > > > >
> > > > > + /*
> > > > > + * Contains a bit mask, used to determine, whether correspondent
> > > > > + * pipe allows SAGV or not.
> > > > > + */
> > > > > + u8 pipe_sagv_reject;
> > > > > +
> > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > };
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 338a82577b76..7e15cf3368ad 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -43,6 +43,7 @@
> > > > > #include "i915_fixed.h"
> > > > > #include "i915_irq.h"
> > > > > #include "i915_trace.h"
> > > > > +#include "display/intel_bw.h"
> > > > > #include "intel_pm.h"
> > > > > #include "intel_sideband.h"
> > > > > #include "../../../platform/x86/intel_ips.h"
> > > > > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > + const struct intel_bw_state *new_bw_state;
> > > > >
> > > > > - if (!intel_can_enable_sagv(state))
> > > > > + /*
> > > > > + * Just return if we can't control SAGV or don't have it.
> > > > > + * This is different from situation when we have SAGV but just can't
> > > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > > + * as it will throw an error. So have to check it here.
> > > > > + */
> > > > > + if (!intel_has_sagv(dev_priv))
> > > > > + return;
> > > > > +
> > > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > > + if (!new_bw_state)
> > > > > + return;
> > > > > +
> > > > > + if (!intel_can_enable_sagv(new_bw_state))
> > > > > intel_disable_sagv(dev_priv);
> > > > > }
> > > > >
> > > > > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > + const struct intel_bw_state *new_bw_state;
> > > > >
> > > > > - if (intel_can_enable_sagv(state))
> > > > > + /*
> > > > > + * Just return if we can't control SAGV or don't have it.
> > > > > + * This is different from situation when we have SAGV but just can't
> > > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > > + * as it will throw an error. So have to check it here.
> > > > > + */
> > > > > + if (!intel_has_sagv(dev_priv))
> > > > > + return;
> > > > > +
> > > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > > + if (!new_bw_state)
> > > > > + return;
> > > > > +
> > > > > + if (intel_can_enable_sagv(new_bw_state))
> > > > > intel_enable_sagv(dev_priv);
> > > > > }
> > > > >
> > > > > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > {
> > > > > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > > struct intel_plane *plane;
> > > > > + const struct intel_plane_state *plane_state;
> > > > > int level, latency;
> > > > >
> > > > > + if (!intel_has_sagv(dev_priv))
> > > > > + return false;
> > > > > +
> > > > > if (!crtc_state->hw.active)
> > > > > return true;
> > > > >
> > > > > + /*
> > > > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > + * more then one pipe enabled
> > > > > + */
> > > > > + if (hweight8(state->active_pipes) > 1)
> > > > > + return false;
> > > > > +
> > > > > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > > return false;
> > > > >
> > > > > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > > > const struct skl_plane_wm *wm =
> > > > > &crtc_state->wm.skl.optimal.planes[plane->id];
> > > > >
> > > > > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > > latency = dev_priv->wm.skl_latency[level];
> > > > >
> > > > > if (skl_needs_memory_bw_wa(dev_priv) &&
> > > > > - plane->base.state->fb->modifier ==
> > > > > + plane_state->uapi.fb->modifier ==
> > > > > I915_FORMAT_MOD_X_TILED)
> > > > > latency += 15;
> > > > >
> > > > > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > > return true;
> > > > > }
> > > > >
> > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > > {
> > > > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > + return bw_state->pipe_sagv_reject == 0;
> > > > > +}
> > > > > +
> > > > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > +{
> > > > > + int ret;
> > > > > struct intel_crtc *crtc;
> > > > > - const struct intel_crtc_state *crtc_state;
> > > > > - enum pipe pipe;
> > > > > + struct intel_crtc_state *new_crtc_state;
> > > > > + struct intel_bw_state *new_bw_state = NULL;
> > > > > + const struct intel_bw_state *old_bw_state = NULL;
> > > > > + int i;
> > > > >
> > > > > - if (!intel_has_sagv(dev_priv))
> > > > > - return false;
> > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > + new_crtc_state, i) {
> > > > > + new_bw_state = intel_atomic_get_bw_state(state);
> > > > > + if (IS_ERR(new_bw_state))
> > > > > + return PTR_ERR(new_bw_state);
> > > > >
> > > > > - /*
> > > > > - * If there are no active CRTCs, no additional checks need be performed
> > > > > - */
> > > > > - if (hweight8(state->active_pipes) == 0)
> > > > > - return true;
> > > > > + old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > >
> > > > > - /*
> > > > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > - * more then one pipe enabled
> > > > > - */
> > > > > - if (hweight8(state->active_pipes) > 1)
> > > > > - return false;
> > > > > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > + else
> > > > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > + }
> > > > >
> > > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > > - pipe = ffs(state->active_pipes) - 1;
> > > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > > + if (!new_bw_state)
> > > > > + return 0;
> > > > >
> > > > > - return intel_crtc_can_enable_sagv(crtc_state);
> > > > > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > > + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + return 0;
> > > > > }
> > > > >
> > > > > /*
> > > > > @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > + if (state->modeset) {
> > > > > + ret = intel_compute_sagv_mask(state);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > /*
> > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > * based on how much ddb is available. Now we can actually
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > > > index 9a6036ab0f90..fd1dc422e6c5 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > > > @@ -9,6 +9,7 @@
> > > > > #include <linux/types.h>
> > > > >
> > > > > #include "i915_reg.h"
> > > > > +#include "display/intel_bw.h"
> > > > >
> > > > > struct drm_device;
> > > > > struct drm_i915_private;
> > > > > @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > > > struct skl_pipe_wm *out);
> > > > > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > > > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > > > > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > > > --
> > > > > 2.24.1.485.gad05a3d8e5
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-30 10:08 ` Ville Syrjälä
@ 2020-04-30 10:14 ` Lisovskiy, Stanislav
2020-04-30 10:37 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 10:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 01:08:20PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 12:52:42PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > > > > > Future platforms require per-crtc SAGV evaluation
> > > > > > and serializing global state when those are changed
> > > > > > from different commits.
> > > > > >
> > > > > > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > > > > > so that it sets bit in reject mask.
> > > > > > - Use bw_state in intel_pre/post_plane_enable_sagv
> > > > > > instead of atomic state
> > > > > >
> > > > > > v3: - Fixed rebase conflict, now using
> > > > > > intel_atomic_crtc_state_for_each_plane_state in
> > > > > > order to call it from atomic check
> > > > > > v4: - Use fb modifier from plane state
> > > > > >
> > > > > > v5: - Make intel_has_sagv static again(Ville)
> > > > > > - Removed unnecessary NULL assignments(Ville)
> > > > > > - Removed unnecessary SAGV debug(Ville)
> > > > > > - Call intel_compute_sagv_mask only for modesets(Ville)
> > > > > > - Serialize global state only if sagv results change, but
> > > > > > not mask itself(Ville)
> > > > > >
> > > > > > v6: - use lock global state instead of serialize(Ville)
> > > > >
> > > > > What I meant is that we need both. Serialize if sagv state is going to
> > > > > change, otherwise lock if the mask changes.
> > > >
> > > > As I understand whenever we modify global state but not a real hw, we do
> > > > only global state locking - pipe sagv mask is not actually a hw, but just
> > > > a virtual thing. It affects the QGV points we enable and if it happens to
> > > > affect those in a way that those change - we'll any way have serialize
> > > > called from intel_bw.c. Thus shouldn't be an issue.
> > >
> > > I don't like the code to rely on magic happening elsewhere. IMO
> > > it just makes it hard to reason about the logic when you have
> > > constantly remind youself what may or may not happen some other
> > > piece of code. Also we don't even have qgv points on all the
> > > platforms, so presumably we may not even excute that other
> > > piece of code always?
> >
> > Agree, sounds reasonable. Would be cool may be to unite both serialize
> > and global state locking, under some helper function, so that same
> > code snippet is not copy-paste all over the place.
> >
> > like intel_lock_or_serialize_state(state, bool global_state_changed, bool hw_state_changed)
>
> intel_lock_or_serialize_state(state,
> a != b,
> x != y);
>
> doesn't really make the intent clear at all. So not really in favor of a
> function that takes two booleans.
bool global_state_changed = new_sagv_pipe_mask != old_sagv_pipe_mask;
bool hw_state_changed = new_can_enable_sagv != old_can_enable_sagv;
intel_lock_or_serialize(state, global_state_changed, hw_state_changed);
I think together with proper comment this looks pretty clear and also
eliminates the need in duplicating conditions all over the place.
Just a proposal though.
Stan
>
> >
> > Stan
> >
> > >
> > > >
> > > > I can change it anyway of course.
> > > >
> > > > Stan
> > > >
> > > > >
> > > > > >
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > > > > > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > > > > > 3 files changed, 93 insertions(+), 29 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > index ac004d6f4276..d6df91058223 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > > > > > struct intel_bw_state {
> > > > > > struct intel_global_state base;
> > > > > >
> > > > > > + /*
> > > > > > + * Contains a bit mask, used to determine, whether correspondent
> > > > > > + * pipe allows SAGV or not.
> > > > > > + */
> > > > > > + u8 pipe_sagv_reject;
> > > > > > +
> > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > };
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index 338a82577b76..7e15cf3368ad 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -43,6 +43,7 @@
> > > > > > #include "i915_fixed.h"
> > > > > > #include "i915_irq.h"
> > > > > > #include "i915_trace.h"
> > > > > > +#include "display/intel_bw.h"
> > > > > > #include "intel_pm.h"
> > > > > > #include "intel_sideband.h"
> > > > > > #include "../../../platform/x86/intel_ips.h"
> > > > > > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > + const struct intel_bw_state *new_bw_state;
> > > > > >
> > > > > > - if (!intel_can_enable_sagv(state))
> > > > > > + /*
> > > > > > + * Just return if we can't control SAGV or don't have it.
> > > > > > + * This is different from situation when we have SAGV but just can't
> > > > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > > > + * as it will throw an error. So have to check it here.
> > > > > > + */
> > > > > > + if (!intel_has_sagv(dev_priv))
> > > > > > + return;
> > > > > > +
> > > > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > > > + if (!new_bw_state)
> > > > > > + return;
> > > > > > +
> > > > > > + if (!intel_can_enable_sagv(new_bw_state))
> > > > > > intel_disable_sagv(dev_priv);
> > > > > > }
> > > > > >
> > > > > > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > + const struct intel_bw_state *new_bw_state;
> > > > > >
> > > > > > - if (intel_can_enable_sagv(state))
> > > > > > + /*
> > > > > > + * Just return if we can't control SAGV or don't have it.
> > > > > > + * This is different from situation when we have SAGV but just can't
> > > > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > > > + * as it will throw an error. So have to check it here.
> > > > > > + */
> > > > > > + if (!intel_has_sagv(dev_priv))
> > > > > > + return;
> > > > > > +
> > > > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > > > + if (!new_bw_state)
> > > > > > + return;
> > > > > > +
> > > > > > + if (intel_can_enable_sagv(new_bw_state))
> > > > > > intel_enable_sagv(dev_priv);
> > > > > > }
> > > > > >
> > > > > > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > > {
> > > > > > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > > > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > > > struct intel_plane *plane;
> > > > > > + const struct intel_plane_state *plane_state;
> > > > > > int level, latency;
> > > > > >
> > > > > > + if (!intel_has_sagv(dev_priv))
> > > > > > + return false;
> > > > > > +
> > > > > > if (!crtc_state->hw.active)
> > > > > > return true;
> > > > > >
> > > > > > + /*
> > > > > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > > + * more then one pipe enabled
> > > > > > + */
> > > > > > + if (hweight8(state->active_pipes) > 1)
> > > > > > + return false;
> > > > > > +
> > > > > > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > > > return false;
> > > > > >
> > > > > > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > > > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > > > > const struct skl_plane_wm *wm =
> > > > > > &crtc_state->wm.skl.optimal.planes[plane->id];
> > > > > >
> > > > > > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > > > latency = dev_priv->wm.skl_latency[level];
> > > > > >
> > > > > > if (skl_needs_memory_bw_wa(dev_priv) &&
> > > > > > - plane->base.state->fb->modifier ==
> > > > > > + plane_state->uapi.fb->modifier ==
> > > > > > I915_FORMAT_MOD_X_TILED)
> > > > > > latency += 15;
> > > > > >
> > > > > > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > > > return true;
> > > > > > }
> > > > > >
> > > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > > > {
> > > > > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > + return bw_state->pipe_sagv_reject == 0;
> > > > > > +}
> > > > > > +
> > > > > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > +{
> > > > > > + int ret;
> > > > > > struct intel_crtc *crtc;
> > > > > > - const struct intel_crtc_state *crtc_state;
> > > > > > - enum pipe pipe;
> > > > > > + struct intel_crtc_state *new_crtc_state;
> > > > > > + struct intel_bw_state *new_bw_state = NULL;
> > > > > > + const struct intel_bw_state *old_bw_state = NULL;
> > > > > > + int i;
> > > > > >
> > > > > > - if (!intel_has_sagv(dev_priv))
> > > > > > - return false;
> > > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > + new_crtc_state, i) {
> > > > > > + new_bw_state = intel_atomic_get_bw_state(state);
> > > > > > + if (IS_ERR(new_bw_state))
> > > > > > + return PTR_ERR(new_bw_state);
> > > > > >
> > > > > > - /*
> > > > > > - * If there are no active CRTCs, no additional checks need be performed
> > > > > > - */
> > > > > > - if (hweight8(state->active_pipes) == 0)
> > > > > > - return true;
> > > > > > + old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > >
> > > > > > - /*
> > > > > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > > - * more then one pipe enabled
> > > > > > - */
> > > > > > - if (hweight8(state->active_pipes) > 1)
> > > > > > - return false;
> > > > > > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > + else
> > > > > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > + }
> > > > > >
> > > > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > > > - pipe = ffs(state->active_pipes) - 1;
> > > > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > > > + if (!new_bw_state)
> > > > > > + return 0;
> > > > > >
> > > > > > - return intel_crtc_can_enable_sagv(crtc_state);
> > > > > > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > > > + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > + }
> > > > > > +
> > > > > > + return 0;
> > > > > > }
> > > > > >
> > > > > > /*
> > > > > > @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > > if (ret)
> > > > > > return ret;
> > > > > >
> > > > > > + if (state->modeset) {
> > > > > > + ret = intel_compute_sagv_mask(state);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > + }
> > > > > > +
> > > > > > /*
> > > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > > * based on how much ddb is available. Now we can actually
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > > > > index 9a6036ab0f90..fd1dc422e6c5 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > > > > @@ -9,6 +9,7 @@
> > > > > > #include <linux/types.h>
> > > > > >
> > > > > > #include "i915_reg.h"
> > > > > > +#include "display/intel_bw.h"
> > > > > >
> > > > > > struct drm_device;
> > > > > > struct drm_i915_private;
> > > > > > @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > > > > struct skl_pipe_wm *out);
> > > > > > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > > > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > > > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > > > > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > > > > > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > > > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > > > > --
> > > > > > 2.24.1.485.gad05a3d8e5
> > > > >
> > > > > --
> > > > > Ville Syrjälä
> > > > > Intel
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-30 10:14 ` Lisovskiy, Stanislav
@ 2020-04-30 10:37 ` Ville Syrjälä
0 siblings, 0 replies; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 10:37 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 01:14:57PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 01:08:20PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 12:52:42PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> > > > > On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > > > > > On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > Future platforms require per-crtc SAGV evaluation
> > > > > > > and serializing global state when those are changed
> > > > > > > from different commits.
> > > > > > >
> > > > > > > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > > > > > > so that it sets bit in reject mask.
> > > > > > > - Use bw_state in intel_pre/post_plane_enable_sagv
> > > > > > > instead of atomic state
> > > > > > >
> > > > > > > v3: - Fixed rebase conflict, now using
> > > > > > > intel_atomic_crtc_state_for_each_plane_state in
> > > > > > > order to call it from atomic check
> > > > > > > v4: - Use fb modifier from plane state
> > > > > > >
> > > > > > > v5: - Make intel_has_sagv static again(Ville)
> > > > > > > - Removed unnecessary NULL assignments(Ville)
> > > > > > > - Removed unnecessary SAGV debug(Ville)
> > > > > > > - Call intel_compute_sagv_mask only for modesets(Ville)
> > > > > > > - Serialize global state only if sagv results change, but
> > > > > > > not mask itself(Ville)
> > > > > > >
> > > > > > > v6: - use lock global state instead of serialize(Ville)
> > > > > >
> > > > > > What I meant is that we need both. Serialize if sagv state is going to
> > > > > > change, otherwise lock if the mask changes.
> > > > >
> > > > > As I understand whenever we modify global state but not a real hw, we do
> > > > > only global state locking - pipe sagv mask is not actually a hw, but just
> > > > > a virtual thing. It affects the QGV points we enable and if it happens to
> > > > > affect those in a way that those change - we'll any way have serialize
> > > > > called from intel_bw.c. Thus shouldn't be an issue.
> > > >
> > > > I don't like the code to rely on magic happening elsewhere. IMO
> > > > it just makes it hard to reason about the logic when you have
> > > > constantly remind youself what may or may not happen some other
> > > > piece of code. Also we don't even have qgv points on all the
> > > > platforms, so presumably we may not even excute that other
> > > > piece of code always?
> > >
> > > Agree, sounds reasonable. Would be cool may be to unite both serialize
> > > and global state locking, under some helper function, so that same
> > > code snippet is not copy-paste all over the place.
> > >
> > > like intel_lock_or_serialize_state(state, bool global_state_changed, bool hw_state_changed)
> >
> > intel_lock_or_serialize_state(state,
> > a != b,
> > x != y);
> >
> > doesn't really make the intent clear at all. So not really in favor of a
> > function that takes two booleans.
>
> bool global_state_changed = new_sagv_pipe_mask != old_sagv_pipe_mask;
> bool hw_state_changed = new_can_enable_sagv != old_can_enable_sagv;
If we consistently make those functions instead of
variables then I could probably buy it.
>
> intel_lock_or_serialize(state, global_state_changed, hw_state_changed);
>
> I think together with proper comment this looks pretty clear and also
> eliminates the need in duplicating conditions all over the place.
If we have to add a comment I'd say the plan has already
failed. Good code needs no comments.
>
> Just a proposal though.
>
> Stan
>
> >
> > >
> > > Stan
> > >
> > > >
> > > > >
> > > > > I can change it anyway of course.
> > > > >
> > > > > Stan
> > > > >
> > > > > >
> > > > > > >
> > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > > > > > > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > > > > > > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > > > > > > 3 files changed, 93 insertions(+), 29 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > index ac004d6f4276..d6df91058223 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > > > > > > struct intel_bw_state {
> > > > > > > struct intel_global_state base;
> > > > > > >
> > > > > > > + /*
> > > > > > > + * Contains a bit mask, used to determine, whether correspondent
> > > > > > > + * pipe allows SAGV or not.
> > > > > > > + */
> > > > > > > + u8 pipe_sagv_reject;
> > > > > > > +
> > > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > > };
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > index 338a82577b76..7e15cf3368ad 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > @@ -43,6 +43,7 @@
> > > > > > > #include "i915_fixed.h"
> > > > > > > #include "i915_irq.h"
> > > > > > > #include "i915_trace.h"
> > > > > > > +#include "display/intel_bw.h"
> > > > > > > #include "intel_pm.h"
> > > > > > > #include "intel_sideband.h"
> > > > > > > #include "../../../platform/x86/intel_ips.h"
> > > > > > > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > > > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > > > > > {
> > > > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > > + const struct intel_bw_state *new_bw_state;
> > > > > > >
> > > > > > > - if (!intel_can_enable_sagv(state))
> > > > > > > + /*
> > > > > > > + * Just return if we can't control SAGV or don't have it.
> > > > > > > + * This is different from situation when we have SAGV but just can't
> > > > > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > > > > + * as it will throw an error. So have to check it here.
> > > > > > > + */
> > > > > > > + if (!intel_has_sagv(dev_priv))
> > > > > > > + return;
> > > > > > > +
> > > > > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > > > > + if (!new_bw_state)
> > > > > > > + return;
> > > > > > > +
> > > > > > > + if (!intel_can_enable_sagv(new_bw_state))
> > > > > > > intel_disable_sagv(dev_priv);
> > > > > > > }
> > > > > > >
> > > > > > > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > > > > > {
> > > > > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > > + const struct intel_bw_state *new_bw_state;
> > > > > > >
> > > > > > > - if (intel_can_enable_sagv(state))
> > > > > > > + /*
> > > > > > > + * Just return if we can't control SAGV or don't have it.
> > > > > > > + * This is different from situation when we have SAGV but just can't
> > > > > > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > > > > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > > > > > + * as it will throw an error. So have to check it here.
> > > > > > > + */
> > > > > > > + if (!intel_has_sagv(dev_priv))
> > > > > > > + return;
> > > > > > > +
> > > > > > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > > > > > + if (!new_bw_state)
> > > > > > > + return;
> > > > > > > +
> > > > > > > + if (intel_can_enable_sagv(new_bw_state))
> > > > > > > intel_enable_sagv(dev_priv);
> > > > > > > }
> > > > > > >
> > > > > > > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > > > {
> > > > > > > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > > > > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > > > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > > > > struct intel_plane *plane;
> > > > > > > + const struct intel_plane_state *plane_state;
> > > > > > > int level, latency;
> > > > > > >
> > > > > > > + if (!intel_has_sagv(dev_priv))
> > > > > > > + return false;
> > > > > > > +
> > > > > > > if (!crtc_state->hw.active)
> > > > > > > return true;
> > > > > > >
> > > > > > > + /*
> > > > > > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > > > + * more then one pipe enabled
> > > > > > > + */
> > > > > > > + if (hweight8(state->active_pipes) > 1)
> > > > > > > + return false;
> > > > > > > +
> > > > > > > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > > > > return false;
> > > > > > >
> > > > > > > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > > > > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > > > > > const struct skl_plane_wm *wm =
> > > > > > > &crtc_state->wm.skl.optimal.planes[plane->id];
> > > > > > >
> > > > > > > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > > > > latency = dev_priv->wm.skl_latency[level];
> > > > > > >
> > > > > > > if (skl_needs_memory_bw_wa(dev_priv) &&
> > > > > > > - plane->base.state->fb->modifier ==
> > > > > > > + plane_state->uapi.fb->modifier ==
> > > > > > > I915_FORMAT_MOD_X_TILED)
> > > > > > > latency += 15;
> > > > > > >
> > > > > > > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > > > > > return true;
> > > > > > > }
> > > > > > >
> > > > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > > > > {
> > > > > > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > > + return bw_state->pipe_sagv_reject == 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > +{
> > > > > > > + int ret;
> > > > > > > struct intel_crtc *crtc;
> > > > > > > - const struct intel_crtc_state *crtc_state;
> > > > > > > - enum pipe pipe;
> > > > > > > + struct intel_crtc_state *new_crtc_state;
> > > > > > > + struct intel_bw_state *new_bw_state = NULL;
> > > > > > > + const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > + int i;
> > > > > > >
> > > > > > > - if (!intel_has_sagv(dev_priv))
> > > > > > > - return false;
> > > > > > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > + new_crtc_state, i) {
> > > > > > > + new_bw_state = intel_atomic_get_bw_state(state);
> > > > > > > + if (IS_ERR(new_bw_state))
> > > > > > > + return PTR_ERR(new_bw_state);
> > > > > > >
> > > > > > > - /*
> > > > > > > - * If there are no active CRTCs, no additional checks need be performed
> > > > > > > - */
> > > > > > > - if (hweight8(state->active_pipes) == 0)
> > > > > > > - return true;
> > > > > > > + old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > >
> > > > > > > - /*
> > > > > > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > > > > > - * more then one pipe enabled
> > > > > > > - */
> > > > > > > - if (hweight8(state->active_pipes) > 1)
> > > > > > > - return false;
> > > > > > > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > + else
> > > > > > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > > + }
> > > > > > >
> > > > > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > > > > - pipe = ffs(state->active_pipes) - 1;
> > > > > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > > > > + if (!new_bw_state)
> > > > > > > + return 0;
> > > > > > >
> > > > > > > - return intel_crtc_can_enable_sagv(crtc_state);
> > > > > > > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > > > > + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> > > > > > > + if (ret)
> > > > > > > + return ret;
> > > > > > > + }
> > > > > > > +
> > > > > > > + return 0;
> > > > > > > }
> > > > > > >
> > > > > > > /*
> > > > > > > @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > > > if (ret)
> > > > > > > return ret;
> > > > > > >
> > > > > > > + if (state->modeset) {
> > > > > > > + ret = intel_compute_sagv_mask(state);
> > > > > > > + if (ret)
> > > > > > > + return ret;
> > > > > > > + }
> > > > > > > +
> > > > > > > /*
> > > > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > > > * based on how much ddb is available. Now we can actually
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > > > > > index 9a6036ab0f90..fd1dc422e6c5 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > > > > > @@ -9,6 +9,7 @@
> > > > > > > #include <linux/types.h>
> > > > > > >
> > > > > > > #include "i915_reg.h"
> > > > > > > +#include "display/intel_bw.h"
> > > > > > >
> > > > > > > struct drm_device;
> > > > > > > struct drm_i915_private;
> > > > > > > @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > > > > > struct skl_pipe_wm *out);
> > > > > > > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > > > > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > > > > > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > > > > > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > > > > > > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > > > > > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > > > > > --
> > > > > > > 2.24.1.485.gad05a3d8e5
> > > > > >
> > > > > > --
> > > > > > Ville Syrjälä
> > > > > > Intel
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
2020-04-30 9:09 ` Ville Syrjälä
@ 2020-04-30 19:17 ` Stanislav Lisovskiy
1 sibling, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-30 19:17 UTC (permalink / raw)
To: intel-gfx
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of atomic state
v3: - Fixed rebase conflict, now using
intel_atomic_crtc_state_for_each_plane_state in
order to call it from atomic check
v4: - Use fb modifier from plane state
v5: - Make intel_has_sagv static again(Ville)
- Removed unnecessary NULL assignments(Ville)
- Removed unnecessary SAGV debug(Ville)
- Call intel_compute_sagv_mask only for modesets(Ville)
- Serialize global state only if sagv results change, but
not mask itself(Ville)
v6: - use lock global state instead of serialize(Ville)
v7: - use both global state lock and serialize depending on
if we need to change only global state or access hw
(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 117 ++++++++++++++++++------
drivers/gpu/drm/i915/intel_pm.h | 3 +-
3 files changed, 97 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..d6df91058223 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_reject;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 338a82577b76..8d458cf0333d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
- if (!intel_can_enable_sagv(state))
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(new_bw_state))
intel_disable_sagv(dev_priv);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
- if (intel_can_enable_sagv(state))
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(new_bw_state))
intel_enable_sagv(dev_priv);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc_state->uapi.crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
int level, latency;
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
if (!crtc_state->hw.active)
return true;
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
@@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
latency = dev_priv->wm.skl_latency[level];
if (skl_needs_memory_bw_wa(dev_priv) &&
- plane->base.state->fb->modifier ==
+ plane_state->uapi.fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
@@ -3819,35 +3861,48 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return bw_state->pipe_sagv_reject == 0;
+}
+
+static int intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *crtc_state;
- enum pipe pipe;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_bw_state *new_bw_state = NULL;
+ const struct intel_bw_state *old_bw_state = NULL;
+ int i;
- if (!intel_has_sagv(dev_priv))
- return false;
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
+ old_bw_state = intel_atomic_get_old_bw_state(state);
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
+ if (intel_crtc_can_enable_sagv(new_crtc_state))
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ if (!new_bw_state)
+ return 0;
- return intel_crtc_can_enable_sagv(crtc_state);
+ if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
/*
@@ -5860,6 +5915,12 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
+ if (state->modeset) {
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
+ }
+
/*
* skl_compute_ddb() will have adjusted the final watermarks
* based on how much ddb is available. Now we can actually
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 9a6036ab0f90..fd1dc422e6c5 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -9,6 +9,7 @@
#include <linux/types.h>
#include "i915_reg.h"
+#include "display/intel_bw.h"
struct drm_device;
struct drm_i915_private;
@@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 1/9] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 2/9] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
@ 2020-04-23 7:58 ` Stanislav Lisovskiy
2020-04-30 9:21 ` Ville Syrjälä
` (2 more replies)
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 4/9] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
` (11 subsequent siblings)
14 siblings, 3 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:58 UTC (permalink / raw)
To: intel-gfx
We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index d6df91058223..898b4a85ccab 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -26,6 +26,9 @@ struct intel_bw_state {
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
+
+ /* bitmask of active pipes */
+ u8 active_pipes;
};
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e15cf3368ad..f7249bca3f6f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
+ bool active_pipes_calculated = false;
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
@@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!active_pipes_calculated) {
+ state->active_pipes = new_bw_state->active_pipes =
+ intel_calc_active_pipes(state, old_bw_state->active_pipes);
+ active_pipes_calculated = true;
+ }
+
if (intel_crtc_can_enable_sagv(new_crtc_state))
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
@@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
- if (state->modeset) {
- ret = intel_compute_sagv_mask(state);
- if (ret)
- return ret;
- }
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
/*
* skl_compute_ddb() will have adjusted the final watermarks
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state Stanislav Lisovskiy
@ 2020-04-30 9:21 ` Ville Syrjälä
2020-04-30 10:05 ` Lisovskiy, Stanislav
2020-04-30 19:20 ` Stanislav Lisovskiy
2020-04-30 19:56 ` Stanislav Lisovskiy
2 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 9:21 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> We need to calculate SAGV mask also in a non-modeset
> commit, however currently active_pipes are only calculated
> for modesets in global atomic state, thus now we will be
> tracking those also in bw_state in order to be able to
> properly access global data.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> 2 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index d6df91058223..898b4a85ccab 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -26,6 +26,9 @@ struct intel_bw_state {
>
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> +
> + /* bitmask of active pipes */
> + u8 active_pipes;
> };
>
> #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7e15cf3368ad..f7249bca3f6f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> struct intel_bw_state *new_bw_state = NULL;
> const struct intel_bw_state *old_bw_state = NULL;
> int i;
> + bool active_pipes_calculated = false;
>
> for_each_new_intel_crtc_in_state(state, crtc,
> new_crtc_state, i) {
> @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>
> old_bw_state = intel_atomic_get_old_bw_state(state);
>
> + if (!active_pipes_calculated) {
> + state->active_pipes = new_bw_state->active_pipes =
I don't think we should touch state->active_pipes here.
> + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> + active_pipes_calculated = true;
> + }
I'd do this after the loop so we don't need this extra boolean. As far
as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
can pull it out into intel_compute_sagv_mask() so that we do the check
after computing the mask. And of course change it to use
bw_state->active_pipes instead.
We're also going to need to lock_global_state() if bw_state->active_pipes
mask changes.
> +
> if (intel_crtc_can_enable_sagv(new_crtc_state))
> new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> else
> @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> - if (state->modeset) {
> - ret = intel_compute_sagv_mask(state);
> - if (ret)
> - return ret;
> - }
> + ret = intel_compute_sagv_mask(state);
> + if (ret)
> + return ret;
We also need to remove the state->modeset checks around
sagv_{pre,post}_update().
>
> /*
> * skl_compute_ddb() will have adjusted the final watermarks
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 9:21 ` Ville Syrjälä
@ 2020-04-30 10:05 ` Lisovskiy, Stanislav
2020-04-30 10:32 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 10:05 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > We need to calculate SAGV mask also in a non-modeset
> > commit, however currently active_pipes are only calculated
> > for modesets in global atomic state, thus now we will be
> > tracking those also in bw_state in order to be able to
> > properly access global data.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > 2 files changed, 13 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > index d6df91058223..898b4a85ccab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -26,6 +26,9 @@ struct intel_bw_state {
> >
> > unsigned int data_rate[I915_MAX_PIPES];
> > u8 num_active_planes[I915_MAX_PIPES];
> > +
> > + /* bitmask of active pipes */
> > + u8 active_pipes;
> > };
> >
> > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 7e15cf3368ad..f7249bca3f6f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > struct intel_bw_state *new_bw_state = NULL;
> > const struct intel_bw_state *old_bw_state = NULL;
> > int i;
> > + bool active_pipes_calculated = false;
> >
> > for_each_new_intel_crtc_in_state(state, crtc,
> > new_crtc_state, i) {
> > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> >
> > old_bw_state = intel_atomic_get_old_bw_state(state);
> >
> > + if (!active_pipes_calculated) {
> > + state->active_pipes = new_bw_state->active_pipes =
>
> I don't think we should touch state->active_pipes here.
Well, that was my question actually here as well. I understand that changing
state->active_pipes here feels like some unneeded side effect, however having
state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
very attractive to me either. That is why I don't like this idea of duplication
at all - having constant need to sync those state, bw_state, cdclk_state, because
they all might have different active_pipes now.
>
> > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > + active_pipes_calculated = true;
> > + }
>
> I'd do this after the loop so we don't need this extra boolean. As far
> as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> can pull it out into intel_compute_sagv_mask() so that we do the check
> after computing the mask. And of course change it to use
> bw_state->active_pipes instead.
intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
will have to have to cycles then - one will compute bw_state->active_pipes,
and another pipe_sagv_mask.
>
> We're also going to need to lock_global_state() if bw_state->active_pipes
> mask changes.
Ohh.. right.
Stan
>
> > +
> > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > else
> > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > - if (state->modeset) {
> > - ret = intel_compute_sagv_mask(state);
> > - if (ret)
> > - return ret;
> > - }
> > + ret = intel_compute_sagv_mask(state);
> > + if (ret)
> > + return ret;
>
> We also need to remove the state->modeset checks around
> sagv_{pre,post}_update().
>
> >
> > /*
> > * skl_compute_ddb() will have adjusted the final watermarks
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 10:05 ` Lisovskiy, Stanislav
@ 2020-04-30 10:32 ` Ville Syrjälä
2020-04-30 10:47 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 10:32 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > We need to calculate SAGV mask also in a non-modeset
> > > commit, however currently active_pipes are only calculated
> > > for modesets in global atomic state, thus now we will be
> > > tracking those also in bw_state in order to be able to
> > > properly access global data.
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > index d6df91058223..898b4a85ccab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > >
> > > unsigned int data_rate[I915_MAX_PIPES];
> > > u8 num_active_planes[I915_MAX_PIPES];
> > > +
> > > + /* bitmask of active pipes */
> > > + u8 active_pipes;
> > > };
> > >
> > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > struct intel_bw_state *new_bw_state = NULL;
> > > const struct intel_bw_state *old_bw_state = NULL;
> > > int i;
> > > + bool active_pipes_calculated = false;
> > >
> > > for_each_new_intel_crtc_in_state(state, crtc,
> > > new_crtc_state, i) {
> > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >
> > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > >
> > > + if (!active_pipes_calculated) {
> > > + state->active_pipes = new_bw_state->active_pipes =
> >
> > I don't think we should touch state->active_pipes here.
>
> Well, that was my question actually here as well. I understand that changing
> state->active_pipes here feels like some unneeded side effect, however having
> state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> very attractive to me either. That is why I don't like this idea of duplication
> at all - having constant need to sync those state, bw_state, cdclk_state, because
> they all might have different active_pipes now.
Having an out of date active_pipes anywhere would be a bug in that
specific code. Also state->active_pipes is definitely going the way of
the dodo soon.
>
> >
> > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > + active_pipes_calculated = true;
> > > + }
> >
> > I'd do this after the loop so we don't need this extra boolean. As far
> > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > can pull it out into intel_compute_sagv_mask() so that we do the check
> > after computing the mask. And of course change it to use
> > bw_state->active_pipes instead.
>
> intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> will have to have to cycles then - one will compute bw_state->active_pipes,
> and another pipe_sagv_mask.
Hmm. Actually I think what we should probably do is keep the
active_pipes check in intel_can_enable_sagv(). Ie something like this:
intel_can_enable_sagv(bw_state) {
if (active_pipes && !is_power_of_2(active_pipes))
return false;
return sagv_reject != 0;
}
compute_sagv() {
for_each_crtc() {
if (crtc_can_sagv())
sagv_reject &= ~pipe;
else
sagv_reject |= pipe;
}
active_pipes = calc_active_pipes();
... lock/serialize etc.
}
That way we don't have to update sagv_reject at all based on
active_pipes. I think that even makes more sense since the
active_pipes check is a global thing and not tied to any specific
crtc.
We can then make the check conditional on pre-icl (or whatever we want)
in a later patch. And finally we can remove it altogether in a separate
patch, since I don't think we should have to do it on any platform.
>
> >
> > We're also going to need to lock_global_state() if bw_state->active_pipes
> > mask changes.
>
> Ohh.. right.
>
>
> Stan
>
> >
> > > +
> > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > else
> > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > if (ret)
> > > return ret;
> > >
> > > - if (state->modeset) {
> > > - ret = intel_compute_sagv_mask(state);
> > > - if (ret)
> > > - return ret;
> > > - }
> > > + ret = intel_compute_sagv_mask(state);
> > > + if (ret)
> > > + return ret;
> >
> > We also need to remove the state->modeset checks around
> > sagv_{pre,post}_update().
> >
> > >
> > > /*
> > > * skl_compute_ddb() will have adjusted the final watermarks
> > > --
> > > 2.24.1.485.gad05a3d8e5
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 10:32 ` Ville Syrjälä
@ 2020-04-30 10:47 ` Lisovskiy, Stanislav
2020-04-30 10:55 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 10:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > We need to calculate SAGV mask also in a non-modeset
> > > > commit, however currently active_pipes are only calculated
> > > > for modesets in global atomic state, thus now we will be
> > > > tracking those also in bw_state in order to be able to
> > > > properly access global data.
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > index d6df91058223..898b4a85ccab 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > > >
> > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > +
> > > > + /* bitmask of active pipes */
> > > > + u8 active_pipes;
> > > > };
> > > >
> > > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > struct intel_bw_state *new_bw_state = NULL;
> > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > int i;
> > > > + bool active_pipes_calculated = false;
> > > >
> > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > new_crtc_state, i) {
> > > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > >
> > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > >
> > > > + if (!active_pipes_calculated) {
> > > > + state->active_pipes = new_bw_state->active_pipes =
> > >
> > > I don't think we should touch state->active_pipes here.
> >
> > Well, that was my question actually here as well. I understand that changing
> > state->active_pipes here feels like some unneeded side effect, however having
> > state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> > very attractive to me either. That is why I don't like this idea of duplication
> > at all - having constant need to sync those state, bw_state, cdclk_state, because
> > they all might have different active_pipes now.
>
> Having an out of date active_pipes anywhere would be a bug in that
> specific code. Also state->active_pipes is definitely going the way of
> the dodo soon.
>
> >
> > >
> > > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > > + active_pipes_calculated = true;
> > > > + }
> > >
> > > I'd do this after the loop so we don't need this extra boolean. As far
> > > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > > can pull it out into intel_compute_sagv_mask() so that we do the check
> > > after computing the mask. And of course change it to use
> > > bw_state->active_pipes instead.
> >
> > intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> > will have to have to cycles then - one will compute bw_state->active_pipes,
> > and another pipe_sagv_mask.
>
> Hmm. Actually I think what we should probably do is keep the
> active_pipes check in intel_can_enable_sagv(). Ie something like this:
>
> intel_can_enable_sagv(bw_state) {
> if (active_pipes && !is_power_of_2(active_pipes))
> return false;
> return sagv_reject != 0;
> }
I need active_pipes check here for skl code only, as it disables SAGV for multipipe
scenarios. Adding this here would generalize it for other platforms and we
don't want that for ICL+.
In fact that is the only reason I need active pipes here - otherwise I think
it was even your comment that we actually don't need those here at all,
as we just iterate through crtcs in state - pretty clearly remember we discussed
this. Just same way how it's done in intel bw check and other places.
Stan
>
> compute_sagv() {
> for_each_crtc() {
> if (crtc_can_sagv())
> sagv_reject &= ~pipe;
> else
> sagv_reject |= pipe;
> }
>
> active_pipes = calc_active_pipes();
>
> ... lock/serialize etc.
> }
>
> That way we don't have to update sagv_reject at all based on
> active_pipes. I think that even makes more sense since the
> active_pipes check is a global thing and not tied to any specific
> crtc.
>
> We can then make the check conditional on pre-icl (or whatever we want)
> in a later patch. And finally we can remove it altogether in a separate
> patch, since I don't think we should have to do it on any platform.
>
> >
> > >
> > > We're also going to need to lock_global_state() if bw_state->active_pipes
> > > mask changes.
> >
> > Ohh.. right.
> >
> >
> > Stan
> >
> > >
> > > > +
> > > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > else
> > > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > if (ret)
> > > > return ret;
> > > >
> > > > - if (state->modeset) {
> > > > - ret = intel_compute_sagv_mask(state);
> > > > - if (ret)
> > > > - return ret;
> > > > - }
> > > > + ret = intel_compute_sagv_mask(state);
> > > > + if (ret)
> > > > + return ret;
> > >
> > > We also need to remove the state->modeset checks around
> > > sagv_{pre,post}_update().
> > >
> > > >
> > > > /*
> > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > --
> > > > 2.24.1.485.gad05a3d8e5
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 10:47 ` Lisovskiy, Stanislav
@ 2020-04-30 10:55 ` Ville Syrjälä
2020-04-30 11:07 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 10:55 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > > We need to calculate SAGV mask also in a non-modeset
> > > > > commit, however currently active_pipes are only calculated
> > > > > for modesets in global atomic state, thus now we will be
> > > > > tracking those also in bw_state in order to be able to
> > > > > properly access global data.
> > > > >
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > index d6df91058223..898b4a85ccab 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > > > >
> > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > +
> > > > > + /* bitmask of active pipes */
> > > > > + u8 active_pipes;
> > > > > };
> > > > >
> > > > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > int i;
> > > > > + bool active_pipes_calculated = false;
> > > > >
> > > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > > new_crtc_state, i) {
> > > > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > >
> > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > >
> > > > > + if (!active_pipes_calculated) {
> > > > > + state->active_pipes = new_bw_state->active_pipes =
> > > >
> > > > I don't think we should touch state->active_pipes here.
> > >
> > > Well, that was my question actually here as well. I understand that changing
> > > state->active_pipes here feels like some unneeded side effect, however having
> > > state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> > > very attractive to me either. That is why I don't like this idea of duplication
> > > at all - having constant need to sync those state, bw_state, cdclk_state, because
> > > they all might have different active_pipes now.
> >
> > Having an out of date active_pipes anywhere would be a bug in that
> > specific code. Also state->active_pipes is definitely going the way of
> > the dodo soon.
> >
> > >
> > > >
> > > > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > > > + active_pipes_calculated = true;
> > > > > + }
> > > >
> > > > I'd do this after the loop so we don't need this extra boolean. As far
> > > > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > > > can pull it out into intel_compute_sagv_mask() so that we do the check
> > > > after computing the mask. And of course change it to use
> > > > bw_state->active_pipes instead.
> > >
> > > intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> > > will have to have to cycles then - one will compute bw_state->active_pipes,
> > > and another pipe_sagv_mask.
> >
> > Hmm. Actually I think what we should probably do is keep the
> > active_pipes check in intel_can_enable_sagv(). Ie something like this:
> >
> > intel_can_enable_sagv(bw_state) {
> > if (active_pipes && !is_power_of_2(active_pipes))
> > return false;
> > return sagv_reject != 0;
> > }
>
> I need active_pipes check here for skl code only, as it disables SAGV for multipipe
> scenarios. Adding this here would generalize it for other platforms and we
> don't want that for ICL+.
Which is why I said "We can then make the check conditional on pre-icl
(or whatever we want) in a later patch". Why in a later patch? Because
currently the check is unconditional and it's generally a good idea to
limit the number of functional changes per patch to a minimum.
>
> In fact that is the only reason I need active pipes here - otherwise I think
> it was even your comment that we actually don't need those here at all,
> as we just iterate through crtcs in state - pretty clearly remember we discussed
> this. Just same way how it's done in intel bw check and other places.
>
> Stan
>
> >
> > compute_sagv() {
> > for_each_crtc() {
> > if (crtc_can_sagv())
> > sagv_reject &= ~pipe;
> > else
> > sagv_reject |= pipe;
> > }
> >
> > active_pipes = calc_active_pipes();
> >
> > ... lock/serialize etc.
> > }
> >
> > That way we don't have to update sagv_reject at all based on
> > active_pipes. I think that even makes more sense since the
> > active_pipes check is a global thing and not tied to any specific
> > crtc.
> >
> > We can then make the check conditional on pre-icl (or whatever we want)
> > in a later patch. And finally we can remove it altogether in a separate
> > patch, since I don't think we should have to do it on any platform.
> >
> > >
> > > >
> > > > We're also going to need to lock_global_state() if bw_state->active_pipes
> > > > mask changes.
> > >
> > > Ohh.. right.
> > >
> > >
> > > Stan
> > >
> > > >
> > > > > +
> > > > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > else
> > > > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > - if (state->modeset) {
> > > > > - ret = intel_compute_sagv_mask(state);
> > > > > - if (ret)
> > > > > - return ret;
> > > > > - }
> > > > > + ret = intel_compute_sagv_mask(state);
> > > > > + if (ret)
> > > > > + return ret;
> > > >
> > > > We also need to remove the state->modeset checks around
> > > > sagv_{pre,post}_update().
> > > >
> > > > >
> > > > > /*
> > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > --
> > > > > 2.24.1.485.gad05a3d8e5
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 10:55 ` Ville Syrjälä
@ 2020-04-30 11:07 ` Lisovskiy, Stanislav
2020-04-30 11:22 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 11:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > > > We need to calculate SAGV mask also in a non-modeset
> > > > > > commit, however currently active_pipes are only calculated
> > > > > > for modesets in global atomic state, thus now we will be
> > > > > > tracking those also in bw_state in order to be able to
> > > > > > properly access global data.
> > > > > >
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > > > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > index d6df91058223..898b4a85ccab 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > > > > >
> > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > +
> > > > > > + /* bitmask of active pipes */
> > > > > > + u8 active_pipes;
> > > > > > };
> > > > > >
> > > > > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > > int i;
> > > > > > + bool active_pipes_calculated = false;
> > > > > >
> > > > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > new_crtc_state, i) {
> > > > > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > >
> > > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > >
> > > > > > + if (!active_pipes_calculated) {
> > > > > > + state->active_pipes = new_bw_state->active_pipes =
> > > > >
> > > > > I don't think we should touch state->active_pipes here.
> > > >
> > > > Well, that was my question actually here as well. I understand that changing
> > > > state->active_pipes here feels like some unneeded side effect, however having
> > > > state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> > > > very attractive to me either. That is why I don't like this idea of duplication
> > > > at all - having constant need to sync those state, bw_state, cdclk_state, because
> > > > they all might have different active_pipes now.
> > >
> > > Having an out of date active_pipes anywhere would be a bug in that
> > > specific code. Also state->active_pipes is definitely going the way of
> > > the dodo soon.
> > >
> > > >
> > > > >
> > > > > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > > > > + active_pipes_calculated = true;
> > > > > > + }
> > > > >
> > > > > I'd do this after the loop so we don't need this extra boolean. As far
> > > > > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > > > > can pull it out into intel_compute_sagv_mask() so that we do the check
> > > > > after computing the mask. And of course change it to use
> > > > > bw_state->active_pipes instead.
> > > >
> > > > intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> > > > will have to have to cycles then - one will compute bw_state->active_pipes,
> > > > and another pipe_sagv_mask.
> > >
> > > Hmm. Actually I think what we should probably do is keep the
> > > active_pipes check in intel_can_enable_sagv(). Ie something like this:
> > >
> > > intel_can_enable_sagv(bw_state) {
> > > if (active_pipes && !is_power_of_2(active_pipes))
> > > return false;
> > > return sagv_reject != 0;
> > > }
> >
> > I need active_pipes check here for skl code only, as it disables SAGV for multipipe
> > scenarios. Adding this here would generalize it for other platforms and we
> > don't want that for ICL+.
>
> Which is why I said "We can then make the check conditional on pre-icl
> (or whatever we want) in a later patch". Why in a later patch? Because
> currently the check is unconditional and it's generally a good idea to
> limit the number of functional changes per patch to a minimum.
Moving active_pipes check out of intel_crtc_can_enable_sagv will result
in wrong SAGV mask calculated.
i.e if you have 2 pipes,
for_each_crtc() {
if (crtc_can_sagv())
sagv_reject &= ~pipe;
else
sagv_reject |= pipe;
}
will calculate sagv_reject as 0 which is wrong and value will be stored
in global state. I think active_pipes should always affect the SAGV mask
otherwise we do get really strange situation: you have SAGV mask as 0,
but you still reject SAGV. So there is no way even then to track what
was the previous SAGV state - even if it's 0 it could have been rejected.
IMO that is quite weird side effect. So removing active_pipes from
intel_crtc_can_enable_sagv doesn't sound like good idea.
I think it is now just a bit too much hassle around simple
active_pipes_calculated boolean check.
Stan
>
> >
> > In fact that is the only reason I need active pipes here - otherwise I think
> > it was even your comment that we actually don't need those here at all,
> > as we just iterate through crtcs in state - pretty clearly remember we discussed
> > this. Just same way how it's done in intel bw check and other places.
> >
> > Stan
> >
> > >
> > > compute_sagv() {
> > > for_each_crtc() {
> > > if (crtc_can_sagv())
> > > sagv_reject &= ~pipe;
> > > else
> > > sagv_reject |= pipe;
> > > }
> > >
> > > active_pipes = calc_active_pipes();
> > >
> > > ... lock/serialize etc.
> > > }
> > >
> > > That way we don't have to update sagv_reject at all based on
> > > active_pipes. I think that even makes more sense since the
> > > active_pipes check is a global thing and not tied to any specific
> > > crtc.
> > >
> > > We can then make the check conditional on pre-icl (or whatever we want)
> > > in a later patch. And finally we can remove it altogether in a separate
> > > patch, since I don't think we should have to do it on any platform.
> > >
> > > >
> > > > >
> > > > > We're also going to need to lock_global_state() if bw_state->active_pipes
> > > > > mask changes.
> > > >
> > > > Ohh.. right.
> > > >
> > > >
> > > > Stan
> > > >
> > > > >
> > > > > > +
> > > > > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > else
> > > > > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > > if (ret)
> > > > > > return ret;
> > > > > >
> > > > > > - if (state->modeset) {
> > > > > > - ret = intel_compute_sagv_mask(state);
> > > > > > - if (ret)
> > > > > > - return ret;
> > > > > > - }
> > > > > > + ret = intel_compute_sagv_mask(state);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > >
> > > > > We also need to remove the state->modeset checks around
> > > > > sagv_{pre,post}_update().
> > > > >
> > > > > >
> > > > > > /*
> > > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > > --
> > > > > > 2.24.1.485.gad05a3d8e5
> > > > >
> > > > > --
> > > > > Ville Syrjälä
> > > > > Intel
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 11:07 ` Lisovskiy, Stanislav
@ 2020-04-30 11:22 ` Ville Syrjälä
2020-04-30 11:29 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 11:22 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > > > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > > > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > We need to calculate SAGV mask also in a non-modeset
> > > > > > > commit, however currently active_pipes are only calculated
> > > > > > > for modesets in global atomic state, thus now we will be
> > > > > > > tracking those also in bw_state in order to be able to
> > > > > > > properly access global data.
> > > > > > >
> > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > > > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > > > > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > index d6df91058223..898b4a85ccab 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > > > > > >
> > > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > > +
> > > > > > > + /* bitmask of active pipes */
> > > > > > > + u8 active_pipes;
> > > > > > > };
> > > > > > >
> > > > > > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > int i;
> > > > > > > + bool active_pipes_calculated = false;
> > > > > > >
> > > > > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > new_crtc_state, i) {
> > > > > > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > >
> > > > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > >
> > > > > > > + if (!active_pipes_calculated) {
> > > > > > > + state->active_pipes = new_bw_state->active_pipes =
> > > > > >
> > > > > > I don't think we should touch state->active_pipes here.
> > > > >
> > > > > Well, that was my question actually here as well. I understand that changing
> > > > > state->active_pipes here feels like some unneeded side effect, however having
> > > > > state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> > > > > very attractive to me either. That is why I don't like this idea of duplication
> > > > > at all - having constant need to sync those state, bw_state, cdclk_state, because
> > > > > they all might have different active_pipes now.
> > > >
> > > > Having an out of date active_pipes anywhere would be a bug in that
> > > > specific code. Also state->active_pipes is definitely going the way of
> > > > the dodo soon.
> > > >
> > > > >
> > > > > >
> > > > > > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > > > > > + active_pipes_calculated = true;
> > > > > > > + }
> > > > > >
> > > > > > I'd do this after the loop so we don't need this extra boolean. As far
> > > > > > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > > > > > can pull it out into intel_compute_sagv_mask() so that we do the check
> > > > > > after computing the mask. And of course change it to use
> > > > > > bw_state->active_pipes instead.
> > > > >
> > > > > intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> > > > > will have to have to cycles then - one will compute bw_state->active_pipes,
> > > > > and another pipe_sagv_mask.
> > > >
> > > > Hmm. Actually I think what we should probably do is keep the
> > > > active_pipes check in intel_can_enable_sagv(). Ie something like this:
> > > >
> > > > intel_can_enable_sagv(bw_state) {
> > > > if (active_pipes && !is_power_of_2(active_pipes))
> > > > return false;
> > > > return sagv_reject != 0;
> > > > }
> > >
> > > I need active_pipes check here for skl code only, as it disables SAGV for multipipe
> > > scenarios. Adding this here would generalize it for other platforms and we
> > > don't want that for ICL+.
> >
> > Which is why I said "We can then make the check conditional on pre-icl
> > (or whatever we want) in a later patch". Why in a later patch? Because
> > currently the check is unconditional and it's generally a good idea to
> > limit the number of functional changes per patch to a minimum.
>
> Moving active_pipes check out of intel_crtc_can_enable_sagv will result
> in wrong SAGV mask calculated.
>
> i.e if you have 2 pipes,
>
> for_each_crtc() {
> if (crtc_can_sagv())
> sagv_reject &= ~pipe;
> else
> sagv_reject |= pipe;
> }
>
> will calculate sagv_reject as 0 which is wrong and value will be stored
> in global state.
No, it accurately reflects whether each of those pipes is capable of
sagv. The single pipe restriction is an additinal constrain on top of
that. In fact I think adjusting sagv_reject_mask based on this would
result in the wrong value potentially. Consider for example:
1. Enable pipe A + B
2. sagv_reject would be calculated as 0x3
3. Disable pipe B
4. sagv_reject will have pipe B removed, leaving its value at 0x1
5. No SAGV even though we only have one pipe enabled, which is wrong
> I think active_pipes should always affect the SAGV mask
> otherwise we do get really strange situation: you have SAGV mask as 0,
> but you still reject SAGV. So there is no way even then to track what
> was the previous SAGV state - even if it's 0 it could have been rejected.
>
> IMO that is quite weird side effect. So removing active_pipes from
> intel_crtc_can_enable_sagv doesn't sound like good idea.
>
> I think it is now just a bit too much hassle around simple
> active_pipes_calculated boolean check.
>
> Stan
>
> >
> > >
> > > In fact that is the only reason I need active pipes here - otherwise I think
> > > it was even your comment that we actually don't need those here at all,
> > > as we just iterate through crtcs in state - pretty clearly remember we discussed
> > > this. Just same way how it's done in intel bw check and other places.
> > >
> > > Stan
> > >
> > > >
> > > > compute_sagv() {
> > > > for_each_crtc() {
> > > > if (crtc_can_sagv())
> > > > sagv_reject &= ~pipe;
> > > > else
> > > > sagv_reject |= pipe;
> > > > }
> > > >
> > > > active_pipes = calc_active_pipes();
> > > >
> > > > ... lock/serialize etc.
> > > > }
> > > >
> > > > That way we don't have to update sagv_reject at all based on
> > > > active_pipes. I think that even makes more sense since the
> > > > active_pipes check is a global thing and not tied to any specific
> > > > crtc.
> > > >
> > > > We can then make the check conditional on pre-icl (or whatever we want)
> > > > in a later patch. And finally we can remove it altogether in a separate
> > > > patch, since I don't think we should have to do it on any platform.
> > > >
> > > > >
> > > > > >
> > > > > > We're also going to need to lock_global_state() if bw_state->active_pipes
> > > > > > mask changes.
> > > > >
> > > > > Ohh.. right.
> > > > >
> > > > >
> > > > > Stan
> > > > >
> > > > > >
> > > > > > > +
> > > > > > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > else
> > > > > > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > > > if (ret)
> > > > > > > return ret;
> > > > > > >
> > > > > > > - if (state->modeset) {
> > > > > > > - ret = intel_compute_sagv_mask(state);
> > > > > > > - if (ret)
> > > > > > > - return ret;
> > > > > > > - }
> > > > > > > + ret = intel_compute_sagv_mask(state);
> > > > > > > + if (ret)
> > > > > > > + return ret;
> > > > > >
> > > > > > We also need to remove the state->modeset checks around
> > > > > > sagv_{pre,post}_update().
> > > > > >
> > > > > > >
> > > > > > > /*
> > > > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > > > --
> > > > > > > 2.24.1.485.gad05a3d8e5
> > > > > >
> > > > > > --
> > > > > > Ville Syrjälä
> > > > > > Intel
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 11:22 ` Ville Syrjälä
@ 2020-04-30 11:29 ` Lisovskiy, Stanislav
2020-04-30 11:40 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 11:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 02:22:02PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > > > > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > We need to calculate SAGV mask also in a non-modeset
> > > > > > > > commit, however currently active_pipes are only calculated
> > > > > > > > for modesets in global atomic state, thus now we will be
> > > > > > > > tracking those also in bw_state in order to be able to
> > > > > > > > properly access global data.
> > > > > > > >
> > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > > > > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > > > > > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > index d6df91058223..898b4a85ccab 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > > > > > > >
> > > > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > > > +
> > > > > > > > + /* bitmask of active pipes */
> > > > > > > > + u8 active_pipes;
> > > > > > > > };
> > > > > > > >
> > > > > > > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > > int i;
> > > > > > > > + bool active_pipes_calculated = false;
> > > > > > > >
> > > > > > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > new_crtc_state, i) {
> > > > > > > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > >
> > > > > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > > >
> > > > > > > > + if (!active_pipes_calculated) {
> > > > > > > > + state->active_pipes = new_bw_state->active_pipes =
> > > > > > >
> > > > > > > I don't think we should touch state->active_pipes here.
> > > > > >
> > > > > > Well, that was my question actually here as well. I understand that changing
> > > > > > state->active_pipes here feels like some unneeded side effect, however having
> > > > > > state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> > > > > > very attractive to me either. That is why I don't like this idea of duplication
> > > > > > at all - having constant need to sync those state, bw_state, cdclk_state, because
> > > > > > they all might have different active_pipes now.
> > > > >
> > > > > Having an out of date active_pipes anywhere would be a bug in that
> > > > > specific code. Also state->active_pipes is definitely going the way of
> > > > > the dodo soon.
> > > > >
> > > > > >
> > > > > > >
> > > > > > > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > > > > > > + active_pipes_calculated = true;
> > > > > > > > + }
> > > > > > >
> > > > > > > I'd do this after the loop so we don't need this extra boolean. As far
> > > > > > > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > > > > > > can pull it out into intel_compute_sagv_mask() so that we do the check
> > > > > > > after computing the mask. And of course change it to use
> > > > > > > bw_state->active_pipes instead.
> > > > > >
> > > > > > intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> > > > > > will have to have to cycles then - one will compute bw_state->active_pipes,
> > > > > > and another pipe_sagv_mask.
> > > > >
> > > > > Hmm. Actually I think what we should probably do is keep the
> > > > > active_pipes check in intel_can_enable_sagv(). Ie something like this:
> > > > >
> > > > > intel_can_enable_sagv(bw_state) {
> > > > > if (active_pipes && !is_power_of_2(active_pipes))
> > > > > return false;
> > > > > return sagv_reject != 0;
> > > > > }
> > > >
> > > > I need active_pipes check here for skl code only, as it disables SAGV for multipipe
> > > > scenarios. Adding this here would generalize it for other platforms and we
> > > > don't want that for ICL+.
> > >
> > > Which is why I said "We can then make the check conditional on pre-icl
> > > (or whatever we want) in a later patch". Why in a later patch? Because
> > > currently the check is unconditional and it's generally a good idea to
> > > limit the number of functional changes per patch to a minimum.
> >
> > Moving active_pipes check out of intel_crtc_can_enable_sagv will result
> > in wrong SAGV mask calculated.
> >
> > i.e if you have 2 pipes,
> >
> > for_each_crtc() {
> > if (crtc_can_sagv())
> > sagv_reject &= ~pipe;
> > else
> > sagv_reject |= pipe;
> > }
> >
> > will calculate sagv_reject as 0 which is wrong and value will be stored
> > in global state.
>
> No, it accurately reflects whether each of those pipes is capable of
> sagv. The single pipe restriction is an additinal constrain on top of
> that. In fact I think adjusting sagv_reject_mask based on this would
> result in the wrong value potentially. Consider for example:
>
> 1. Enable pipe A + B
> 2. sagv_reject would be calculated as 0x3
> 3. Disable pipe B
> 4. sagv_reject will have pipe B removed, leaving its value at 0x1
> 5. No SAGV even though we only have one pipe enabled, which is wrong
Quite good example. I think it means that pipe_sagv_mask should
be affected not only by per crtc checks, but also by overall active_pipes
state then. I.e ok, I remove active_pipes from intel_crtc_can_enable_sagv,
however that active_pipes && !is_power_of_2(active_pipes) check should
then also assign pipe_sagv_reject mask to ~0, if it evaluates to true.
I.e then we will always have intel_can_enable_sagv result reflected in
sagv mask, which is handy, also intel_can_enable_sagv would still
just evaluate sagv mask.
Stan
>
> > I think active_pipes should always affect the SAGV mask
> > otherwise we do get really strange situation: you have SAGV mask as 0,
> > but you still reject SAGV. So there is no way even then to track what
> > was the previous SAGV state - even if it's 0 it could have been rejected.
> >
> > IMO that is quite weird side effect. So removing active_pipes from
> > intel_crtc_can_enable_sagv doesn't sound like good idea.
> >
> > I think it is now just a bit too much hassle around simple
> > active_pipes_calculated boolean check.
> >
> > Stan
> >
> > >
> > > >
> > > > In fact that is the only reason I need active pipes here - otherwise I think
> > > > it was even your comment that we actually don't need those here at all,
> > > > as we just iterate through crtcs in state - pretty clearly remember we discussed
> > > > this. Just same way how it's done in intel bw check and other places.
> > > >
> > > > Stan
> > > >
> > > > >
> > > > > compute_sagv() {
> > > > > for_each_crtc() {
> > > > > if (crtc_can_sagv())
> > > > > sagv_reject &= ~pipe;
> > > > > else
> > > > > sagv_reject |= pipe;
> > > > > }
> > > > >
> > > > > active_pipes = calc_active_pipes();
> > > > >
> > > > > ... lock/serialize etc.
> > > > > }
> > > > >
> > > > > That way we don't have to update sagv_reject at all based on
> > > > > active_pipes. I think that even makes more sense since the
> > > > > active_pipes check is a global thing and not tied to any specific
> > > > > crtc.
> > > > >
> > > > > We can then make the check conditional on pre-icl (or whatever we want)
> > > > > in a later patch. And finally we can remove it altogether in a separate
> > > > > patch, since I don't think we should have to do it on any platform.
> > > > >
> > > > > >
> > > > > > >
> > > > > > > We're also going to need to lock_global_state() if bw_state->active_pipes
> > > > > > > mask changes.
> > > > > >
> > > > > > Ohh.. right.
> > > > > >
> > > > > >
> > > > > > Stan
> > > > > >
> > > > > > >
> > > > > > > > +
> > > > > > > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > > else
> > > > > > > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > > > > if (ret)
> > > > > > > > return ret;
> > > > > > > >
> > > > > > > > - if (state->modeset) {
> > > > > > > > - ret = intel_compute_sagv_mask(state);
> > > > > > > > - if (ret)
> > > > > > > > - return ret;
> > > > > > > > - }
> > > > > > > > + ret = intel_compute_sagv_mask(state);
> > > > > > > > + if (ret)
> > > > > > > > + return ret;
> > > > > > >
> > > > > > > We also need to remove the state->modeset checks around
> > > > > > > sagv_{pre,post}_update().
> > > > > > >
> > > > > > > >
> > > > > > > > /*
> > > > > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > > > > --
> > > > > > > > 2.24.1.485.gad05a3d8e5
> > > > > > >
> > > > > > > --
> > > > > > > Ville Syrjälä
> > > > > > > Intel
> > > > >
> > > > > --
> > > > > Ville Syrjälä
> > > > > Intel
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 11:29 ` Lisovskiy, Stanislav
@ 2020-04-30 11:40 ` Ville Syrjälä
2020-04-30 11:48 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2020-04-30 11:40 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 02:29:51PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 02:22:02PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > > > > On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > > > > > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > > > > > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > > We need to calculate SAGV mask also in a non-modeset
> > > > > > > > > commit, however currently active_pipes are only calculated
> > > > > > > > > for modesets in global atomic state, thus now we will be
> > > > > > > > > tracking those also in bw_state in order to be able to
> > > > > > > > > properly access global data.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > > > ---
> > > > > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > > > > > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > > > > > > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > > index d6df91058223..898b4a85ccab 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > > > > > > > >
> > > > > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > > > > +
> > > > > > > > > + /* bitmask of active pipes */
> > > > > > > > > + u8 active_pipes;
> > > > > > > > > };
> > > > > > > > >
> > > > > > > > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > > > int i;
> > > > > > > > > + bool active_pipes_calculated = false;
> > > > > > > > >
> > > > > > > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > > new_crtc_state, i) {
> > > > > > > > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > >
> > > > > > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > > > >
> > > > > > > > > + if (!active_pipes_calculated) {
> > > > > > > > > + state->active_pipes = new_bw_state->active_pipes =
> > > > > > > >
> > > > > > > > I don't think we should touch state->active_pipes here.
> > > > > > >
> > > > > > > Well, that was my question actually here as well. I understand that changing
> > > > > > > state->active_pipes here feels like some unneeded side effect, however having
> > > > > > > state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> > > > > > > very attractive to me either. That is why I don't like this idea of duplication
> > > > > > > at all - having constant need to sync those state, bw_state, cdclk_state, because
> > > > > > > they all might have different active_pipes now.
> > > > > >
> > > > > > Having an out of date active_pipes anywhere would be a bug in that
> > > > > > specific code. Also state->active_pipes is definitely going the way of
> > > > > > the dodo soon.
> > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > > > > > > > + active_pipes_calculated = true;
> > > > > > > > > + }
> > > > > > > >
> > > > > > > > I'd do this after the loop so we don't need this extra boolean. As far
> > > > > > > > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > > > > > > > can pull it out into intel_compute_sagv_mask() so that we do the check
> > > > > > > > after computing the mask. And of course change it to use
> > > > > > > > bw_state->active_pipes instead.
> > > > > > >
> > > > > > > intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> > > > > > > will have to have to cycles then - one will compute bw_state->active_pipes,
> > > > > > > and another pipe_sagv_mask.
> > > > > >
> > > > > > Hmm. Actually I think what we should probably do is keep the
> > > > > > active_pipes check in intel_can_enable_sagv(). Ie something like this:
> > > > > >
> > > > > > intel_can_enable_sagv(bw_state) {
> > > > > > if (active_pipes && !is_power_of_2(active_pipes))
> > > > > > return false;
> > > > > > return sagv_reject != 0;
> > > > > > }
> > > > >
> > > > > I need active_pipes check here for skl code only, as it disables SAGV for multipipe
> > > > > scenarios. Adding this here would generalize it for other platforms and we
> > > > > don't want that for ICL+.
> > > >
> > > > Which is why I said "We can then make the check conditional on pre-icl
> > > > (or whatever we want) in a later patch". Why in a later patch? Because
> > > > currently the check is unconditional and it's generally a good idea to
> > > > limit the number of functional changes per patch to a minimum.
> > >
> > > Moving active_pipes check out of intel_crtc_can_enable_sagv will result
> > > in wrong SAGV mask calculated.
> > >
> > > i.e if you have 2 pipes,
> > >
> > > for_each_crtc() {
> > > if (crtc_can_sagv())
> > > sagv_reject &= ~pipe;
> > > else
> > > sagv_reject |= pipe;
> > > }
> > >
> > > will calculate sagv_reject as 0 which is wrong and value will be stored
> > > in global state.
> >
> > No, it accurately reflects whether each of those pipes is capable of
> > sagv. The single pipe restriction is an additinal constrain on top of
> > that. In fact I think adjusting sagv_reject_mask based on this would
> > result in the wrong value potentially. Consider for example:
> >
> > 1. Enable pipe A + B
> > 2. sagv_reject would be calculated as 0x3
> > 3. Disable pipe B
> > 4. sagv_reject will have pipe B removed, leaving its value at 0x1
> > 5. No SAGV even though we only have one pipe enabled, which is wrong
>
> Quite good example. I think it means that pipe_sagv_mask should
> be affected not only by per crtc checks, but also by overall active_pipes
> state then. I.e ok, I remove active_pipes from intel_crtc_can_enable_sagv,
> however that active_pipes && !is_power_of_2(active_pipes) check should
> then also assign pipe_sagv_reject mask to ~0, if it evaluates to true.
That would clobber the bits of sagv_reject for all crtcs, not just
the ones part of the state currently. Ie. the very same example
I gave would still do the wrong thing.
>
> I.e then we will always have intel_can_enable_sagv result reflected in
> sagv mask, which is handy, also intel_can_enable_sagv would still
> just evaluate sagv mask.
>
> Stan
>
> >
> > > I think active_pipes should always affect the SAGV mask
> > > otherwise we do get really strange situation: you have SAGV mask as 0,
> > > but you still reject SAGV. So there is no way even then to track what
> > > was the previous SAGV state - even if it's 0 it could have been rejected.
> > >
> > > IMO that is quite weird side effect. So removing active_pipes from
> > > intel_crtc_can_enable_sagv doesn't sound like good idea.
> > >
> > > I think it is now just a bit too much hassle around simple
> > > active_pipes_calculated boolean check.
> > >
> > > Stan
> > >
> > > >
> > > > >
> > > > > In fact that is the only reason I need active pipes here - otherwise I think
> > > > > it was even your comment that we actually don't need those here at all,
> > > > > as we just iterate through crtcs in state - pretty clearly remember we discussed
> > > > > this. Just same way how it's done in intel bw check and other places.
> > > > >
> > > > > Stan
> > > > >
> > > > > >
> > > > > > compute_sagv() {
> > > > > > for_each_crtc() {
> > > > > > if (crtc_can_sagv())
> > > > > > sagv_reject &= ~pipe;
> > > > > > else
> > > > > > sagv_reject |= pipe;
> > > > > > }
> > > > > >
> > > > > > active_pipes = calc_active_pipes();
> > > > > >
> > > > > > ... lock/serialize etc.
> > > > > > }
> > > > > >
> > > > > > That way we don't have to update sagv_reject at all based on
> > > > > > active_pipes. I think that even makes more sense since the
> > > > > > active_pipes check is a global thing and not tied to any specific
> > > > > > crtc.
> > > > > >
> > > > > > We can then make the check conditional on pre-icl (or whatever we want)
> > > > > > in a later patch. And finally we can remove it altogether in a separate
> > > > > > patch, since I don't think we should have to do it on any platform.
> > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > We're also going to need to lock_global_state() if bw_state->active_pipes
> > > > > > > > mask changes.
> > > > > > >
> > > > > > > Ohh.. right.
> > > > > > >
> > > > > > >
> > > > > > > Stan
> > > > > > >
> > > > > > > >
> > > > > > > > > +
> > > > > > > > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > > > else
> > > > > > > > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > > > > > if (ret)
> > > > > > > > > return ret;
> > > > > > > > >
> > > > > > > > > - if (state->modeset) {
> > > > > > > > > - ret = intel_compute_sagv_mask(state);
> > > > > > > > > - if (ret)
> > > > > > > > > - return ret;
> > > > > > > > > - }
> > > > > > > > > + ret = intel_compute_sagv_mask(state);
> > > > > > > > > + if (ret)
> > > > > > > > > + return ret;
> > > > > > > >
> > > > > > > > We also need to remove the state->modeset checks around
> > > > > > > > sagv_{pre,post}_update().
> > > > > > > >
> > > > > > > > >
> > > > > > > > > /*
> > > > > > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > > > > > --
> > > > > > > > > 2.24.1.485.gad05a3d8e5
> > > > > > > >
> > > > > > > > --
> > > > > > > > Ville Syrjälä
> > > > > > > > Intel
> > > > > >
> > > > > > --
> > > > > > Ville Syrjälä
> > > > > > Intel
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
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^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-30 11:40 ` Ville Syrjälä
@ 2020-04-30 11:48 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-30 11:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Apr 30, 2020 at 02:40:37PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 02:29:51PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 02:22:02PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > > > > > > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > > > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > > > > > > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > > > We need to calculate SAGV mask also in a non-modeset
> > > > > > > > > > commit, however currently active_pipes are only calculated
> > > > > > > > > > for modesets in global atomic state, thus now we will be
> > > > > > > > > > tracking those also in bw_state in order to be able to
> > > > > > > > > > properly access global data.
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > > > > ---
> > > > > > > > > > drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
> > > > > > > > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > > > > > > > > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > > > index d6df91058223..898b4a85ccab 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > > > > > > > > @@ -26,6 +26,9 @@ struct intel_bw_state {
> > > > > > > > > >
> > > > > > > > > > unsigned int data_rate[I915_MAX_PIPES];
> > > > > > > > > > u8 num_active_planes[I915_MAX_PIPES];
> > > > > > > > > > +
> > > > > > > > > > + /* bitmask of active pipes */
> > > > > > > > > > + u8 active_pipes;
> > > > > > > > > > };
> > > > > > > > > >
> > > > > > > > > > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > index 7e15cf3368ad..f7249bca3f6f 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > @@ -3874,6 +3874,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > > > struct intel_bw_state *new_bw_state = NULL;
> > > > > > > > > > const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > > > > int i;
> > > > > > > > > > + bool active_pipes_calculated = false;
> > > > > > > > > >
> > > > > > > > > > for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > > > new_crtc_state, i) {
> > > > > > > > > > @@ -3883,6 +3884,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > > >
> > > > > > > > > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > > > > >
> > > > > > > > > > + if (!active_pipes_calculated) {
> > > > > > > > > > + state->active_pipes = new_bw_state->active_pipes =
> > > > > > > > >
> > > > > > > > > I don't think we should touch state->active_pipes here.
> > > > > > > >
> > > > > > > > Well, that was my question actually here as well. I understand that changing
> > > > > > > > state->active_pipes here feels like some unneeded side effect, however having
> > > > > > > > state->active_pipes and bw_state->active_pipes going out of sync doesn't sound
> > > > > > > > very attractive to me either. That is why I don't like this idea of duplication
> > > > > > > > at all - having constant need to sync those state, bw_state, cdclk_state, because
> > > > > > > > they all might have different active_pipes now.
> > > > > > >
> > > > > > > Having an out of date active_pipes anywhere would be a bug in that
> > > > > > > specific code. Also state->active_pipes is definitely going the way of
> > > > > > > the dodo soon.
> > > > > > >
> > > > > > > >
> > > > > > > > >
> > > > > > > > > > + intel_calc_active_pipes(state, old_bw_state->active_pipes);
> > > > > > > > > > + active_pipes_calculated = true;
> > > > > > > > > > + }
> > > > > > > > >
> > > > > > > > > I'd do this after the loop so we don't need this extra boolean. As far
> > > > > > > > > as the active_pipes check in intel_crtc_can_enable_sagv(), I think we
> > > > > > > > > can pull it out into intel_compute_sagv_mask() so that we do the check
> > > > > > > > > after computing the mask. And of course change it to use
> > > > > > > > > bw_state->active_pipes instead.
> > > > > > > >
> > > > > > > > intel_crtc_can_enable_sagv is called per crtc - so can't just pull it out,
> > > > > > > > will have to have to cycles then - one will compute bw_state->active_pipes,
> > > > > > > > and another pipe_sagv_mask.
> > > > > > >
> > > > > > > Hmm. Actually I think what we should probably do is keep the
> > > > > > > active_pipes check in intel_can_enable_sagv(). Ie something like this:
> > > > > > >
> > > > > > > intel_can_enable_sagv(bw_state) {
> > > > > > > if (active_pipes && !is_power_of_2(active_pipes))
> > > > > > > return false;
> > > > > > > return sagv_reject != 0;
> > > > > > > }
> > > > > >
> > > > > > I need active_pipes check here for skl code only, as it disables SAGV for multipipe
> > > > > > scenarios. Adding this here would generalize it for other platforms and we
> > > > > > don't want that for ICL+.
> > > > >
> > > > > Which is why I said "We can then make the check conditional on pre-icl
> > > > > (or whatever we want) in a later patch". Why in a later patch? Because
> > > > > currently the check is unconditional and it's generally a good idea to
> > > > > limit the number of functional changes per patch to a minimum.
> > > >
> > > > Moving active_pipes check out of intel_crtc_can_enable_sagv will result
> > > > in wrong SAGV mask calculated.
> > > >
> > > > i.e if you have 2 pipes,
> > > >
> > > > for_each_crtc() {
> > > > if (crtc_can_sagv())
> > > > sagv_reject &= ~pipe;
> > > > else
> > > > sagv_reject |= pipe;
> > > > }
> > > >
> > > > will calculate sagv_reject as 0 which is wrong and value will be stored
> > > > in global state.
> > >
> > > No, it accurately reflects whether each of those pipes is capable of
> > > sagv. The single pipe restriction is an additinal constrain on top of
> > > that. In fact I think adjusting sagv_reject_mask based on this would
> > > result in the wrong value potentially. Consider for example:
> > >
> > > 1. Enable pipe A + B
> > > 2. sagv_reject would be calculated as 0x3
> > > 3. Disable pipe B
> > > 4. sagv_reject will have pipe B removed, leaving its value at 0x1
> > > 5. No SAGV even though we only have one pipe enabled, which is wrong
> >
> > Quite good example. I think it means that pipe_sagv_mask should
> > be affected not only by per crtc checks, but also by overall active_pipes
> > state then. I.e ok, I remove active_pipes from intel_crtc_can_enable_sagv,
> > however that active_pipes && !is_power_of_2(active_pipes) check should
> > then also assign pipe_sagv_reject mask to ~0, if it evaluates to true.
>
> That would clobber the bits of sagv_reject for all crtcs, not just
> the ones part of the state currently. Ie. the very same example
> I gave would still do the wrong thing.
Sounds like we might want to reserve one bit from SAGV mask as "global
SAGV reject" flag, for non-crtc related checks.
I.e if we have active_pipes > 1 for skl, we just set sagv_mask |= 0x80
for instance - that will make your example work and also we will be storing
SAGV result in a single variable.
Stan
>
> >
> > I.e then we will always have intel_can_enable_sagv result reflected in
> > sagv mask, which is handy, also intel_can_enable_sagv would still
> > just evaluate sagv mask.
> >
> > Stan
> >
> > >
> > > > I think active_pipes should always affect the SAGV mask
> > > > otherwise we do get really strange situation: you have SAGV mask as 0,
> > > > but you still reject SAGV. So there is no way even then to track what
> > > > was the previous SAGV state - even if it's 0 it could have been rejected.
> > > >
> > > > IMO that is quite weird side effect. So removing active_pipes from
> > > > intel_crtc_can_enable_sagv doesn't sound like good idea.
> > > >
> > > > I think it is now just a bit too much hassle around simple
> > > > active_pipes_calculated boolean check.
> > > >
> > > > Stan
> > > >
> > > > >
> > > > > >
> > > > > > In fact that is the only reason I need active pipes here - otherwise I think
> > > > > > it was even your comment that we actually don't need those here at all,
> > > > > > as we just iterate through crtcs in state - pretty clearly remember we discussed
> > > > > > this. Just same way how it's done in intel bw check and other places.
> > > > > >
> > > > > > Stan
> > > > > >
> > > > > > >
> > > > > > > compute_sagv() {
> > > > > > > for_each_crtc() {
> > > > > > > if (crtc_can_sagv())
> > > > > > > sagv_reject &= ~pipe;
> > > > > > > else
> > > > > > > sagv_reject |= pipe;
> > > > > > > }
> > > > > > >
> > > > > > > active_pipes = calc_active_pipes();
> > > > > > >
> > > > > > > ... lock/serialize etc.
> > > > > > > }
> > > > > > >
> > > > > > > That way we don't have to update sagv_reject at all based on
> > > > > > > active_pipes. I think that even makes more sense since the
> > > > > > > active_pipes check is a global thing and not tied to any specific
> > > > > > > crtc.
> > > > > > >
> > > > > > > We can then make the check conditional on pre-icl (or whatever we want)
> > > > > > > in a later patch. And finally we can remove it altogether in a separate
> > > > > > > patch, since I don't think we should have to do it on any platform.
> > > > > > >
> > > > > > > >
> > > > > > > > >
> > > > > > > > > We're also going to need to lock_global_state() if bw_state->active_pipes
> > > > > > > > > mask changes.
> > > > > > > >
> > > > > > > > Ohh.. right.
> > > > > > > >
> > > > > > > >
> > > > > > > > Stan
> > > > > > > >
> > > > > > > > >
> > > > > > > > > > +
> > > > > > > > > > if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > > > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > > > > else
> > > > > > > > > > @@ -5911,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > > > > > > > > > if (ret)
> > > > > > > > > > return ret;
> > > > > > > > > >
> > > > > > > > > > - if (state->modeset) {
> > > > > > > > > > - ret = intel_compute_sagv_mask(state);
> > > > > > > > > > - if (ret)
> > > > > > > > > > - return ret;
> > > > > > > > > > - }
> > > > > > > > > > + ret = intel_compute_sagv_mask(state);
> > > > > > > > > > + if (ret)
> > > > > > > > > > + return ret;
> > > > > > > > >
> > > > > > > > > We also need to remove the state->modeset checks around
> > > > > > > > > sagv_{pre,post}_update().
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > /*
> > > > > > > > > > * skl_compute_ddb() will have adjusted the final watermarks
> > > > > > > > > > --
> > > > > > > > > > 2.24.1.485.gad05a3d8e5
> > > > > > > > >
> > > > > > > > > --
> > > > > > > > > Ville Syrjälä
> > > > > > > > > Intel
> > > > > > >
> > > > > > > --
> > > > > > > Ville Syrjälä
> > > > > > > Intel
> > > > >
> > > > > --
> > > > > Ville Syrjälä
> > > > > Intel
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state Stanislav Lisovskiy
2020-04-30 9:21 ` Ville Syrjälä
@ 2020-04-30 19:20 ` Stanislav Lisovskiy
2020-04-30 19:56 ` Stanislav Lisovskiy
2 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-30 19:20 UTC (permalink / raw)
To: intel-gfx
We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.
v2: - Removed pre/post plane SAGV updates from modeset(Ville)
- Now tracking active pipes in intel_can_enable_sagv(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
drivers/gpu/drm/i915/display/intel_display.c | 9 ++++----
drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++------------
3 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index d6df91058223..898b4a85ccab 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -26,6 +26,9 @@ struct intel_bw_state {
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
+
+ /* bitmask of active pipes */
+ u8 active_pipes;
};
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index adb08a00bb57..136826edaf49 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15365,11 +15365,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_set_cdclk_pre_plane_update(state);
- intel_sagv_pre_plane_update(state);
-
intel_modeset_verify_disabled(dev_priv, state);
}
+ intel_sagv_pre_plane_update(state);
+
/* Complete the events for pipes that have now been disabled */
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
bool modeset = needs_modeset(new_crtc_state);
@@ -15462,11 +15462,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_check_cpu_fifo_underruns(dev_priv);
intel_check_pch_fifo_underruns(dev_priv);
- if (state->modeset) {
+ if (state->modeset)
intel_verify_planes(state);
- intel_sagv_post_plane_update(state);
- }
+ intel_sagv_post_plane_update(state);
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8d458cf0333d..14689a2efb20 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3806,7 +3806,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
@@ -3819,13 +3818,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
@@ -3863,6 +3855,9 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
+ if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
+ return false;
+
return bw_state->pipe_sagv_reject == 0;
}
@@ -3892,6 +3887,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
if (!new_bw_state)
return 0;
+ new_bw_state->active_pipes =
+ intel_calc_active_pipes(state, old_bw_state->active_pipes);
+
if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
if (ret)
@@ -5915,11 +5913,9 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
- if (state->modeset) {
- ret = intel_compute_sagv_mask(state);
- if (ret)
- return ret;
- }
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
/*
* skl_compute_ddb() will have adjusted the final watermarks
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state Stanislav Lisovskiy
2020-04-30 9:21 ` Ville Syrjälä
2020-04-30 19:20 ` Stanislav Lisovskiy
@ 2020-04-30 19:56 ` Stanislav Lisovskiy
2 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-30 19:56 UTC (permalink / raw)
To: intel-gfx
We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.
v2: - Removed pre/post plane SAGV updates from modeset(Ville)
- Now tracking active pipes in intel_can_enable_sagv(Ville)
v3: - lock global state if active_pipes change as well(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 3 +++
drivers/gpu/drm/i915/display/intel_display.c | 9 +++----
drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++----------
3 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index d6df91058223..898b4a85ccab 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -26,6 +26,9 @@ struct intel_bw_state {
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
+
+ /* bitmask of active pipes */
+ u8 active_pipes;
};
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index adb08a00bb57..136826edaf49 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15365,11 +15365,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_set_cdclk_pre_plane_update(state);
- intel_sagv_pre_plane_update(state);
-
intel_modeset_verify_disabled(dev_priv, state);
}
+ intel_sagv_pre_plane_update(state);
+
/* Complete the events for pipes that have now been disabled */
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
bool modeset = needs_modeset(new_crtc_state);
@@ -15462,11 +15462,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_check_cpu_fifo_underruns(dev_priv);
intel_check_pch_fifo_underruns(dev_priv);
- if (state->modeset) {
+ if (state->modeset)
intel_verify_planes(state);
- intel_sagv_post_plane_update(state);
- }
+ intel_sagv_post_plane_update(state);
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8d458cf0333d..005549d0b778 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3806,7 +3806,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
@@ -3819,13 +3818,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
@@ -3863,6 +3855,9 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
+ if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
+ return false;
+
return bw_state->pipe_sagv_reject == 0;
}
@@ -3892,6 +3887,14 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
if (!new_bw_state)
return 0;
+ new_bw_state->active_pipes =
+ intel_calc_active_pipes(state, old_bw_state->active_pipes);
+ if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
if (ret)
@@ -5915,11 +5918,9 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
- if (state->modeset) {
- ret = intel_compute_sagv_mask(state);
- if (ret)
- return ret;
- }
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
/*
* skl_compute_ddb() will have adjusted the final watermarks
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 4/9] drm/i915: Separate icl and skl SAGV checking
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (2 preceding siblings ...)
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 3/9] drm/i915: Track active_pipes in bw_state Stanislav Lisovskiy
@ 2020-04-23 7:58 ` Stanislav Lisovskiy
2020-04-30 19:59 ` Stanislav Lisovskiy
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 5/9] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
` (10 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:58 UTC (permalink / raw)
To: intel-gfx
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3, v4, v5: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 38 ++++++++++++++++++++++++---------
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f7249bca3f6f..059bc312c9de 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3806,7 +3806,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
@@ -3819,13 +3818,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
@@ -3861,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
+static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
return bw_state->pipe_sagv_reject == 0;
@@ -3868,9 +3878,10 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
static int intel_compute_sagv_mask(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3878,6 +3889,8 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
+ bool can_sagv;
+
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
@@ -3890,7 +3903,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
active_pipes_calculated = true;
}
- if (intel_crtc_can_enable_sagv(new_crtc_state))
+ if (INTEL_GEN(dev_priv) >= 11)
+ can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
+ else
+ can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
+
+ if (can_sagv)
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Intel-gfx] [PATCH v26 4/9] drm/i915: Separate icl and skl SAGV checking
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 4/9] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
@ 2020-04-30 19:59 ` Stanislav Lisovskiy
0 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-30 19:59 UTC (permalink / raw)
To: intel-gfx
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3, v4, v5, v6: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 005549d0b778..700ec80c40fb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
+static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
@@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
static int intel_compute_sagv_mask(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
+ bool can_sagv;
+
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (intel_crtc_can_enable_sagv(new_crtc_state))
+ if (INTEL_GEN(dev_priv) >= 11)
+ can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
+ else
+ can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
+
+ if (can_sagv)
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 5/9] drm/i915: Add TGL+ SAGV support
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (3 preceding siblings ...)
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 4/9] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
@ 2020-04-23 7:58 ` Stanislav Lisovskiy
2020-04-30 20:00 ` Stanislav Lisovskiy
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands Stanislav Lisovskiy
` (9 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:58 UTC (permalink / raw)
To: intel-gfx
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
3 files changed, 130 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index adb08a00bb57..0380a42b1d41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13948,7 +13948,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
@@ -14003,7 +14005,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ba8c08145c88..23a425e565a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,11 +688,14 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 059bc312c9de..eeee4707d672 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
return intel_crtc_can_enable_sagv(crtc_state);
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
return bw_state->pipe_sagv_reject == 0;
@@ -3881,7 +3884,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3903,7 +3906,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
active_pipes_calculated = true;
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
else
can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
@@ -3917,6 +3922,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
if (!new_bw_state)
return 0;
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+ /*
+ * Due to drm limitation at commit state, when
+ * changes are written the whole atomic state is
+ * zeroed away => which prevents from using it,
+ * so just sticking it into pipe wm state for
+ * keeping it simple - anyway this is related to wm.
+ * Proper way in ideal universe would be of course not
+ * to lose parent atomic state object from child crtc_state,
+ * and stick to OOP programming principles, which had been
+ * scientifically proven to work.
+ */
+ pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
+ }
+
if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
ret = intel_atomic_lock_global_state(&new_bw_state->base);
if (ret)
@@ -4656,12 +4679,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
int level,
int color_plane)
{
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ if (!level) {
+ if (pipe_wm->can_sagv)
+ return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
+ }
return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum plane_id plane_id;
+
+ if (!crtc_state->hw.active)
+ return true;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *plane_alloc =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
+ return false;
+ }
+
+ return true;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5243,10 +5293,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
@@ -5260,6 +5317,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
+static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ const struct skl_wm_params *wm_params,
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct skl_wm_level *sagv_wm = color_plane == 1 ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
+
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
+}
+
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5340,7 +5431,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5362,7 +5454,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
return 0;
}
@@ -5747,6 +5840,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_l,
+ new_wm->sagv_wm0.plane_res_l);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5762,6 +5861,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
new_wm->trans_wm.plane_res_b);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_b,
+ new_wm->sagv_wm0.plane_res_b);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5776,6 +5881,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.min_ddb_alloc,
+ new_wm->sagv_wm0.min_ddb_alloc);
}
}
}
@@ -6068,6 +6179,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
skl_wm_level_from_reg_val(val, &wm->wm[level]);
}
+ memcpy(&wm->sagv_wm0, &wm->wm[0],
+ sizeof(struct skl_wm_level));
+
if (plane_id != PLANE_CURSOR)
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
else
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread* [Intel-gfx] [PATCH v26 5/9] drm/i915: Add TGL+ SAGV support
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 5/9] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
@ 2020-04-30 20:00 ` Stanislav Lisovskiy
0 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-30 20:00 UTC (permalink / raw)
To: intel-gfx
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5, v6: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
3 files changed, 130 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 136826edaf49..aeaa78f9fc18 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13948,7 +13948,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
@@ -14003,7 +14005,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ba8c08145c88..23a425e565a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,11 +688,14 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 700ec80c40fb..76fc852d4b96 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
return intel_crtc_can_enable_sagv(crtc_state);
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
@@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
else
can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
@@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
return ret;
}
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+ /*
+ * Due to drm limitation at commit state, when
+ * changes are written the whole atomic state is
+ * zeroed away => which prevents from using it,
+ * so just sticking it into pipe wm state for
+ * keeping it simple - anyway this is related to wm.
+ * Proper way in ideal universe would be of course not
+ * to lose parent atomic state object from child crtc_state,
+ * and stick to OOP programming principles, which had been
+ * scientifically proven to work.
+ */
+ pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
+ }
+
if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
if (ret)
@@ -4664,12 +4687,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
int level,
int color_plane)
{
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ if (!level) {
+ if (pipe_wm->can_sagv)
+ return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
+ }
return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum plane_id plane_id;
+
+ if (!crtc_state->hw.active)
+ return true;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *plane_alloc =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
+ return false;
+ }
+
+ return true;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5251,10 +5301,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
@@ -5268,6 +5325,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
+static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ const struct skl_wm_params *wm_params,
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct skl_wm_level *sagv_wm = color_plane == 1 ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
+
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
+}
+
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5348,7 +5439,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5370,7 +5462,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
return 0;
}
@@ -5755,6 +5848,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_l,
+ new_wm->sagv_wm0.plane_res_l);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5770,6 +5869,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
new_wm->trans_wm.plane_res_b);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_b,
+ new_wm->sagv_wm0.plane_res_b);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5784,6 +5889,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.min_ddb_alloc,
+ new_wm->sagv_wm0.min_ddb_alloc);
}
}
}
@@ -6076,6 +6187,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
skl_wm_level_from_reg_val(val, &wm->wm[level]);
}
+ memcpy(&wm->sagv_wm0, &wm->wm[0],
+ sizeof(struct skl_wm_level));
+
if (plane_id != PLANE_CURSOR)
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
else
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (4 preceding siblings ...)
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 5/9] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
@ 2020-04-23 7:58 ` Stanislav Lisovskiy
2020-05-04 16:12 ` Ville Syrjälä
2020-05-05 7:21 ` Stanislav Lisovskiy
2020-04-23 7:59 ` [Intel-gfx] [PATCH v26 7/9] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
` (8 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:58 UTC (permalink / raw)
To: intel-gfx
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a1965467374..5a077a921568 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9086,6 +9086,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9107,6 +9108,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define ICL_PCODE_EXIT_TCCOLD 0x12
@@ -9140,6 +9142,9 @@ enum {
#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
#define GEN8_LSLICESTAT_MASK 0x7
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
+
#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
#define CHV_SS_PG_ENABLE (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 14daf6af6854..59ef364549cf 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands Stanislav Lisovskiy
@ 2020-05-04 16:12 ` Ville Syrjälä
2020-05-05 7:21 ` Stanislav Lisovskiy
1 sibling, 0 replies; 42+ messages in thread
From: Ville Syrjälä @ 2020-05-04 16:12 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, Apr 23, 2020 at 10:58:59AM +0300, Stanislav Lisovskiy wrote:
> We need a new PCode request commands and reply codes
> to be added as a prepartion patch for QGV points
> restricting for new SAGV support.
>
> v2: - Extracted those changes into separate patch
> (Ville Syrjälä)
>
> v3: - Moved new PCode masks to another place from
> PCode commands(Ville)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_sideband.c | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4a1965467374..5a077a921568 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9086,6 +9086,7 @@ enum {
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
> #define GEN11_PCODE_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS 0x5
> @@ -9107,6 +9108,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> @@ -9140,6 +9142,9 @@ enum {
> #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
> #define GEN8_LSLICESTAT_MASK 0x7
>
> +#define GEN11_PCODE_POINTS_RESTRICTED 0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
These still look misplaced. They are things you specify to the
ICL_PCODE_SAGV_DE_MEM_SS_CONFIG command no?
In the meantime pushed patches 2,3,7. With those it looks like
we should finally have sensible sagv support for pre-icl. Yay!
> +
> #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
> #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
> #define CHV_SS_PG_ENABLE (1 << 1)
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 14daf6af6854..59ef364549cf 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
> return -ENXIO;
> case GEN11_PCODE_LOCKED:
> return -EBUSY;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> return -EOVERFLOW;
> default:
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 42+ messages in thread* [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-05-04 16:12 ` Ville Syrjälä
@ 2020-05-05 7:21 ` Stanislav Lisovskiy
1 sibling, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 7:21 UTC (permalink / raw)
To: intel-gfx
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
v4: - Moved new PCode masks to correspondent PCode
command, with identation(Ville)
- Changed naming to ICL_ instead of GEN11_
to fit more nicely into existing definition
style.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a1965467374..8118d1e39f6a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9086,6 +9086,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9107,6 +9108,9 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
+#define ICL_PCODE_POINTS_RESTRICTED 0x0
+#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define ICL_PCODE_EXIT_TCCOLD 0x12
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 14daf6af6854..59ef364549cf 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 7/9] drm/i915: Rename bw_state to new_bw_state
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (5 preceding siblings ...)
2020-04-23 7:58 ` [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands Stanislav Lisovskiy
@ 2020-04-23 7:59 ` Stanislav Lisovskiy
2020-04-23 7:59 ` [Intel-gfx] [PATCH v26 8/9] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
` (7 subsequent siblings)
14 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:59 UTC (permalink / raw)
To: intel-gfx
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
v2: Removed spurious space
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 4aa54fcb0629..6e7cc3a4f1aa 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -414,7 +414,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
+ struct intel_bw_state *new_bw_state = NULL;
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
@@ -443,29 +443,29 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(&dev_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(&bw_state->base);
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
if (ret)
return ret;
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread* [Intel-gfx] [PATCH v26 8/9] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (6 preceding siblings ...)
2020-04-23 7:59 ` [Intel-gfx] [PATCH v26 7/9] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
@ 2020-04-23 7:59 ` Stanislav Lisovskiy
2020-05-05 7:23 ` Stanislav Lisovskiy
2020-04-23 7:59 ` [Intel-gfx] [PATCH v26 9/9] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
` (6 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:59 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
v11: - Remove unneeded headers and spaces(Matthew Roper)
- Remove unneeded intel_qgv_info qi struct from bw check and zero
out the needed one(Matthew Roper)
- Changed QGV error message to have more clear meaning(Matthew Roper)
- Use state->modeset_set instead of any_ms(Matthew Roper)
- Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
- Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
- Moved unrelated changes to other patch(using latency as parameter
for plane wm calculation, moved to SAGV refactoring patch)
v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
- Remove unnecessary mask being zero check when unmasking
qgv points as this is completely legal(Matt Roper)
- Check if we are setting the same mask as already being set
in hardware to prevent error from PCode.
- Fix error message when restricting/unrestricting qgv points
to "mask/unmask" which sounds more accurate(Matt Roper)
- Move sagv status setting to icl_get_bw_info from atomic check
as this should be calculated only once.(Matt Roper)
- Edited comments for the case when we can't enable SAGV and
use only 1 QGV point with highest bandwidth to be more
understandable.(Matt Roper)
v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
- Changed comment for zero new_mask in qgv points masking function
to better reflect reality(Ville Syrjälä)
- Simplified bit mask operation in qgv points masking function
(Ville Syrjälä)
- Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
however this still can't be under modeset condition(Ville Syrjälä)
- Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
(Ville Syrjälä)
- Extracted PCode changes to separate patch.(Ville Syrjälä)
- Now treat num_planes 0 same as 1 to avoid confusion and
returning max_bw as 0, which would prevent choosing QGV
point having max bandwidth in case if SAGV is not allowed,
as per BSpec(Ville Syrjälä)
- Do the actual qgv_points_mask swap in the same place as
all other global state parts like cdclk are swapped.
In the next patch, this all will be moved to bw state as
global state, once new global state patch series from Ville
lands
v14: - Now using global state to serialize access to qgv points
- Added global state locking back, otherwise we seem to read
bw state in a wrong way.
v15: - Added TODO comment for near atomic global state locking in
bw code.
v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
with Jani Nikula.
- Take bw_state_changed flag into use.
v17: - Moved qgv point related manipulations next to SAGV code, as
those are semantically related(Ville Syrjälä)
- Renamed those into intel_sagv_(pre)|(post)_plane_update
(Ville Syrjälä)
v18: - Move sagv related calls from commit tail into
intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)
v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
for commit tail stage.
v20: - Return max bandwidth for 0 planes(Ville)
- Constify old_bw_state in bw_atomic_check(Ville)
- Removed some debugs(Ville)
- Added data rate to debug print when no QGV points(Ville)
- Removed some comments(Ville)
v21, v22, v23: - Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 139 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_bw.h | 9 ++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 66 ++++++++-
drivers/gpu/drm/i915/intel_pm.h | 2 +
5 files changed, 181 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..f7c04f07b7cf 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
break;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
return 0;
}
@@ -248,6 +281,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
{
int i;
+ /*
+ * Let's return max bw for 0 planes
+ */
+ num_planes = max(1, num_planes);
+
for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
const struct intel_bw_info *bi =
&dev_priv->max_bw[i];
@@ -277,34 +315,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11) {
- /*
- * Any bw group has same amount of QGV points
- */
- const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
- unsigned int min_bw = UINT_MAX;
- int i;
-
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- for (i = 0; i < bi->num_qgv_points; i++) {
- unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
- min_bw = min(bw, min_bw);
- }
- return min_bw;
- } else {
- return UINT_MAX;
- }
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -415,10 +425,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
- unsigned int data_rate, max_data_rate;
+ const struct intel_bw_state *old_bw_state = NULL;
+ unsigned int data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -465,19 +480,73 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
return ret;
data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+
num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
- data_rate = DIV_ROUND_UP(data_rate, 1000);
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= BIT(i);
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
- if (data_rate > max_data_rate) {
- drm_dbg_kms(&dev_priv->drm,
- "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+ " bandwidth %d for display configuration.\n", data_rate);
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv(new_bw_state)) {
+ allowed_points = BIT(max_bw_point);
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return -EINVAL;
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 898b4a85ccab..bbcaaa73ec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,13 @@ struct intel_bw_state {
*/
u8 pipe_sagv_reject;
+ /*
+ * Current QGV points mask, which restricts
+ * some particular SAGV states, not to confuse
+ * with pipe_sagv_mask.
+ */
+ u8 qgv_points_mask;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
@@ -47,5 +54,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 23a425e565a8..92db9b0ab381 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -693,6 +693,9 @@ struct skl_plane_wm {
bool is_planar;
};
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
bool can_sagv;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eeee4707d672..479f26bf6c48 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,7 +3761,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
@@ -3777,15 +3780,48 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (!intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(new_bw_state)) {
intel_disable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to mask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+ /*
+ * If new mask is zero - means there is nothing to mask,
+ * we can only unmask, which should be done in unmask.
+ */
+ if (!new_mask)
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not mask required qgv points(%d)\n", ret);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
-
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
@@ -3800,8 +3836,32 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(new_bw_state)) {
intel_enable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to unmask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = new_bw_state->qgv_points_mask;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not unmask required qgv points(%d)\n", ret);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index fd1dc422e6c5..4ae91ad5d5b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,6 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 42+ messages in thread* [Intel-gfx] [PATCH v26 8/9] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-04-23 7:59 ` [Intel-gfx] [PATCH v26 8/9] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-05-05 7:23 ` Stanislav Lisovskiy
0 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-05 7:23 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
v11: - Remove unneeded headers and spaces(Matthew Roper)
- Remove unneeded intel_qgv_info qi struct from bw check and zero
out the needed one(Matthew Roper)
- Changed QGV error message to have more clear meaning(Matthew Roper)
- Use state->modeset_set instead of any_ms(Matthew Roper)
- Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
- Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
- Moved unrelated changes to other patch(using latency as parameter
for plane wm calculation, moved to SAGV refactoring patch)
v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
- Remove unnecessary mask being zero check when unmasking
qgv points as this is completely legal(Matt Roper)
- Check if we are setting the same mask as already being set
in hardware to prevent error from PCode.
- Fix error message when restricting/unrestricting qgv points
to "mask/unmask" which sounds more accurate(Matt Roper)
- Move sagv status setting to icl_get_bw_info from atomic check
as this should be calculated only once.(Matt Roper)
- Edited comments for the case when we can't enable SAGV and
use only 1 QGV point with highest bandwidth to be more
understandable.(Matt Roper)
v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
- Changed comment for zero new_mask in qgv points masking function
to better reflect reality(Ville Syrjälä)
- Simplified bit mask operation in qgv points masking function
(Ville Syrjälä)
- Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
however this still can't be under modeset condition(Ville Syrjälä)
- Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
(Ville Syrjälä)
- Extracted PCode changes to separate patch.(Ville Syrjälä)
- Now treat num_planes 0 same as 1 to avoid confusion and
returning max_bw as 0, which would prevent choosing QGV
point having max bandwidth in case if SAGV is not allowed,
as per BSpec(Ville Syrjälä)
- Do the actual qgv_points_mask swap in the same place as
all other global state parts like cdclk are swapped.
In the next patch, this all will be moved to bw state as
global state, once new global state patch series from Ville
lands
v14: - Now using global state to serialize access to qgv points
- Added global state locking back, otherwise we seem to read
bw state in a wrong way.
v15: - Added TODO comment for near atomic global state locking in
bw code.
v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
with Jani Nikula.
- Take bw_state_changed flag into use.
v17: - Moved qgv point related manipulations next to SAGV code, as
those are semantically related(Ville Syrjälä)
- Renamed those into intel_sagv_(pre)|(post)_plane_update
(Ville Syrjälä)
v18: - Move sagv related calls from commit tail into
intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)
v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
for commit tail stage.
v20: - Return max bandwidth for 0 planes(Ville)
- Constify old_bw_state in bw_atomic_check(Ville)
- Removed some debugs(Ville)
- Added data rate to debug print when no QGV points(Ville)
- Removed some comments(Ville)
v21, v22, v23: - Fixed rebase conflict
v24: - Changed PCode mask to use ICL_ prefix
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 139 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_bw.h | 9 ++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 66 ++++++++-
drivers/gpu/drm/i915/intel_pm.h | 2 +
5 files changed, 181 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..a192fd02c463 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ ICL_PCODE_POINTS_RESTRICTED_MASK,
+ ICL_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
break;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
return 0;
}
@@ -248,6 +281,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
{
int i;
+ /*
+ * Let's return max bw for 0 planes
+ */
+ num_planes = max(1, num_planes);
+
for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
const struct intel_bw_info *bi =
&dev_priv->max_bw[i];
@@ -277,34 +315,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11) {
- /*
- * Any bw group has same amount of QGV points
- */
- const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
- unsigned int min_bw = UINT_MAX;
- int i;
-
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- for (i = 0; i < bi->num_qgv_points; i++) {
- unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
- min_bw = min(bw, min_bw);
- }
- return min_bw;
- } else {
- return UINT_MAX;
- }
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -415,10 +425,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
- unsigned int data_rate, max_data_rate;
+ const struct intel_bw_state *old_bw_state = NULL;
+ unsigned int data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -465,19 +480,73 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
return ret;
data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+
num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
- data_rate = DIV_ROUND_UP(data_rate, 1000);
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= BIT(i);
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
- if (data_rate > max_data_rate) {
- drm_dbg_kms(&dev_priv->drm,
- "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+ " bandwidth %d for display configuration.\n", data_rate);
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv(new_bw_state)) {
+ allowed_points = BIT(max_bw_point);
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return -EINVAL;
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 898b4a85ccab..bbcaaa73ec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,13 @@ struct intel_bw_state {
*/
u8 pipe_sagv_reject;
+ /*
+ * Current QGV points mask, which restricts
+ * some particular SAGV states, not to confuse
+ * with pipe_sagv_mask.
+ */
+ u8 qgv_points_mask;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
@@ -47,5 +54,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 23a425e565a8..92db9b0ab381 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -693,6 +693,9 @@ struct skl_plane_wm {
bool is_planar;
};
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
bool can_sagv;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 76fc852d4b96..ed378416d553 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,7 +3761,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
@@ -3777,15 +3780,48 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (!intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(new_bw_state)) {
intel_disable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to mask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+ /*
+ * If new mask is zero - means there is nothing to mask,
+ * we can only unmask, which should be done in unmask.
+ */
+ if (!new_mask)
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not mask required qgv points(%d)\n", ret);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
-
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
@@ -3800,8 +3836,32 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(new_bw_state)) {
intel_enable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to unmask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = new_bw_state->qgv_points_mask;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not unmask required qgv points(%d)\n", ret);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index fd1dc422e6c5..4ae91ad5d5b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,6 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v26 9/9] drm/i915: Enable SAGV support for Gen12
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (7 preceding siblings ...)
2020-04-23 7:59 ` [Intel-gfx] [PATCH v26 8/9] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-04-23 7:59 ` Stanislav Lisovskiy
2020-04-23 9:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev27) Patchwork
` (5 subsequent siblings)
14 siblings, 0 replies; 42+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-23 7:59 UTC (permalink / raw)
To: intel-gfx
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 479f26bf6c48..d03164ba98b6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev27)
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (8 preceding siblings ...)
2020-04-23 7:59 ` [Intel-gfx] [PATCH v26 9/9] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
@ 2020-04-23 9:06 ` Patchwork
2020-04-23 9:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
14 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2020-04-23 9:06 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev27)
URL : https://patchwork.freedesktop.org/series/75129/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f963df93cc7d drm/i915: Introduce skl_plane_wm_level accessor.
75ab029a2591 drm/i915: Use bw state for per crtc SAGV evaluation
b0cc5c6eec63 drm/i915: Track active_pipes in bw_state
-:45: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#45: FILE: drivers/gpu/drm/i915/intel_pm.c:3888:
+ state->active_pipes = new_bw_state->active_pipes =
total: 0 errors, 0 warnings, 1 checks, 42 lines checked
38d87c8a7846 drm/i915: Separate icl and skl SAGV checking
44aab96e8376 drm/i915: Add TGL+ SAGV support
2eadba427c66 drm/i915: Added required new PCode commands
a7b5caac439f drm/i915: Rename bw_state to new_bw_state
c8050b966b6e drm/i915: Restrict qgv points which don't have enough bandwidth.
f1e652ab8841 drm/i915: Enable SAGV support for Gen12
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev27)
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (9 preceding siblings ...)
2020-04-23 9:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev27) Patchwork
@ 2020-04-23 9:30 ` Patchwork
2020-04-23 11:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2020-04-23 9:30 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev27)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8350 -> Patchwork_17434
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/index.html
Known issues
------------
Here are the changes found in Patchwork_17434 that come from known issues:
### IGT changes ###
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [SKIP][2] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Participating hosts (48 -> 44)
------------------------------
Additional (1): fi-icl-dsi
Missing (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8350 -> Patchwork_17434
CI-20190529: 20190529
CI_DRM_8350: 018bab6d1c4ac37bff9306384383fab59750e140 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5606: 678afb3954bec6227c8762756a0ad6d9946d49b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17434: f1e652ab88416c2f154b474bce71a23d4e3ae3ee @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f1e652ab8841 drm/i915: Enable SAGV support for Gen12
c8050b966b6e drm/i915: Restrict qgv points which don't have enough bandwidth.
a7b5caac439f drm/i915: Rename bw_state to new_bw_state
2eadba427c66 drm/i915: Added required new PCode commands
44aab96e8376 drm/i915: Add TGL+ SAGV support
38d87c8a7846 drm/i915: Separate icl and skl SAGV checking
b0cc5c6eec63 drm/i915: Track active_pipes in bw_state
75ab029a2591 drm/i915: Use bw state for per crtc SAGV evaluation
f963df93cc7d drm/i915: Introduce skl_plane_wm_level accessor.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev27)
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (10 preceding siblings ...)
2020-04-23 9:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-23 11:29 ` Patchwork
2020-04-30 22:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev32) Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2020-04-23 11:29 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev27)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8350_full -> Patchwork_17434_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17434_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#1528])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-tglb6/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-tglb8/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#69])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-skl1/igt@gem_workarounds@suspend-resume-context.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-skl2/igt@gem_workarounds@suspend-resume-context.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#454])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live@requests:
- shard-snb: [PASS][9] -> [FAIL][10] ([i915#1763])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-snb1/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-snb5/igt@i915_selftest@live@requests.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642] / [fdo#111068])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [INCOMPLETE][19] ([i915#155]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-kbl2/igt@gem_softpin@noreloc-s3.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-kbl7/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [INCOMPLETE][21] ([i915#151] / [i915#69]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-skl10/igt@i915_pm_rpm@system-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-skl2/igt@i915_pm_rpm@system-suspend.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1}:
- shard-skl: [FAIL][23] ([i915#46]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1}:
- shard-skl: [FAIL][25] ([i915#79]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* {igt@kms_flip@flip-vs-suspend-interruptible@a-dp1}:
- shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +6 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* {igt@kms_flip@flip-vs-suspend-interruptible@b-edp1}:
- shard-skl: [INCOMPLETE][29] ([i915#198]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][31] ([fdo#108145] / [i915#265]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][33] ([fdo#109441]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* {igt@perf@polling-small-buf}:
- shard-iclb: [FAIL][35] ([i915#1722]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-iclb2/igt@perf@polling-small-buf.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-iclb5/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][37] ([fdo#109642] / [fdo#111068]) -> [FAIL][38] ([i915#608])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8350/shard-iclb5/igt@kms_psr2_su@page_flip.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/shard-iclb2/igt@kms_psr2_su@page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1763]: https://gitlab.freedesktop.org/drm/intel/issues/1763
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
[i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8350 -> Patchwork_17434
CI-20190529: 20190529
CI_DRM_8350: 018bab6d1c4ac37bff9306384383fab59750e140 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5606: 678afb3954bec6227c8762756a0ad6d9946d49b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17434: f1e652ab88416c2f154b474bce71a23d4e3ae3ee @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17434/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev32)
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (11 preceding siblings ...)
2020-04-23 11:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-04-30 22:07 ` Patchwork
2020-05-01 5:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-05-05 8:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev34) Patchwork
14 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2020-04-30 22:07 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev32)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8403 -> Patchwork_17531
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/index.html
Known issues
------------
Here are the changes found in Patchwork_17531 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@sanitycheck:
- fi-bwr-2160: [PASS][1] -> [INCOMPLETE][2] ([i915#489])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/fi-bwr-2160/igt@i915_selftest@live@sanitycheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/fi-bwr-2160/igt@i915_selftest@live@sanitycheck.html
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
Participating hosts (51 -> 43)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-8809g fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8403 -> Patchwork_17531
CI-20190529: 20190529
CI_DRM_8403: 09978e99929f6e5acfe1e959f6499a134f210887 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5619: 94de923ca8d4cc8f532b8062d87aaad9da6ef956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17531: d476c016bc161fca38b14532185fe96d7cab1e04 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d476c016bc16 drm/i915: Enable SAGV support for Gen12
d4948b0fe076 drm/i915: Restrict qgv points which don't have enough bandwidth.
41c561f0dc26 drm/i915: Rename bw_state to new_bw_state
ce75f7bbf7e7 drm/i915: Added required new PCode commands
f2b4f78b7f22 drm/i915: Add TGL+ SAGV support
0cbc47e3c84c drm/i915: Separate icl and skl SAGV checking
c9d261232770 drm/i915: Track active_pipes in bw_state
9942ef866255 drm/i915: Use bw state for per crtc SAGV evaluation
bca922b59afd drm/i915: Introduce skl_plane_wm_level accessor.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev32)
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (12 preceding siblings ...)
2020-04-30 22:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev32) Patchwork
@ 2020-05-01 5:52 ` Patchwork
2020-05-05 8:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev34) Patchwork
14 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2020-05-01 5:52 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev32)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8403_full -> Patchwork_17531_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17531_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@allowed-all:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-kbl7/igt@gen9_exec_parse@allowed-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-kbl7/igt@gen9_exec_parse@allowed-all.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#52] / [i915#54])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-skl2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-skl10/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#1188])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Possible fixes ####
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-glk: [FAIL][17] ([i915#72]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-glk5/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-hsw: [FAIL][19] ([IGT#5]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-hsw1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-hsw7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][21] ([i915#180]) -> [PASS][22] +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* {igt@kms_flip@flip-vs-suspend@a-dp1}:
- shard-kbl: [INCOMPLETE][23] ([i915#155]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-kbl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][25] ([i915#1188]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-skl5/igt@kms_hdr@bpc-switch.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-skl6/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [FAIL][27] ([i915#899]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-glk6/igt@kms_plane_lowres@pipe-a-tiling-x.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][29] ([fdo#109441]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-iclb8/igt@kms_psr@psr2_basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][33] ([i915#658]) -> [SKIP][34] ([i915#588])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [SKIP][35] ([i915#468]) -> [FAIL][36] ([i915#454]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [DMESG-FAIL][37] ([i915#180] / [i915#95]) -> [FAIL][38] ([i915#93] / [i915#95])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: [FAIL][39] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][40] ([fdo#108145] / [i915#265])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][41] ([i915#31]) -> [FAIL][42] ([i915#31] / [i915#95])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8403/shard-apl8/igt@kms_setmode@basic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/shard-apl7/igt@kms_setmode@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8403 -> Patchwork_17531
CI-20190529: 20190529
CI_DRM_8403: 09978e99929f6e5acfe1e959f6499a134f210887 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5619: 94de923ca8d4cc8f532b8062d87aaad9da6ef956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17531: d476c016bc161fca38b14532185fe96d7cab1e04 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17531/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev34)
2020-04-23 7:58 [Intel-gfx] [PATCH v26 0/9] SAGV support for Gen12+ Stanislav Lisovskiy
` (13 preceding siblings ...)
2020-05-01 5:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-05-05 8:11 ` Patchwork
2020-05-05 8:51 ` Lisovskiy, Stanislav
14 siblings, 1 reply; 42+ messages in thread
From: Patchwork @ 2020-05-05 8:11 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev34)
URL : https://patchwork.freedesktop.org/series/75129/
State : failure
== Summary ==
Applying: drm/i915: Introduce skl_plane_wm_level accessor.
Applying: drm/i915: Use bw state for per crtc SAGV evaluation
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_bw.h
M drivers/gpu/drm/i915/intel_pm.c
M drivers/gpu/drm/i915/intel_pm.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_pm.c
Auto-merging drivers/gpu/drm/i915/display/intel_bw.h
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915: Use bw state for per crtc SAGV evaluation
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev34)
2020-05-05 8:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev34) Patchwork
@ 2020-05-05 8:51 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 42+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-05 8:51 UTC (permalink / raw)
To: intel-gfx, Saarinen, Jani
As patches 2,3,7 were pushed - can't now send particular patches, because it fails to apply
same patch twice.
So will _have to_ resend the whole series again.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Tuesday, May 5, 2020 11:11:06 AM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev34)
== Series Details ==
Series: SAGV support for Gen12+ (rev34)
URL : https://patchwork.freedesktop.org/series/75129/
State : failure
== Summary ==
Applying: drm/i915: Introduce skl_plane_wm_level accessor.
Applying: drm/i915: Use bw state for per crtc SAGV evaluation
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_bw.h
M drivers/gpu/drm/i915/intel_pm.c
M drivers/gpu/drm/i915/intel_pm.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_pm.c
Auto-merging drivers/gpu/drm/i915/display/intel_bw.h
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915: Use bw state for per crtc SAGV evaluation
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread