* [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation
@ 2020-04-23 10:15 Chris Wilson
2020-04-23 10:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev3) Patchwork
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Chris Wilson @ 2020-04-23 10:15 UTC (permalink / raw)
To: intel-gfx
No unprivileged context should ever be allowed to modify state that is
visible to another; there should be no backchannels available or control
leakage for malicious actors.
This test tries to write to a set of random registers using
non-privileged instructions (ala userspace). It should only be allowed
to write into its context state, and all writes should not be visible to
a second context. To verify this, we store the value of the register
before writing to it in context A (as this should be the default value
inherited from the golden context state) and do a read back from context
B of the same register. The reads from both contexts should be identical,
the default value, except for a few free running counters (either global
or local).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 411 ++++++++++++++++++
1 file changed, 411 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index f4f933240b39..b5b3981076f3 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1865,6 +1865,416 @@ static int igt_vm_isolation(void *arg)
return err;
}
+static struct i915_vma *create_vma(struct i915_address_space *vm, size_t sz)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(vm->i915, sz);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma))
+ i915_gem_object_put(obj);
+
+ return vma;
+}
+
+static int iso_write(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ u32 *ctl)
+{
+ struct i915_vma *batch, *vma;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int i;
+
+ ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ batch = create_vma(ce->vm, 64 << 10);
+ if (IS_ERR(batch))
+ return PTR_ERR(batch);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_batch;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err_batch;
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_unpin_batch;
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_vma;
+ }
+
+ for (i = 0; i < 1024; i++) {
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = ctl[4 * i + 0];
+ *cs++ = ctl[4 * i + 1];
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_vma;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_rq;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (err == 0)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto err_rq;
+
+ err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+
+err_rq:
+ i915_request_add(rq);
+err_vma:
+ i915_vma_unpin(vma);
+err_unpin_batch:
+ i915_vma_unpin(batch);
+err_batch:
+ i915_vma_put(batch);
+ return err;
+}
+
+static int iso_read(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ u32 *ctl,
+ int idx)
+{
+ struct i915_vma *batch, *vma;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int i;
+
+ ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ batch = create_vma(ce->vm, 64 << 10);
+ if (IS_ERR(batch))
+ return PTR_ERR(batch);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_batch;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err_batch;
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_unpin_batch;
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_vma;
+ }
+
+ for (i = 0; i < 1024; i++) {
+ u64 addr = vma->node.start + (4 * i + idx) * sizeof(u32);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = ctl[4 * i + 0];
+ *cs++ = lower_32_bits(addr);
+ *cs++ = upper_32_bits(addr);
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_vma;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_rq;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (err == 0)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto err_rq;
+
+ err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+
+err_rq:
+ i915_request_add(rq);
+err_vma:
+ i915_vma_unpin(vma);
+err_unpin_batch:
+ i915_vma_unpin(batch);
+err_batch:
+ i915_vma_put(batch);
+ return err;
+}
+
+static bool is_timestamp(struct drm_i915_private *i915, u32 x)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (x == engine->mmio_base + 0x358)
+ return true;
+
+ if (x == engine->mmio_base + 0x35c)
+ return true;
+
+ if (x == engine->mmio_base + 0x3a8)
+ return true;
+ }
+
+ return false;
+}
+
+static bool is_whitelist(struct drm_i915_private *i915, u32 x)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ const struct i915_wa_list *w = &engine->whitelist;
+ int i;
+
+ for (i = 0; i < w->count; i++) {
+ if (x == i915_mmio_reg_offset(w->list[i].reg))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static u32 random_reg(struct drm_i915_private *i915,
+ struct rnd_state *prng)
+{
+ u32 x;
+
+ /*
+ * Pick any u32 aligned value that is not known to a free running
+ * counter (e.g. a timestamp).
+ */
+ do {
+ x = prandom_u32_state(prng) % 10000 * sizeof(u32);
+ if (!is_timestamp(i915, x) && !is_whitelist(i915, x))
+ return x;
+ } while (1);
+}
+
+static void hexdump(const void *buf, size_t len)
+{
+ const size_t rowsize = 8 * sizeof(u32);
+ const void *prev = NULL;
+ bool skip = false;
+ size_t pos;
+
+ for (pos = 0; pos < len; pos += rowsize) {
+ char line[128];
+
+ if (prev && !memcmp(prev, buf + pos, rowsize)) {
+ if (!skip) {
+ pr_info("*\n");
+ skip = true;
+ }
+ continue;
+ }
+
+ WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
+ rowsize, sizeof(u32),
+ line, sizeof(line),
+ false) >= sizeof(line));
+ pr_info("[%04zx] %s\n", pos, line);
+
+ prev = buf + pos;
+ skip = false;
+ }
+}
+
+static bool skip_isolation(const struct intel_engine_cs *engine)
+{
+ if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
+ return true;
+
+ if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) < 12)
+ return true;
+
+ return false;
+}
+
+static int igt_reg_isolation(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_gem_context *ctx_a, *ctx_b;
+ struct drm_i915_gem_object *obj;
+ struct intel_engine_cs *engine;
+ struct igt_live_test t;
+ I915_RND_STATE(prng);
+ struct file *file;
+ u32 *ctl;
+ int err;
+ int i;
+
+ if (INTEL_GEN(i915) < 8) /* for LRM/SRM */
+ return 0;
+
+ /*
+ * No state that we can write to from our context should be
+ * observable by another.
+ */
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ err = igt_live_test_begin(&t, i915, __func__, "");
+ if (err)
+ goto out_file;
+
+ ctx_a = live_context(i915, file);
+ if (IS_ERR(ctx_a)) {
+ err = PTR_ERR(ctx_a);
+ goto out_file;
+ }
+
+ ctx_b = live_context(i915, file);
+ if (IS_ERR(ctx_b)) {
+ err = PTR_ERR(ctx_b);
+ goto out_file;
+ }
+
+ obj = i915_gem_object_create_internal(i915, 16 * 1024);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_file;
+ }
+
+ ctl = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(ctl)) {
+ err = PTR_ERR(ctl);
+ goto out_obj;
+ }
+
+ for (i = 0; i < 1024; i++) {
+ ctl[4 * i + 0] = random_reg(i915, &prng);
+ ctl[4 * i + 1] = prandom_u32_state(&prng); /* poison */
+ }
+
+ for_each_uabi_engine(engine, i915) {
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN) &&
+ skip_isolation(engine))
+ continue; /* Just don't even ask */
+
+ for (i = 0; i < 1024; i++) {
+ ctl[4 * i + 2] = 0xdeadbeef; /* before */
+ ctl[4 * i + 3] = 0x00c0ffee; /* after */
+ }
+ i915_gem_object_flush_map(obj);
+
+ err = iso_read(ctx_b, engine, obj, ctl, 2);
+ if (err)
+ break;
+
+ err = iso_read(ctx_a, engine, obj, ctl, 2);
+ if (err)
+ break;
+
+ /* Twice to record after the first pristine context save */
+ err = iso_read(ctx_b, engine, obj, ctl, 2);
+ if (err)
+ break;
+
+ err = iso_write(ctx_a, engine, obj, ctl);
+ if (err)
+ break;
+
+ err = iso_read(ctx_b, engine, obj, ctl, 3);
+ if (err)
+ break;
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_ALL |
+ I915_WAIT_INTERRUPTIBLE,
+ HZ / 2);
+ if (err)
+ break;
+
+ for (i = 0; i < 1024; i++) {
+ if (ctl[4 * i + 2] == ctl[4 * i + 3])
+ continue;
+
+ pr_err("%s: poison 0x%x with %08x, in:%08x, out:%08x\n",
+ engine->name,
+ ctl[4 * i + 0],
+ ctl[4 * i + 1],
+ ctl[4 * i + 2],
+ ctl[4 * i + 3]);
+
+ /* If we read back the poison in its entirety, whoops */
+ if (ctl[4 * i + 3] == ctl[4 * i + 1])
+ err = -EINVAL;
+ }
+ if (err) {
+ hexdump(ctl, 16 * 1024);
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(obj);
+ if (igt_live_test_end(&t))
+ err = -EIO;
+
+out_obj:
+ i915_gem_object_put(obj);
+out_file:
+ fput(file);
+ return err;
+}
+
static bool skip_unused_engines(struct intel_context *ce, void *data)
{
return !ce->state;
@@ -2000,6 +2410,7 @@ int i915_gem_context_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ctx_sseu),
SUBTEST(igt_shared_ctx_exec),
SUBTEST(igt_vm_isolation),
+ SUBTEST(igt_reg_isolation),
};
if (intel_gt_is_wedged(&i915->gt))
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev3)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
@ 2020-04-23 10:59 ` Patchwork
2020-04-23 12:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 10:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev3)
URL : https://patchwork.freedesktop.org/series/76339/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7d2826951e5a drm/i915/selftests: Verify context isolation
-:319: WARNING:LINE_SPACING: Missing a blank line after declarations
#319: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:2156:
+ struct igt_live_test t;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 423 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Verify context isolation (rev3)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
2020-04-23 10:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev3) Patchwork
@ 2020-04-23 12:03 ` Patchwork
2020-04-23 12:05 ` Patchwork
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 12:03 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev3)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8351 -> Patchwork_17437
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17437 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17437, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17437:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-tgl-y/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-tgl-y/igt@i915_selftest@live@gem_contexts.html
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-icl-u2/igt@i915_selftest@live@gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-icl-u2/igt@i915_selftest@live@gem_contexts.html
- fi-icl-y: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-icl-y/igt@i915_selftest@live@gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-icl-y/igt@i915_selftest@live@gem_contexts.html
- fi-icl-guc: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-icl-guc/igt@i915_selftest@live@gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-icl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bdw-5557u: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-tgl-dsi}: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
- {fi-tgl-u}: [PASS][13] -> [INCOMPLETE][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
- {fi-ehl-1}: [PASS][15] -> [INCOMPLETE][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_17437 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gem_contexts:
- fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18] ([i915#1591])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-kefka: [PASS][19] -> [INCOMPLETE][20] ([i915#392])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
- fi-apl-guc: [PASS][21] -> [INCOMPLETE][22] ([i915#1591])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-apl-guc/igt@i915_selftest@live@gem_contexts.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-apl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-glk-dsi: [PASS][23] -> [INCOMPLETE][24] ([i915#1591] / [i915#58] / [k.org#198133])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-skl-6700k2: [PASS][25] -> [INCOMPLETE][26] ([i915#1591])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-8700k: [PASS][27] -> [INCOMPLETE][28] ([i915#1591])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-n3050: [PASS][29] -> [INCOMPLETE][30] ([i915#392])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
- fi-whl-u: [PASS][31] -> [INCOMPLETE][32] ([i915#1591])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-whl-u/igt@i915_selftest@live@gem_contexts.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-whl-u/igt@i915_selftest@live@gem_contexts.html
- fi-cml-s: [PASS][33] -> [INCOMPLETE][34] ([i915#1591])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
- fi-skl-guc: [PASS][35] -> [INCOMPLETE][36] ([i915#1591])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-guc/igt@i915_selftest@live@gem_contexts.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-guc: [PASS][37] -> [INCOMPLETE][38] ([fdo#106070] / [i915#1591])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bxt-dsi: [PASS][39] -> [INCOMPLETE][40] ([i915#1591])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-cml-u2: [PASS][41] -> [INCOMPLETE][42] ([i915#1591])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cml-u2/igt@i915_selftest@live@gem_contexts.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cml-u2/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-8809g: [PASS][43] -> [INCOMPLETE][44] ([i915#1591] / [i915#794])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-8809g/igt@i915_selftest@live@gem_contexts.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-8809g/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-r: [PASS][45] -> [INCOMPLETE][46] ([i915#1591] / [i915#794])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-r/igt@i915_selftest@live@gem_contexts.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-r/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-8109u: [PASS][47] -> [INCOMPLETE][48] ([i915#1591])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
- fi-skl-lmem: [PASS][49] -> [INCOMPLETE][50] ([i915#1591])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-guc: [PASS][51] -> [INCOMPLETE][52] ([i915#1591] / [i915#794])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-guc/igt@i915_selftest@live@gem_contexts.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-nick: [PASS][53] -> [INCOMPLETE][54] ([i915#392])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7500u: [PASS][55] -> [INCOMPLETE][56] ([i915#1591] / [i915#794])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-x1275: [PASS][57] -> [INCOMPLETE][58] ([i915#1591] / [i915#794])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-x1275/igt@i915_selftest@live@gem_contexts.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-x1275/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@late_gt_pm:
- fi-snb-2600: [PASS][59] -> [FAIL][60] ([i915#1763])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-snb-2600/igt@i915_selftest@live@late_gt_pm.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-snb-2600/igt@i915_selftest@live@late_gt_pm.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_timelines:
- fi-bwr-2160: [INCOMPLETE][61] ([i915#489]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[i915#1591]: https://gitlab.freedesktop.org/drm/intel/issues/1591
[i915#1763]: https://gitlab.freedesktop.org/drm/intel/issues/1763
[i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (50 -> 42)
------------------------------
Missing (8): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8351 -> Patchwork_17437
CI-20190529: 20190529
CI_DRM_8351: 63580ab8ee4dc3b1b824be6637085ac6b2c8ba6d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5608: e7bcaf1dd251d454706c7cd64282f531aec50183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17437: 7d2826951e5a63ae51fb66e29597402190b0137a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7d2826951e5a drm/i915/selftests: Verify context isolation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Verify context isolation (rev3)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
2020-04-23 10:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev3) Patchwork
2020-04-23 12:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-04-23 12:05 ` Patchwork
2020-04-23 12:16 ` [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation Chris Wilson
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 12:05 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev3)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8351 -> Patchwork_17437
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17437 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17437, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17437:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-tgl-y/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-tgl-y/igt@i915_selftest@live@gem_contexts.html
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-icl-u2/igt@i915_selftest@live@gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-icl-u2/igt@i915_selftest@live@gem_contexts.html
- fi-icl-y: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-icl-y/igt@i915_selftest@live@gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-icl-y/igt@i915_selftest@live@gem_contexts.html
- fi-icl-guc: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-icl-guc/igt@i915_selftest@live@gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-icl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bdw-5557u: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-tgl-dsi}: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
- {fi-tgl-u}: [PASS][13] -> [INCOMPLETE][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
- {fi-ehl-1}: [PASS][15] -> [INCOMPLETE][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_17437 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gem_contexts:
- fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18] ([i915#1591])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-kefka: [PASS][19] -> [INCOMPLETE][20] ([i915#392])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
- fi-apl-guc: [PASS][21] -> [INCOMPLETE][22] ([i915#1591])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-apl-guc/igt@i915_selftest@live@gem_contexts.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-apl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-glk-dsi: [PASS][23] -> [INCOMPLETE][24] ([i915#1591] / [i915#58] / [k.org#198133])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-skl-6700k2: [PASS][25] -> [INCOMPLETE][26] ([i915#1591])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-8700k: [PASS][27] -> [INCOMPLETE][28] ([i915#1591])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-n3050: [PASS][29] -> [INCOMPLETE][30] ([i915#392])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
- fi-whl-u: [PASS][31] -> [INCOMPLETE][32] ([i915#1591])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-whl-u/igt@i915_selftest@live@gem_contexts.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-whl-u/igt@i915_selftest@live@gem_contexts.html
- fi-cml-s: [PASS][33] -> [INCOMPLETE][34] ([i915#1591])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
- fi-skl-guc: [PASS][35] -> [INCOMPLETE][36] ([i915#1591])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-guc/igt@i915_selftest@live@gem_contexts.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-guc: [PASS][37] -> [INCOMPLETE][38] ([fdo#106070] / [i915#1591])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bxt-dsi: [PASS][39] -> [INCOMPLETE][40] ([i915#1591])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-cml-u2: [PASS][41] -> [INCOMPLETE][42] ([i915#1591])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cml-u2/igt@i915_selftest@live@gem_contexts.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cml-u2/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-8809g: [PASS][43] -> [INCOMPLETE][44] ([i915#1591] / [i915#794])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-8809g/igt@i915_selftest@live@gem_contexts.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-8809g/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-r: [PASS][45] -> [INCOMPLETE][46] ([i915#1591] / [i915#794])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-r/igt@i915_selftest@live@gem_contexts.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-r/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-8109u: [PASS][47] -> [INCOMPLETE][48] ([i915#1591])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
- fi-skl-lmem: [PASS][49] -> [INCOMPLETE][50] ([i915#1591])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-guc: [PASS][51] -> [INCOMPLETE][52] ([i915#1591] / [i915#794])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-guc/igt@i915_selftest@live@gem_contexts.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-nick: [PASS][53] -> [INCOMPLETE][54] ([i915#392])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7500u: [PASS][55] -> [INCOMPLETE][56] ([i915#1591] / [i915#794])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-x1275: [PASS][57] -> [INCOMPLETE][58] ([i915#1591] / [i915#794])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-kbl-x1275/igt@i915_selftest@live@gem_contexts.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-kbl-x1275/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@late_gt_pm:
- fi-snb-2600: [PASS][59] -> [FAIL][60] ([i915#1763])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-snb-2600/igt@i915_selftest@live@late_gt_pm.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-snb-2600/igt@i915_selftest@live@late_gt_pm.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_timelines:
- fi-bwr-2160: [INCOMPLETE][61] ([i915#489]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8351/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[i915#1591]: https://gitlab.freedesktop.org/drm/intel/issues/1591
[i915#1763]: https://gitlab.freedesktop.org/drm/intel/issues/1763
[i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (50 -> 42)
------------------------------
Missing (8): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8351 -> Patchwork_17437
CI-20190529: 20190529
CI_DRM_8351: 63580ab8ee4dc3b1b824be6637085ac6b2c8ba6d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5608: e7bcaf1dd251d454706c7cd64282f531aec50183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17437: 7d2826951e5a63ae51fb66e29597402190b0137a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7d2826951e5a drm/i915/selftests: Verify context isolation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17437/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
` (2 preceding siblings ...)
2020-04-23 12:05 ` Patchwork
@ 2020-04-23 12:16 ` Chris Wilson
2020-04-23 13:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev4) Patchwork
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-04-23 12:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
No unprivileged context should ever be allowed to modify logical state
that is visible to another; there should be no backchannels available or
control leakage for malicious actors.
This test tries to write to a set of random registers using
non-privileged instructions (ala userspace). It should only be allowed
to write into its context state, and all writes should not be visible to
a second context. To verify this, we store the value of the register
before writing to it in context A (as this should be the default value
inherited from the golden context state) and do a read back from context
B of the same register. The reads from both contexts should be identical,
the default value, except for a few free running counters (either global
or local).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 438 ++++++++++++++++++
1 file changed, 438 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index f4f933240b39..e7020a8f7c1f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1865,6 +1865,443 @@ static int igt_vm_isolation(void *arg)
return err;
}
+static struct i915_vma *create_vma(struct i915_address_space *vm, size_t sz)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(vm->i915, sz);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma))
+ i915_gem_object_put(obj);
+
+ return vma;
+}
+
+struct iso_details {
+ unsigned long count;
+};
+
+enum {
+ ISO_REG = 0,
+ ISO_POISON,
+ ISO_BEFORE,
+ ISO_AFTER,
+ __ISO__
+};
+
+static int iso_write(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ const struct iso_details *iso,
+ u32 *ctl)
+{
+ struct i915_vma *batch, *vma;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int i;
+
+ ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ batch = create_vma(ce->vm, PAGE_ALIGN(16 * iso->count + 4));
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_ce;
+ }
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_batch;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err_batch;
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_unpin_batch;
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_vma;
+ }
+
+ for (i = 0; i < iso->count; i++) {
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = ctl[i * __ISO__ + ISO_REG];
+ *cs++ = ctl[i * __ISO__ + ISO_POISON];
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_vma;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_rq;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (err == 0)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto err_rq;
+
+ err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+
+err_rq:
+ i915_request_add(rq);
+err_vma:
+ i915_vma_unpin(vma);
+err_unpin_batch:
+ i915_vma_unpin(batch);
+err_batch:
+ i915_vma_put(batch);
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static int iso_read(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ const struct iso_details *iso,
+ u32 *ctl,
+ int idx)
+{
+ struct i915_vma *batch, *vma;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int i;
+
+ ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ batch = create_vma(ce->vm, PAGE_ALIGN(16 * iso->count + 4));
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_ce;
+ }
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_batch;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err_batch;
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_unpin_batch;
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_vma;
+ }
+
+ for (i = 0; i < iso->count; i++) {
+ u64 addr = vma->node.start + (i * __ISO__ + idx) * sizeof(u32);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = ctl[i * __ISO__ + ISO_REG];
+ *cs++ = lower_32_bits(addr);
+ *cs++ = upper_32_bits(addr);
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_vma;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_rq;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (err == 0)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto err_rq;
+
+ err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+
+err_rq:
+ i915_request_add(rq);
+err_vma:
+ i915_vma_unpin(vma);
+err_unpin_batch:
+ i915_vma_unpin(batch);
+err_batch:
+ i915_vma_put(batch);
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static bool is_timestamp(struct drm_i915_private *i915, u32 x)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (x == engine->mmio_base + 0x358)
+ return true;
+
+ if (x == engine->mmio_base + 0x35c)
+ return true;
+
+ if (x == engine->mmio_base + 0x3a8)
+ return true;
+ }
+
+ return false;
+}
+
+static bool is_whitelist(struct drm_i915_private *i915, u32 x)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ const struct i915_wa_list *w = &engine->whitelist;
+ int i;
+
+ for (i = 0; i < w->count; i++) {
+ if (x == i915_mmio_reg_offset(w->list[i].reg))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static u32 random_reg(struct drm_i915_private *i915,
+ struct rnd_state *prng)
+{
+ u32 x;
+
+ /*
+ * Pick any u32 aligned value that is not known to a free running
+ * counter (e.g. a timestamp).
+ */
+ do {
+ x = prandom_u32_state(prng) % 10000 * sizeof(u32);
+ if (!is_timestamp(i915, x) && !is_whitelist(i915, x))
+ return x;
+ } while (1);
+}
+
+static void hexdump(const void *buf, size_t len)
+{
+ const size_t rowsize = 8 * sizeof(u32);
+ const void *prev = NULL;
+ bool skip = false;
+ size_t pos;
+
+ for (pos = 0; pos < len; pos += rowsize) {
+ char line[128];
+
+ if (prev && !memcmp(prev, buf + pos, rowsize)) {
+ if (!skip) {
+ pr_info("*\n");
+ skip = true;
+ }
+ continue;
+ }
+
+ WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
+ rowsize, sizeof(u32),
+ line, sizeof(line),
+ false) >= sizeof(line));
+ pr_info("[%04zx] %s\n", pos, line);
+
+ prev = buf + pos;
+ skip = false;
+ }
+}
+
+static bool skip_isolation(const struct intel_engine_cs *engine)
+{
+ if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
+ return true;
+
+ if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) < 12)
+ return true;
+
+ return false;
+}
+
+static int igt_reg_isolation(void *arg)
+{
+ const struct iso_details iso = { .count = 1024 };
+ struct drm_i915_private *i915 = arg;
+ struct i915_gem_context *ctx_a, *ctx_b;
+ struct drm_i915_gem_object *obj;
+ struct intel_engine_cs *engine;
+ struct igt_live_test t;
+ I915_RND_STATE(prng);
+ struct file *file;
+ unsigned long sz;
+ u32 *ctl;
+ int err;
+ int i;
+
+ if (INTEL_GEN(i915) < 8) /* for LRM/SRM */
+ return 0;
+
+ /*
+ * No state that we can write to from our context should be
+ * observable by another.
+ */
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ err = igt_live_test_begin(&t, i915, __func__, "");
+ if (err)
+ goto out_file;
+
+ ctx_a = live_context(i915, file);
+ if (IS_ERR(ctx_a)) {
+ err = PTR_ERR(ctx_a);
+ goto out_file;
+ }
+
+ ctx_b = live_context(i915, file);
+ if (IS_ERR(ctx_b)) {
+ err = PTR_ERR(ctx_b);
+ goto out_file;
+ }
+
+ sz = PAGE_ALIGN(__ISO__ * iso.count * sizeof(u32));
+ obj = i915_gem_object_create_internal(i915, sz);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_file;
+ }
+
+ ctl = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(ctl)) {
+ err = PTR_ERR(ctl);
+ goto out_obj;
+ }
+
+ for (i = 0; i < iso.count; i++) {
+ ctl[i * __ISO__ + ISO_REG] = random_reg(i915, &prng);
+ ctl[i * __ISO__ + ISO_POISON] = prandom_u32_state(&prng);
+ }
+
+ for_each_uabi_engine(engine, i915) {
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN) &&
+ skip_isolation(engine))
+ continue; /* Just don't even ask */
+
+ for (i = 0; i < iso.count; i++) {
+ ctl[i * __ISO__ + ISO_BEFORE] = 0xdeadbeef;
+ ctl[i * __ISO__ + ISO_AFTER] = 0x00c0ffee;
+ }
+ i915_gem_object_flush_map(obj);
+
+ err = iso_read(ctx_b, engine, obj, &iso, ctl, ISO_BEFORE);
+ if (err)
+ break;
+
+ err = iso_read(ctx_a, engine, obj, &iso, ctl, ISO_BEFORE);
+ if (err)
+ break;
+
+ /* Twice to record after the first pristine context save */
+ err = iso_read(ctx_b, engine, obj, &iso, ctl, ISO_BEFORE);
+ if (err)
+ break;
+
+ err = iso_write(ctx_a, engine, obj, &iso, ctl);
+ if (err)
+ break;
+
+ err = iso_read(ctx_b, engine, obj, &iso, ctl, ISO_AFTER);
+ if (err)
+ break;
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_ALL |
+ I915_WAIT_INTERRUPTIBLE,
+ HZ / 2);
+ if (err)
+ break;
+
+ for (i = 0; i < iso.count; i++) {
+ const u32 *result = &ctl[__ISO__ * i];
+
+ if (result[ISO_BEFORE] == result[ISO_AFTER])
+ continue;
+
+ pr_err("%s: poison 0x%x with %08x, in:%08x, out:%08x\n",
+ engine->name,
+ result[ISO_REG],
+ result[ISO_POISON],
+ result[ISO_BEFORE],
+ result[ISO_AFTER]);
+
+ /* If we read back the poison in its entirety, whoops */
+ if (result[ISO_AFTER] == result[ISO_POISON])
+ err = -EINVAL;
+ }
+ if (err) {
+ hexdump(ctl, __ISO__ * iso.count * sizeof(u32));
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(obj);
+ if (igt_live_test_end(&t))
+ err = -EIO;
+
+out_obj:
+ i915_gem_object_put(obj);
+out_file:
+ fput(file);
+ return err;
+}
+
static bool skip_unused_engines(struct intel_context *ce, void *data)
{
return !ce->state;
@@ -2000,6 +2437,7 @@ int i915_gem_context_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ctx_sseu),
SUBTEST(igt_shared_ctx_exec),
SUBTEST(igt_vm_isolation),
+ SUBTEST(igt_reg_isolation),
};
if (intel_gt_is_wedged(&i915->gt))
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev4)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
` (3 preceding siblings ...)
2020-04-23 12:16 ` [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation Chris Wilson
@ 2020-04-23 13:27 ` Patchwork
2020-04-23 14:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 13:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev4)
URL : https://patchwork.freedesktop.org/series/76339/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bfe16faeae8a drm/i915/selftests: Verify context isolation
-:342: WARNING:LINE_SPACING: Missing a blank line after declarations
#342: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:2179:
+ struct igt_live_test t;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 450 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Verify context isolation (rev4)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
` (4 preceding siblings ...)
2020-04-23 13:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev4) Patchwork
@ 2020-04-23 14:05 ` Patchwork
2020-04-23 15:51 ` [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation Chris Wilson
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 14:05 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev4)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8352 -> Patchwork_17440
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17440 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17440, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17440:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8352/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_pm:
- fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8352/fi-cfl-8700k/igt@i915_selftest@live@gt_pm.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/fi-cfl-8700k/igt@i915_selftest@live@gt_pm.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-tgl-dsi}: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8352/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
- {fi-tgl-u}: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8352/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_17440 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@ring_submission:
- fi-snb-2600: [PASS][9] -> [FAIL][10] ([i915#1763])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8352/fi-snb-2600/igt@i915_selftest@live@ring_submission.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/fi-snb-2600/igt@i915_selftest@live@ring_submission.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_lrc:
- fi-snb-2600: [FAIL][11] ([i915#1763]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8352/fi-snb-2600/igt@i915_selftest@live@gt_lrc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/fi-snb-2600/igt@i915_selftest@live@gt_lrc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1763]: https://gitlab.freedesktop.org/drm/intel/issues/1763
Participating hosts (48 -> 43)
------------------------------
Additional (1): fi-bsw-kefka
Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8352 -> Patchwork_17440
CI-20190529: 20190529
CI_DRM_8352: 248cbab28d58c203de956df1db4cdeb53ea97a89 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5608: e7bcaf1dd251d454706c7cd64282f531aec50183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17440: bfe16faeae8a18db3ae6444cbf0b7ade48c6ff9d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bfe16faeae8a drm/i915/selftests: Verify context isolation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17440/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
` (5 preceding siblings ...)
2020-04-23 14:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-04-23 15:51 ` Chris Wilson
2020-04-23 16:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev5) Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-04-23 15:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
No unprivileged context should ever be allowed to modify logical state
that is visible to another; there should be no backchannels available or
control leakage for malicious actors.
This test tries to write to a set of random registers using
non-privileged instructions (ala userspace). It should only be allowed
to write into its context state, and all writes should not be visible to
a second context. To verify this, we store the value of the register
before writing to it in context A (as this should be the default value
inherited from the golden context state) and do a read back from context
B of the same register. The reads from both contexts should be identical,
the default value, except for a few free running counters (either global
or local).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 441 ++++++++++++++++++
1 file changed, 441 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index f4f933240b39..c5c3433174dc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1865,6 +1865,446 @@ static int igt_vm_isolation(void *arg)
return err;
}
+static struct i915_vma *create_vma(struct i915_address_space *vm, size_t sz)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(vm->i915, sz);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma))
+ i915_gem_object_put(obj);
+
+ return vma;
+}
+
+struct iso_details {
+ unsigned long count;
+};
+
+enum {
+ ISO_REG = 0,
+ ISO_POISON,
+ ISO_BEFORE,
+ ISO_AFTER,
+ __ISO__
+};
+
+static int iso_write(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ const struct iso_details *iso,
+ u32 *ctl)
+{
+ struct i915_vma *batch, *vma;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int i;
+
+ ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ batch = create_vma(ce->vm, PAGE_ALIGN(16 * iso->count + 4));
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_ce;
+ }
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_batch;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err_batch;
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_unpin_batch;
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_vma;
+ }
+
+ for (i = 0; i < iso->count; i++) {
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = ctl[i * __ISO__ + ISO_REG];
+ *cs++ = ctl[i * __ISO__ + ISO_POISON];
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_vma;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_rq;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (err == 0)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto err_rq;
+
+ err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+
+err_rq:
+ i915_request_add(rq);
+err_vma:
+ i915_vma_unpin(vma);
+err_unpin_batch:
+ i915_vma_unpin(batch);
+err_batch:
+ i915_vma_put(batch);
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static int iso_read(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ const struct iso_details *iso,
+ u32 *ctl,
+ int idx)
+{
+ struct i915_vma *batch, *vma;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int i;
+
+ ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ batch = create_vma(ce->vm, PAGE_ALIGN(16 * iso->count + 4));
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_ce;
+ }
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_batch;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err_batch;
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_unpin_batch;
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_vma;
+ }
+
+ for (i = 0; i < iso->count; i++) {
+ u64 addr = vma->node.start + (i * __ISO__ + idx) * sizeof(u32);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = ctl[i * __ISO__ + ISO_REG];
+ *cs++ = lower_32_bits(addr);
+ *cs++ = upper_32_bits(addr);
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_vma;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_rq;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (err == 0)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto err_rq;
+
+ err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+
+err_rq:
+ i915_request_add(rq);
+err_vma:
+ i915_vma_unpin(vma);
+err_unpin_batch:
+ i915_vma_unpin(batch);
+err_batch:
+ i915_vma_put(batch);
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static bool is_timestamp(struct drm_i915_private *i915, u32 x)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (x == engine->mmio_base + 0x358)
+ return true;
+
+ if (x == engine->mmio_base + 0x35c)
+ return true;
+
+ if (x == engine->mmio_base + 0x3a8)
+ return true;
+ }
+
+ return false;
+}
+
+static bool is_whitelist(struct drm_i915_private *i915, u32 x)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ const struct i915_wa_list *w = &engine->whitelist;
+ int i;
+
+ for (i = 0; i < w->count; i++) {
+ if (x == i915_mmio_reg_offset(w->list[i].reg))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static u32 random_reg(struct drm_i915_private *i915,
+ struct rnd_state *prng)
+{
+ u32 x;
+
+ /*
+ * Pick any u32 aligned value that is not known to a free running
+ * counter (e.g. a timestamp).
+ */
+ do {
+ x = prandom_u32_state(prng) % 10000 * sizeof(u32);
+ if (!is_timestamp(i915, x) && !is_whitelist(i915, x))
+ return x;
+ } while (1);
+}
+
+static void hexdump(const void *buf, size_t len)
+{
+ const size_t rowsize = 8 * sizeof(u32);
+ const void *prev = NULL;
+ bool skip = false;
+ size_t pos;
+
+ for (pos = 0; pos < len; pos += rowsize) {
+ char line[128];
+
+ if (prev && !memcmp(prev, buf + pos, rowsize)) {
+ if (!skip) {
+ pr_info("*\n");
+ skip = true;
+ }
+ continue;
+ }
+
+ WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
+ rowsize, sizeof(u32),
+ line, sizeof(line),
+ false) >= sizeof(line));
+ pr_info("[%04zx] %s\n", pos, line);
+
+ prev = buf + pos;
+ skip = false;
+ }
+}
+
+static bool skip_isolation(const struct intel_engine_cs *engine)
+{
+ if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
+ return true;
+
+ if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) < 12)
+ return true;
+
+ if (IS_BROADWELL(engine->i915))
+ return true;
+
+ return false;
+}
+
+static int igt_reg_isolation(void *arg)
+{
+ const struct iso_details iso = { .count = 1024 };
+ struct drm_i915_private *i915 = arg;
+ struct i915_gem_context *ctx_a, *ctx_b;
+ struct drm_i915_gem_object *obj;
+ struct intel_engine_cs *engine;
+ struct igt_live_test t;
+ I915_RND_STATE(prng);
+ struct file *file;
+ unsigned long sz;
+ u32 *ctl;
+ int err;
+ int i;
+
+ if (INTEL_GEN(i915) < 8) /* for LRM/SRM */
+ return 0;
+
+ /*
+ * No state that we can write to from our context should be
+ * observable by another.
+ */
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ err = igt_live_test_begin(&t, i915, __func__, "");
+ if (err)
+ goto out_file;
+
+ ctx_a = live_context(i915, file);
+ if (IS_ERR(ctx_a)) {
+ err = PTR_ERR(ctx_a);
+ goto out_file;
+ }
+
+ ctx_b = live_context(i915, file);
+ if (IS_ERR(ctx_b)) {
+ err = PTR_ERR(ctx_b);
+ goto out_file;
+ }
+
+ sz = PAGE_ALIGN(__ISO__ * iso.count * sizeof(u32));
+ obj = i915_gem_object_create_internal(i915, sz);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_file;
+ }
+
+ ctl = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(ctl)) {
+ err = PTR_ERR(ctl);
+ goto out_obj;
+ }
+
+ for (i = 0; i < iso.count; i++) {
+ ctl[i * __ISO__ + ISO_REG] = random_reg(i915, &prng);
+ ctl[i * __ISO__ + ISO_POISON] = prandom_u32_state(&prng);
+ }
+
+ for_each_uabi_engine(engine, i915) {
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN) &&
+ skip_isolation(engine))
+ continue; /* Just don't even ask */
+
+ for (i = 0; i < iso.count; i++) {
+ ctl[i * __ISO__ + ISO_BEFORE] = 0xdeadbeef;
+ ctl[i * __ISO__ + ISO_AFTER] = 0x00c0ffee;
+ }
+ i915_gem_object_flush_map(obj);
+
+ err = iso_read(ctx_b, engine, obj, &iso, ctl, ISO_BEFORE);
+ if (err)
+ break;
+
+ err = iso_read(ctx_a, engine, obj, &iso, ctl, ISO_BEFORE);
+ if (err)
+ break;
+
+ /* Twice to record after the first pristine context save */
+ err = iso_read(ctx_b, engine, obj, &iso, ctl, ISO_BEFORE);
+ if (err)
+ break;
+
+ err = iso_write(ctx_a, engine, obj, &iso, ctl);
+ if (err)
+ break;
+
+ err = iso_read(ctx_b, engine, obj, &iso, ctl, ISO_AFTER);
+ if (err)
+ break;
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_ALL |
+ I915_WAIT_INTERRUPTIBLE,
+ HZ / 2);
+ if (err)
+ break;
+
+ for (i = 0; i < iso.count; i++) {
+ const u32 *result = &ctl[__ISO__ * i];
+
+ if (result[ISO_BEFORE] == result[ISO_AFTER])
+ continue;
+
+ pr_err("%s: poison 0x%x with %08x, in:%08x, out:%08x\n",
+ engine->name,
+ result[ISO_REG],
+ result[ISO_POISON],
+ result[ISO_BEFORE],
+ result[ISO_AFTER]);
+
+ /* If we read back the poison in its entirety, whoops */
+ if (result[ISO_AFTER] == result[ISO_POISON])
+ err = -EINVAL;
+ }
+ if (err) {
+ hexdump(ctl, __ISO__ * iso.count * sizeof(u32));
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(obj);
+ if (igt_live_test_end(&t))
+ err = -EIO;
+
+out_obj:
+ i915_gem_object_put(obj);
+out_file:
+ fput(file);
+ return err;
+}
+
static bool skip_unused_engines(struct intel_context *ce, void *data)
{
return !ce->state;
@@ -2000,6 +2440,7 @@ int i915_gem_context_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ctx_sseu),
SUBTEST(igt_shared_ctx_exec),
SUBTEST(igt_vm_isolation),
+ SUBTEST(igt_reg_isolation),
};
if (intel_gt_is_wedged(&i915->gt))
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev5)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
` (6 preceding siblings ...)
2020-04-23 15:51 ` [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation Chris Wilson
@ 2020-04-23 16:24 ` Patchwork
2020-04-23 16:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-23 18:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 16:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev5)
URL : https://patchwork.freedesktop.org/series/76339/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0b8abccda505 drm/i915/selftests: Verify context isolation
-:345: WARNING:LINE_SPACING: Missing a blank line after declarations
#345: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:2182:
+ struct igt_live_test t;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 453 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Verify context isolation (rev5)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
` (7 preceding siblings ...)
2020-04-23 16:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev5) Patchwork
@ 2020-04-23 16:49 ` Patchwork
2020-04-23 18:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 16:49 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev5)
URL : https://patchwork.freedesktop.org/series/76339/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8353 -> Patchwork_17443
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17443:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/fi-tgl-u/igt@i915_selftest@live@gem_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Participating hosts (49 -> 43)
------------------------------
Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8353 -> Patchwork_17443
CI-20190529: 20190529
CI_DRM_8353: ce2d0a17f95f9c6cdfed244b19da590d714d87ae @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5608: e7bcaf1dd251d454706c7cd64282f531aec50183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17443: 0b8abccda505e3702187d5cae3b3dcfd687ca426 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0b8abccda505 drm/i915/selftests: Verify context isolation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Verify context isolation (rev5)
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
` (8 preceding siblings ...)
2020-04-23 16:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-23 18:23 ` Patchwork
9 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-04-23 18:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev5)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8353_full -> Patchwork_17443_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17443_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17443_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17443_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-tglb6/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-tglb6/igt@i915_selftest@live@gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_17443_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_params@invalid-bsd-ring:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-iclb4/igt@gem_exec_params@invalid-bsd-ring.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-iclb7/igt@gem_exec_params@invalid-bsd-ring.html
* igt@gem_exec_suspend@basic-s3:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-apl6/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-apl7/igt@gem_exec_suspend@basic-s3.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-kbl3/igt@i915_suspend@debugfs-reader.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-kbl1/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([i915#155])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-kbl7/igt@i915_suspend@fence-restore-tiled2untiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-kbl4/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-offscreen:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#54] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-64x64-offscreen.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-offscreen.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#899])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-glk4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][19] -> [FAIL][20] ([i915#31])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-apl6/igt@kms_setmode@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-apl7/igt@kms_setmode@basic.html
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#31])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-skl2/igt@kms_setmode@basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-skl4/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@kms_cursor_edge_walk@pipe-a-256x256-left-edge:
- shard-glk: [FAIL][23] ([i915#118] / [i915#70] / [i915#95]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-glk9/igt@kms_cursor_edge_walk@pipe-a-256x256-left-edge.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-glk2/igt@kms_cursor_edge_walk@pipe-a-256x256-left-edge.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1}:
- shard-apl: [FAIL][25] ([i915#46]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* {igt@kms_flip@flip-vs-suspend@c-dp1}:
- shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-apl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-apl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][29] ([i915#1188]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][33] ([i915#69]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-skl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* {igt@perf@polling-parameterized}:
- shard-hsw: [FAIL][37] ([i915#1542]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-hsw1/igt@perf@polling-parameterized.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-hsw4/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][39] ([i915#468]) -> [FAIL][40] ([i915#454])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-tglb8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-snb: [SKIP][41] ([fdo#109271]) -> [INCOMPLETE][42] ([i915#82])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-snb2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-snb5/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@system-suspend:
- shard-snb: [INCOMPLETE][43] ([i915#82]) -> [SKIP][44] ([fdo#109271])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8353/shard-snb1/igt@i915_pm_rpm@system-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/shard-snb1/igt@i915_pm_rpm@system-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8353 -> Patchwork_17443
CI-20190529: 20190529
CI_DRM_8353: ce2d0a17f95f9c6cdfed244b19da590d714d87ae @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5608: e7bcaf1dd251d454706c7cd64282f531aec50183 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17443: 0b8abccda505e3702187d5cae3b3dcfd687ca426 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17443/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-04-23 18:23 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-23 10:15 [Intel-gfx] [CI] drm/i915/selftests: Verify context isolation Chris Wilson
2020-04-23 10:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev3) Patchwork
2020-04-23 12:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-04-23 12:05 ` Patchwork
2020-04-23 12:16 ` [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation Chris Wilson
2020-04-23 13:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev4) Patchwork
2020-04-23 14:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-04-23 15:51 ` [Intel-gfx] [PATCH] drm/i915/selftests: Verify context isolation Chris Wilson
2020-04-23 16:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Verify context isolation (rev5) Patchwork
2020-04-23 16:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-23 18:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.