* [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency
@ 2020-04-27 15:45 Chris Wilson
2020-04-27 16:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Fix up clock frequency (rev5) Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2020-04-27 15:45 UTC (permalink / raw)
To: intel-gfx
The bspec lists both the clock frequency and the effective interval. The
interval corresponds to observed behaviour, so adjust the frequency to
match.
v2: Mika rightfully asked if we could measure the clock frequency from a
selftest.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 +-
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 139 ++++++++++++++++++
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
4 files changed, 147 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 852a7d731b3b..999079686846 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -7,9 +7,9 @@
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
+#define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
+#define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
#define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
-#define MHZ_24 24000000 /* 24MHz, 83.333ns */
-#define MHZ_25 25000000 /* 25MHz, 80ns */
static u32 read_clock_frequency(const struct intel_gt *gt)
{
@@ -21,19 +21,19 @@ static u32 read_clock_frequency(const struct intel_gt *gt)
config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
switch (config) {
- case 0: return MHZ_24;
+ case 0: return MHZ_12;
case 1:
case 2: return MHZ_19_2;
default:
- case 3: return MHZ_25;
+ case 3: return MHZ_12_5;
}
} else if (INTEL_GEN(gt->i915) >= 9) {
if (IS_GEN9_LP(gt->i915))
return MHZ_19_2;
else
- return MHZ_24;
+ return MHZ_12;
} else {
- return MHZ_25;
+ return MHZ_12_5;
}
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index e02fdec58826..242181a5214c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -53,6 +53,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rps_clock_interval),
SUBTEST(live_rps_control),
SUBTEST(live_rps_frequency_cs),
SUBTEST(live_rps_frequency_srm),
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index e13cbcb82825..181b29fa5b58 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -208,6 +208,145 @@ static void show_pstate_limits(struct intel_rps *rps)
}
}
+int live_rps_clock_interval(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >->rps;
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err = 0;
+
+ if (!rps->enabled)
+ return 0;
+
+ if (igt_spinner_init(&spin, gt))
+ return -ENOMEM;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ intel_gt_pm_get(gt);
+ intel_rps_disable(>->rps);
+
+ intel_gt_check_clock_frequency(gt);
+
+ for_each_engine(engine, gt, id) {
+ unsigned long saved_heartbeat;
+ struct i915_request *rq;
+ ktime_t dt;
+ u32 cycles;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ saved_heartbeat = engine_heartbeat_disable(engine);
+
+ rq = igt_spinner_create_request(&spin,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ engine_heartbeat_enable(engine, saved_heartbeat);
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(&spin, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ igt_spinner_end(&spin);
+ engine_heartbeat_enable(engine, saved_heartbeat);
+ intel_gt_set_wedged(engine->gt);
+ err = -EIO;
+ break;
+ }
+
+ intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
+
+ intel_uncore_write_fw(gt->uncore, GEN6_RP_CUR_UP_EI, 0);
+
+ /* Set the evaluation interval to infinity! */
+ intel_uncore_write_fw(gt->uncore,
+ GEN6_RP_UP_EI, 0xffffffff);
+ intel_uncore_write_fw(gt->uncore,
+ GEN6_RP_UP_THRESHOLD, 0xffffffff);
+
+ intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL,
+ GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG);
+
+ if (wait_for(intel_uncore_read_fw(gt->uncore,
+ GEN6_RP_CUR_UP_EI),
+ 10)) {
+ /* Just skip the test; assume lack of HW support */
+ pr_notice("%s: rps evalution interval not ticking\n",
+ engine->name);
+ err = -ENODEV;
+ } else {
+ preempt_disable();
+ dt = ktime_get();
+ cycles = -intel_uncore_read_fw(gt->uncore,
+ GEN6_RP_CUR_UP_EI);
+ udelay(1000);
+ dt = ktime_sub(ktime_get(), dt);
+ cycles += intel_uncore_read_fw(gt->uncore,
+ GEN6_RP_CUR_UP_EI);
+ preempt_enable();
+ }
+
+ intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, 0);
+ intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
+
+ igt_spinner_end(&spin);
+ engine_heartbeat_enable(engine, saved_heartbeat);
+
+ if (err == 0) {
+ u64 time = intel_gt_pm_interval_to_ns(gt, cycles);
+ u32 expected =
+ intel_gt_ns_to_pm_interval(gt, ktime_to_ns(dt));
+
+ pr_info("%s: rps counted %d C0 cycles [%lldns] in %lldns [%d cycles], using GT clock frequency of %uKHz\n",
+ engine->name, cycles, time, ktime_to_ns(dt), expected,
+ gt->clock_frequency / 1000);
+
+ if (10 * time < 9 * ktime_to_ns(dt) ||
+ 10 * time > 11 * ktime_to_ns(dt)) {
+ pr_err("%s: rps clock time does not match walltime!\n",
+ engine->name);
+ err = -EINVAL;
+ }
+
+ if (10 * expected < 9 * cycles ||
+ 10 * expected > 11 * cycles) {
+ pr_err("%s: walltime does not match rps clock ticks!\n",
+ engine->name);
+ err = -EINVAL;
+ }
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ break; /* once is enough */
+ }
+
+ intel_rps_enable(>->rps);
+ intel_gt_pm_put(gt);
+
+ igt_spinner_fini(&spin);
+
+ intel_gt_pm_wait_for_idle(gt);
+ rps->work.func = saved_work;
+
+ if (err == -ENODEV) /* skipped, don't report a fail */
+ err = 0;
+
+ return err;
+}
+
int live_rps_control(void *arg)
{
struct intel_gt *gt = arg;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.h b/drivers/gpu/drm/i915/gt/selftest_rps.h
index 76c4b19553e6..6e82a631cfa1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.h
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.h
@@ -7,6 +7,7 @@
#define SELFTEST_RPS_H
int live_rps_control(void *arg);
+int live_rps_clock_interval(void *arg);
int live_rps_frequency_cs(void *arg);
int live_rps_frequency_srm(void *arg);
int live_rps_power(void *arg);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Fix up clock frequency (rev5)
2020-04-27 15:45 [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency Chris Wilson
@ 2020-04-27 16:09 ` Patchwork
2020-04-27 16:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-27 19:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-27 16:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Fix up clock frequency (rev5)
URL : https://patchwork.freedesktop.org/series/76512/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0411865923e7 drm/i915/gt: Fix up clock frequency
-:159: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#159: FILE: drivers/gpu/drm/i915/gt/selftest_rps.c:293:
+ udelay(1000);
total: 0 errors, 0 warnings, 1 checks, 193 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Fix up clock frequency (rev5)
2020-04-27 15:45 [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency Chris Wilson
2020-04-27 16:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Fix up clock frequency (rev5) Patchwork
@ 2020-04-27 16:32 ` Patchwork
2020-04-27 19:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-27 16:32 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Fix up clock frequency (rev5)
URL : https://patchwork.freedesktop.org/series/76512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8373 -> Patchwork_17481
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/index.html
Known issues
------------
Here are the changes found in Patchwork_17481 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_selftest@live@gt_lrc:
- fi-bwr-2160: [INCOMPLETE][1] ([i915#489]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-bwr-2160/igt@i915_selftest@live@gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/fi-bwr-2160/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-x1275: [DMESG-FAIL][3] ([i915#1791]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-kbl-x1275/igt@i915_selftest@live@gt_pm.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/fi-kbl-x1275/igt@i915_selftest@live@gt_pm.html
- fi-icl-u2: [DMESG-FAIL][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-icl-u2/igt@i915_selftest@live@gt_pm.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/fi-icl-u2/igt@i915_selftest@live@gt_pm.html
- fi-skl-lmem: [DMESG-FAIL][7] ([i915#1791]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-skl-lmem/igt@i915_selftest@live@gt_pm.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/fi-skl-lmem/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [FAIL][9] -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([i915#227]) -> [PASS][12] +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][13] ([fdo#109271]) -> [FAIL][14] ([i915#62])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1791]: https://gitlab.freedesktop.org/drm/intel/issues/1791
[i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Participating hosts (49 -> 41)
------------------------------
Missing (8): fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-cfl-8109u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8373 -> Patchwork_17481
CI-20190529: 20190529
CI_DRM_8373: 9d63a10e83b2d271007e281fe875d6f650a1849e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5612: c8dc1fd926a550308b971ca7d83fe0a927a38152 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17481: 0411865923e7ac26cda739830d80717451927d8d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0411865923e7 drm/i915/gt: Fix up clock frequency
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Fix up clock frequency (rev5)
2020-04-27 15:45 [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency Chris Wilson
2020-04-27 16:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Fix up clock frequency (rev5) Patchwork
2020-04-27 16:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-27 19:20 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-27 19:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Fix up clock frequency (rev5)
URL : https://patchwork.freedesktop.org/series/76512/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8373_full -> Patchwork_17481_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17481_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17481_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17481_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_whisper@basic-normal:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-tglb1/igt@gem_exec_whisper@basic-normal.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-tglb6/igt@gem_exec_whisper@basic-normal.html
Known issues
------------
Here are the changes found in Patchwork_17481_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#52] / [i915#54])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-glk1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-glk9/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-tglb: [PASS][5] -> [SKIP][6] ([i915#668]) +4 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl10/igt@kms_hdr@bpc-switch.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl10/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-iclb2/igt@kms_psr@psr2_basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-iclb5/igt@kms_psr@psr2_basic.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][17] -> [FAIL][18] ([i915#31])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-hsw8/igt@kms_setmode@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-hsw8/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_exec_schedule@smoketest-all:
- shard-tglb: [INCOMPLETE][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-tglb5/igt@gem_exec_schedule@smoketest-all.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-tglb3/igt@gem_exec_schedule@smoketest-all.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding:
- shard-skl: [FAIL][21] ([i915#54]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [FAIL][23] ([i915#96]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1}:
- shard-skl: [FAIL][25] ([i915#79]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* {igt@kms_flip@flip-vs-suspend-interruptible@a-dp1}:
- shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* {igt@kms_flip@flip-vs-suspend@a-dp1}:
- shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-apl4/igt@kms_flip@flip-vs-suspend@a-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
* {igt@kms_flip@plain-flip-ts-check@a-hdmi-a1}:
- shard-glk: [FAIL][31] ([i915#34]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-glk6/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-glk5/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][33] ([i915#1188]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][35] ([fdo#108145] / [i915#265]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [FAIL][37] ([i915#899]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-x.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-glk5/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [INCOMPLETE][41] ([i915#69]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* {igt@perf@polling-parameterized}:
- shard-hsw: [FAIL][43] ([i915#1542]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-hsw8/igt@perf@polling-parameterized.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-hsw7/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: [FAIL][45] ([i915#454]) -> [INCOMPLETE][46] ([i915#198])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/shard-skl6/igt@i915_pm_dc@dc6-dpms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/shard-skl4/igt@i915_pm_dc@dc6-dpms.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8373 -> Patchwork_17481
CI-20190529: 20190529
CI_DRM_8373: 9d63a10e83b2d271007e281fe875d6f650a1849e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5612: c8dc1fd926a550308b971ca7d83fe0a927a38152 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17481: 0411865923e7ac26cda739830d80717451927d8d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17481/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency
@ 2020-04-27 14:25 Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2020-04-27 14:25 UTC (permalink / raw)
To: intel-gfx
The bspec lists both the clock frequency and the effective interval. The
interval corresponds to observed behaviour, so adjust the frequency to
match.
v2: Mika rightfully asked if we could measure the clock frequency from a
selftest.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 +-
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 133 ++++++++++++++++++
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
4 files changed, 141 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 852a7d731b3b..999079686846 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -7,9 +7,9 @@
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
+#define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
+#define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
#define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
-#define MHZ_24 24000000 /* 24MHz, 83.333ns */
-#define MHZ_25 25000000 /* 25MHz, 80ns */
static u32 read_clock_frequency(const struct intel_gt *gt)
{
@@ -21,19 +21,19 @@ static u32 read_clock_frequency(const struct intel_gt *gt)
config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
switch (config) {
- case 0: return MHZ_24;
+ case 0: return MHZ_12;
case 1:
case 2: return MHZ_19_2;
default:
- case 3: return MHZ_25;
+ case 3: return MHZ_12_5;
}
} else if (INTEL_GEN(gt->i915) >= 9) {
if (IS_GEN9_LP(gt->i915))
return MHZ_19_2;
else
- return MHZ_24;
+ return MHZ_12;
} else {
- return MHZ_25;
+ return MHZ_12_5;
}
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index e02fdec58826..242181a5214c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -53,6 +53,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rps_clock_interval),
SUBTEST(live_rps_control),
SUBTEST(live_rps_frequency_cs),
SUBTEST(live_rps_frequency_srm),
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index e13cbcb82825..a7218dcebd2d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -208,6 +208,139 @@ static void show_pstate_limits(struct intel_rps *rps)
}
}
+int live_rps_clock_interval(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >->rps;
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err = 0;
+
+ if (!rps->enabled)
+ return 0;
+
+ if (igt_spinner_init(&spin, gt))
+ return -ENOMEM;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ intel_gt_pm_get(gt);
+ intel_rps_disable(>->rps);
+
+ intel_gt_check_clock_frequency(gt);
+
+ for_each_engine(engine, gt, id) {
+ unsigned long saved_heartbeat;
+ struct i915_request *rq;
+ ktime_t dt;
+ u32 cycles;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ saved_heartbeat = engine_heartbeat_disable(engine);
+
+ rq = igt_spinner_create_request(&spin,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ engine_heartbeat_enable(engine, saved_heartbeat);
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(&spin, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ igt_spinner_end(&spin);
+ engine_heartbeat_enable(engine, saved_heartbeat);
+ intel_gt_set_wedged(engine->gt);
+ err = -EIO;
+ break;
+ }
+
+ intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
+
+ intel_uncore_write_fw(gt->uncore, GEN6_RP_CUR_UP_EI, 0);
+
+ /* Set the evaluation interval to infinity! */
+ intel_uncore_write_fw(gt->uncore,
+ GEN6_RP_UP_EI, 0xffffffff);
+ intel_uncore_write_fw(gt->uncore,
+ GEN6_RP_UP_THRESHOLD, 0xffffffff);
+
+ intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL,
+ GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG);
+
+ if (wait_for(intel_uncore_read_fw(gt->uncore,
+ GEN6_RP_CUR_UP_EI),
+ 10)) {
+ pr_err("%s: rps evalution interval not ticking\n",
+ engine->name);
+ err = -ENODEV;
+ } else {
+ dt = ktime_get();
+ cycles = -intel_uncore_read_fw(gt->uncore,
+ GEN6_RP_CUR_UP_EI);
+ usleep_range(1000, 2000);
+ dt = ktime_sub(ktime_get(), dt);
+ cycles += intel_uncore_read_fw(gt->uncore,
+ GEN6_RP_CUR_UP_EI);
+ }
+
+ intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, 0);
+ intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
+
+ igt_spinner_end(&spin);
+ engine_heartbeat_enable(engine, saved_heartbeat);
+
+ if (err == 0) {
+ u64 time = intel_gt_pm_interval_to_ns(gt, cycles);
+ u32 expected =
+ intel_gt_ns_to_pm_interval(gt, ktime_to_ns(dt));
+
+ pr_info("%s: rps counted %d C0 cycles [%lldns] in %lldns [%d cycles], using GT clock frequency of %uKHz\n",
+ engine->name, cycles, time, ktime_to_ns(dt), expected,
+ gt->clock_frequency / 1000);
+
+ if (10 * time < 9 * ktime_to_ns(dt) ||
+ 10 * time > 11 * ktime_to_ns(dt)) {
+ pr_err("%s: rps clock time does not match walltime!\n",
+ engine->name);
+ err = -EINVAL;
+ }
+
+ if (10 * expected < 9 * cycles ||
+ 10 * expected > 11 * cycles) {
+ pr_err("%s: walltime does not match rps clock ticks!\n",
+ engine->name);
+ err = -EINVAL;
+ }
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ break; /* once is enough */
+ }
+
+ intel_rps_enable(>->rps);
+ intel_gt_pm_put(gt);
+
+ igt_spinner_fini(&spin);
+
+ intel_gt_pm_wait_for_idle(gt);
+ rps->work.func = saved_work;
+
+ return err;
+}
+
int live_rps_control(void *arg)
{
struct intel_gt *gt = arg;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.h b/drivers/gpu/drm/i915/gt/selftest_rps.h
index 76c4b19553e6..6e82a631cfa1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.h
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.h
@@ -7,6 +7,7 @@
#define SELFTEST_RPS_H
int live_rps_control(void *arg);
+int live_rps_clock_interval(void *arg);
int live_rps_frequency_cs(void *arg);
int live_rps_frequency_srm(void *arg);
int live_rps_power(void *arg);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency
@ 2020-04-27 12:57 Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2020-04-27 12:57 UTC (permalink / raw)
To: intel-gfx
The bspec lists both the clock frequency and the effective interval. The
interval corresponds to observed behaviour, so adjust the frequency to
match.
v2: Mika rightfully asked if we could measure the clock frequency from a
selftest.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 +-
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 125 ++++++++++++++++++
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
4 files changed, 133 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 852a7d731b3b..999079686846 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -7,9 +7,9 @@
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
+#define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
+#define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
#define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
-#define MHZ_24 24000000 /* 24MHz, 83.333ns */
-#define MHZ_25 25000000 /* 25MHz, 80ns */
static u32 read_clock_frequency(const struct intel_gt *gt)
{
@@ -21,19 +21,19 @@ static u32 read_clock_frequency(const struct intel_gt *gt)
config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
switch (config) {
- case 0: return MHZ_24;
+ case 0: return MHZ_12;
case 1:
case 2: return MHZ_19_2;
default:
- case 3: return MHZ_25;
+ case 3: return MHZ_12_5;
}
} else if (INTEL_GEN(gt->i915) >= 9) {
if (IS_GEN9_LP(gt->i915))
return MHZ_19_2;
else
- return MHZ_24;
+ return MHZ_12;
} else {
- return MHZ_25;
+ return MHZ_12_5;
}
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index e02fdec58826..242181a5214c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -53,6 +53,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rps_clock_interval),
SUBTEST(live_rps_control),
SUBTEST(live_rps_frequency_cs),
SUBTEST(live_rps_frequency_srm),
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index e13cbcb82825..29e445bbf103 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -208,6 +208,131 @@ static void show_pstate_limits(struct intel_rps *rps)
}
}
+int live_rps_clock_interval(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >->rps;
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err = 0;
+
+ if (!rps->enabled)
+ return 0;
+
+ if (igt_spinner_init(&spin, gt))
+ return -ENOMEM;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ intel_gt_pm_get(gt);
+ intel_rps_disable(>->rps);
+
+ intel_gt_check_clock_frequency(gt);
+
+ for_each_engine(engine, gt, id) {
+ unsigned long saved_heartbeat;
+ struct i915_request *rq;
+ u32 cycles, expected;
+ ktime_t dt;
+ u64 time;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ saved_heartbeat = engine_heartbeat_disable(engine);
+
+ rq = igt_spinner_create_request(&spin,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(&spin, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ igt_spinner_end(&spin);
+ engine_heartbeat_enable(engine, saved_heartbeat);
+ intel_gt_set_wedged(engine->gt);
+ err = -EIO;
+ break;
+ }
+
+ intel_uncore_write(gt->uncore, GEN6_RP_CUR_UP_EI, 0);
+
+ /* Set the evaluation interval to infinity! */
+ intel_uncore_write(gt->uncore,
+ GEN6_RP_UP_EI, 0xffffffff);
+ intel_uncore_write(gt->uncore,
+ GEN6_RP_UP_THRESHOLD, 0xffffffff);
+
+ intel_uncore_write(gt->uncore, GEN6_RP_CONTROL,
+ GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG);
+
+ if (wait_for(intel_uncore_read(gt->uncore, GEN6_RP_CUR_UP_EI),
+ 10)) {
+ pr_err("%s: rps evalution interval not ticking\n",
+ engine->name);
+ igt_spinner_end(&spin);
+ engine_heartbeat_enable(engine, saved_heartbeat);
+ err = -ENODEV;
+ break;
+ }
+
+ dt = ktime_get();
+ cycles = -intel_uncore_read(gt->uncore, GEN6_RP_CUR_UP_EI);
+ usleep_range(1000, 2000);
+ dt = ktime_sub(ktime_get(), dt);
+ cycles += intel_uncore_read(gt->uncore, GEN6_RP_CUR_UP_EI);
+
+ intel_uncore_write(gt->uncore, GEN6_RP_CONTROL, 0);
+
+ igt_spinner_end(&spin);
+ engine_heartbeat_enable(engine, saved_heartbeat);
+
+ time = intel_gt_pm_interval_to_ns(gt, cycles);
+ expected = intel_gt_ns_to_pm_interval(gt, ktime_to_ns(dt));
+ pr_info("%s: rps counted %d C0 cycles [%lldns] in %lldns [%d cycles], using GT clock frequency of %uKHz\n",
+ engine->name, cycles, time, ktime_to_ns(dt), expected,
+ gt->clock_frequency / 1000);
+
+ if (10 * time < 9 * ktime_to_ns(dt) ||
+ 10 * time > 11 * ktime_to_ns(dt)) {
+ pr_err("%s: rps clock time does not match walltime!\n",
+ engine->name);
+ err = -EINVAL;
+ }
+
+ if (10 * expected < 9 * cycles || 10 * expected > 11 * cycles) {
+ pr_err("%s: walltime does not match rps clock ticks!\n",
+ engine->name);
+ err = -EINVAL;
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ break; /* once is enough */
+ }
+
+ intel_rps_enable(>->rps);
+ intel_gt_pm_put(gt);
+
+ igt_spinner_fini(&spin);
+
+ intel_gt_pm_wait_for_idle(gt);
+ rps->work.func = saved_work;
+
+ return err;
+}
+
int live_rps_control(void *arg)
{
struct intel_gt *gt = arg;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.h b/drivers/gpu/drm/i915/gt/selftest_rps.h
index 76c4b19553e6..6e82a631cfa1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.h
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.h
@@ -7,6 +7,7 @@
#define SELFTEST_RPS_H
int live_rps_control(void *arg);
+int live_rps_clock_interval(void *arg);
int live_rps_frequency_cs(void *arg);
int live_rps_frequency_srm(void *arg);
int live_rps_power(void *arg);
--
2.20.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-04-27 19:20 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-27 15:45 [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency Chris Wilson
2020-04-27 16:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Fix up clock frequency (rev5) Patchwork
2020-04-27 16:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-27 19:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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2020-04-27 14:25 [Intel-gfx] [CI] drm/i915/gt: Fix up clock frequency Chris Wilson
2020-04-27 12:57 Chris Wilson
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