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From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
To: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	Philipp Tomsich
	<philipp.tomsich-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>
Cc: patrick-Er2xLVyhcs+zQB+pC5nmwQ@public.gmane.org,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org,
	Jagan Teki
	<jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>,
	sunil-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org,
	linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org
Subject: [PATCH v2 4/8] clk: rk3399: Enable/Disable the PCIEPHY clk
Date: Thu, 30 Apr 2020 12:34:08 +0530	[thread overview]
Message-ID: <20200430070412.12499-5-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20200430070412.12499-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Enable/Disable the PCIEPHY clk for rk3399.

CLK is clear in both enable and disable functionality.

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
Changes for v2:
- clear the clk in enable

 drivers/clk/rockchip/clk_rk3399.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index df70e9fa88..7feba92f9e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1136,6 +1136,9 @@ static int rk3399_clk_enable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_PCIEPHY_REF:
+		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
 		return -ENOENT;
@@ -1209,6 +1212,9 @@ static int rk3399_clk_disable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_PCIEPHY_REF:
+		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
 		return -ENOENT;
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [PATCH v2 4/8] clk: rk3399: Enable/Disable the PCIEPHY clk
Date: Thu, 30 Apr 2020 12:34:08 +0530	[thread overview]
Message-ID: <20200430070412.12499-5-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20200430070412.12499-1-jagan@amarulasolutions.com>

Enable/Disable the PCIEPHY clk for rk3399.

CLK is clear in both enable and disable functionality.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- clear the clk in enable

 drivers/clk/rockchip/clk_rk3399.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index df70e9fa88..7feba92f9e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1136,6 +1136,9 @@ static int rk3399_clk_enable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_PCIEPHY_REF:
+		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
 		return -ENOENT;
@@ -1209,6 +1212,9 @@ static int rk3399_clk_disable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_PCIEPHY_REF:
+		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
 		return -ENOENT;
-- 
2.17.1

  parent reply	other threads:[~2020-04-30  7:04 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30  7:04 [PATCH v2 0/8] rockchip: Add PCIe host support Jagan Teki
2020-04-30  7:04 ` Jagan Teki
     [not found] ` <20200430070412.12499-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2020-04-30  7:04   ` [PATCH v2 1/8] iopoll: Add dealy to read poll Jagan Teki
2020-04-30  7:04     ` Jagan Teki
2020-04-30 14:46     ` Tom Rini
2020-04-30 14:46       ` Tom Rini
2020-04-30 21:03       ` Jagan Teki
2020-04-30 21:03         ` Jagan Teki
2020-04-30 22:06         ` Tom Rini
2020-04-30 22:06           ` Tom Rini
2020-05-01 14:52           ` Jagan Teki
2020-05-01 14:52             ` Jagan Teki
2020-04-30  7:04   ` [PATCH v2 2/8] iopoll: Add readl_poll_sleep_timeout Jagan Teki
2020-04-30  7:04     ` Jagan Teki
2020-04-30  7:04   ` [PATCH v2 3/8] clk: rk3399: Add enable/disable clks Jagan Teki
2020-04-30  7:04     ` Jagan Teki
2020-04-30  7:04   ` Jagan Teki [this message]
2020-04-30  7:04     ` [PATCH v2 4/8] clk: rk3399: Enable/Disable the PCIEPHY clk Jagan Teki
2020-04-30  7:04   ` [PATCH v2 5/8] pci: Add Rockchip PCIe controller driver Jagan Teki
2020-04-30  7:04     ` Jagan Teki
2020-04-30  7:04   ` [PATCH v2 6/8] pci: Add Rockchip PCIe PHY " Jagan Teki
2020-04-30  7:04     ` Jagan Teki
2020-04-30  7:04   ` [PATCH v2 7/8] rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2 Jagan Teki
2020-04-30  7:04     ` Jagan Teki
2020-04-30  7:04   ` [PATCH v2 8/8] rockchip: Enable PCIe/M.2 on rock960 board Jagan Teki
2020-04-30  7:04     ` Jagan Teki
     [not found]     ` <20200430070412.12499-9-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2020-05-03 13:39       ` Manivannan Sadhasivam
2020-05-03 13:39         ` Manivannan Sadhasivam
2020-05-09 16:46         ` Jagan Teki
2020-05-09 16:46           ` Jagan Teki

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