* [PULL v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property
2020-04-30 10:19 [PULL v1 0/6] Xilinx queue 2020-04-30 Edgar E. Iglesias
@ 2020-04-30 10:19 ` Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 2/6] target/microblaze: Add the ill-opcode-exception property Edgar E. Iglesias
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Edgar E. Iglesias @ 2020-04-30 10:19 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the opcode-0x0-illegal CPU property to control if the core
should trap opcode zero as illegal.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 6 +++++-
target/microblaze/translate.c | 2 +-
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 1a700a880c..d51587b342 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -303,6 +303,7 @@ struct MicroBlazeCPU {
bool endi;
bool dopb_bus_exception;
bool iopb_bus_exception;
+ bool opcode_0_illegal;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index c9cf2364ca..418a0cd1fa 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -206,7 +206,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.dopb_bus_exception ?
PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ?
- PVR2_IOPB_BUS_EXC_MASK : 0);
+ PVR2_IOPB_BUS_EXC_MASK : 0) |
+ (cpu->cfg.opcode_0_illegal ?
+ PVR2_OPCODE_0x0_ILL_MASK : 0);
env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
PVR5_DCACHE_WRITEBACK_MASK : 0;
@@ -274,6 +276,8 @@ static Property mb_properties[] = {
/* Enables bus exceptions on failed instruction fetches. */
DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
cfg.iopb_bus_exception, false),
+ DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
+ cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_END_OF_LIST(),
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 37a844db99..222632b670 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
LOG_DIS("%8.8x\t", dc->ir);
if (ir == 0) {
- trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
+ trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
/* Don't decode nop/zero instructions any further. */
return;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PULL v1 2/6] target/microblaze: Add the ill-opcode-exception property
2020-04-30 10:19 [PULL v1 0/6] Xilinx queue 2020-04-30 Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property Edgar E. Iglesias
@ 2020-04-30 10:19 ` Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 3/6] target/microblaze: Add the div-zero-exception property Edgar E. Iglesias
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Edgar E. Iglesias @ 2020-04-30 10:19 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the ill-opcode-exception property to control if illegal
instructions will raise exceptions.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 4 ++++
target/microblaze/translate.c | 2 +-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index d51587b342..71d7317a58 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -303,6 +303,7 @@ struct MicroBlazeCPU {
bool endi;
bool dopb_bus_exception;
bool iopb_bus_exception;
+ bool illegal_opcode_exception;
bool opcode_0_illegal;
char *version;
uint8_t pvr;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 418a0cd1fa..2cc6b1513c 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ?
PVR2_IOPB_BUS_EXC_MASK : 0) |
+ (cpu->cfg.illegal_opcode_exception ?
+ PVR2_ILL_OPCODE_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
PVR2_OPCODE_0x0_ILL_MASK : 0);
@@ -276,6 +278,8 @@ static Property mb_properties[] = {
/* Enables bus exceptions on failed instruction fetches. */
DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
cfg.iopb_bus_exception, false),
+ DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
+ cfg.illegal_opcode_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 222632b670..b4a78551ef 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry)
static bool trap_illegal(DisasContext *dc, bool cond)
{
if (cond && (dc->tb_flags & MSR_EE_FLAG)
- && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
+ && dc->cpu->cfg.illegal_opcode_exception) {
tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PULL v1 3/6] target/microblaze: Add the div-zero-exception property
2020-04-30 10:19 [PULL v1 0/6] Xilinx queue 2020-04-30 Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 2/6] target/microblaze: Add the ill-opcode-exception property Edgar E. Iglesias
@ 2020-04-30 10:19 ` Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 4/6] target/microblaze: Add the unaligned-exceptions property Edgar E. Iglesias
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Edgar E. Iglesias @ 2020-04-30 10:19 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the div-zero-exception property to control if the core
traps divizions by zero.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 4 ++++
target/microblaze/op_helper.c | 5 +++--
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 71d7317a58..3c07f9b3f7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -305,6 +305,7 @@ struct MicroBlazeCPU {
bool iopb_bus_exception;
bool illegal_opcode_exception;
bool opcode_0_illegal;
+ bool div_zero_exception;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 2cc6b1513c..4211f50c11 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ?
PVR2_IOPB_BUS_EXC_MASK : 0) |
+ (cpu->cfg.div_zero_exception ?
+ PVR2_DIV_ZERO_EXC_MASK : 0) |
(cpu->cfg.illegal_opcode_exception ?
PVR2_ILL_OPCODE_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
@@ -280,6 +282,8 @@ static Property mb_properties[] = {
cfg.iopb_bus_exception, false),
DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
cfg.illegal_opcode_exception, false),
+ DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
+ cfg.div_zero_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 18677ddfca..f3b17a95b3 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
+ MicroBlazeCPU *cpu = env_archcpu(env);
+
if (b == 0) {
env->sregs[SR_MSR] |= MSR_DZ;
- if ((env->sregs[SR_MSR] & MSR_EE)
- && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
+ if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO;
helper_raise_exception(env, EXCP_HW_EXCP);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PULL v1 4/6] target/microblaze: Add the unaligned-exceptions property
2020-04-30 10:19 [PULL v1 0/6] Xilinx queue 2020-04-30 Edgar E. Iglesias
` (2 preceding siblings ...)
2020-04-30 10:19 ` [PULL v1 3/6] target/microblaze: Add the div-zero-exception property Edgar E. Iglesias
@ 2020-04-30 10:19 ` Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 5/6] target/microblaze: Add the pvr-user1 property Edgar E. Iglesias
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Edgar E. Iglesias @ 2020-04-30 10:19 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the unaligned-exceptions property to control if the core
traps unaligned memory accesses.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 4 ++++
target/microblaze/translate.c | 4 ++--
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3c07f9b3f7..ef9081db40 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -306,6 +306,7 @@ struct MicroBlazeCPU {
bool illegal_opcode_exception;
bool opcode_0_illegal;
bool div_zero_exception;
+ bool unaligned_exceptions;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 4211f50c11..585e60e817 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -211,6 +211,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_DIV_ZERO_EXC_MASK : 0) |
(cpu->cfg.illegal_opcode_exception ?
PVR2_ILL_OPCODE_EXC_MASK : 0) |
+ (cpu->cfg.unaligned_exceptions ?
+ PVR2_UNALIGNED_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
PVR2_OPCODE_0x0_ILL_MASK : 0);
@@ -284,6 +286,8 @@ static Property mb_properties[] = {
cfg.illegal_opcode_exception, false),
DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
cfg.div_zero_exception, false),
+ DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
+ cfg.unaligned_exceptions, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b4a78551ef..20b7427811 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
v = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
- if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
TCGv_i32 t0 = tcg_const_i32(0);
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);
@@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
/* Verify alignment if needed. */
- if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
TCGv_i32 t1 = tcg_const_i32(1);
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PULL v1 5/6] target/microblaze: Add the pvr-user1 property
2020-04-30 10:19 [PULL v1 0/6] Xilinx queue 2020-04-30 Edgar E. Iglesias
` (3 preceding siblings ...)
2020-04-30 10:19 ` [PULL v1 4/6] target/microblaze: Add the unaligned-exceptions property Edgar E. Iglesias
@ 2020-04-30 10:19 ` Edgar E. Iglesias
2020-04-30 10:19 ` [PULL v1 6/6] target/microblaze: Add the pvr-user2 property Edgar E. Iglesias
2020-04-30 18:25 ` [PULL v1 0/6] Xilinx queue 2020-04-30 Peter Maydell
6 siblings, 0 replies; 8+ messages in thread
From: Edgar E. Iglesias @ 2020-04-30 10:19 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the pvr-user1 property to control the user-defined
PVR0 User1 field.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index ef9081db40..7bb5a3d6c6 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -307,6 +307,7 @@ struct MicroBlazeCPU {
bool opcode_0_illegal;
bool div_zero_exception;
bool unaligned_exceptions;
+ uint8_t pvr_user1;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 585e60e817..df5ee21dd6 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -193,7 +193,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
(version_code << PVR0_VERSION_SHIFT) |
- (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
+ (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
+ cpu->cfg.pvr_user1;
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
@@ -292,6 +293,7 @@ static Property mb_properties[] = {
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
+ DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PULL v1 6/6] target/microblaze: Add the pvr-user2 property
2020-04-30 10:19 [PULL v1 0/6] Xilinx queue 2020-04-30 Edgar E. Iglesias
` (4 preceding siblings ...)
2020-04-30 10:19 ` [PULL v1 5/6] target/microblaze: Add the pvr-user1 property Edgar E. Iglesias
@ 2020-04-30 10:19 ` Edgar E. Iglesias
2020-04-30 18:25 ` [PULL v1 0/6] Xilinx queue 2020-04-30 Peter Maydell
6 siblings, 0 replies; 8+ messages in thread
From: Edgar E. Iglesias @ 2020-04-30 10:19 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the pvr-user2 property to control the user-defined
PVR1 User2 register.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 7bb5a3d6c6..a31134b65c 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -308,6 +308,7 @@ struct MicroBlazeCPU {
bool div_zero_exception;
bool unaligned_exceptions;
uint8_t pvr_user1;
+ uint32_t pvr_user2;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index df5ee21dd6..aa9983069a 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -196,6 +196,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
cpu->cfg.pvr_user1;
+ env->pvr.regs[1] = cpu->cfg.pvr_user2;
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
@@ -294,6 +295,7 @@ static Property mb_properties[] = {
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
+ DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PULL v1 0/6] Xilinx queue 2020-04-30
2020-04-30 10:19 [PULL v1 0/6] Xilinx queue 2020-04-30 Edgar E. Iglesias
` (5 preceding siblings ...)
2020-04-30 10:19 ` [PULL v1 6/6] target/microblaze: Add the pvr-user2 property Edgar E. Iglesias
@ 2020-04-30 18:25 ` Peter Maydell
6 siblings, 0 replies; 8+ messages in thread
From: Peter Maydell @ 2020-04-30 18:25 UTC (permalink / raw)
To: Edgar E. Iglesias; +Cc: Edgar Iglesias, QEMU Developers
On Thu, 30 Apr 2020 at 11:19, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100)
>
> are available in the Git repository at:
>
> git@github.com:edgarigl/qemu.git tags/edgar/xilinx-next-2020-04-30.for-upstream
>
> for you to fetch changes up to 3ed43b5031ed2d7ef501bb81b87caed960218461:
>
> target/microblaze: Add the pvr-user2 property (2020-04-30 12:11:03 +0200)
>
> ----------------------------------------------------------------
> For upstream
>
> ----------------------------------------------------------------
> Edgar E. Iglesias (6):
> target/microblaze: Add the opcode-0x0-illegal CPU property
> target/microblaze: Add the ill-opcode-exception property
> target/microblaze: Add the div-zero-exception property
> target/microblaze: Add the unaligned-exceptions property
> target/microblaze: Add the pvr-user1 property
> target/microblaze: Add the pvr-user2 property
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread