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* [PATCH v2 0/3] arm64: Make NOP handling a whitelist
@ 2020-04-28 17:24 Mark Brown
  2020-04-28 17:24 ` [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs Mark Brown
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: Mark Brown @ 2020-04-28 17:24 UTC (permalink / raw)
  To: Will Deacon, Catalin Marinas; +Cc: Mark Brown, linux-arm-kernel

Currently we default to assuming any unrecognized instruction in the
hint space can be safely handled as a NOP.  This is not robust and any
code that really wants a NOP should be using the explicitly defined NOP
so let's instead invert this and whitelist those instructions which it
is safe to handle as NOPs.

Patch 2 adds defines for the HINTs for BTI landing pads which will be
used by the in-kernel BTI series to generate landing pads in JITed BPF
code so it'd be good if this could be applied on or merged into the BTI
branch.

v2:
 - Fix values for BTI HINTs.
 - Rebase on v5.7-rc3+for-next/bti

Mark Brown (3):
  arm64: insn: Don't assume unrecognized HINTs are NOPs
  arm64: insn: Add constants for PAC and BTI instruction decode
  arm64: insn: Report PAC and BTI instructions as NOPs

 arch/arm64/include/asm/insn.h | 22 ++++++++++++++++++++--
 arch/arm64/kernel/insn.c      | 32 ++++++++++++++++++++++++--------
 2 files changed, 44 insertions(+), 10 deletions(-)

-- 
2.20.1


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^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs
  2020-04-28 17:24 [PATCH v2 0/3] arm64: Make NOP handling a whitelist Mark Brown
@ 2020-04-28 17:24 ` Mark Brown
  2020-04-30 16:08   ` Will Deacon
  2020-04-28 17:24 ` [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode Mark Brown
  2020-04-28 17:24 ` [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs Mark Brown
  2 siblings, 1 reply; 11+ messages in thread
From: Mark Brown @ 2020-04-28 17:24 UTC (permalink / raw)
  To: Will Deacon, Catalin Marinas; +Cc: Mark Brown, linux-arm-kernel

Currently the kernel assumes that any HINT which it does not explicitly
recognise is a NOP.  This is not robust as new instructions may be added
which need special handling, including recent extensions like PAC, and
in any case software should only be using explicit NOP instructions for
deliberate NOPs.

This has the effect of rendering PAC and BTI instructions unprobeable
which means that probes can't be inserted on the first instruction of
functions built with those features.

Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/insn.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 4a9e773a177f..535a3a7a053e 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -58,14 +58,10 @@ bool __kprobes aarch64_insn_is_nop(u32 insn)
 		return false;
 
 	switch (insn & 0xFE0) {
-	case AARCH64_INSN_HINT_YIELD:
-	case AARCH64_INSN_HINT_WFE:
-	case AARCH64_INSN_HINT_WFI:
-	case AARCH64_INSN_HINT_SEV:
-	case AARCH64_INSN_HINT_SEVL:
-		return false;
-	default:
+	case AARCH64_INSN_HINT_NOP:
 		return true;
+	default:
+		return false;
 	}
 }
 
-- 
2.20.1


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^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode
  2020-04-28 17:24 [PATCH v2 0/3] arm64: Make NOP handling a whitelist Mark Brown
  2020-04-28 17:24 ` [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs Mark Brown
@ 2020-04-28 17:24 ` Mark Brown
  2020-04-30 16:07   ` Will Deacon
  2020-04-28 17:24 ` [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs Mark Brown
  2 siblings, 1 reply; 11+ messages in thread
From: Mark Brown @ 2020-04-28 17:24 UTC (permalink / raw)
  To: Will Deacon, Catalin Marinas; +Cc: Mark Brown, linux-arm-kernel

Add constants for decoding the various PAC and BTI instructions defined
in the HINT space. Since we are now decoding both the op2 and CRm fields
rename the enum as well; this is compatible with what the existing users
are doing.

Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/insn.h | 22 ++++++++++++++++++++--
 arch/arm64/kernel/insn.c      |  2 +-
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index bb313dde58a4..e5a87f98a548 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -39,13 +39,31 @@ enum aarch64_insn_encoding_class {
 					 * system instructions */
 };
 
-enum aarch64_insn_hint_op {
+enum aarch64_insn_hint_cr_op {
 	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
 	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
 	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
 	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
 	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
 	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
+
+	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
+	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
+	AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5,
+	AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5,
+	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
+	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
+	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
+	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
+	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
+	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
+	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
+	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
+
+	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
+	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
+	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
+	AARCH64_INSN_HINT_BTIJC = 0x2C << 5,
 };
 
 enum aarch64_insn_imm_type {
@@ -370,7 +388,7 @@ u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
 				     enum aarch64_insn_branch_type type);
 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 				     enum aarch64_insn_condition cond);
-u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
+u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
 u32 aarch64_insn_gen_nop(void);
 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
 				enum aarch64_insn_branch_type type);
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 535a3a7a053e..fd77cdd87c47 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -570,7 +570,7 @@ u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 					     offset >> 2);
 }
 
-u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
+u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)
 {
 	return aarch64_insn_get_hint_value() | op;
 }
-- 
2.20.1


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^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs
  2020-04-28 17:24 [PATCH v2 0/3] arm64: Make NOP handling a whitelist Mark Brown
  2020-04-28 17:24 ` [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs Mark Brown
  2020-04-28 17:24 ` [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode Mark Brown
@ 2020-04-28 17:24 ` Mark Brown
  2020-04-30 16:09   ` Will Deacon
  2 siblings, 1 reply; 11+ messages in thread
From: Mark Brown @ 2020-04-28 17:24 UTC (permalink / raw)
  To: Will Deacon, Catalin Marinas; +Cc: Mark Brown, linux-arm-kernel

In order to allow probing of PAC and BTI instructions without more
specialized support recognize them as NOPs.

Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/insn.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index fd77cdd87c47..82afc582d29a 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -57,7 +57,27 @@ bool __kprobes aarch64_insn_is_nop(u32 insn)
 	if (!aarch64_insn_is_hint(insn))
 		return false;
 
+	/*
+	 * The PAC and BTI instructons are not strictly NOPs but until
+	 * better support is added we can treat them as such.
+	 */
 	switch (insn & 0xFE0) {
+	case AARCH64_INSN_HINT_PACIA_1716:
+	case AARCH64_INSN_HINT_PACIB_1716:
+	case AARCH64_INSN_HINT_AUTIA_1716:
+	case AARCH64_INSN_HINT_AUTIB_1716:
+	case AARCH64_INSN_HINT_PACIAZ:
+	case AARCH64_INSN_HINT_PACIASP:
+	case AARCH64_INSN_HINT_PACIBZ:
+	case AARCH64_INSN_HINT_PACIBSP:
+	case AARCH64_INSN_HINT_AUTIAZ:
+	case AARCH64_INSN_HINT_AUTIASP:
+	case AARCH64_INSN_HINT_AUTIBZ:
+	case AARCH64_INSN_HINT_AUTIBSP:
+	case AARCH64_INSN_HINT_BTI:
+	case AARCH64_INSN_HINT_BTIC:
+	case AARCH64_INSN_HINT_BTIJ:
+	case AARCH64_INSN_HINT_BTIJC:
 	case AARCH64_INSN_HINT_NOP:
 		return true;
 	default:
-- 
2.20.1


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^ permalink raw reply related	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode
  2020-04-28 17:24 ` [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode Mark Brown
@ 2020-04-30 16:07   ` Will Deacon
  2020-04-30 16:45     ` Mark Brown
  0 siblings, 1 reply; 11+ messages in thread
From: Will Deacon @ 2020-04-30 16:07 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, linux-arm-kernel

On Tue, Apr 28, 2020 at 06:24:32PM +0100, Mark Brown wrote:
> Add constants for decoding the various PAC and BTI instructions defined
> in the HINT space. Since we are now decoding both the op2 and CRm fields
> rename the enum as well; this is compatible with what the existing users
> are doing.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  arch/arm64/include/asm/insn.h | 22 ++++++++++++++++++++--
>  arch/arm64/kernel/insn.c      |  2 +-
>  2 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index bb313dde58a4..e5a87f98a548 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -39,13 +39,31 @@ enum aarch64_insn_encoding_class {
>  					 * system instructions */
>  };
>  
> -enum aarch64_insn_hint_op {
> +enum aarch64_insn_hint_cr_op {
>  	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
>  	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
>  	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
>  	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
>  	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
>  	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
> +
> +	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
> +	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
> +	AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5,
> +	AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5,

These still look wrong to me.

> +	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
> +	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
> +	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
> +	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
> +	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
> +	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,

This one is typo'd in the Arm ARM as AUTHASP. Seems nobody can get this
stuff right!

> +	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
> +	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
> +
> +	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
> +	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
> +	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
> +	AARCH64_INSN_HINT_BTIJC = 0x2C << 5,

This looks wrong as well.

Will

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs
  2020-04-28 17:24 ` [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs Mark Brown
@ 2020-04-30 16:08   ` Will Deacon
  0 siblings, 0 replies; 11+ messages in thread
From: Will Deacon @ 2020-04-30 16:08 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, linux-arm-kernel

On Tue, Apr 28, 2020 at 06:24:31PM +0100, Mark Brown wrote:
> Currently the kernel assumes that any HINT which it does not explicitly
> recognise is a NOP.  This is not robust as new instructions may be added
> which need special handling, including recent extensions like PAC, and
> in any case software should only be using explicit NOP instructions for
> deliberate NOPs.

Hmm, I'm not sure that using PAC as the justification makes tonnes of sense
here, since you go ahead and whitelist the PAC hints in patch 3!

Will

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs
  2020-04-28 17:24 ` [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs Mark Brown
@ 2020-04-30 16:09   ` Will Deacon
  2020-04-30 17:16     ` Mark Brown
  0 siblings, 1 reply; 11+ messages in thread
From: Will Deacon @ 2020-04-30 16:09 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, linux-arm-kernel

On Tue, Apr 28, 2020 at 06:24:33PM +0100, Mark Brown wrote:
> In order to allow probing of PAC and BTI instructions without more
> specialized support recognize them as NOPs.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  arch/arm64/kernel/insn.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
> index fd77cdd87c47..82afc582d29a 100644
> --- a/arch/arm64/kernel/insn.c
> +++ b/arch/arm64/kernel/insn.c
> @@ -57,7 +57,27 @@ bool __kprobes aarch64_insn_is_nop(u32 insn)
>  	if (!aarch64_insn_is_hint(insn))
>  		return false;
>  
> +	/*
> +	 * The PAC and BTI instructons are not strictly NOPs but until
> +	 * better support is added we can treat them as such.
> +	 */
>  	switch (insn & 0xFE0) {

Are you deliberately omitting XPACLRI? If so, maybe add a comment to say
why, since it looks a bit weird without it.

Will

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode
  2020-04-30 16:07   ` Will Deacon
@ 2020-04-30 16:45     ` Mark Brown
  0 siblings, 0 replies; 11+ messages in thread
From: Mark Brown @ 2020-04-30 16:45 UTC (permalink / raw)
  To: Will Deacon; +Cc: Catalin Marinas, linux-arm-kernel


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On Thu, Apr 30, 2020 at 05:07:30PM +0100, Will Deacon wrote:
> On Tue, Apr 28, 2020 at 06:24:32PM +0100, Mark Brown wrote:

> > +	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
> > +	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
> > +	AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5,
> > +	AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5,

> These still look wrong to me.

Ack, I think I must've glazed over after checking PACIA which is right
or missed stuff when cut'n'pasting to verify.

> > +	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
> > +	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
> > +	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
> > +	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
> > +	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
> > +	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,

> This one is typo'd in the Arm ARM as AUTHASP. Seems nobody can get this
> stuff right!

It seems to have been fixed in the current revision - or at least
AUTIASP is there and text search isn't finding any instances of
AUTHASP.

> > +	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
> > +	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
> > +	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
> > +	AARCH64_INSN_HINT_BTIJC = 0x2C << 5,

> This looks wrong as well.

_JC is wrong, yes.

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs
  2020-04-30 16:09   ` Will Deacon
@ 2020-04-30 17:16     ` Mark Brown
  2020-04-30 17:20       ` Will Deacon
  0 siblings, 1 reply; 11+ messages in thread
From: Mark Brown @ 2020-04-30 17:16 UTC (permalink / raw)
  To: Will Deacon; +Cc: Catalin Marinas, linux-arm-kernel


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On Thu, Apr 30, 2020 at 05:09:29PM +0100, Will Deacon wrote:
> On Tue, Apr 28, 2020 at 06:24:33PM +0100, Mark Brown wrote:

> > +	/*
> > +	 * The PAC and BTI instructons are not strictly NOPs but until
> > +	 * better support is added we can treat them as such.
> > +	 */
> >  	switch (insn & 0xFE0) {

> Are you deliberately omitting XPACLRI? If so, maybe add a comment to say
> why, since it looks a bit weird without it.

Not deliberately, no - I'm not sure I'd heard of it before and it's one
of those cases where the spec doesn't call out the instruction as being
in the hint space.

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs
  2020-04-30 17:16     ` Mark Brown
@ 2020-04-30 17:20       ` Will Deacon
  2020-04-30 17:36         ` Mark Brown
  0 siblings, 1 reply; 11+ messages in thread
From: Will Deacon @ 2020-04-30 17:20 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, linux-arm-kernel

On Thu, Apr 30, 2020 at 06:16:45PM +0100, Mark Brown wrote:
> On Thu, Apr 30, 2020 at 05:09:29PM +0100, Will Deacon wrote:
> > On Tue, Apr 28, 2020 at 06:24:33PM +0100, Mark Brown wrote:
> 
> > > +	/*
> > > +	 * The PAC and BTI instructons are not strictly NOPs but until
> > > +	 * better support is added we can treat them as such.
> > > +	 */
> > >  	switch (insn & 0xFE0) {
> 
> > Are you deliberately omitting XPACLRI? If so, maybe add a comment to say
> > why, since it looks a bit weird without it.
> 
> Not deliberately, no - I'm not sure I'd heard of it before and it's one
> of those cases where the spec doesn't call out the instruction as being
> in the hint space.

Hmm, so I only spotted it because of "Decode" pseudocode for HINT on p.929
of rev F.a of the Arm ARM (the one with the AUTHASP typo).

Will

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs
  2020-04-30 17:20       ` Will Deacon
@ 2020-04-30 17:36         ` Mark Brown
  0 siblings, 0 replies; 11+ messages in thread
From: Mark Brown @ 2020-04-30 17:36 UTC (permalink / raw)
  To: Will Deacon; +Cc: Catalin Marinas, linux-arm-kernel


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On Thu, Apr 30, 2020 at 06:20:40PM +0100, Will Deacon wrote:
> On Thu, Apr 30, 2020 at 06:16:45PM +0100, Mark Brown wrote:
> > On Thu, Apr 30, 2020 at 05:09:29PM +0100, Will Deacon wrote:

> > > Are you deliberately omitting XPACLRI? If so, maybe add a comment to say
> > > why, since it looks a bit weird without it.

> > Not deliberately, no - I'm not sure I'd heard of it before and it's one
> > of those cases where the spec doesn't call out the instruction as being
> > in the hint space.

> Hmm, so I only spotted it because of "Decode" pseudocode for HINT on p.929
> of rev F.a of the Arm ARM (the one with the AUTHASP typo).

Ah, I see - that's indeed a useful enumeration of the currently defined
HINTs.  IIRC I wrote this code before I became aware that HINT was
defined as an instruction rather than just being an encoding space!
Thanks for the pointer.

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^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-04-30 17:36 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-28 17:24 [PATCH v2 0/3] arm64: Make NOP handling a whitelist Mark Brown
2020-04-28 17:24 ` [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs Mark Brown
2020-04-30 16:08   ` Will Deacon
2020-04-28 17:24 ` [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode Mark Brown
2020-04-30 16:07   ` Will Deacon
2020-04-30 16:45     ` Mark Brown
2020-04-28 17:24 ` [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs Mark Brown
2020-04-30 16:09   ` Will Deacon
2020-04-30 17:16     ` Mark Brown
2020-04-30 17:20       ` Will Deacon
2020-04-30 17:36         ` Mark Brown

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