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From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands
Date: Tue,  5 May 2020 13:22:45 +0300	[thread overview]
Message-ID: <20200505102247.32452-5-stanislav.lisovskiy@intel.com> (raw)
In-Reply-To: <20200505102247.32452-1-stanislav.lisovskiy@intel.com>

We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.

v2: - Extracted those changes into separate patch
      (Ville Syrjälä)

v3: - Moved new PCode masks to another place from
      PCode commands(Ville)

v4: - Moved new PCode masks to correspondent PCode
      command, with identation(Ville)
    - Changed naming to ICL_ instead of GEN11_
      to fit more nicely into existing definition
      style.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       | 4 ++++
 drivers/gpu/drm/i915/intel_sideband.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fd9f2904d93c..f23a18ee28f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9064,6 +9064,7 @@ enum {
 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
 #define     GEN11_PCODE_LOCKED			0x6
+#define     GEN11_PCODE_REJECTED		0x11
 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
 #define   GEN6_PCODE_READ_RC6VIDS		0x5
@@ -9085,6 +9086,9 @@ enum {
 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
+#define     ICL_PCODE_POINTS_RESTRICTED		0x0
+#define     ICL_PCODE_POINTS_RESTRICTED_MASK	0x1
 #define   GEN6_PCODE_READ_D_COMP		0x10
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   ICL_PCODE_EXIT_TCCOLD			0x12
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index d5129c1dd452..916ccd1c0e96 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
 		return -ENXIO;
 	case GEN11_PCODE_LOCKED:
 		return -EBUSY;
+	case GEN11_PCODE_REJECTED:
+		return -EACCES;
 	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
 		return -EOVERFLOW;
 	default:
-- 
2.24.1.485.gad05a3d8e5

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  parent reply	other threads:[~2020-05-05 10:27 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-05 10:22 [Intel-gfx] [PATCH v27 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 2/6] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
2020-05-05 10:42   ` Ville Syrjälä
2020-05-05 11:01     ` Ville Syrjälä
2020-05-05 20:37       ` Lisovskiy, Stanislav
2020-05-06  7:31         ` Ville Syrjälä
2020-05-06  7:55     ` Lisovskiy, Stanislav
2020-05-06  8:08       ` Ville Syrjälä
2020-05-06  8:43         ` Lisovskiy, Stanislav
2020-05-06  9:15           ` Ville Syrjälä
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
2020-05-05 10:59   ` Ville Syrjälä
2020-05-06  8:31     ` Lisovskiy, Stanislav
2020-05-06  9:12       ` Ville Syrjälä
2020-05-06 12:12         ` Lisovskiy, Stanislav
2020-05-06 13:16           ` Ville Syrjälä
2020-05-06 13:42             ` Lisovskiy, Stanislav
2020-05-05 10:22 ` Stanislav Lisovskiy [this message]
2020-05-05 11:04   ` [Intel-gfx] [PATCH v27 4/6] drm/i915: Added required new PCode commands Ville Syrjälä
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-05-05 10:22 ` [Intel-gfx] [PATCH v27 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-05-05 13:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev35) Patchwork
2020-05-06  1:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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