From: Will Deacon <will@kernel.org>
To: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Douglas Anderson <dianders@chromium.org>,
Jason Wessel <jason.wessel@windriver.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, patches@linaro.org
Subject: Re: [PATCH v2] arm64: cacheflush: Fix KGDB trap detection
Date: Tue, 5 May 2020 16:09:16 +0100 [thread overview]
Message-ID: <20200505150916.GC24239@willie-the-truck> (raw)
In-Reply-To: <20200505141529.2qb35fbqudtac3ys@holly.lan>
On Tue, May 05, 2020 at 03:15:29PM +0100, Daniel Thompson wrote:
> On Mon, May 04, 2020 at 09:48:04PM +0100, Will Deacon wrote:
> > On Mon, May 04, 2020 at 06:05:18PM +0100, Daniel Thompson wrote:
> > > diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> > > index e6cca3d4acf7..ce50c1f1f1ea 100644
> > > --- a/arch/arm64/include/asm/cacheflush.h
> > > +++ b/arch/arm64/include/asm/cacheflush.h
> > > @@ -79,7 +79,7 @@ static inline void flush_icache_range(unsigned long start, unsigned long end)
> > > * IPI all online CPUs so that they undergo a context synchronization
> > > * event and are forced to refetch the new instructions.
> > > */
> > > -#ifdef CONFIG_KGDB
> > > +
> > > /*
> > > * KGDB performs cache maintenance with interrupts disabled, so we
> > > * will deadlock trying to IPI the secondary CPUs. In theory, we can
> > > @@ -89,9 +89,9 @@ static inline void flush_icache_range(unsigned long start, unsigned long end)
> > > * the patching operation, so we don't need extra IPIs here anyway.
> > > * In which case, add a KGDB-specific bodge and return early.
> > > */
> > > - if (kgdb_connected && irqs_disabled())
> > > + if (in_dbg_master())
> >
> > Does this imply that irqs are disabled?
>
> Yes.
>
> Assuming CONFIG_KGDB is enabled then in_dbg_master() expands to:
>
> (raw_smp_processor_id() == atomic_read(&kgdb_active))
Aha, so this can drop the raw_ prefix and call smp_processor_id() instead?
I can queue the arm64 patch regardless.
Cheers,
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Daniel Thompson <daniel.thompson@linaro.org>
Cc: patches@linaro.org, Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org,
Douglas Anderson <dianders@chromium.org>,
Jason Wessel <jason.wessel@windriver.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] arm64: cacheflush: Fix KGDB trap detection
Date: Tue, 5 May 2020 16:09:16 +0100 [thread overview]
Message-ID: <20200505150916.GC24239@willie-the-truck> (raw)
In-Reply-To: <20200505141529.2qb35fbqudtac3ys@holly.lan>
On Tue, May 05, 2020 at 03:15:29PM +0100, Daniel Thompson wrote:
> On Mon, May 04, 2020 at 09:48:04PM +0100, Will Deacon wrote:
> > On Mon, May 04, 2020 at 06:05:18PM +0100, Daniel Thompson wrote:
> > > diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> > > index e6cca3d4acf7..ce50c1f1f1ea 100644
> > > --- a/arch/arm64/include/asm/cacheflush.h
> > > +++ b/arch/arm64/include/asm/cacheflush.h
> > > @@ -79,7 +79,7 @@ static inline void flush_icache_range(unsigned long start, unsigned long end)
> > > * IPI all online CPUs so that they undergo a context synchronization
> > > * event and are forced to refetch the new instructions.
> > > */
> > > -#ifdef CONFIG_KGDB
> > > +
> > > /*
> > > * KGDB performs cache maintenance with interrupts disabled, so we
> > > * will deadlock trying to IPI the secondary CPUs. In theory, we can
> > > @@ -89,9 +89,9 @@ static inline void flush_icache_range(unsigned long start, unsigned long end)
> > > * the patching operation, so we don't need extra IPIs here anyway.
> > > * In which case, add a KGDB-specific bodge and return early.
> > > */
> > > - if (kgdb_connected && irqs_disabled())
> > > + if (in_dbg_master())
> >
> > Does this imply that irqs are disabled?
>
> Yes.
>
> Assuming CONFIG_KGDB is enabled then in_dbg_master() expands to:
>
> (raw_smp_processor_id() == atomic_read(&kgdb_active))
Aha, so this can drop the raw_ prefix and call smp_processor_id() instead?
I can queue the arm64 patch regardless.
Cheers,
Will
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next prev parent reply other threads:[~2020-05-05 15:09 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 17:05 [PATCH v2] arm64: cacheflush: Fix KGDB trap detection Daniel Thompson
2020-05-04 17:05 ` Daniel Thompson
2020-05-04 20:48 ` Will Deacon
2020-05-04 20:48 ` Will Deacon
2020-05-05 14:15 ` Daniel Thompson
2020-05-05 14:15 ` Daniel Thompson
2020-05-05 15:09 ` Will Deacon [this message]
2020-05-05 15:09 ` Will Deacon
2020-05-06 15:06 ` Daniel Thompson
2020-05-06 15:06 ` Daniel Thompson
2020-05-05 16:13 ` Will Deacon
2020-05-05 16:13 ` Will Deacon
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