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From: Michael Walle <michael@walle.cc>
To: u-boot@lists.denx.de
Subject: [PATCH v4 05/12] phy: atheros: Clarify the intention of ar8021_config
Date: Thu,  7 May 2020 00:11:52 +0200	[thread overview]
Message-ID: <20200506221159.1298-6-michael@walle.cc> (raw)
In-Reply-To: <20200506221159.1298-1-michael@walle.cc>

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3e59c3f391..3cc162828c 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -56,10 +56,10 @@ static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
 
 static int ar8021_config(struct phy_device *phydev)
 {
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
-		  AR803x_DEBUG_REG_5);
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+		  BMCR_ANENABLE | BMCR_ANRESTART);
+
+	ar803x_enable_tx_delay(phydev, true);
 
 	phydev->supported = phydev->drv->features;
 	return 0;
-- 
2.20.1

  parent reply	other threads:[~2020-05-06 22:11 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-06 22:11 [PATCH v4 00/12] phy: atheros: dt bindings and cleanup Michael Walle
2020-05-06 22:11 ` [PATCH v4 01/12] phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Michael Walle
2020-05-07 18:51   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 02/12] phy: atheros: Use common functions for RGMII internal delays Michael Walle
2020-05-07 18:52   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 03/12] phy: atheros: Clarify the configuration of the CLK_25M output pin Michael Walle
2020-05-07 18:52   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 04/12] phy: atheros: Explicitly disable RGMII delays Michael Walle
2020-05-07 18:52   ` Tom Rini
2020-05-06 22:11 ` Michael Walle [this message]
2020-05-07 18:52   ` [PATCH v4 05/12] phy: atheros: Clarify the intention of ar8021_config Tom Rini
2020-05-06 22:11 ` [PATCH v4 06/12] phy: atheros: fix AR8021 PHY ID mask Michael Walle
2020-05-07 18:53   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 07/12] phy: atheros: use defines for PHY IDs Michael Walle
2020-05-07 18:53   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 08/12] phy: atheros: introduce debug read and write functions Michael Walle
2020-05-07 18:53   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 09/12] phy: atheros: move delay config to common function Michael Walle
2020-05-07 18:53   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 10/12] phy: atheros: add device tree bindings and config Michael Walle
2020-05-07 18:53   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 11/12] phy: atheros: ar8035: remove static clock config Michael Walle
2020-05-07 18:53   ` Tom Rini
2020-05-06 22:11 ` [PATCH v4 12/12] phy: atheros: consolidate {ar8031|ar8035}_config() Michael Walle
2020-05-07 18:53   ` Tom Rini

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